[binutils][aarch64] Allow movprfx for SVE2 instructions.
[deliverable/binutils-gdb.git] / include / ChangeLog
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12019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
2
3 * opcode/aarch64.h (AARCH64_FEATURE_SVE2
4 AARCH64_FEATURE_SVE2_AES, AARCH64_FEATURE_SVE2_BITPERM,
5 AARCH64_FEATURE_SVE2_SM4, AARCH64_FEATURE_SVE2_SHA3): New
6 feature macros.
7
82019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
9 Faraz Shahbazker <fshahbazker@wavecomp.com>
10
11 * opcode/mips.h (ASE_EVA_R6): New macro.
12 (M_LLWPE_AB, M_SCWPE_AB): New enum values.
13
142019-05-01 Sudakshina Das <sudi.das@arm.com>
15
16 * opcode/aarch64.h (AARCH64_FEATURE_TME): New.
17 (enum aarch64_opnd): Add AARCH64_OPND_TME_UIMM16.
18
192019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
20 Faraz Shahbazker <fshahbazker@wavecomp.com>
21
22 * opcode/mips.h (M_LLWP_AB, M_LLDP_AB): New enum values.
23 (M_SCWP_AB, M_SCDP_AB): Likewise.
24
252019-04-25 Maciej W. Rozycki <macro@linux-mips.org>
26
27 * opcode/mips.h: Update comment for MIPS32 CODE20 operand.
28
292019-04-15 Sudakshina Das <sudi.das@arm.com>
30
31 * elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF12.
32
332019-04-15 Sudakshina Das <sudi.das@arm.com>
34
35 * elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF18.
36
372019-04-15 Sudakshina Das <sudi.das@arm.com>
38
39 * elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF16.
40
412019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
42
43 * elf/arm.h (TAG_CPU_ARCH_V8_1M_MAIN): new macro.
44 (MAX_TAG_CPU_ARCH): Set value to above macro.
45 * opcode/arm.h (ARM_EXT2_V8_1M_MAIN): New macro.
46 (ARM_AEXT_V8_1M_MAIN): Likewise.
47 (ARM_AEXT2_V8_1M_MAIN): Likewise.
48 (ARM_ARCH_V8_1M_MAIN): Likewise.
49
502019-04-11 Sudakshina Das <sudi.das@arm.com>
51
52 * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_Rt_SP.
53
542019-04-08 H.J. Lu <hongjiu.lu@intel.com>
55
56 * elf/common.h (GNU_PROPERTY_X86_ISA_1_AVX512_BF16): New.
57
582019-04-07 Alan Modra <amodra@gmail.com>
59
60 Merge from gcc.
61 2019-04-03 Vineet Gupta <vgupta@synopsys.com>
62 PR89877
63 * longlong.h [__arc__] (add_ssaaaa): Add cc clobber.
64 (sub_ddmmss): Likewise.
65
662019-04-06 H.J. Lu <hongjiu.lu@intel.com>
67
68 * bfdlink.h (bfd_link_info): Remove x86-specific linker options.
69
702019-04-01 Andre Vieira <andre.simoesdiasvieira@arm.com>
71
72 * opcode/arm.h (FPU_NEON_ARMV8_1): New.
73 (FPU_ARCH_NEON_VFP_ARMV8_1): Use FPU_NEON_ARMV8_1.
74 (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1): Likewise.
75 (FPU_ARCH_DOTPROD_NEON_VFP_ARMV8): Likewise.
76 (FPU_ARCH_NEON_VFP_ARMV8_2_FP16): New.
77 (FPU_ARCH_NEON_VFP_ARMV8_2_FP16FML): New.
78 (FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML): New.
79 (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4): New.
80
812019-03-28 Alan Modra <amodra@gmail.com>
82
83 PR 24390
84 * opcode/ppc.h (PPC_OPERAND_CR_REG): Comment.
85
862019-03-25 Tamar Christina <tamar.christina@arm.com>
87
88 * dis-asm.h (struct disassemble_info): Add stop_offset.
89
902019-03-13 Sudakshina Das <sudi.das@arm.com>
91
92 * elf/aarch64.h (DT_AARCH64_PAC_PLT): New.
93
942019-03-13 Sudakshina Das <sudi.das@arm.com>
95 Szabolcs Nagy <szabolcs.nagy@arm.com>
96
97 * elf/aarch64.h (DT_AARCH64_BTI_PLT): New.
98
992019-03-13 Sudakshina Das <sudi.das@arm.com>
100
101 * elf/common.h (GNU_PROPERTY_AARCH64_FEATURE_1_AND): New.
102 (GNU_PROPERTY_AARCH64_FEATURE_1_BTI): New.
103 (GNU_PROPERTY_AARCH64_FEATURE_1_PAC): New.
104
1052019-02-20 Alan Hayward <alan.hayward@arm.com>
106
107 * elf/common.h (NT_ARM_PAC_MASK): Add define.
108
1092019-02-15 Saagar Jha <saagar@saagarjha.com>
110
111 * mach-o/loader.h: Use new OS names in comments.
112
1132019-02-11 Philippe Waroquiers <philippe.waroquiers@skynet.be>
114
115 * splay-tree.h (splay_tree_delete_key_fn): Update comment.
116 (splay_tree_delete_value_fn): Likewise.
117
1182019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
119
120 * opcode/s390.h (enum s390_opcode_cpu_val): Add
121 S390_OPCODE_ARCH13.
122
1232019-01-25 Sudakshina Das <sudi.das@arm.com>
124 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
125
126 * opcode/aarch64.h (enum aarch64_opnd): Remove
127 AARCH64_OPND_ADDR_SIMPLE_2.
128 (enum aarch64_insn_class): Remove ldstgv_indexed.
129
1302019-01-22 Tom Tromey <tom@tromey.com>
131
132 * coff/ecoff.h: Include coff/sym.h.
133
1342018-06-24 Nick Clifton <nickc@redhat.com>
135
136 2.32 branch created.
137
1382019-01-16 Kito Cheng <kito@andestech.com>
139
140 * elf/riscv.h (SHT_RISCV_ATTRIBUTES): Define.
141 (Tag_RISCV_arch): Likewise.
142 (Tag_RISCV_priv_spec): Likewise.
143 (Tag_RISCV_priv_spec_minor): Likewise.
144 (Tag_RISCV_priv_spec_revision): Likewise.
145 (Tag_RISCV_unaligned_access): Likewise.
146 (Tag_RISCV_stack_align): Likewise.
147
1482019-01-14 Pavel I. Kryukov <kryukov@frtk.ru>
149
150 * dis-asm.h: include <string.h>
151
1522019-01-10 Nick Clifton <nickc@redhat.com>
153
154 * Merge from GCC:
155 2018-12-22 Jason Merrill <jason@redhat.com>
156
157 * demangle.h: Remove support for ancient GNU (pre-3.0), Lucid,
158 ARM, HP, and EDG demangling styles.
159
1602019-01-09 Sandra Loosemore <sandra@codesourcery.com>
161
162 Merge from GCC:
163 PR other/16615
164
165 * libiberty.h: Mechanically replace "can not" with "cannot".
166 * plugin-api.h: Likewise.
167
1682018-12-25 Yoshinori Sato <ysato@users.sourceforge.jp>
169
170 * elf/rx.h (EF_RX_CPU_MASK): Update new bits.
171 (E_FLAG_RX_V3): New RXv3 type.
172 * opcode/rx.h (RX_Size): Add double size.
173 (RX_Operand_Type): Add double FPU registers.
174 (RX_Opcode_ID): Add new instuctions.
175
1762019-01-01 Alan Modra <amodra@gmail.com>
177
178 Update year range in copyright notice of all files.
179
180For older changes see ChangeLog-2018
181\f
182Copyright (C) 2019 Free Software Foundation, Inc.
183
184Copying and distribution of this file, with or without modification,
185are permitted in any medium without royalty provided the copyright
186notice and this notice are preserved.
187
188Local Variables:
189mode: change-log
190left-margin: 8
191fill-column: 74
192version-control: never
193End:
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