| 1 | /* alpha.h -- Header file for Alpha opcode table |
| 2 | Copyright (C) 1996-2020 Free Software Foundation, Inc. |
| 3 | Contributed by Richard Henderson <rth@tamu.edu>, |
| 4 | patterned after the PPC opcode table written by Ian Lance Taylor. |
| 5 | |
| 6 | This file is part of GDB, GAS, and the GNU binutils. |
| 7 | |
| 8 | GDB, GAS, and the GNU binutils are free software; you can redistribute |
| 9 | them and/or modify them under the terms of the GNU General Public |
| 10 | License as published by the Free Software Foundation; either version 3, |
| 11 | or (at your option) any later version. |
| 12 | |
| 13 | GDB, GAS, and the GNU binutils are distributed in the hope that they |
| 14 | will be useful, but WITHOUT ANY WARRANTY; without even the implied |
| 15 | warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See |
| 16 | the GNU General Public License for more details. |
| 17 | |
| 18 | You should have received a copy of the GNU General Public License |
| 19 | along with this file; see the file COPYING3. If not, write to the Free |
| 20 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, |
| 21 | MA 02110-1301, USA. */ |
| 22 | |
| 23 | #ifndef OPCODE_ALPHA_H |
| 24 | #define OPCODE_ALPHA_H |
| 25 | |
| 26 | /* The opcode table is an array of struct alpha_opcode. */ |
| 27 | |
| 28 | struct alpha_opcode |
| 29 | { |
| 30 | /* The opcode name. */ |
| 31 | const char *name; |
| 32 | |
| 33 | /* The opcode itself. Those bits which will be filled in with |
| 34 | operands are zeroes. */ |
| 35 | unsigned opcode; |
| 36 | |
| 37 | /* The opcode mask. This is used by the disassembler. This is a |
| 38 | mask containing ones indicating those bits which must match the |
| 39 | opcode field, and zeroes indicating those bits which need not |
| 40 | match (and are presumably filled in by operands). */ |
| 41 | unsigned mask; |
| 42 | |
| 43 | /* One bit flags for the opcode. These are primarily used to |
| 44 | indicate specific processors and environments support the |
| 45 | instructions. The defined values are listed below. */ |
| 46 | unsigned flags; |
| 47 | |
| 48 | /* An array of operand codes. Each code is an index into the |
| 49 | operand table. They appear in the order which the operands must |
| 50 | appear in assembly code, and are terminated by a zero. */ |
| 51 | unsigned char operands[4]; |
| 52 | }; |
| 53 | |
| 54 | /* The table itself is sorted by major opcode number, and is otherwise |
| 55 | in the order in which the disassembler should consider |
| 56 | instructions. */ |
| 57 | extern const struct alpha_opcode alpha_opcodes[]; |
| 58 | extern const unsigned alpha_num_opcodes; |
| 59 | |
| 60 | /* Values defined for the flags field of a struct alpha_opcode. */ |
| 61 | |
| 62 | /* CPU Availability */ |
| 63 | #define AXP_OPCODE_BASE 0x0001 /* Base architecture -- all cpus. */ |
| 64 | #define AXP_OPCODE_EV4 0x0002 /* EV4 specific PALcode insns. */ |
| 65 | #define AXP_OPCODE_EV5 0x0004 /* EV5 specific PALcode insns. */ |
| 66 | #define AXP_OPCODE_EV6 0x0008 /* EV6 specific PALcode insns. */ |
| 67 | #define AXP_OPCODE_BWX 0x0100 /* Byte/word extension (amask bit 0). */ |
| 68 | #define AXP_OPCODE_CIX 0x0200 /* "Count" extension (amask bit 1). */ |
| 69 | #define AXP_OPCODE_MAX 0x0400 /* Multimedia extension (amask bit 8). */ |
| 70 | |
| 71 | #define AXP_OPCODE_NOPAL (~(AXP_OPCODE_EV4|AXP_OPCODE_EV5|AXP_OPCODE_EV6)) |
| 72 | |
| 73 | /* A macro to extract the major opcode from an instruction. */ |
| 74 | #define AXP_OP(i) (((i) >> 26) & 0x3F) |
| 75 | |
| 76 | /* The total number of major opcodes. */ |
| 77 | #define AXP_NOPS 0x40 |
| 78 | |
| 79 | \f |
| 80 | /* The operands table is an array of struct alpha_operand. */ |
| 81 | |
| 82 | struct alpha_operand |
| 83 | { |
| 84 | /* The number of bits in the operand. */ |
| 85 | unsigned int bits : 5; |
| 86 | |
| 87 | /* How far the operand is left shifted in the instruction. */ |
| 88 | unsigned int shift : 5; |
| 89 | |
| 90 | /* The default relocation type for this operand. */ |
| 91 | signed int default_reloc : 16; |
| 92 | |
| 93 | /* One bit syntax flags. */ |
| 94 | unsigned int flags : 16; |
| 95 | |
| 96 | /* Insertion function. This is used by the assembler. To insert an |
| 97 | operand value into an instruction, check this field. |
| 98 | |
| 99 | If it is NULL, execute |
| 100 | i |= (op & ((1 << o->bits) - 1)) << o->shift; |
| 101 | (i is the instruction which we are filling in, o is a pointer to |
| 102 | this structure, and op is the opcode value; this assumes twos |
| 103 | complement arithmetic). |
| 104 | |
| 105 | If this field is not NULL, then simply call it with the |
| 106 | instruction and the operand value. It will return the new value |
| 107 | of the instruction. If the ERRMSG argument is not NULL, then if |
| 108 | the operand value is illegal, *ERRMSG will be set to a warning |
| 109 | string (the operand will be inserted in any case). If the |
| 110 | operand value is legal, *ERRMSG will be unchanged (most operands |
| 111 | can accept any value). */ |
| 112 | unsigned (*insert) (unsigned instruction, int op, const char **errmsg); |
| 113 | |
| 114 | /* Extraction function. This is used by the disassembler. To |
| 115 | extract this operand type from an instruction, check this field. |
| 116 | |
| 117 | If it is NULL, compute |
| 118 | op = ((i) >> o->shift) & ((1 << o->bits) - 1); |
| 119 | if ((o->flags & AXP_OPERAND_SIGNED) != 0 |
| 120 | && (op & (1 << (o->bits - 1))) != 0) |
| 121 | op -= 1 << o->bits; |
| 122 | (i is the instruction, o is a pointer to this structure, and op |
| 123 | is the result; this assumes twos complement arithmetic). |
| 124 | |
| 125 | If this field is not NULL, then simply call it with the |
| 126 | instruction value. It will return the value of the operand. If |
| 127 | the INVALID argument is not NULL, *INVALID will be set to |
| 128 | non-zero if this operand type can not actually be extracted from |
| 129 | this operand (i.e., the instruction does not match). If the |
| 130 | operand is valid, *INVALID will not be changed. */ |
| 131 | int (*extract) (unsigned instruction, int *invalid); |
| 132 | }; |
| 133 | |
| 134 | /* Elements in the table are retrieved by indexing with values from |
| 135 | the operands field of the alpha_opcodes table. */ |
| 136 | |
| 137 | extern const struct alpha_operand alpha_operands[]; |
| 138 | extern const unsigned alpha_num_operands; |
| 139 | |
| 140 | /* Values defined for the flags field of a struct alpha_operand. */ |
| 141 | |
| 142 | /* Mask for selecting the type for typecheck purposes */ |
| 143 | #define AXP_OPERAND_TYPECHECK_MASK \ |
| 144 | (AXP_OPERAND_PARENS | AXP_OPERAND_COMMA | AXP_OPERAND_IR | \ |
| 145 | AXP_OPERAND_FPR | AXP_OPERAND_RELATIVE | AXP_OPERAND_SIGNED | \ |
| 146 | AXP_OPERAND_UNSIGNED) |
| 147 | |
| 148 | /* This operand does not actually exist in the assembler input. This |
| 149 | is used to support extended mnemonics, for which two operands fields |
| 150 | are identical. The assembler should call the insert function with |
| 151 | any op value. The disassembler should call the extract function, |
| 152 | ignore the return value, and check the value placed in the invalid |
| 153 | argument. */ |
| 154 | #define AXP_OPERAND_FAKE 01 |
| 155 | |
| 156 | /* The operand should be wrapped in parentheses rather than separated |
| 157 | from the previous by a comma. This is used for the load and store |
| 158 | instructions which want their operands to look like "Ra,disp(Rb)". */ |
| 159 | #define AXP_OPERAND_PARENS 02 |
| 160 | |
| 161 | /* Used in combination with PARENS, this supresses the supression of |
| 162 | the comma. This is used for "jmp Ra,(Rb),hint". */ |
| 163 | #define AXP_OPERAND_COMMA 04 |
| 164 | |
| 165 | /* This operand names an integer register. */ |
| 166 | #define AXP_OPERAND_IR 010 |
| 167 | |
| 168 | /* This operand names a floating point register. */ |
| 169 | #define AXP_OPERAND_FPR 020 |
| 170 | |
| 171 | /* This operand is a relative branch displacement. The disassembler |
| 172 | prints these symbolically if possible. */ |
| 173 | #define AXP_OPERAND_RELATIVE 040 |
| 174 | |
| 175 | /* This operand takes signed values. */ |
| 176 | #define AXP_OPERAND_SIGNED 0100 |
| 177 | |
| 178 | /* This operand takes unsigned values. This exists primarily so that |
| 179 | a flags value of 0 can be treated as end-of-arguments. */ |
| 180 | #define AXP_OPERAND_UNSIGNED 0200 |
| 181 | |
| 182 | /* Supress overflow detection on this field. This is used for hints. */ |
| 183 | #define AXP_OPERAND_NOOVERFLOW 0400 |
| 184 | |
| 185 | /* Mask for optional argument default value. */ |
| 186 | #define AXP_OPERAND_OPTIONAL_MASK 07000 |
| 187 | |
| 188 | /* This operand defaults to zero. This is used for jump hints. */ |
| 189 | #define AXP_OPERAND_DEFAULT_ZERO 01000 |
| 190 | |
| 191 | /* This operand should default to the first (real) operand and is used |
| 192 | in conjunction with AXP_OPERAND_OPTIONAL. This allows |
| 193 | "and $0,3,$0" to be written as "and $0,3", etc. I don't like |
| 194 | it, but it's what DEC does. */ |
| 195 | #define AXP_OPERAND_DEFAULT_FIRST 02000 |
| 196 | |
| 197 | /* Similarly, this operand should default to the second (real) operand. |
| 198 | This allows "negl $0" instead of "negl $0,$0". */ |
| 199 | #define AXP_OPERAND_DEFAULT_SECOND 04000 |
| 200 | |
| 201 | \f |
| 202 | /* Register common names */ |
| 203 | |
| 204 | #define AXP_REG_V0 0 |
| 205 | #define AXP_REG_T0 1 |
| 206 | #define AXP_REG_T1 2 |
| 207 | #define AXP_REG_T2 3 |
| 208 | #define AXP_REG_T3 4 |
| 209 | #define AXP_REG_T4 5 |
| 210 | #define AXP_REG_T5 6 |
| 211 | #define AXP_REG_T6 7 |
| 212 | #define AXP_REG_T7 8 |
| 213 | #define AXP_REG_S0 9 |
| 214 | #define AXP_REG_S1 10 |
| 215 | #define AXP_REG_S2 11 |
| 216 | #define AXP_REG_S3 12 |
| 217 | #define AXP_REG_S4 13 |
| 218 | #define AXP_REG_S5 14 |
| 219 | #define AXP_REG_FP 15 |
| 220 | #define AXP_REG_A0 16 |
| 221 | #define AXP_REG_A1 17 |
| 222 | #define AXP_REG_A2 18 |
| 223 | #define AXP_REG_A3 19 |
| 224 | #define AXP_REG_A4 20 |
| 225 | #define AXP_REG_A5 21 |
| 226 | #define AXP_REG_T8 22 |
| 227 | #define AXP_REG_T9 23 |
| 228 | #define AXP_REG_T10 24 |
| 229 | #define AXP_REG_T11 25 |
| 230 | #define AXP_REG_RA 26 |
| 231 | #define AXP_REG_PV 27 |
| 232 | #define AXP_REG_T12 27 |
| 233 | #define AXP_REG_AT 28 |
| 234 | #define AXP_REG_GP 29 |
| 235 | #define AXP_REG_SP 30 |
| 236 | #define AXP_REG_ZERO 31 |
| 237 | |
| 238 | #endif /* OPCODE_ALPHA_H */ |