| 1 | /* ppc.h -- Header file for PowerPC opcode table |
| 2 | Copyright (C) 1994-2020 Free Software Foundation, Inc. |
| 3 | Written by Ian Lance Taylor, Cygnus Support |
| 4 | |
| 5 | This file is part of GDB, GAS, and the GNU binutils. |
| 6 | |
| 7 | GDB, GAS, and the GNU binutils are free software; you can redistribute |
| 8 | them and/or modify them under the terms of the GNU General Public |
| 9 | License as published by the Free Software Foundation; either version 3, |
| 10 | or (at your option) any later version. |
| 11 | |
| 12 | GDB, GAS, and the GNU binutils are distributed in the hope that they |
| 13 | will be useful, but WITHOUT ANY WARRANTY; without even the implied |
| 14 | warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See |
| 15 | the GNU General Public License for more details. |
| 16 | |
| 17 | You should have received a copy of the GNU General Public License |
| 18 | along with this file; see the file COPYING3. If not, write to the Free |
| 19 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, |
| 20 | MA 02110-1301, USA. */ |
| 21 | |
| 22 | #ifndef PPC_H |
| 23 | #define PPC_H |
| 24 | |
| 25 | #include "bfd_stdint.h" |
| 26 | |
| 27 | #ifdef __cplusplus |
| 28 | extern "C" { |
| 29 | #endif |
| 30 | |
| 31 | typedef uint64_t ppc_cpu_t; |
| 32 | |
| 33 | /* The opcode table is an array of struct powerpc_opcode. */ |
| 34 | |
| 35 | struct powerpc_opcode |
| 36 | { |
| 37 | /* The opcode name. */ |
| 38 | const char *name; |
| 39 | |
| 40 | /* The opcode itself. Those bits which will be filled in with |
| 41 | operands are zeroes. */ |
| 42 | uint64_t opcode; |
| 43 | |
| 44 | /* The opcode mask. This is used by the disassembler. This is a |
| 45 | mask containing ones indicating those bits which must match the |
| 46 | opcode field, and zeroes indicating those bits which need not |
| 47 | match (and are presumably filled in by operands). */ |
| 48 | uint64_t mask; |
| 49 | |
| 50 | /* One bit flags for the opcode. These are used to indicate which |
| 51 | specific processors support the instructions. The defined values |
| 52 | are listed below. */ |
| 53 | ppc_cpu_t flags; |
| 54 | |
| 55 | /* One bit flags for the opcode. These are used to indicate which |
| 56 | specific processors no longer support the instructions. The defined |
| 57 | values are listed below. */ |
| 58 | ppc_cpu_t deprecated; |
| 59 | |
| 60 | /* An array of operand codes. Each code is an index into the |
| 61 | operand table. They appear in the order which the operands must |
| 62 | appear in assembly code, and are terminated by a zero. */ |
| 63 | unsigned char operands[8]; |
| 64 | }; |
| 65 | |
| 66 | /* The table itself is sorted by major opcode number, and is otherwise |
| 67 | in the order in which the disassembler should consider |
| 68 | instructions. */ |
| 69 | extern const struct powerpc_opcode powerpc_opcodes[]; |
| 70 | extern const unsigned int powerpc_num_opcodes; |
| 71 | extern const struct powerpc_opcode prefix_opcodes[]; |
| 72 | extern const unsigned int prefix_num_opcodes; |
| 73 | extern const struct powerpc_opcode vle_opcodes[]; |
| 74 | extern const unsigned int vle_num_opcodes; |
| 75 | extern const struct powerpc_opcode spe2_opcodes[]; |
| 76 | extern const unsigned int spe2_num_opcodes; |
| 77 | |
| 78 | /* Values defined for the flags field of a struct powerpc_opcode. */ |
| 79 | |
| 80 | /* Opcode is defined for the PowerPC architecture. */ |
| 81 | #define PPC_OPCODE_PPC 0x1ull |
| 82 | |
| 83 | /* Opcode is defined for the POWER (RS/6000) architecture. */ |
| 84 | #define PPC_OPCODE_POWER 0x2ull |
| 85 | |
| 86 | /* Opcode is defined for the POWER2 (Rios 2) architecture. */ |
| 87 | #define PPC_OPCODE_POWER2 0x4ull |
| 88 | |
| 89 | /* Opcode is only defined on 64 bit architectures. */ |
| 90 | #define PPC_OPCODE_64 0x8ull |
| 91 | |
| 92 | /* Opcode is supported by the Motorola PowerPC 601 processor. The 601 |
| 93 | is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions, |
| 94 | but it also supports many additional POWER instructions. */ |
| 95 | #define PPC_OPCODE_601 0x10ull |
| 96 | |
| 97 | /* Opcode is supported in both the Power and PowerPC architectures |
| 98 | (ie, compiler's -mcpu=common or assembler's -mcom). More than just |
| 99 | the intersection of PPC_OPCODE_PPC with the union of PPC_OPCODE_POWER |
| 100 | and PPC_OPCODE_POWER2 because many instructions changed mnemonics |
| 101 | between POWER and POWERPC. */ |
| 102 | #define PPC_OPCODE_COMMON 0x20ull |
| 103 | |
| 104 | /* Opcode is supported for any Power or PowerPC platform (this is |
| 105 | for the assembler's -many option, and it eliminates duplicates). */ |
| 106 | #define PPC_OPCODE_ANY 0x40ull |
| 107 | |
| 108 | /* Opcode is supported as part of the 64-bit bridge. */ |
| 109 | #define PPC_OPCODE_64_BRIDGE 0x80ull |
| 110 | |
| 111 | /* Opcode is supported by Altivec Vector Unit */ |
| 112 | #define PPC_OPCODE_ALTIVEC 0x100ull |
| 113 | |
| 114 | /* Opcode is supported by PowerPC 403 processor. */ |
| 115 | #define PPC_OPCODE_403 0x200ull |
| 116 | |
| 117 | /* Opcode is supported by PowerPC BookE processor. */ |
| 118 | #define PPC_OPCODE_BOOKE 0x400ull |
| 119 | |
| 120 | /* Opcode is only supported by Power4 architecture. */ |
| 121 | #define PPC_OPCODE_POWER4 0x800ull |
| 122 | |
| 123 | /* Opcode is only supported by e500x2 Core. |
| 124 | This bit, PPC_OPCODE_EFS, PPC_OPCODE_VLE, and all those with APU in |
| 125 | their comment mark opcodes so that when those instructions are used |
| 126 | an APUinfo entry can be generated. */ |
| 127 | #define PPC_OPCODE_SPE 0x1000ull |
| 128 | |
| 129 | /* Opcode is supported by Integer select APU. */ |
| 130 | #define PPC_OPCODE_ISEL 0x2000ull |
| 131 | |
| 132 | /* Opcode is an e500 SPE floating point instruction. */ |
| 133 | #define PPC_OPCODE_EFS 0x4000ull |
| 134 | |
| 135 | /* Opcode is supported by branch locking APU. */ |
| 136 | #define PPC_OPCODE_BRLOCK 0x8000ull |
| 137 | |
| 138 | /* Opcode is supported by performance monitor APU. */ |
| 139 | #define PPC_OPCODE_PMR 0x10000ull |
| 140 | |
| 141 | /* Opcode is supported by cache locking APU. */ |
| 142 | #define PPC_OPCODE_CACHELCK 0x20000ull |
| 143 | |
| 144 | /* Opcode is supported by machine check APU. */ |
| 145 | #define PPC_OPCODE_RFMCI 0x40000ull |
| 146 | |
| 147 | /* Opcode is supported by PowerPC 440 processor. */ |
| 148 | #define PPC_OPCODE_440 0x80000ull |
| 149 | |
| 150 | /* Opcode is only supported by Power5 architecture. */ |
| 151 | #define PPC_OPCODE_POWER5 0x100000ull |
| 152 | |
| 153 | /* Opcode is supported by PowerPC e300 family. */ |
| 154 | #define PPC_OPCODE_E300 0x200000ull |
| 155 | |
| 156 | /* Opcode is only supported by Power6 architecture. */ |
| 157 | #define PPC_OPCODE_POWER6 0x400000ull |
| 158 | |
| 159 | /* Opcode is only supported by PowerPC Cell family. */ |
| 160 | #define PPC_OPCODE_CELL 0x800000ull |
| 161 | |
| 162 | /* Opcode is supported by CPUs with paired singles support. */ |
| 163 | #define PPC_OPCODE_PPCPS 0x1000000ull |
| 164 | |
| 165 | /* Opcode is supported by Power E500MC */ |
| 166 | #define PPC_OPCODE_E500MC 0x2000000ull |
| 167 | |
| 168 | /* Opcode is supported by PowerPC 405 processor. */ |
| 169 | #define PPC_OPCODE_405 0x4000000ull |
| 170 | |
| 171 | /* Opcode is supported by Vector-Scalar (VSX) Unit */ |
| 172 | #define PPC_OPCODE_VSX 0x8000000ull |
| 173 | |
| 174 | /* Opcode is only supported by Power7 architecture. */ |
| 175 | #define PPC_OPCODE_POWER7 0x10000000ull |
| 176 | |
| 177 | /* Opcode is supported by A2. */ |
| 178 | #define PPC_OPCODE_A2 0x20000000ull |
| 179 | |
| 180 | /* Opcode is supported by PowerPC 476 processor. */ |
| 181 | #define PPC_OPCODE_476 0x40000000ull |
| 182 | |
| 183 | /* Opcode is supported by AppliedMicro Titan core */ |
| 184 | #define PPC_OPCODE_TITAN 0x80000000ull |
| 185 | |
| 186 | /* Opcode which is supported by the e500 family */ |
| 187 | #define PPC_OPCODE_E500 0x100000000ull |
| 188 | |
| 189 | /* Opcode is supported by Power E6500 */ |
| 190 | #define PPC_OPCODE_E6500 0x200000000ull |
| 191 | |
| 192 | /* Opcode is supported by Thread management APU */ |
| 193 | #define PPC_OPCODE_TMR 0x400000000ull |
| 194 | |
| 195 | /* Opcode which is supported by the VLE extension. */ |
| 196 | #define PPC_OPCODE_VLE 0x800000000ull |
| 197 | |
| 198 | /* Opcode is only supported by Power8 architecture. */ |
| 199 | #define PPC_OPCODE_POWER8 0x1000000000ull |
| 200 | |
| 201 | /* Opcode is supported by ppc750cl/Gekko/Broadway. */ |
| 202 | #define PPC_OPCODE_750 0x2000000000ull |
| 203 | |
| 204 | /* Opcode is supported by ppc7450. */ |
| 205 | #define PPC_OPCODE_7450 0x4000000000ull |
| 206 | |
| 207 | /* Opcode is supported by ppc821/850/860. */ |
| 208 | #define PPC_OPCODE_860 0x8000000000ull |
| 209 | |
| 210 | /* Opcode is only supported by Power9 architecture. */ |
| 211 | #define PPC_OPCODE_POWER9 0x10000000000ull |
| 212 | |
| 213 | /* Opcode is supported by e200z4. */ |
| 214 | #define PPC_OPCODE_E200Z4 0x20000000000ull |
| 215 | |
| 216 | /* Disassemble to instructions matching later in the opcode table |
| 217 | with fewer "mask" bits set rather than the earlist match. Fewer |
| 218 | "mask" bits set imply a more general form of the opcode, in fact |
| 219 | the underlying machine instruction. */ |
| 220 | #define PPC_OPCODE_RAW 0x40000000000ull |
| 221 | |
| 222 | /* Opcode is supported by PowerPC LSP */ |
| 223 | #define PPC_OPCODE_LSP 0x80000000000ull |
| 224 | |
| 225 | /* Opcode is only supported by Freescale SPE2 APU. */ |
| 226 | #define PPC_OPCODE_SPE2 0x100000000000ull |
| 227 | |
| 228 | /* Opcode is supported by EFS2. */ |
| 229 | #define PPC_OPCODE_EFS2 0x200000000000ull |
| 230 | |
| 231 | /* Opcode is only supported by power10 architecture. */ |
| 232 | #define PPC_OPCODE_POWER10 0x400000000000ull |
| 233 | |
| 234 | /* A macro to extract the major opcode from an instruction. */ |
| 235 | #define PPC_OP(i) (((i) >> 26) & 0x3f) |
| 236 | |
| 237 | /* A macro to determine if the instruction is a 2-byte VLE insn. */ |
| 238 | #define PPC_OP_SE_VLE(m) ((m) <= 0xffff) |
| 239 | |
| 240 | /* A macro to extract the major opcode from a VLE instruction. */ |
| 241 | #define VLE_OP(i,m) (((i) >> ((m) <= 0xffff ? 10 : 26)) & 0x3f) |
| 242 | |
| 243 | /* A macro to convert a VLE opcode to a VLE opcode segment. */ |
| 244 | #define VLE_OP_TO_SEG(i) ((i) >> 1) |
| 245 | |
| 246 | /* A macro to extract the extended opcode from a SPE2 instruction. */ |
| 247 | #define SPE2_XOP(i) ((i) & 0x7ff) |
| 248 | |
| 249 | /* A macro to convert a SPE2 extended opcode to a SPE2 xopcode segment. */ |
| 250 | #define SPE2_XOP_TO_SEG(i) ((i) >> 7) |
| 251 | |
| 252 | /* A macro to extract the prefix word from an 8-byte PREFIX instruction. */ |
| 253 | #define PPC_GET_PREFIX(i) (((i) >> 32) & ((1LL << 32) - 1)) |
| 254 | |
| 255 | /* A macro to extract the suffix word from an 8-byte PREFIX instruction. */ |
| 256 | #define PPC_GET_SUFFIX(i) ((i) & ((1LL << 32) - 1)) |
| 257 | |
| 258 | /* A macro to determine whether insn I is an 8-byte prefix instruction. */ |
| 259 | #define PPC_PREFIX_P(i) (PPC_OP (PPC_GET_PREFIX (i)) == 0x1) |
| 260 | |
| 261 | /* A macro used to hash 8-byte PREFIX instructions. */ |
| 262 | #define PPC_PREFIX_SEG(i) (PPC_OP (i) >> 1) |
| 263 | |
| 264 | \f |
| 265 | /* The operands table is an array of struct powerpc_operand. */ |
| 266 | |
| 267 | struct powerpc_operand |
| 268 | { |
| 269 | /* A bitmask of bits in the operand. */ |
| 270 | uint64_t bitm; |
| 271 | |
| 272 | /* The shift operation to be applied to the operand. No shift |
| 273 | is made if this is zero. For positive values, the operand |
| 274 | is shifted left by SHIFT. For negative values, the operand |
| 275 | is shifted right by -SHIFT. Use PPC_OPSHIFT_INV to indicate |
| 276 | that BITM and SHIFT cannot be used to determine where the |
| 277 | operand goes in the insn. */ |
| 278 | int shift; |
| 279 | |
| 280 | /* Insertion function. This is used by the assembler. To insert an |
| 281 | operand value into an instruction, check this field. |
| 282 | |
| 283 | If it is NULL, execute |
| 284 | if (o->shift >= 0) |
| 285 | i |= (op & o->bitm) << o->shift; |
| 286 | else |
| 287 | i |= (op & o->bitm) >> -o->shift; |
| 288 | (i is the instruction which we are filling in, o is a pointer to |
| 289 | this structure, and op is the operand value). |
| 290 | |
| 291 | If this field is not NULL, then simply call it with the |
| 292 | instruction and the operand value. It will return the new value |
| 293 | of the instruction. If the operand value is illegal, *ERRMSG |
| 294 | will be set to a warning string (the operand will be inserted in |
| 295 | any case). If the operand value is legal, *ERRMSG will be |
| 296 | unchanged (most operands can accept any value). */ |
| 297 | uint64_t (*insert) |
| 298 | (uint64_t instruction, int64_t op, ppc_cpu_t dialect, const char **errmsg); |
| 299 | |
| 300 | /* Extraction function. This is used by the disassembler. To |
| 301 | extract this operand type from an instruction, check this field. |
| 302 | |
| 303 | If it is NULL, compute |
| 304 | if (o->shift >= 0) |
| 305 | op = (i >> o->shift) & o->bitm; |
| 306 | else |
| 307 | op = (i << -o->shift) & o->bitm; |
| 308 | if ((o->flags & PPC_OPERAND_SIGNED) != 0) |
| 309 | sign_extend (op); |
| 310 | (i is the instruction, o is a pointer to this structure, and op |
| 311 | is the result). |
| 312 | |
| 313 | If this field is not NULL, then simply call it with the |
| 314 | instruction value. It will return the value of the operand. |
| 315 | *INVALID will be set to one by the extraction function if this |
| 316 | operand type can not be extracted from this operand (i.e., the |
| 317 | instruction does not match). If the operand is valid, *INVALID |
| 318 | will not be changed. *INVALID will always be non-negative when |
| 319 | used to extract a field from an instruction. |
| 320 | |
| 321 | The extraction function is also called by both the assembler and |
| 322 | disassembler if an operand is optional, in which case the |
| 323 | function should return the default value of the operand. |
| 324 | *INVALID is negative in this case, and is the negative count of |
| 325 | omitted optional operands up to and including this operand. */ |
| 326 | int64_t (*extract) (uint64_t instruction, ppc_cpu_t dialect, int *invalid); |
| 327 | |
| 328 | /* One bit syntax flags. */ |
| 329 | unsigned long flags; |
| 330 | }; |
| 331 | |
| 332 | /* Elements in the table are retrieved by indexing with values from |
| 333 | the operands field of the powerpc_opcodes table. */ |
| 334 | |
| 335 | extern const struct powerpc_operand powerpc_operands[]; |
| 336 | extern const unsigned int num_powerpc_operands; |
| 337 | |
| 338 | /* Use with the shift field of a struct powerpc_operand to indicate |
| 339 | that BITM and SHIFT cannot be used to determine where the operand |
| 340 | goes in the insn. */ |
| 341 | #define PPC_OPSHIFT_INV (-1U << 31) |
| 342 | |
| 343 | /* Values defined for the flags field of a struct powerpc_operand. |
| 344 | Keep the register bits low: They need to fit in an unsigned short. */ |
| 345 | |
| 346 | /* This operand names a register. The disassembler uses this to print |
| 347 | register names with a leading 'r'. */ |
| 348 | #define PPC_OPERAND_GPR (0x1) |
| 349 | |
| 350 | /* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0. */ |
| 351 | #define PPC_OPERAND_GPR_0 (0x2) |
| 352 | |
| 353 | /* This operand names a floating point register. The disassembler |
| 354 | prints these with a leading 'f'. */ |
| 355 | #define PPC_OPERAND_FPR (0x4) |
| 356 | |
| 357 | /* This operand names a vector unit register. The disassembler |
| 358 | prints these with a leading 'v'. */ |
| 359 | #define PPC_OPERAND_VR (0x8) |
| 360 | |
| 361 | /* This operand names a vector-scalar unit register. The disassembler |
| 362 | prints these with a leading 'vs'. */ |
| 363 | #define PPC_OPERAND_VSR (0x10) |
| 364 | |
| 365 | /* This operand may use the symbolic names for the CR fields (even |
| 366 | without -mregnames), which are |
| 367 | lt 0 gt 1 eq 2 so 3 un 3 |
| 368 | cr0 0 cr1 1 cr2 2 cr3 3 |
| 369 | cr4 4 cr5 5 cr6 6 cr7 7 |
| 370 | These may be combined arithmetically, as in cr2*4+gt. These are |
| 371 | only supported on the PowerPC, not the POWER. */ |
| 372 | #define PPC_OPERAND_CR_BIT (0x20) |
| 373 | |
| 374 | /* This is a CR FIELD that does not use symbolic names (unless |
| 375 | -mregnames is in effect). If both PPC_OPERAND_CR_BIT and |
| 376 | PPC_OPERAND_CR_REG are set then treat the field as per |
| 377 | PPC_OPERAND_CR_BIT for assembly, but as if neither of these |
| 378 | bits are set for disassembly. */ |
| 379 | #define PPC_OPERAND_CR_REG (0x40) |
| 380 | |
| 381 | /* This operand names a special purpose register. */ |
| 382 | #define PPC_OPERAND_SPR (0x80) |
| 383 | |
| 384 | /* This operand names a paired-single graphics quantization register. */ |
| 385 | #define PPC_OPERAND_GQR (0x100) |
| 386 | |
| 387 | /* This operand is a relative branch displacement. The disassembler |
| 388 | prints these symbolically if possible. */ |
| 389 | #define PPC_OPERAND_RELATIVE (0x200) |
| 390 | |
| 391 | /* This operand is an absolute branch address. The disassembler |
| 392 | prints these symbolically if possible. */ |
| 393 | #define PPC_OPERAND_ABSOLUTE (0x400) |
| 394 | |
| 395 | /* This operand takes signed values. */ |
| 396 | #define PPC_OPERAND_SIGNED (0x800) |
| 397 | |
| 398 | /* This operand takes signed values, but also accepts a full positive |
| 399 | range of values when running in 32 bit mode. That is, if bits is |
| 400 | 16, it takes any value from -0x8000 to 0xffff. In 64 bit mode, |
| 401 | this flag is ignored. */ |
| 402 | #define PPC_OPERAND_SIGNOPT (0x1000) |
| 403 | |
| 404 | /* The next operand should be wrapped in parentheses rather than |
| 405 | separated from this one by a comma. This is used for the load and |
| 406 | store instructions which want their operands to look like |
| 407 | reg,displacement(reg) |
| 408 | */ |
| 409 | #define PPC_OPERAND_PARENS (0x2000) |
| 410 | |
| 411 | /* This operand is for the DS field in a DS form instruction. */ |
| 412 | #define PPC_OPERAND_DS (0x4000) |
| 413 | |
| 414 | /* This operand is for the DQ field in a DQ form instruction. */ |
| 415 | #define PPC_OPERAND_DQ (0x8000) |
| 416 | |
| 417 | /* This operand should be regarded as a negative number for the |
| 418 | purposes of overflow checking (i.e., the normal most negative |
| 419 | number is disallowed and one more than the normal most positive |
| 420 | number is allowed). This flag will only be set for a signed |
| 421 | operand. */ |
| 422 | #define PPC_OPERAND_NEGATIVE (0x10000) |
| 423 | |
| 424 | /* Valid range of operand is 0..n rather than 0..n-1. */ |
| 425 | #define PPC_OPERAND_PLUS1 (0x20000) |
| 426 | |
| 427 | /* This operand is optional, and is zero if omitted. This is used for |
| 428 | example, in the optional BF field in the comparison instructions. The |
| 429 | assembler must count the number of operands remaining on the line, |
| 430 | and the number of operands remaining for the opcode, and decide |
| 431 | whether this operand is present or not. The disassembler should |
| 432 | print this operand out only if it is not zero. */ |
| 433 | #define PPC_OPERAND_OPTIONAL (0x80000) |
| 434 | |
| 435 | /* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand |
| 436 | is omitted, then for the next operand use this operand value plus |
| 437 | 1, ignoring the next operand field for the opcode. This wretched |
| 438 | hack is needed because the Power rotate instructions can take |
| 439 | either 4 or 5 operands. The disassembler should print this operand |
| 440 | out regardless of the PPC_OPERAND_OPTIONAL field. */ |
| 441 | #define PPC_OPERAND_NEXT (0x100000) |
| 442 | |
| 443 | /* This flag is only used with PPC_OPERAND_OPTIONAL. The operand is |
| 444 | only optional when generating 32-bit code. */ |
| 445 | #define PPC_OPERAND_OPTIONAL32 (0x400000) |
| 446 | |
| 447 | /* Xilinx APU and FSL related operands */ |
| 448 | #define PPC_OPERAND_FSL (0x800000) |
| 449 | #define PPC_OPERAND_FCR (0x1000000) |
| 450 | #define PPC_OPERAND_UDI (0x2000000) |
| 451 | \f |
| 452 | /* The POWER and PowerPC assemblers use a few macros. We keep them |
| 453 | with the operands table for simplicity. The macro table is an |
| 454 | array of struct powerpc_macro. */ |
| 455 | |
| 456 | struct powerpc_macro |
| 457 | { |
| 458 | /* The macro name. */ |
| 459 | const char *name; |
| 460 | |
| 461 | /* The number of operands the macro takes. */ |
| 462 | unsigned int operands; |
| 463 | |
| 464 | /* One bit flags for the opcode. These are used to indicate which |
| 465 | specific processors support the instructions. The values are the |
| 466 | same as those for the struct powerpc_opcode flags field. */ |
| 467 | ppc_cpu_t flags; |
| 468 | |
| 469 | /* A format string to turn the macro into a normal instruction. |
| 470 | Each %N in the string is replaced with operand number N (zero |
| 471 | based). */ |
| 472 | const char *format; |
| 473 | }; |
| 474 | |
| 475 | extern const struct powerpc_macro powerpc_macros[]; |
| 476 | extern const int powerpc_num_macros; |
| 477 | |
| 478 | extern ppc_cpu_t ppc_parse_cpu (ppc_cpu_t, ppc_cpu_t *, const char *); |
| 479 | |
| 480 | static inline int64_t |
| 481 | ppc_optional_operand_value (const struct powerpc_operand *operand, |
| 482 | uint64_t insn, |
| 483 | ppc_cpu_t dialect, |
| 484 | int num_optional) |
| 485 | { |
| 486 | if (operand->extract) |
| 487 | return (*operand->extract) (insn, dialect, &num_optional); |
| 488 | return 0; |
| 489 | } |
| 490 | |
| 491 | /* PowerPC VLE insns. */ |
| 492 | #define E_OPCODE_MASK 0xfc00f800 |
| 493 | |
| 494 | /* Form I16L, uses 16A relocs. */ |
| 495 | #define E_OR2I_INSN 0x7000C000 |
| 496 | #define E_AND2I_DOT_INSN 0x7000C800 |
| 497 | #define E_OR2IS_INSN 0x7000D000 |
| 498 | #define E_LIS_INSN 0x7000E000 |
| 499 | #define E_AND2IS_DOT_INSN 0x7000E800 |
| 500 | |
| 501 | /* Form I16A, uses 16D relocs. */ |
| 502 | #define E_ADD2I_DOT_INSN 0x70008800 |
| 503 | #define E_ADD2IS_INSN 0x70009000 |
| 504 | #define E_CMP16I_INSN 0x70009800 |
| 505 | #define E_MULL2I_INSN 0x7000A000 |
| 506 | #define E_CMPL16I_INSN 0x7000A800 |
| 507 | #define E_CMPH16I_INSN 0x7000B000 |
| 508 | #define E_CMPHL16I_INSN 0x7000B800 |
| 509 | |
| 510 | #define E_LI_INSN 0x70000000 |
| 511 | #define E_LI_MASK 0xfc008000 |
| 512 | |
| 513 | #ifdef __cplusplus |
| 514 | } |
| 515 | #endif |
| 516 | |
| 517 | #endif /* PPC_H */ |