| 1 | #ifndef S12Z_H |
| 2 | #define S12Z_H |
| 3 | |
| 4 | /* This byte is used to prefix instructions in "page 2" of the opcode |
| 5 | space */ |
| 6 | #define PAGE2_PREBYTE (0x1b) |
| 7 | |
| 8 | struct reg |
| 9 | { |
| 10 | char *name; /* The canonical name of the register */ |
| 11 | int bytes; /* its size, in bytes */ |
| 12 | }; |
| 13 | |
| 14 | |
| 15 | /* How many registers do we have. Actually there are only 13, |
| 16 | because CCL and CCH are the low and high bytes of CCW. But |
| 17 | for assemnbly / disassembly purposes they are considered |
| 18 | distinct registers. */ |
| 19 | #define S12Z_N_REGISTERS 15 |
| 20 | |
| 21 | extern const struct reg registers[S12Z_N_REGISTERS]; |
| 22 | |
| 23 | enum { |
| 24 | REG_D2 = 0, |
| 25 | REG_D3, |
| 26 | REG_D4, |
| 27 | REG_D5, |
| 28 | REG_D0, |
| 29 | REG_D1, |
| 30 | REG_D6, |
| 31 | REG_D7, |
| 32 | REG_X, |
| 33 | REG_Y, |
| 34 | REG_S, |
| 35 | REG_P, |
| 36 | REG_CCH, |
| 37 | REG_CCL, |
| 38 | REG_CCW |
| 39 | }; |
| 40 | |
| 41 | /* Any of the registers d0, d1, ... d7 */ |
| 42 | #define REG_BIT_Dn \ |
| 43 | ((0x1U << REG_D2) | \ |
| 44 | (0x1U << REG_D3) | \ |
| 45 | (0x1U << REG_D4) | \ |
| 46 | (0x1U << REG_D5) | \ |
| 47 | (0x1U << REG_D6) | \ |
| 48 | (0x1U << REG_D7) | \ |
| 49 | (0x1U << REG_D0) | \ |
| 50 | (0x1U << REG_D1)) |
| 51 | |
| 52 | /* Any of the registers x, y or z */ |
| 53 | #define REG_BIT_XYS \ |
| 54 | ((0x1U << REG_X) | \ |
| 55 | (0x1U << REG_Y) | \ |
| 56 | (0x1U << REG_S)) |
| 57 | |
| 58 | /* Any of the registers x, y, z or p */ |
| 59 | #define REG_BIT_XYSP \ |
| 60 | ((0x1U << REG_X) | \ |
| 61 | (0x1U << REG_Y) | \ |
| 62 | (0x1U << REG_S) | \ |
| 63 | (0x1U << REG_P)) |
| 64 | |
| 65 | /* The x register or the y register */ |
| 66 | #define REG_BIT_XY \ |
| 67 | ((0x1U << REG_X) | \ |
| 68 | (0x1U << REG_Y)) |
| 69 | |
| 70 | |
| 71 | #endif |