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NS32K arg_bufs uninitialised
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12020-03-22 Alan Modra <amodra@gmail.com>
2
3 * ns32k-dis.c (print_insn_arg): Update comment.
4 (print_insn_ns32k): Reduce size of index_offset array, and
5 initialize, passing -1 to print_insn_arg for args that are not
6 an index. Don't exit arg loop early. Abort on bad arg number.
7
82020-03-22 Alan Modra <amodra@gmail.com>
9
10 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
11 * s12z-opc.c: Formatting.
12 (operands_f): Return an int.
13 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
14 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
15 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
16 (exg_sex_discrim): Likewise.
17 (create_immediate_operand, create_bitfield_operand),
18 (create_register_operand_with_size, create_register_all_operand),
19 (create_register_all16_operand, create_simple_memory_operand),
20 (create_memory_operand, create_memory_auto_operand): Don't
21 segfault on malloc failure.
22 (z_ext24_decode): Return an int status, negative on fail, zero
23 on success.
24 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
25 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
26 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
27 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
28 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
29 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
30 (loop_primitive_decode, shift_decode, psh_pul_decode),
31 (bit_field_decode): Similarly.
32 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
33 to return value, update callers.
34 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
35 Don't segfault on NULL operand.
36 (decode_operation): Return OP_INVALID on first fail.
37 (decode_s12z): Check all reads, returning -1 on fail.
38
392020-03-20 Alan Modra <amodra@gmail.com>
40
41 * metag-dis.c (print_insn_metag): Don't ignore status from
42 read_memory_func.
43
442020-03-20 Alan Modra <amodra@gmail.com>
45
46 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
47 Initialize parts of buffer not written when handling a possible
48 2-byte insn at end of section. Don't attempt decoding of such
49 an insn by the 4-byte machinery.
50
512020-03-20 Alan Modra <amodra@gmail.com>
52
53 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
54 partially filled buffer. Prevent lookup of 4-byte insns when
55 only VLE 2-byte insns are possible due to section size. Print
56 ".word" rather than ".long" for 2-byte leftovers.
57
582020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
59
60 PR 25641
61 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
62
632020-03-13 Jan Beulich <jbeulich@suse.com>
64
65 * i386-dis.c (X86_64_0D): Rename to ...
66 (X86_64_0E): ... this.
67
682020-03-09 H.J. Lu <hongjiu.lu@intel.com>
69
70 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
71 * Makefile.in: Regenerated.
72
732020-03-09 Jan Beulich <jbeulich@suse.com>
74
75 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
76 3-operand pseudos.
77 * i386-tbl.h: Re-generate.
78
792020-03-09 Jan Beulich <jbeulich@suse.com>
80
81 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
82 vprot*, vpsha*, and vpshl*.
83 * i386-tbl.h: Re-generate.
84
852020-03-09 Jan Beulich <jbeulich@suse.com>
86
87 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
88 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
89 * i386-tbl.h: Re-generate.
90
912020-03-09 Jan Beulich <jbeulich@suse.com>
92
93 * i386-gen.c (set_bitfield): Ignore zero-length field names.
94 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
95 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
96 * i386-tbl.h: Re-generate.
97
982020-03-09 Jan Beulich <jbeulich@suse.com>
99
100 * i386-gen.c (struct template_arg, struct template_instance,
101 struct template_param, struct template, templates,
102 parse_template, expand_templates): New.
103 (process_i386_opcodes): Various local variables moved to
104 expand_templates. Call parse_template and expand_templates.
105 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
106 * i386-tbl.h: Re-generate.
107
1082020-03-06 Jan Beulich <jbeulich@suse.com>
109
110 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
111 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
112 register and memory source templates. Replace VexW= by VexW*
113 where applicable.
114 * i386-tbl.h: Re-generate.
115
1162020-03-06 Jan Beulich <jbeulich@suse.com>
117
118 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
119 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
120 * i386-tbl.h: Re-generate.
121
1222020-03-06 Jan Beulich <jbeulich@suse.com>
123
124 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
125 * i386-tbl.h: Re-generate.
126
1272020-03-06 Jan Beulich <jbeulich@suse.com>
128
129 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
130 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
131 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
132 VexW0 on SSE2AVX variants.
133 (vmovq): Drop NoRex64 from XMM/XMM variants.
134 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
135 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
136 applicable use VexW0.
137 * i386-tbl.h: Re-generate.
138
1392020-03-06 Jan Beulich <jbeulich@suse.com>
140
141 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
142 * i386-opc.h (Rex64): Delete.
143 (struct i386_opcode_modifier): Remove rex64 field.
144 * i386-opc.tbl (crc32): Drop Rex64.
145 Replace Rex64 with Size64 everywhere else.
146 * i386-tbl.h: Re-generate.
147
1482020-03-06 Jan Beulich <jbeulich@suse.com>
149
150 * i386-dis.c (OP_E_memory): Exclude recording of used address
151 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
152 addressed memory operands for MPX insns.
153
1542020-03-06 Jan Beulich <jbeulich@suse.com>
155
156 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
157 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
158 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
159 (ptwrite): Split into non-64-bit and 64-bit forms.
160 * i386-tbl.h: Re-generate.
161
1622020-03-06 Jan Beulich <jbeulich@suse.com>
163
164 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
165 template.
166 * i386-tbl.h: Re-generate.
167
1682020-03-04 Jan Beulich <jbeulich@suse.com>
169
170 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
171 (prefix_table): Move vmmcall here. Add vmgexit.
172 (rm_table): Replace vmmcall entry by prefix_table[] escape.
173 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
174 (cpu_flags): Add CpuSEV_ES entry.
175 * i386-opc.h (CpuSEV_ES): New.
176 (union i386_cpu_flags): Add cpusev_es field.
177 * i386-opc.tbl (vmgexit): New.
178 * i386-init.h, i386-tbl.h: Re-generate.
179
1802020-03-03 H.J. Lu <hongjiu.lu@intel.com>
181
182 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
183 with MnemonicSize.
184 * i386-opc.h (IGNORESIZE): New.
185 (DEFAULTSIZE): Likewise.
186 (IgnoreSize): Removed.
187 (DefaultSize): Likewise.
188 (MnemonicSize): New.
189 (i386_opcode_modifier): Replace ignoresize/defaultsize with
190 mnemonicsize.
191 * i386-opc.tbl (IgnoreSize): New.
192 (DefaultSize): Likewise.
193 * i386-tbl.h: Regenerated.
194
1952020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
196
197 PR 25627
198 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
199 instructions.
200
2012020-03-03 H.J. Lu <hongjiu.lu@intel.com>
202
203 PR gas/25622
204 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
205 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
206 * i386-tbl.h: Regenerated.
207
2082020-02-26 Alan Modra <amodra@gmail.com>
209
210 * aarch64-asm.c: Indent labels correctly.
211 * aarch64-dis.c: Likewise.
212 * aarch64-gen.c: Likewise.
213 * aarch64-opc.c: Likewise.
214 * alpha-dis.c: Likewise.
215 * i386-dis.c: Likewise.
216 * nds32-asm.c: Likewise.
217 * nfp-dis.c: Likewise.
218 * visium-dis.c: Likewise.
219
2202020-02-25 Claudiu Zissulescu <claziss@gmail.com>
221
222 * arc-regs.h (int_vector_base): Make it available for all ARC
223 CPUs.
224
2252020-02-20 Nelson Chu <nelson.chu@sifive.com>
226
227 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
228 changed.
229
2302020-02-19 Nelson Chu <nelson.chu@sifive.com>
231
232 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
233 c.mv/c.li if rs1 is zero.
234
2352020-02-17 H.J. Lu <hongjiu.lu@intel.com>
236
237 * i386-gen.c (cpu_flag_init): Replace CpuABM with
238 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
239 CPU_POPCNT_FLAGS.
240 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
241 * i386-opc.h (CpuABM): Removed.
242 (CpuPOPCNT): New.
243 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
244 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
245 popcnt. Remove CpuABM from lzcnt.
246 * i386-init.h: Regenerated.
247 * i386-tbl.h: Likewise.
248
2492020-02-17 Jan Beulich <jbeulich@suse.com>
250
251 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
252 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
253 VexW1 instead of open-coding them.
254 * i386-tbl.h: Re-generate.
255
2562020-02-17 Jan Beulich <jbeulich@suse.com>
257
258 * i386-opc.tbl (AddrPrefixOpReg): Define.
259 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
260 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
261 templates. Drop NoRex64.
262 * i386-tbl.h: Re-generate.
263
2642020-02-17 Jan Beulich <jbeulich@suse.com>
265
266 PR gas/6518
267 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
268 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
269 into Intel syntax instance (with Unpsecified) and AT&T one
270 (without).
271 (vcvtneps2bf16): Likewise, along with folding the two so far
272 separate ones.
273 * i386-tbl.h: Re-generate.
274
2752020-02-16 H.J. Lu <hongjiu.lu@intel.com>
276
277 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
278 CPU_ANY_SSE4A_FLAGS.
279
2802020-02-17 Alan Modra <amodra@gmail.com>
281
282 * i386-gen.c (cpu_flag_init): Correct last change.
283
2842020-02-16 H.J. Lu <hongjiu.lu@intel.com>
285
286 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
287 CPU_ANY_SSE4_FLAGS.
288
2892020-02-14 H.J. Lu <hongjiu.lu@intel.com>
290
291 * i386-opc.tbl (movsx): Remove Intel syntax comments.
292 (movzx): Likewise.
293
2942020-02-14 Jan Beulich <jbeulich@suse.com>
295
296 PR gas/25438
297 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
298 destination for Cpu64-only variant.
299 (movzx): Fold patterns.
300 * i386-tbl.h: Re-generate.
301
3022020-02-13 Jan Beulich <jbeulich@suse.com>
303
304 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
305 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
306 CPU_ANY_SSE4_FLAGS entry.
307 * i386-init.h: Re-generate.
308
3092020-02-12 Jan Beulich <jbeulich@suse.com>
310
311 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
312 with Unspecified, making the present one AT&T syntax only.
313 * i386-tbl.h: Re-generate.
314
3152020-02-12 Jan Beulich <jbeulich@suse.com>
316
317 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
318 * i386-tbl.h: Re-generate.
319
3202020-02-12 Jan Beulich <jbeulich@suse.com>
321
322 PR gas/24546
323 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
324 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
325 Amd64 and Intel64 templates.
326 (call, jmp): Likewise for far indirect variants. Dro
327 Unspecified.
328 * i386-tbl.h: Re-generate.
329
3302020-02-11 Jan Beulich <jbeulich@suse.com>
331
332 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
333 * i386-opc.h (ShortForm): Delete.
334 (struct i386_opcode_modifier): Remove shortform field.
335 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
336 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
337 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
338 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
339 Drop ShortForm.
340 * i386-tbl.h: Re-generate.
341
3422020-02-11 Jan Beulich <jbeulich@suse.com>
343
344 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
345 fucompi): Drop ShortForm from operand-less templates.
346 * i386-tbl.h: Re-generate.
347
3482020-02-11 Alan Modra <amodra@gmail.com>
349
350 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
351 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
352 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
353 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
354 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
355
3562020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
357
358 * arm-dis.c (print_insn_cde): Define 'V' parse character.
359 (cde_opcodes): Add VCX* instructions.
360
3612020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
362 Matthew Malcomson <matthew.malcomson@arm.com>
363
364 * arm-dis.c (struct cdeopcode32): New.
365 (CDE_OPCODE): New macro.
366 (cde_opcodes): New disassembly table.
367 (regnames): New option to table.
368 (cde_coprocs): New global variable.
369 (print_insn_cde): New
370 (print_insn_thumb32): Use print_insn_cde.
371 (parse_arm_disassembler_options): Parse coprocN args.
372
3732020-02-10 H.J. Lu <hongjiu.lu@intel.com>
374
375 PR gas/25516
376 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
377 with ISA64.
378 * i386-opc.h (AMD64): Removed.
379 (Intel64): Likewose.
380 (AMD64): New.
381 (INTEL64): Likewise.
382 (INTEL64ONLY): Likewise.
383 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
384 * i386-opc.tbl (Amd64): New.
385 (Intel64): Likewise.
386 (Intel64Only): Likewise.
387 Replace AMD64 with Amd64. Update sysenter/sysenter with
388 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
389 * i386-tbl.h: Regenerated.
390
3912020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
392
393 PR 25469
394 * z80-dis.c: Add support for GBZ80 opcodes.
395
3962020-02-04 Alan Modra <amodra@gmail.com>
397
398 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
399
4002020-02-03 Alan Modra <amodra@gmail.com>
401
402 * m32c-ibld.c: Regenerate.
403
4042020-02-01 Alan Modra <amodra@gmail.com>
405
406 * frv-ibld.c: Regenerate.
407
4082020-01-31 Jan Beulich <jbeulich@suse.com>
409
410 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
411 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
412 (OP_E_memory): Replace xmm_mdq_mode case label by
413 vex_scalar_w_dq_mode one.
414 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
415
4162020-01-31 Jan Beulich <jbeulich@suse.com>
417
418 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
419 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
420 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
421 (intel_operand_size): Drop vex_w_dq_mode case label.
422
4232020-01-31 Richard Sandiford <richard.sandiford@arm.com>
424
425 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
426 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
427
4282020-01-30 Alan Modra <amodra@gmail.com>
429
430 * m32c-ibld.c: Regenerate.
431
4322020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
433
434 * bpf-opc.c: Regenerate.
435
4362020-01-30 Jan Beulich <jbeulich@suse.com>
437
438 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
439 (dis386): Use them to replace C2/C3 table entries.
440 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
441 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
442 ones. Use Size64 instead of DefaultSize on Intel64 ones.
443 * i386-tbl.h: Re-generate.
444
4452020-01-30 Jan Beulich <jbeulich@suse.com>
446
447 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
448 forms.
449 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
450 DefaultSize.
451 * i386-tbl.h: Re-generate.
452
4532020-01-30 Alan Modra <amodra@gmail.com>
454
455 * tic4x-dis.c (tic4x_dp): Make unsigned.
456
4572020-01-27 H.J. Lu <hongjiu.lu@intel.com>
458 Jan Beulich <jbeulich@suse.com>
459
460 PR binutils/25445
461 * i386-dis.c (MOVSXD_Fixup): New function.
462 (movsxd_mode): New enum.
463 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
464 (intel_operand_size): Handle movsxd_mode.
465 (OP_E_register): Likewise.
466 (OP_G): Likewise.
467 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
468 register on movsxd. Add movsxd with 16-bit destination register
469 for AMD64 and Intel64 ISAs.
470 * i386-tbl.h: Regenerated.
471
4722020-01-27 Tamar Christina <tamar.christina@arm.com>
473
474 PR 25403
475 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
476 * aarch64-asm-2.c: Regenerate
477 * aarch64-dis-2.c: Likewise.
478 * aarch64-opc-2.c: Likewise.
479
4802020-01-21 Jan Beulich <jbeulich@suse.com>
481
482 * i386-opc.tbl (sysret): Drop DefaultSize.
483 * i386-tbl.h: Re-generate.
484
4852020-01-21 Jan Beulich <jbeulich@suse.com>
486
487 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
488 Dword.
489 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
490 * i386-tbl.h: Re-generate.
491
4922020-01-20 Nick Clifton <nickc@redhat.com>
493
494 * po/de.po: Updated German translation.
495 * po/pt_BR.po: Updated Brazilian Portuguese translation.
496 * po/uk.po: Updated Ukranian translation.
497
4982020-01-20 Alan Modra <amodra@gmail.com>
499
500 * hppa-dis.c (fput_const): Remove useless cast.
501
5022020-01-20 Alan Modra <amodra@gmail.com>
503
504 * arm-dis.c (print_insn_arm): Wrap 'T' value.
505
5062020-01-18 Nick Clifton <nickc@redhat.com>
507
508 * configure: Regenerate.
509 * po/opcodes.pot: Regenerate.
510
5112020-01-18 Nick Clifton <nickc@redhat.com>
512
513 Binutils 2.34 branch created.
514
5152020-01-17 Christian Biesinger <cbiesinger@google.com>
516
517 * opintl.h: Fix spelling error (seperate).
518
5192020-01-17 H.J. Lu <hongjiu.lu@intel.com>
520
521 * i386-opc.tbl: Add {vex} pseudo prefix.
522 * i386-tbl.h: Regenerated.
523
5242020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
525
526 PR 25376
527 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
528 (neon_opcodes): Likewise.
529 (select_arm_features): Make sure we enable MVE bits when selecting
530 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
531 any architecture.
532
5332020-01-16 Jan Beulich <jbeulich@suse.com>
534
535 * i386-opc.tbl: Drop stale comment from XOP section.
536
5372020-01-16 Jan Beulich <jbeulich@suse.com>
538
539 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
540 (extractps): Add VexWIG to SSE2AVX forms.
541 * i386-tbl.h: Re-generate.
542
5432020-01-16 Jan Beulich <jbeulich@suse.com>
544
545 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
546 Size64 from and use VexW1 on SSE2AVX forms.
547 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
548 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
549 * i386-tbl.h: Re-generate.
550
5512020-01-15 Alan Modra <amodra@gmail.com>
552
553 * tic4x-dis.c (tic4x_version): Make unsigned long.
554 (optab, optab_special, registernames): New file scope vars.
555 (tic4x_print_register): Set up registernames rather than
556 malloc'd registertable.
557 (tic4x_disassemble): Delete optable and optable_special. Use
558 optab and optab_special instead. Throw away old optab,
559 optab_special and registernames when info->mach changes.
560
5612020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
562
563 PR 25377
564 * z80-dis.c (suffix): Use .db instruction to generate double
565 prefix.
566
5672020-01-14 Alan Modra <amodra@gmail.com>
568
569 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
570 values to unsigned before shifting.
571
5722020-01-13 Thomas Troeger <tstroege@gmx.de>
573
574 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
575 flow instructions.
576 (print_insn_thumb16, print_insn_thumb32): Likewise.
577 (print_insn): Initialize the insn info.
578 * i386-dis.c (print_insn): Initialize the insn info fields, and
579 detect jumps.
580
5812012-01-13 Claudiu Zissulescu <claziss@gmail.com>
582
583 * arc-opc.c (C_NE): Make it required.
584
5852012-01-13 Claudiu Zissulescu <claziss@gmail.com>
586
587 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
588 reserved register name.
589
5902020-01-13 Alan Modra <amodra@gmail.com>
591
592 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
593 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
594
5952020-01-13 Alan Modra <amodra@gmail.com>
596
597 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
598 result of wasm_read_leb128 in a uint64_t and check that bits
599 are not lost when copying to other locals. Use uint32_t for
600 most locals. Use PRId64 when printing int64_t.
601
6022020-01-13 Alan Modra <amodra@gmail.com>
603
604 * score-dis.c: Formatting.
605 * score7-dis.c: Formatting.
606
6072020-01-13 Alan Modra <amodra@gmail.com>
608
609 * score-dis.c (print_insn_score48): Use unsigned variables for
610 unsigned values. Don't left shift negative values.
611 (print_insn_score32): Likewise.
612 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
613
6142020-01-13 Alan Modra <amodra@gmail.com>
615
616 * tic4x-dis.c (tic4x_print_register): Remove dead code.
617
6182020-01-13 Alan Modra <amodra@gmail.com>
619
620 * fr30-ibld.c: Regenerate.
621
6222020-01-13 Alan Modra <amodra@gmail.com>
623
624 * xgate-dis.c (print_insn): Don't left shift signed value.
625 (ripBits): Formatting, use 1u.
626
6272020-01-10 Alan Modra <amodra@gmail.com>
628
629 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
630 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
631
6322020-01-10 Alan Modra <amodra@gmail.com>
633
634 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
635 and XRREG value earlier to avoid a shift with negative exponent.
636 * m10200-dis.c (disassemble): Similarly.
637
6382020-01-09 Nick Clifton <nickc@redhat.com>
639
640 PR 25224
641 * z80-dis.c (ld_ii_ii): Use correct cast.
642
6432020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
644
645 PR 25224
646 * z80-dis.c (ld_ii_ii): Use character constant when checking
647 opcode byte value.
648
6492020-01-09 Jan Beulich <jbeulich@suse.com>
650
651 * i386-dis.c (SEP_Fixup): New.
652 (SEP): Define.
653 (dis386_twobyte): Use it for sysenter/sysexit.
654 (enum x86_64_isa): Change amd64 enumerator to value 1.
655 (OP_J): Compare isa64 against intel64 instead of amd64.
656 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
657 forms.
658 * i386-tbl.h: Re-generate.
659
6602020-01-08 Alan Modra <amodra@gmail.com>
661
662 * z8k-dis.c: Include libiberty.h
663 (instr_data_s): Make max_fetched unsigned.
664 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
665 Don't exceed byte_info bounds.
666 (output_instr): Make num_bytes unsigned.
667 (unpack_instr): Likewise for nibl_count and loop.
668 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
669 idx unsigned.
670 * z8k-opc.h: Regenerate.
671
6722020-01-07 Shahab Vahedi <shahab@synopsys.com>
673
674 * arc-tbl.h (llock): Use 'LLOCK' as class.
675 (llockd): Likewise.
676 (scond): Use 'SCOND' as class.
677 (scondd): Likewise.
678 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
679 (scondd): Likewise.
680
6812020-01-06 Alan Modra <amodra@gmail.com>
682
683 * m32c-ibld.c: Regenerate.
684
6852020-01-06 Alan Modra <amodra@gmail.com>
686
687 PR 25344
688 * z80-dis.c (suffix): Don't use a local struct buffer copy.
689 Peek at next byte to prevent recursion on repeated prefix bytes.
690 Ensure uninitialised "mybuf" is not accessed.
691 (print_insn_z80): Don't zero n_fetch and n_used here,..
692 (print_insn_z80_buf): ..do it here instead.
693
6942020-01-04 Alan Modra <amodra@gmail.com>
695
696 * m32r-ibld.c: Regenerate.
697
6982020-01-04 Alan Modra <amodra@gmail.com>
699
700 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
701
7022020-01-04 Alan Modra <amodra@gmail.com>
703
704 * crx-dis.c (match_opcode): Avoid shift left of signed value.
705
7062020-01-04 Alan Modra <amodra@gmail.com>
707
708 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
709
7102020-01-03 Jan Beulich <jbeulich@suse.com>
711
712 * aarch64-tbl.h (aarch64_opcode_table): Use
713 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
714
7152020-01-03 Jan Beulich <jbeulich@suse.com>
716
717 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
718 forms of SUDOT and USDOT.
719
7202020-01-03 Jan Beulich <jbeulich@suse.com>
721
722 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
723 uzip{1,2}.
724 * opcodes/aarch64-dis-2.c: Re-generate.
725
7262020-01-03 Jan Beulich <jbeulich@suse.com>
727
728 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
729 FMMLA encoding.
730 * opcodes/aarch64-dis-2.c: Re-generate.
731
7322020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
733
734 * z80-dis.c: Add support for eZ80 and Z80 instructions.
735
7362020-01-01 Alan Modra <amodra@gmail.com>
737
738 Update year range in copyright notice of all files.
739
740For older changes see ChangeLog-2019
741\f
742Copyright (C) 2020 Free Software Foundation, Inc.
743
744Copying and distribution of this file, with or without modification,
745are permitted in any medium without royalty provided the copyright
746notice and this notice are preserved.
747
748Local Variables:
749mode: change-log
750left-margin: 8
751fill-column: 74
752version-control: never
753End:
GDB Binutils - Deliverables
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