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12017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
2
3 * arc-dis.c (parse_option): Update quarkse_em option..
4 * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
5 QUARKSE1.
6 (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
7
82017-05-03 Kito Cheng <kito.cheng@gmail.com>
9
10 * riscv-dis.c (print_insn_args): Handle 'Co' operands.
11
122017-05-01 Michael Clark <michaeljclark@mac.com>
13
14 * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
15 register.
16
172017-05-02 Maciej W. Rozycki <macro@imgtec.com>
18
19 * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
20 and branches and not synthetic data instructions.
21
222017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de>
23
24 * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
25
262017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
27
28 * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
29 * arc-opc.c (insert_r13el): New function.
30 (R13_EL): Define.
31 * arc-tbl.h: Add new enter/leave variants.
32
332017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
34
35 * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
36
372017-04-25 Maciej W. Rozycki <macro@imgtec.com>
38
39 * mips-dis.c (print_mips_disassembler_options): Add
40 `no-aliases'.
41
422017-04-25 Maciej W. Rozycki <macro@imgtec.com>
43
44 * mips16-opc.c (AL): New macro.
45 (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
46 of "ld" and "lw" as aliases.
47
482017-04-24 Tamar Christina <tamar.christina@arm.com>
49
50 * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
51 arguments.
52
532017-04-22 Alexander Fedotov <alfedotov@gmail.com>
54 Alan Modra <amodra@gmail.com>
55
56 * ppc-opc.c (ELEV): Define.
57 (vle_opcodes): Add se_rfgi and e_sc.
58 (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
59 for E200Z4.
60
612017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
62
63 * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
64
652017-04-21 Nick Clifton <nickc@redhat.com>
66
67 PR binutils/21380
68 * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
69 LD3R and LD4R.
70
712017-04-13 Alan Modra <amodra@gmail.com>
72
73 * epiphany-desc.c: Regenerate.
74 * fr30-desc.c: Regenerate.
75 * frv-desc.c: Regenerate.
76 * ip2k-desc.c: Regenerate.
77 * iq2000-desc.c: Regenerate.
78 * lm32-desc.c: Regenerate.
79 * m32c-desc.c: Regenerate.
80 * m32r-desc.c: Regenerate.
81 * mep-desc.c: Regenerate.
82 * mt-desc.c: Regenerate.
83 * or1k-desc.c: Regenerate.
84 * xc16x-desc.c: Regenerate.
85 * xstormy16-desc.c: Regenerate.
86
872017-04-11 Alan Modra <amodra@gmail.com>
88
89 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
90 PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
91 PPC_OPCODE_TMR for e6500.
92 * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
93 (PPCVEC3): Define as PPC_OPCODE_POWER9.
94 (PPCVSX2): Define as PPC_OPCODE_POWER8.
95 (PPCVSX3): Define as PPC_OPCODE_POWER9.
96 (PPCHTM): Define as PPC_OPCODE_POWER8.
97 (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
98
992017-04-10 Alan Modra <amodra@gmail.com>
100
101 * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
102 * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
103 (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
104 removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
105
1062017-04-09 Pip Cet <pipcet@gmail.com>
107
108 * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
109 appropriate floating-point precision directly.
110
1112017-04-07 Alan Modra <amodra@gmail.com>
112
113 * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
114 lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
115 lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
116 lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
117 vector instructions with E6500 not PPCVEC2.
118
1192017-04-06 Pip Cet <pipcet@gmail.com>
120
121 * Makefile.am: Add wasm32-dis.c.
122 * configure.ac: Add wasm32-dis.c to wasm32 target.
123 * disassemble.c: Add wasm32 disassembler code.
124 * wasm32-dis.c: New file.
125 * Makefile.in: Regenerate.
126 * configure: Regenerate.
127 * po/POTFILES.in: Regenerate.
128 * po/opcodes.pot: Regenerate.
129
1302017-04-05 Pedro Alves <palves@redhat.com>
131
132 * arc-dis.c (parse_option, parse_disassembler_options): Constify.
133 * arm-dis.c (parse_arm_disassembler_options): Constify.
134 * ppc-dis.c (powerpc_init_dialect): Constify local.
135 * vax-dis.c (parse_disassembler_options): Constify.
136
1372017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
138
139 * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
140 RISCV_GP_SYMBOL.
141
1422017-03-30 Pip Cet <pipcet@gmail.com>
143
144 * configure.ac: Add (empty) bfd_wasm32_arch target.
145 * configure: Regenerate
146 * po/opcodes.pot: Regenerate.
147
1482017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
149
150 Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
151 OSA2015.
152 * opcodes/sparc-opc.c (asi_table): New ASIs.
153
1542017-03-29 Alan Modra <amodra@gmail.com>
155
156 * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
157 "raw" option.
158 (lookup_powerpc): Don't special case -1 dialect. Handle
159 PPC_OPCODE_RAW.
160 (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
161 lookup_powerpc call, pass it on second.
162
1632017-03-27 Alan Modra <amodra@gmail.com>
164
165 PR 21303
166 * ppc-dis.c (struct ppc_mopt): Comment.
167 (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
168
1692017-03-27 Rinat Zelig <rinat@mellanox.com>
170
171 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
172 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
173 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
174 (insert_nps_misc_imm_offset): New function.
175 (extract_nps_misc imm_offset): New function.
176 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
177 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
178
1792017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
180
181 * s390-mkopc.c (main): Remove vx2 check.
182 * s390-opc.txt: Remove vx2 instruction flags.
183
1842017-03-21 Rinat Zelig <rinat@mellanox.com>
185
186 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
187 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
188 (insert_nps_imm_offset): New function.
189 (extract_nps_imm_offset): New function.
190 (insert_nps_imm_entry): New function.
191 (extract_nps_imm_entry): New function.
192
1932017-03-17 Alan Modra <amodra@gmail.com>
194
195 PR 21248
196 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
197 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
198 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
199
2002017-03-14 Kito Cheng <kito.cheng@gmail.com>
201
202 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
203 <c.andi>: Likewise.
204 <c.addiw> Likewise.
205
2062017-03-14 Kito Cheng <kito.cheng@gmail.com>
207
208 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
209
2102017-03-13 Andrew Waterman <andrew@sifive.com>
211
212 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
213 <srl> Likewise.
214 <srai> Likewise.
215 <sra> Likewise.
216
2172017-03-09 H.J. Lu <hongjiu.lu@intel.com>
218
219 * i386-gen.c (opcode_modifiers): Replace S with Load.
220 * i386-opc.h (S): Removed.
221 (Load): New.
222 (i386_opcode_modifier): Replace s with load.
223 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
224 and {evex}. Replace S with Load.
225 * i386-tbl.h: Regenerated.
226
2272017-03-09 H.J. Lu <hongjiu.lu@intel.com>
228
229 * i386-opc.tbl: Use CpuCET on rdsspq.
230 * i386-tbl.h: Regenerated.
231
2322017-03-08 Peter Bergner <bergner@vnet.ibm.com>
233
234 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
235 <vsx>: Do not use PPC_OPCODE_VSX3;
236
2372017-03-08 Peter Bergner <bergner@vnet.ibm.com>
238
239 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
240
2412017-03-06 H.J. Lu <hongjiu.lu@intel.com>
242
243 * i386-dis.c (REG_0F1E_MOD_3): New enum.
244 (MOD_0F1E_PREFIX_1): Likewise.
245 (MOD_0F38F5_PREFIX_2): Likewise.
246 (MOD_0F38F6_PREFIX_0): Likewise.
247 (RM_0F1E_MOD_3_REG_7): Likewise.
248 (PREFIX_MOD_0_0F01_REG_5): Likewise.
249 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
250 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
251 (PREFIX_0F1E): Likewise.
252 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
253 (PREFIX_0F38F5): Likewise.
254 (dis386_twobyte): Use PREFIX_0F1E.
255 (reg_table): Add REG_0F1E_MOD_3.
256 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
257 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
258 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
259 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
260 (three_byte_table): Use PREFIX_0F38F5.
261 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
262 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
263 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
264 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
265 PREFIX_MOD_3_0F01_REG_5_RM_2.
266 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
267 (cpu_flags): Add CpuCET.
268 * i386-opc.h (CpuCET): New enum.
269 (CpuUnused): Commented out.
270 (i386_cpu_flags): Add cpucet.
271 * i386-opc.tbl: Add Intel CET instructions.
272 * i386-init.h: Regenerated.
273 * i386-tbl.h: Likewise.
274
2752017-03-06 Alan Modra <amodra@gmail.com>
276
277 PR 21124
278 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
279 (extract_raq, extract_ras, extract_rbx): New functions.
280 (powerpc_operands): Use opposite corresponding insert function.
281 (Q_MASK): Define.
282 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
283 register restriction.
284
2852017-02-28 Peter Bergner <bergner@vnet.ibm.com>
286
287 * disassemble.c Include "safe-ctype.h".
288 (disassemble_init_for_target): Handle s390 init.
289 (remove_whitespace_and_extra_commas): New function.
290 (disassembler_options_cmp): Likewise.
291 * arm-dis.c: Include "libiberty.h".
292 (NUM_ELEM): Delete.
293 (regnames): Use long disassembler style names.
294 Add force-thumb and no-force-thumb options.
295 (NUM_ARM_REGNAMES): Rename from this...
296 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
297 (get_arm_regname_num_options): Delete.
298 (set_arm_regname_option): Likewise.
299 (get_arm_regnames): Likewise.
300 (parse_disassembler_options): Likewise.
301 (parse_arm_disassembler_option): Rename from this...
302 (parse_arm_disassembler_options): ...to this. Make static.
303 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
304 (print_insn): Use parse_arm_disassembler_options.
305 (disassembler_options_arm): New function.
306 (print_arm_disassembler_options): Handle updated regnames.
307 * ppc-dis.c: Include "libiberty.h".
308 (ppc_opts): Add "32" and "64" entries.
309 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
310 (powerpc_init_dialect): Add break to switch statement.
311 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
312 (disassembler_options_powerpc): New function.
313 (print_ppc_disassembler_options): Use ARRAY_SIZE.
314 Remove printing of "32" and "64".
315 * s390-dis.c: Include "libiberty.h".
316 (init_flag): Remove unneeded variable.
317 (struct s390_options_t): New structure type.
318 (options): New structure.
319 (init_disasm): Rename from this...
320 (disassemble_init_s390): ...to this. Add initializations for
321 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
322 (print_insn_s390): Delete call to init_disasm.
323 (disassembler_options_s390): New function.
324 (print_s390_disassembler_options): Print using information from
325 struct 'options'.
326 * po/opcodes.pot: Regenerate.
327
3282017-02-28 Jan Beulich <jbeulich@suse.com>
329
330 * i386-dis.c (PCMPESTR_Fixup): New.
331 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
332 (prefix_table): Use PCMPESTR_Fixup.
333 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
334 PCMPESTR_Fixup.
335 (vex_w_table): Delete VPCMPESTR{I,M} entries.
336 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
337 Split 64-bit and non-64-bit variants.
338 * opcodes/i386-tbl.h: Re-generate.
339
3402017-02-24 Richard Sandiford <richard.sandiford@arm.com>
341
342 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
343 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
344 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
345 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
346 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
347 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
348 (OP_SVE_V_HSD): New macros.
349 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
350 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
351 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
352 (aarch64_opcode_table): Add new SVE instructions.
353 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
354 for rotation operands. Add new SVE operands.
355 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
356 (ins_sve_quad_index): Likewise.
357 (ins_imm_rotate): Split into...
358 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
359 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
360 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
361 functions.
362 (aarch64_ins_sve_addr_ri_s4): New function.
363 (aarch64_ins_sve_quad_index): Likewise.
364 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
365 * aarch64-asm-2.c: Regenerate.
366 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
367 (ext_sve_quad_index): Likewise.
368 (ext_imm_rotate): Split into...
369 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
370 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
371 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
372 functions.
373 (aarch64_ext_sve_addr_ri_s4): New function.
374 (aarch64_ext_sve_quad_index): Likewise.
375 (aarch64_ext_sve_index): Allow quad indices.
376 (do_misc_decoding): Likewise.
377 * aarch64-dis-2.c: Regenerate.
378 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
379 aarch64_field_kinds.
380 (OPD_F_OD_MASK): Widen by one bit.
381 (OPD_F_NO_ZR): Bump accordingly.
382 (get_operand_field_width): New function.
383 * aarch64-opc.c (fields): Add new SVE fields.
384 (operand_general_constraint_met_p): Handle new SVE operands.
385 (aarch64_print_operand): Likewise.
386 * aarch64-opc-2.c: Regenerate.
387
3882017-02-24 Richard Sandiford <richard.sandiford@arm.com>
389
390 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
391 (aarch64_feature_compnum): ...this.
392 (SIMD_V8_3): Replace with...
393 (COMPNUM): ...this.
394 (CNUM_INSN): New macro.
395 (aarch64_opcode_table): Use it for the complex number instructions.
396
3972017-02-24 Jan Beulich <jbeulich@suse.com>
398
399 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
400
4012017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
402
403 Add support for associating SPARC ASIs with an architecture level.
404 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
405 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
406 decoding of SPARC ASIs.
407
4082017-02-23 Jan Beulich <jbeulich@suse.com>
409
410 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
411 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
412
4132017-02-21 Jan Beulich <jbeulich@suse.com>
414
415 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
416 1 (instead of to itself). Correct typo.
417
4182017-02-14 Andrew Waterman <andrew@sifive.com>
419
420 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
421 pseudoinstructions.
422
4232017-02-15 Richard Sandiford <richard.sandiford@arm.com>
424
425 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
426 (aarch64_sys_reg_supported_p): Handle them.
427
4282017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
429
430 * arc-opc.c (UIMM6_20R): Define.
431 (SIMM12_20): Use above.
432 (SIMM12_20R): Define.
433 (SIMM3_5_S): Use above.
434 (UIMM7_A32_11R_S): Define.
435 (UIMM7_9_S): Use above.
436 (UIMM3_13R_S): Define.
437 (SIMM11_A32_7_S): Use above.
438 (SIMM9_8R): Define.
439 (UIMM10_A32_8_S): Use above.
440 (UIMM8_8R_S): Define.
441 (W6): Use above.
442 (arc_relax_opcodes): Use all above defines.
443
4442017-02-15 Vineet Gupta <vgupta@synopsys.com>
445
446 * arc-regs.h: Distinguish some of the registers different on
447 ARC700 and HS38 cpus.
448
4492017-02-14 Alan Modra <amodra@gmail.com>
450
451 PR 21118
452 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
453 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
454
4552017-02-11 Stafford Horne <shorne@gmail.com>
456 Alan Modra <amodra@gmail.com>
457
458 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
459 Use insn_bytes_value and insn_int_value directly instead. Don't
460 free allocated memory until function exit.
461
4622017-02-10 Nicholas Piggin <npiggin@gmail.com>
463
464 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
465
4662017-02-03 Nick Clifton <nickc@redhat.com>
467
468 PR 21096
469 * aarch64-opc.c (print_register_list): Ensure that the register
470 list index will fir into the tb buffer.
471 (print_register_offset_address): Likewise.
472 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
473
4742017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
475
476 PR 21056
477 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
478 instructions when the previous fetch packet ends with a 32-bit
479 instruction.
480
4812017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
482
483 * pru-opc.c: Remove vague reference to a future GDB port.
484
4852017-01-20 Nick Clifton <nickc@redhat.com>
486
487 * po/ga.po: Updated Irish translation.
488
4892017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
490
491 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
492
4932017-01-13 Yao Qi <yao.qi@linaro.org>
494
495 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
496 if FETCH_DATA returns 0.
497 (m68k_scan_mask): Likewise.
498 (print_insn_m68k): Update code to handle -1 return value.
499
5002017-01-13 Yao Qi <yao.qi@linaro.org>
501
502 * m68k-dis.c (enum print_insn_arg_error): New.
503 (NEXTBYTE): Replace -3 with
504 PRINT_INSN_ARG_MEMORY_ERROR.
505 (NEXTULONG): Likewise.
506 (NEXTSINGLE): Likewise.
507 (NEXTDOUBLE): Likewise.
508 (NEXTDOUBLE): Likewise.
509 (NEXTPACKED): Likewise.
510 (FETCH_ARG): Likewise.
511 (FETCH_DATA): Update comments.
512 (print_insn_arg): Update comments. Replace magic numbers with
513 enum.
514 (match_insn_m68k): Likewise.
515
5162017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
517
518 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
519 * i386-dis-evex.h (evex_table): Updated.
520 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
521 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
522 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
523 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
524 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
525 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
526 * i386-init.h: Regenerate.
527 * i386-tbl.h: Ditto.
528
5292017-01-12 Yao Qi <yao.qi@linaro.org>
530
531 * msp430-dis.c (msp430_singleoperand): Return -1 if
532 msp430dis_opcode_signed returns false.
533 (msp430_doubleoperand): Likewise.
534 (msp430_branchinstr): Return -1 if
535 msp430dis_opcode_unsigned returns false.
536 (msp430x_calla_instr): Likewise.
537 (print_insn_msp430): Likewise.
538
5392017-01-05 Nick Clifton <nickc@redhat.com>
540
541 PR 20946
542 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
543 could not be matched.
544 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
545 NULL.
546
5472017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
548
549 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
550 (aarch64_opcode_table): Use RCPC_INSN.
551
5522017-01-03 Kito Cheng <kito.cheng@gmail.com>
553
554 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
555 extension.
556 * riscv-opcodes/all-opcodes: Likewise.
557
5582017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
559
560 * riscv-dis.c (print_insn_args): Add fall through comment.
561
5622017-01-03 Nick Clifton <nickc@redhat.com>
563
564 * po/sr.po: New Serbian translation.
565 * configure.ac (ALL_LINGUAS): Add sr.
566 * configure: Regenerate.
567
5682017-01-02 Alan Modra <amodra@gmail.com>
569
570 * epiphany-desc.h: Regenerate.
571 * epiphany-opc.h: Regenerate.
572 * fr30-desc.h: Regenerate.
573 * fr30-opc.h: Regenerate.
574 * frv-desc.h: Regenerate.
575 * frv-opc.h: Regenerate.
576 * ip2k-desc.h: Regenerate.
577 * ip2k-opc.h: Regenerate.
578 * iq2000-desc.h: Regenerate.
579 * iq2000-opc.h: Regenerate.
580 * lm32-desc.h: Regenerate.
581 * lm32-opc.h: Regenerate.
582 * m32c-desc.h: Regenerate.
583 * m32c-opc.h: Regenerate.
584 * m32r-desc.h: Regenerate.
585 * m32r-opc.h: Regenerate.
586 * mep-desc.h: Regenerate.
587 * mep-opc.h: Regenerate.
588 * mt-desc.h: Regenerate.
589 * mt-opc.h: Regenerate.
590 * or1k-desc.h: Regenerate.
591 * or1k-opc.h: Regenerate.
592 * xc16x-desc.h: Regenerate.
593 * xc16x-opc.h: Regenerate.
594 * xstormy16-desc.h: Regenerate.
595 * xstormy16-opc.h: Regenerate.
596
5972017-01-02 Alan Modra <amodra@gmail.com>
598
599 Update year range in copyright notice of all files.
600
601For older changes see ChangeLog-2016
602\f
603Copyright (C) 2017 Free Software Foundation, Inc.
604
605Copying and distribution of this file, with or without modification,
606are permitted in any medium without royalty provided the copyright
607notice and this notice are preserved.
608
609Local Variables:
610mode: change-log
611left-margin: 8
612fill-column: 74
613version-control: never
614End:
GDB Binutils - Deliverables
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