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[ARC] Add XY registers, update neg instruction.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
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CommitLineData
12016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
2
3 * arc-tbl.h (neg): New instruction variant.
4
52016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
6
7 * arc-dis.c (find_format, find_format, get_auxreg)
8 (print_insn_arc): Changed.
9 * arc-ext.h (INSERT_XOP): Likewise.
10
112016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
12
13 * tic54x-dis.c (sprint_mmr): Adjust.
14 * tic54x-opc.c: Likewise.
15
162016-05-19 Alan Modra <amodra@gmail.com>
17
18 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
19
202016-05-19 Alan Modra <amodra@gmail.com>
21
22 * ppc-opc.c: Formatting.
23 (NSISIGNOPT): Define.
24 (powerpc_opcodes <subis>): Use NSISIGNOPT.
25
262016-05-18 Maciej W. Rozycki <macro@imgtec.com>
27
28 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
29 replacing references to `micromips_ase' throughout.
30 (_print_insn_mips): Don't use file-level microMIPS annotation to
31 determine the disassembly mode with the symbol table.
32
332016-05-13 Peter Bergner <bergner@vnet.ibm.com>
34
35 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
36
372016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
38
39 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
40 mips64r6.
41 * mips-opc.c (D34): New macro.
42 (mips_builtin_opcodes): Define bposge32c for DSPr3.
43
442016-05-10 Alexander Fomin <alexander.fomin@intel.com>
45
46 * i386-dis.c (prefix_table): Add RDPID instruction.
47 * i386-gen.c (cpu_flag_init): Add RDPID flag.
48 (cpu_flags): Add RDPID bitfield.
49 * i386-opc.h (enum): Add RDPID element.
50 (i386_cpu_flags): Add RDPID field.
51 * i386-opc.tbl: Add RDPID instruction.
52 * i386-init.h: Regenerate.
53 * i386-tbl.h: Regenerate.
54
552016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
56
57 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
58 branch type of a symbol.
59 (print_insn): Likewise.
60
612016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
62
63 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
64 Mainline Security Extensions instructions.
65 (thumb_opcodes): Add entries for narrow ARMv8-M Security
66 Extensions instructions.
67 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
68 instructions.
69 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
70 special registers.
71
722016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
73
74 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
75
762016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
77
78 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
79 (arcExtMap_genOpcode): Likewise.
80 * arc-opc.c (arg_32bit_rc): Define new variable.
81 (arg_32bit_u6): Likewise.
82 (arg_32bit_limm): Likewise.
83
842016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
85
86 * aarch64-gen.c (VERIFIER): Define.
87 * aarch64-opc.c (VERIFIER): Define.
88 (verify_ldpsw): Use static linkage.
89 * aarch64-opc.h (verify_ldpsw): Remove.
90 * aarch64-tbl.h: Use VERIFIER for verifiers.
91
922016-04-28 Nick Clifton <nickc@redhat.com>
93
94 PR target/19722
95 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
96 * aarch64-opc.c (verify_ldpsw): New function.
97 * aarch64-opc.h (verify_ldpsw): New prototype.
98 * aarch64-tbl.h: Add initialiser for verifier field.
99 (LDPSW): Set verifier to verify_ldpsw.
100
1012016-04-23 H.J. Lu <hongjiu.lu@intel.com>
102
103 PR binutils/19983
104 PR binutils/19984
105 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
106 smaller than address size.
107
1082016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
109
110 * alpha-dis.c: Regenerate.
111 * crx-dis.c: Likewise.
112 * disassemble.c: Likewise.
113 * epiphany-opc.c: Likewise.
114 * fr30-opc.c: Likewise.
115 * frv-opc.c: Likewise.
116 * ip2k-opc.c: Likewise.
117 * iq2000-opc.c: Likewise.
118 * lm32-opc.c: Likewise.
119 * lm32-opinst.c: Likewise.
120 * m32c-opc.c: Likewise.
121 * m32r-opc.c: Likewise.
122 * m32r-opinst.c: Likewise.
123 * mep-opc.c: Likewise.
124 * mt-opc.c: Likewise.
125 * or1k-opc.c: Likewise.
126 * or1k-opinst.c: Likewise.
127 * tic80-opc.c: Likewise.
128 * xc16x-opc.c: Likewise.
129 * xstormy16-opc.c: Likewise.
130
1312016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
132
133 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
134 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
135 calcsd, and calcxd instructions.
136 * arc-opc.c (insert_nps_bitop_size): Delete.
137 (extract_nps_bitop_size): Delete.
138 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
139 (extract_nps_qcmp_m3): Define.
140 (extract_nps_qcmp_m2): Define.
141 (extract_nps_qcmp_m1): Define.
142 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
143 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
144 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
145 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
146 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
147 NPS_QCMP_M3.
148
1492016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
150
151 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
152
1532016-04-15 H.J. Lu <hongjiu.lu@intel.com>
154
155 * Makefile.in: Regenerated with automake 1.11.6.
156 * aclocal.m4: Likewise.
157
1582016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
159
160 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
161 instructions.
162 * arc-opc.c (insert_nps_cmem_uimm16): New function.
163 (extract_nps_cmem_uimm16): New function.
164 (arc_operands): Add NPS_XLDST_UIMM16 operand.
165
1662016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
167
168 * arc-dis.c (arc_insn_length): New function.
169 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
170 (find_format): Change insnLen parameter to unsigned.
171
1722016-04-13 Nick Clifton <nickc@redhat.com>
173
174 PR target/19937
175 * v850-opc.c (v850_opcodes): Correct masks for long versions of
176 the LD.B and LD.BU instructions.
177
1782016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
179
180 * arc-dis.c (find_format): Check for extension flags.
181 (print_flags): New function.
182 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
183 .extAuxRegister.
184 * arc-ext.c (arcExtMap_coreRegName): Use
185 LAST_EXTENSION_CORE_REGISTER.
186 (arcExtMap_coreReadWrite): Likewise.
187 (dump_ARC_extmap): Update printing.
188 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
189 (arc_aux_regs): Add cpu field.
190 * arc-regs.h: Add cpu field, lower case name aux registers.
191
1922016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
193
194 * arc-tbl.h: Add rtsc, sleep with no arguments.
195
1962016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
197
198 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
199 Initialize.
200 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
201 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
202 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
203 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
204 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
205 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
206 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
207 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
208 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
209 (arc_opcode arc_opcodes): Null terminate the array.
210 (arc_num_opcodes): Remove.
211 * arc-ext.h (INSERT_XOP): Define.
212 (extInstruction_t): Likewise.
213 (arcExtMap_instName): Delete.
214 (arcExtMap_insn): New function.
215 (arcExtMap_genOpcode): Likewise.
216 * arc-ext.c (ExtInstruction): Remove.
217 (create_map): Zero initialize instruction fields.
218 (arcExtMap_instName): Remove.
219 (arcExtMap_insn): New function.
220 (dump_ARC_extmap): More info while debuging.
221 (arcExtMap_genOpcode): New function.
222 * arc-dis.c (find_format): New function.
223 (print_insn_arc): Use find_format.
224 (arc_get_disassembler): Enable dump_ARC_extmap only when
225 debugging.
226
2272016-04-11 Maciej W. Rozycki <macro@imgtec.com>
228
229 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
230 instruction bits out.
231
2322016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
233
234 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
235 * arc-opc.c (arc_flag_operands): Add new flags.
236 (arc_flag_classes): Add new classes.
237
2382016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
239
240 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
241
2422016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
243
244 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
245 encode1, rflt, crc16, and crc32 instructions.
246 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
247 (arc_flag_classes): Add C_NPS_R.
248 (insert_nps_bitop_size_2b): New function.
249 (extract_nps_bitop_size_2b): Likewise.
250 (insert_nps_bitop_uimm8): Likewise.
251 (extract_nps_bitop_uimm8): Likewise.
252 (arc_operands): Add new operand entries.
253
2542016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
255
256 * arc-regs.h: Add a new subclass field. Add double assist
257 accumulator register values.
258 * arc-tbl.h: Use DPA subclass to mark the double assist
259 instructions. Use DPX/SPX subclas to mark the FPX instructions.
260 * arc-opc.c (RSP): Define instead of SP.
261 (arc_aux_regs): Add the subclass field.
262
2632016-04-05 Jiong Wang <jiong.wang@arm.com>
264
265 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
266
2672016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
268
269 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
270 NPS_R_SRC1.
271
2722016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
273
274 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
275 issues. No functional changes.
276
2772016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
278
279 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
280 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
281 (RTT): Remove duplicate.
282 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
283 (PCT_CONFIG*): Remove.
284 (D1L, D1H, D2H, D2L): Define.
285
2862016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
287
288 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
289
2902016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
291
292 * arc-tbl.h (invld07): Remove.
293 * arc-ext-tbl.h: New file.
294 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
295 * arc-opc.c (arc_opcodes): Add ext-tbl include.
296
2972016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
298
299 Fix -Wstack-usage warnings.
300 * aarch64-dis.c (print_operands): Substitute size.
301 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
302
3032016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
304
305 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
306 to get a proper diagnostic when an invalid ASR register is used.
307
3082016-03-22 Nick Clifton <nickc@redhat.com>
309
310 * configure: Regenerate.
311
3122016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
313
314 * arc-nps400-tbl.h: New file.
315 * arc-opc.c: Add top level comment.
316 (insert_nps_3bit_dst): New function.
317 (extract_nps_3bit_dst): New function.
318 (insert_nps_3bit_src2): New function.
319 (extract_nps_3bit_src2): New function.
320 (insert_nps_bitop_size): New function.
321 (extract_nps_bitop_size): New function.
322 (arc_flag_operands): Add nps400 entries.
323 (arc_flag_classes): Add nps400 entries.
324 (arc_operands): Add nps400 entries.
325 (arc_opcodes): Add nps400 include.
326
3272016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
328
329 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
330 the new class enum values.
331
3322016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
333
334 * arc-dis.c (print_insn_arc): Handle nps400.
335
3362016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
337
338 * arc-opc.c (BASE): Delete.
339
3402016-03-18 Nick Clifton <nickc@redhat.com>
341
342 PR target/19721
343 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
344 of MOV insn that aliases an ORR insn.
345
3462016-03-16 Jiong Wang <jiong.wang@arm.com>
347
348 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
349
3502016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
351
352 * mcore-opc.h: Add const qualifiers.
353 * microblaze-opc.h (struct op_code_struct): Likewise.
354 * sh-opc.h: Likewise.
355 * tic4x-dis.c (tic4x_print_indirect): Likewise.
356 (tic4x_print_op): Likewise.
357
3582016-03-02 Alan Modra <amodra@gmail.com>
359
360 * or1k-desc.h: Regenerate.
361 * fr30-ibld.c: Regenerate.
362 * rl78-decode.c: Regenerate.
363
3642016-03-01 Nick Clifton <nickc@redhat.com>
365
366 PR target/19747
367 * rl78-dis.c (print_insn_rl78_common): Fix typo.
368
3692016-02-24 Renlin Li <renlin.li@arm.com>
370
371 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
372 (print_insn_coprocessor): Support fp16 instructions.
373
3742016-02-24 Renlin Li <renlin.li@arm.com>
375
376 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
377 vminnm, vrint(mpna).
378
3792016-02-24 Renlin Li <renlin.li@arm.com>
380
381 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
382 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
383
3842016-02-15 H.J. Lu <hongjiu.lu@intel.com>
385
386 * i386-dis.c (print_insn): Parenthesize expression to prevent
387 truncated addresses.
388 (OP_J): Likewise.
389
3902016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
391 Janek van Oirschot <jvanoirs@synopsys.com>
392
393 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
394 variable.
395
3962016-02-04 Nick Clifton <nickc@redhat.com>
397
398 PR target/19561
399 * msp430-dis.c (print_insn_msp430): Add a special case for
400 decoding an RRC instruction with the ZC bit set in the extension
401 word.
402
4032016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
404
405 * cgen-ibld.in (insert_normal): Rework calculation of shift.
406 * epiphany-ibld.c: Regenerate.
407 * fr30-ibld.c: Regenerate.
408 * frv-ibld.c: Regenerate.
409 * ip2k-ibld.c: Regenerate.
410 * iq2000-ibld.c: Regenerate.
411 * lm32-ibld.c: Regenerate.
412 * m32c-ibld.c: Regenerate.
413 * m32r-ibld.c: Regenerate.
414 * mep-ibld.c: Regenerate.
415 * mt-ibld.c: Regenerate.
416 * or1k-ibld.c: Regenerate.
417 * xc16x-ibld.c: Regenerate.
418 * xstormy16-ibld.c: Regenerate.
419
4202016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
421
422 * epiphany-dis.c: Regenerated from latest cpu files.
423
4242016-02-01 Michael McConville <mmcco@mykolab.com>
425
426 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
427 test bit.
428
4292016-01-25 Renlin Li <renlin.li@arm.com>
430
431 * arm-dis.c (mapping_symbol_for_insn): New function.
432 (find_ifthen_state): Call mapping_symbol_for_insn().
433
4342016-01-20 Matthew Wahab <matthew.wahab@arm.com>
435
436 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
437 of MSR UAO immediate operand.
438
4392016-01-18 Maciej W. Rozycki <macro@imgtec.com>
440
441 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
442 instruction support.
443
4442016-01-17 Alan Modra <amodra@gmail.com>
445
446 * configure: Regenerate.
447
4482016-01-14 Nick Clifton <nickc@redhat.com>
449
450 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
451 instructions that can support stack pointer operations.
452 * rl78-decode.c: Regenerate.
453 * rl78-dis.c: Fix display of stack pointer in MOVW based
454 instructions.
455
4562016-01-14 Matthew Wahab <matthew.wahab@arm.com>
457
458 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
459 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
460 erxtatus_el1 and erxaddr_el1.
461
4622016-01-12 Matthew Wahab <matthew.wahab@arm.com>
463
464 * arm-dis.c (arm_opcodes): Add "esb".
465 (thumb_opcodes): Likewise.
466
4672016-01-11 Peter Bergner <bergner@vnet.ibm.com>
468
469 * ppc-opc.c <xscmpnedp>: Delete.
470 <xvcmpnedp>: Likewise.
471 <xvcmpnedp.>: Likewise.
472 <xvcmpnesp>: Likewise.
473 <xvcmpnesp.>: Likewise.
474
4752016-01-08 Andreas Schwab <schwab@linux-m68k.org>
476
477 PR gas/13050
478 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
479 addition to ISA_A.
480
4812016-01-01 Alan Modra <amodra@gmail.com>
482
483 Update year range in copyright notice of all files.
484
485For older changes see ChangeLog-2015
486\f
487Copyright (C) 2016 Free Software Foundation, Inc.
488
489Copying and distribution of this file, with or without modification,
490are permitted in any medium without royalty provided the copyright
491notice and this notice are preserved.
492
493Local Variables:
494mode: change-log
495left-margin: 8
496fill-column: 74
497version-control: never
498End:
GDB Binutils - Deliverables
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