| | 1 | 2017-06-29 Maciej W. Rozycki <macro@imgtec.com> |
| | 2 | |
| | 3 | * mips-dis.c (mips_calculate_combination_ases): New function. |
| | 4 | (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT |
| | 5 | calculation to the new function. |
| | 6 | (set_default_mips_dis_options): Call the new function. |
| | 7 | |
| | 8 | 2017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com> |
| | 9 | |
| | 10 | * arc-dis.c (parse_disassembler_options): Use |
| | 11 | FOR_EACH_DISASSEMBLER_OPTION. |
| | 12 | |
| | 13 | 2017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com> |
| | 14 | |
| | 15 | * arc-dis.c (parse_option): Use disassembler_options_cmp to compare |
| | 16 | disassembler option strings. |
| | 17 | (parse_cpu_option): Likewise. |
| | 18 | |
| | 19 | 2017-06-28 Tamar Christina <tamar.christina@arm.com> |
| | 20 | |
| | 21 | * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod. |
| | 22 | * aarch64-dis.c (aarch64_ext_reglane): Likewise. |
| | 23 | * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New. |
| | 24 | (aarch64_feature_dotprod, DOT_INSN): New. |
| | 25 | (udot, sdot): New. |
| | 26 | * aarch64-dis-2.c: Regenerated. |
| | 27 | |
| | 28 | 2017-06-28 Jiong Wang <jiong.wang@arm.com> |
| | 29 | |
| | 30 | * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot. |
| | 31 | |
| | 32 | 2017-06-28 Maciej W. Rozycki <macro@imgtec.com> |
| | 33 | Matthew Fortune <matthew.fortune@imgtec.com> |
| | 34 | Andrew Bennett <andrew.bennett@imgtec.com> |
| | 35 | |
| | 36 | * mips-formats.h (INT_BIAS): New macro. |
| | 37 | (INT_ADJ): Redefine in INT_BIAS terms. |
| | 38 | * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry. |
| | 39 | (mips_print_save_restore): New function. |
| | 40 | (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment. |
| | 41 | (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort' |
| | 42 | call. |
| | 43 | (print_insn_args): Handle OP_SAVE_RESTORE_LIST. |
| | 44 | (print_mips16_insn_arg): Call `mips_print_save_restore' for |
| | 45 | OP_SAVE_RESTORE_LIST handling, factored out from here. |
| | 46 | * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case. |
| | 47 | (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros. |
| | 48 | (mips_builtin_opcodes): Add "restore" and "save" entries. |
| | 49 | * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases. |
| | 50 | (IAMR2): New macro. |
| | 51 | (mips16_opcodes): Add "copyw" and "ucopyw" entries. |
| | 52 | |
| | 53 | 2017-06-23 Andrew Waterman <andrew@sifive.com> |
| | 54 | |
| | 55 | * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an |
| | 56 | alias; do not mark SLTI instruction as an alias. |
| | 57 | |
| | 58 | 2017-06-21 H.J. Lu <hongjiu.lu@intel.com> |
| | 59 | |
| | 60 | * i386-dis.c (RM_0FAE_REG_5): Removed. |
| | 61 | (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise. |
| | 62 | (PREFIX_MOD_3_0F01_REG_5_RM_0): New. |
| | 63 | (PREFIX_MOD_3_0FAE_REG_5): Likewise. |
| | 64 | (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1. Add |
| | 65 | PREFIX_MOD_3_0F01_REG_5_RM_0. |
| | 66 | (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5. Add |
| | 67 | PREFIX_MOD_3_0FAE_REG_5. |
| | 68 | (mod_table): Update MOD_0FAE_REG_5. |
| | 69 | (rm_table): Update RM_0F01_REG_5. Remove RM_0FAE_REG_5. |
| | 70 | * i386-opc.tbl: Update incsspd, incsspq and setssbsy. |
| | 71 | * i386-tbl.h: Regenerated. |
| | 72 | |
| | 73 | 2017-06-21 H.J. Lu <hongjiu.lu@intel.com> |
| | 74 | |
| | 75 | * i386-dis.c (prefix_table): Replace savessp with saveprevssp. |
| | 76 | * i386-opc.tbl: Likewise. |
| | 77 | * i386-tbl.h: Regenerated. |
| | 78 | |
| | 79 | 2017-06-21 H.J. Lu <hongjiu.lu@intel.com> |
| | 80 | |
| | 81 | * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}" |
| | 82 | and "jmp{&|}". |
| | 83 | (NOTRACK_Fixup): Support memory indirect branch with NOTRACK |
| | 84 | prefix. |
| | 85 | |
| | 86 | 2017-06-19 Nick Clifton <nickc@redhat.com> |
| | 87 | |
| | 88 | PR binutils/21614 |
| | 89 | * score-dis.c (score_opcodes): Add sentinel. |
| | 90 | |
| | 91 | 2017-06-16 Alan Modra <amodra@gmail.com> |
| | 92 | |
| | 93 | * rx-decode.c: Regenerate. |
| | 94 | |
| | 95 | 2017-06-15 H.J. Lu <hongjiu.lu@intel.com> |
| | 96 | |
| | 97 | PR binutils/21594 |
| | 98 | * i386-dis.c (OP_E_register): Check valid bnd register. |
| | 99 | (OP_G): Likewise. |
| | 100 | |
| | 101 | 2017-06-15 Nick Clifton <nickc@redhat.com> |
| | 102 | |
| | 103 | PR binutils/21595 |
| | 104 | * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of |
| | 105 | range value. |
| | 106 | |
| | 107 | 2017-06-15 Nick Clifton <nickc@redhat.com> |
| | 108 | |
| | 109 | PR binutils/21588 |
| | 110 | * rl78-decode.opc (OP_BUF_LEN): Define. |
| | 111 | (GETBYTE): Check for the index exceeding OP_BUF_LEN. |
| | 112 | (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf |
| | 113 | array. |
| | 114 | * rl78-decode.c: Regenerate. |
| | 115 | |
| | 116 | 2017-06-15 Nick Clifton <nickc@redhat.com> |
| | 117 | |
| | 118 | PR binutils/21586 |
| | 119 | * bfin-dis.c (gregs): Clip index to prevent overflow. |
| | 120 | (regs): Likewise. |
| | 121 | (regs_lo): Likewise. |
| | 122 | (regs_hi): Likewise. |
| | 123 | |
| | 124 | 2017-06-14 Nick Clifton <nickc@redhat.com> |
| | 125 | |
| | 126 | PR binutils/21576 |
| | 127 | * score7-dis.c (score_opcodes): Add sentinel. |
| | 128 | |
| | 129 | 2017-06-14 Yao Qi <yao.qi@linaro.org> |
| | 130 | |
| | 131 | * aarch64-dis.c: Include disassemble.h instead of dis-asm.h. |
| | 132 | * arm-dis.c: Likewise. |
| | 133 | * ia64-dis.c: Likewise. |
| | 134 | * mips-dis.c: Likewise. |
| | 135 | * spu-dis.c: Likewise. |
| | 136 | * disassemble.h (print_insn_aarch64): New declaration, moved from |
| | 137 | include/dis-asm.h. |
| | 138 | (print_insn_big_arm, print_insn_big_mips): Likewise. |
| | 139 | (print_insn_i386, print_insn_ia64): Likewise. |
| | 140 | (print_insn_little_arm, print_insn_little_mips): Likewise. |
| | 141 | |
| | 142 | 2017-06-14 Nick Clifton <nickc@redhat.com> |
| | 143 | |
| | 144 | PR binutils/21587 |
| | 145 | * rx-decode.opc: Include libiberty.h |
| | 146 | (GET_SCALE): New macro - validates access to SCALE array. |
| | 147 | (GET_PSCALE): New macro - validates access to PSCALE array. |
| | 148 | (DIs, SIs, S2Is, rx_disp): Use new macros. |
| | 149 | * rx-decode.c: Regenerate. |
| | 150 | |
| | 151 | 2017-07-14 Andre Vieira <andre.simoesdiasvieira@arm.com> |
| | 152 | |
| | 153 | * arm-dis.c (print_insn_arm): Remove bogus entry for bx. |
| | 154 | |
| | 155 | 2017-05-30 Anton Kolesov <anton.kolesov@synopsys.com> |
| | 156 | |
| | 157 | * arc-dis.c (enforced_isa_mask): Declare. |
| | 158 | (cpu_types): Likewise. |
| | 159 | (parse_cpu_option): New function. |
| | 160 | (parse_disassembler_options): Use it. |
| | 161 | (print_insn_arc): Use enforced_isa_mask. |
| | 162 | (print_arc_disassembler_options): Document new options. |
| | 163 | |
| | 164 | 2017-05-24 Yao Qi <yao.qi@linaro.org> |
| | 165 | |
| | 166 | * alpha-dis.c: Include disassemble.h, don't include |
| | 167 | dis-asm.h. |
| | 168 | * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise. |
| | 169 | * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise. |
| | 170 | * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise. |
| | 171 | * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise. |
| | 172 | * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise. |
| | 173 | * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise. |
| | 174 | * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise. |
| | 175 | * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise. |
| | 176 | * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise. |
| | 177 | * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise. |
| | 178 | * moxie-dis.c, msp430-dis.c, mt-dis.c: |
| | 179 | * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise. |
| | 180 | * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise. |
| | 181 | * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise. |
| | 182 | * rl78-dis.c, s390-dis.c, score-dis.c: Likewise. |
| | 183 | * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise. |
| | 184 | * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise. |
| | 185 | * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise. |
| | 186 | * v850-dis.c, vax-dis.c, visium-dis.c: Likewise. |
| | 187 | * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise. |
| | 188 | * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise. |
| | 189 | * z80-dis.c, z8k-dis.c: Likewise. |
| | 190 | * disassemble.h: New file. |
| | 191 | |
| | 192 | 2017-05-24 Yao Qi <yao.qi@linaro.org> |
| | 193 | |
| | 194 | * rl78-dis.c (rl78_get_disassembler): If parameter abfd |
| | 195 | is NULL, set cpu to E_FLAG_RL78_ANY_CPU. |
| | 196 | |
| | 197 | 2017-05-24 Yao Qi <yao.qi@linaro.org> |
| | 198 | |
| | 199 | * disassemble.c (disassembler): Add arguments a, big and mach. |
| | 200 | Use them. |
| | 201 | |
| | 202 | 2017-05-22 H.J. Lu <hongjiu.lu@intel.com> |
| | 203 | |
| | 204 | * i386-dis.c (NOTRACK_Fixup): New. |
| | 205 | (NOTRACK): Likewise. |
| | 206 | (NOTRACK_PREFIX): Likewise. |
| | 207 | (last_active_prefix): Likewise. |
| | 208 | (reg_table): Use NOTRACK on indirect call and jmp. |
| | 209 | (ckprefix): Set last_active_prefix. |
| | 210 | (prefix_name): Return "notrack" for NOTRACK_PREFIX. |
| | 211 | * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk. |
| | 212 | * i386-opc.h (NoTrackPrefixOk): New. |
| | 213 | (i386_opcode_modifier): Add notrackprefixok. |
| | 214 | * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp. |
| | 215 | Add notrack. |
| | 216 | * i386-tbl.h: Regenerated. |
| | 217 | |
| | 218 | 2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com> |
| | 219 | |
| | 220 | * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8. |
| | 221 | (X_IMM2): Define. |
| | 222 | (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and |
| | 223 | bfd_mach_sparc_v9m8. |
| | 224 | (print_insn_sparc): Handle new operand types. |
| | 225 | * sparc-opc.c (MASK_M8): Define. |
| | 226 | (v6): Add MASK_M8. |
| | 227 | (v6notlet): Likewise. |
| | 228 | (v7): Likewise. |
| | 229 | (v8): Likewise. |
| | 230 | (v9): Likewise. |
| | 231 | (v9a): Likewise. |
| | 232 | (v9b): Likewise. |
| | 233 | (v9c): Likewise. |
| | 234 | (v9d): Likewise. |
| | 235 | (v9e): Likewise. |
| | 236 | (v9v): Likewise. |
| | 237 | (v9m): Likewise. |
| | 238 | (v9andleon): Likewise. |
| | 239 | (m8): Define. |
| | 240 | (HWS_VM8): Define. |
| | 241 | (HWS2_VM8): Likewise. |
| | 242 | (sparc_opcode_archs): Add entry for "m8". |
| | 243 | (sparc_opcodes): Add OSA2017 and M8 instructions |
| | 244 | dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl, |
| | 245 | fpx{ll,ra,rl}64x, |
| | 246 | ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d}, |
| | 247 | ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb, |
| | 248 | revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x}, |
| | 249 | stm{h,w,x}a, stmf{s,d}, stmf{s,d}a. |
| | 250 | (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT, |
| | 251 | ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR, |
| | 252 | ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL, |
| | 253 | ASI_CORE_SELECT_COMMIT_NHT. |
| | 254 | |
| | 255 | 2017-05-18 Alan Modra <amodra@gmail.com> |
| | 256 | |
| | 257 | * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE. |
| | 258 | * aarch64-dis.c: Likewise. |
| | 259 | * aarch64-gen.c: Likewise. |
| | 260 | * aarch64-opc.c: Likewise. |
| | 261 | |
| | 262 | 2017-05-15 Maciej W. Rozycki <macro@imgtec.com> |
| | 263 | Matthew Fortune <matthew.fortune@imgtec.com> |
| | 264 | |
| | 265 | * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and |
| | 266 | ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry. |
| | 267 | (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag. |
| | 268 | (print_insn_arg) <OP_REG28>: Add handler. |
| | 269 | (validate_insn_args) <OP_REG28>: Handle. |
| | 270 | (print_mips16_insn_arg): Handle MIPS16 instructions that require |
| | 271 | 32-bit encoding and 9-bit immediates. |
| | 272 | (print_insn_mips16): Handle MIPS16 instructions that require |
| | 273 | 32-bit encoding and MFC0/MTC0 operand decoding. |
| | 274 | * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'> |
| | 275 | <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers. |
| | 276 | (RD_C0, WR_C0, E2, E2MT): New macros. |
| | 277 | (mips16_opcodes): Add entries for MIPS16e2 instructions: |
| | 278 | GP-relative "addiu" and its "addu" spelling, "andi", "cache", |
| | 279 | "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh", |
| | 280 | "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0", |
| | 281 | "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause", |
| | 282 | "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw" |
| | 283 | instructions, "swl", "swr", "sync" and its "sync_acquire", |
| | 284 | "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases, |
| | 285 | "xori", "dmt", "dvpe", "emt" and "evpe". Add split |
| | 286 | regular/extended entries for original MIPS16 ISA revision |
| | 287 | instructions whose extended forms are subdecoded in the MIPS16e2 |
| | 288 | ISA revision: "li", "sll" and "srl". |
| | 289 | |
| | 290 | 2017-05-15 Maciej W. Rozycki <macro@imgtec.com> |
| | 291 | |
| | 292 | * mips-dis.c (print_insn_args) <default>: Remove an MT ASE |
| | 293 | reference in CP0 move operand decoding. |
| | 294 | |
| | 295 | 2017-05-12 Maciej W. Rozycki <macro@imgtec.com> |
| | 296 | |
| | 297 | * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand |
| | 298 | type to hexadecimal. |
| | 299 | (mips16_opcodes): Add operandless "break" and "sdbbp" entries. |
| | 300 | |
| | 301 | 2017-05-11 Maciej W. Rozycki <macro@imgtec.com> |
| | 302 | |
| | 303 | * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs", |
| | 304 | "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release", |
| | 305 | "sync_rmb" and "sync_wmb" as aliases. |
| | 306 | * micromips-opc.c (micromips_opcodes): Mark "sync_acquire", |
| | 307 | "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases. |
| | 308 | |
| | 309 | 2017-05-10 Claudiu Zissulescu <claziss@synopsys.com> |
| | 310 | |
| | 311 | * arc-dis.c (parse_option): Update quarkse_em option.. |
| | 312 | * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to |
| | 313 | QUARKSE1. |
| | 314 | (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2. |
| | 315 | |
| | 316 | 2017-05-03 Kito Cheng <kito.cheng@gmail.com> |
| | 317 | |
| | 318 | * riscv-dis.c (print_insn_args): Handle 'Co' operands. |
| | 319 | |
| | 320 | 2017-05-01 Michael Clark <michaeljclark@mac.com> |
| | 321 | |
| | 322 | * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary |
| | 323 | register. |
| | 324 | |
| | 325 | 2017-05-02 Maciej W. Rozycki <macro@imgtec.com> |
| | 326 | |
| | 327 | * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps |
| | 328 | and branches and not synthetic data instructions. |
| | 329 | |
| | 330 | 2017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de> |
| | 331 | |
| | 332 | * arm-dis.c (print_insn_thumb32): Fix value_in_comment. |
| | 333 | |
| | 334 | 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com> |
| | 335 | |
| | 336 | * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics. |
| | 337 | * arc-opc.c (insert_r13el): New function. |
| | 338 | (R13_EL): Define. |
| | 339 | * arc-tbl.h: Add new enter/leave variants. |
| | 340 | |
| | 341 | 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com> |
| | 342 | |
| | 343 | * arc-tbl.h: Reorder NOP entry to be before MOV instructions. |
| | 344 | |
| | 345 | 2017-04-25 Maciej W. Rozycki <macro@imgtec.com> |
| | 346 | |
| | 347 | * mips-dis.c (print_mips_disassembler_options): Add |
| | 348 | `no-aliases'. |
| | 349 | |
| | 350 | 2017-04-25 Maciej W. Rozycki <macro@imgtec.com> |
| | 351 | |
| | 352 | * mips16-opc.c (AL): New macro. |
| | 353 | (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms |
| | 354 | of "ld" and "lw" as aliases. |
| | 355 | |
| | 356 | 2017-04-24 Tamar Christina <tamar.christina@arm.com> |
| | 357 | |
| | 358 | * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE |
| | 359 | arguments. |
| | 360 | |
| | 361 | 2017-04-22 Alexander Fedotov <alfedotov@gmail.com> |
| | 362 | Alan Modra <amodra@gmail.com> |
| | 363 | |
| | 364 | * ppc-opc.c (ELEV): Define. |
| | 365 | (vle_opcodes): Add se_rfgi and e_sc. |
| | 366 | (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx |
| | 367 | for E200Z4. |
| | 368 | |
| | 369 | 2017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com> |
| | 370 | |
| | 371 | * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9. |
| | 372 | |
| | 373 | 2017-04-21 Nick Clifton <nickc@redhat.com> |
| | 374 | |
| | 375 | PR binutils/21380 |
| | 376 | * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R, |
| | 377 | LD3R and LD4R. |
| | 378 | |
| | 379 | 2017-04-13 Alan Modra <amodra@gmail.com> |
| | 380 | |
| | 381 | * epiphany-desc.c: Regenerate. |
| | 382 | * fr30-desc.c: Regenerate. |
| | 383 | * frv-desc.c: Regenerate. |
| | 384 | * ip2k-desc.c: Regenerate. |
| | 385 | * iq2000-desc.c: Regenerate. |
| | 386 | * lm32-desc.c: Regenerate. |
| | 387 | * m32c-desc.c: Regenerate. |
| | 388 | * m32r-desc.c: Regenerate. |
| | 389 | * mep-desc.c: Regenerate. |
| | 390 | * mt-desc.c: Regenerate. |
| | 391 | * or1k-desc.c: Regenerate. |
| | 392 | * xc16x-desc.c: Regenerate. |
| | 393 | * xstormy16-desc.c: Regenerate. |
| | 394 | |
| | 395 | 2017-04-11 Alan Modra <amodra@gmail.com> |
| | 396 | |
| | 397 | * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2, |
| | 398 | PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set |
| | 399 | PPC_OPCODE_TMR for e6500. |
| | 400 | * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500. |
| | 401 | (PPCVEC3): Define as PPC_OPCODE_POWER9. |
| | 402 | (PPCVSX2): Define as PPC_OPCODE_POWER8. |
| | 403 | (PPCVSX3): Define as PPC_OPCODE_POWER9. |
| | 404 | (PPCHTM): Define as PPC_OPCODE_POWER8. |
| | 405 | (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500. |
| | 406 | |
| | 407 | 2017-04-10 Alan Modra <amodra@gmail.com> |
| | 408 | |
| | 409 | * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440. |
| | 410 | * ppc-opc.c (MULHW): Add PPC_OPCODE_476. |
| | 411 | (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit |
| | 412 | removal of PPC_OPCODE_440 from ppc476 cpu selection bits. |
| | 413 | |
| | 414 | 2017-04-09 Pip Cet <pipcet@gmail.com> |
| | 415 | |
| | 416 | * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify |
| | 417 | appropriate floating-point precision directly. |
| | 418 | |
| | 419 | 2017-04-07 Alan Modra <amodra@gmail.com> |
| | 420 | |
| | 421 | * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl, |
| | 422 | lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx, |
| | 423 | lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx, |
| | 424 | lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only |
| | 425 | vector instructions with E6500 not PPCVEC2. |
| | 426 | |
| | 427 | 2017-04-06 Pip Cet <pipcet@gmail.com> |
| | 428 | |
| | 429 | * Makefile.am: Add wasm32-dis.c. |
| | 430 | * configure.ac: Add wasm32-dis.c to wasm32 target. |
| | 431 | * disassemble.c: Add wasm32 disassembler code. |
| | 432 | * wasm32-dis.c: New file. |
| | 433 | * Makefile.in: Regenerate. |
| | 434 | * configure: Regenerate. |
| | 435 | * po/POTFILES.in: Regenerate. |
| | 436 | * po/opcodes.pot: Regenerate. |
| | 437 | |
| | 438 | 2017-04-05 Pedro Alves <palves@redhat.com> |
| | 439 | |
| | 440 | * arc-dis.c (parse_option, parse_disassembler_options): Constify. |
| | 441 | * arm-dis.c (parse_arm_disassembler_options): Constify. |
| | 442 | * ppc-dis.c (powerpc_init_dialect): Constify local. |
| | 443 | * vax-dis.c (parse_disassembler_options): Constify. |
| | 444 | |
| | 445 | 2017-04-03 Palmer Dabbelt <palmer@dabbelt.com> |
| | 446 | |
| | 447 | * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to |
| | 448 | RISCV_GP_SYMBOL. |
| | 449 | |
| | 450 | 2017-03-30 Pip Cet <pipcet@gmail.com> |
| | 451 | |
| | 452 | * configure.ac: Add (empty) bfd_wasm32_arch target. |
| | 453 | * configure: Regenerate |
| | 454 | * po/opcodes.pot: Regenerate. |
| | 455 | |
| | 456 | 2017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com> |
| | 457 | |
| | 458 | Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, & |
| | 459 | OSA2015. |
| | 460 | * opcodes/sparc-opc.c (asi_table): New ASIs. |
| | 461 | |
| | 462 | 2017-03-29 Alan Modra <amodra@gmail.com> |
| | 463 | |
| | 464 | * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add |
| | 465 | "raw" option. |
| | 466 | (lookup_powerpc): Don't special case -1 dialect. Handle |
| | 467 | PPC_OPCODE_RAW. |
| | 468 | (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first |
| | 469 | lookup_powerpc call, pass it on second. |
| | 470 | |
| | 471 | 2017-03-27 Alan Modra <amodra@gmail.com> |
| | 472 | |
| | 473 | PR 21303 |
| | 474 | * ppc-dis.c (struct ppc_mopt): Comment. |
| | 475 | (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu. |
| | 476 | |
| | 477 | 2017-03-27 Rinat Zelig <rinat@mellanox.com> |
| | 478 | |
| | 479 | * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format. |
| | 480 | * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR, |
| | 481 | F_NPS_M, F_NPS_CORE, F_NPS_ALL. |
| | 482 | (insert_nps_misc_imm_offset): New function. |
| | 483 | (extract_nps_misc imm_offset): New function. |
| | 484 | (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T. |
| | 485 | (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T. |
| | 486 | |
| | 487 | 2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com> |
| | 488 | |
| | 489 | * s390-mkopc.c (main): Remove vx2 check. |
| | 490 | * s390-opc.txt: Remove vx2 instruction flags. |
| | 491 | |
| | 492 | 2017-03-21 Rinat Zelig <rinat@mellanox.com> |
| | 493 | |
| | 494 | * arc-nps400-tbl.h: Add cp32/cp16 instructions format. |
| | 495 | * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET. |
| | 496 | (insert_nps_imm_offset): New function. |
| | 497 | (extract_nps_imm_offset): New function. |
| | 498 | (insert_nps_imm_entry): New function. |
| | 499 | (extract_nps_imm_entry): New function. |
| | 500 | |
| | 501 | 2017-03-17 Alan Modra <amodra@gmail.com> |
| | 502 | |
| | 503 | PR 21248 |
| | 504 | * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33, |
| | 505 | mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after |
| | 506 | those spr mnemonics they alias. Similarly for mtibatl, mtibatu. |
| | 507 | |
| | 508 | 2017-03-14 Kito Cheng <kito.cheng@gmail.com> |
| | 509 | |
| | 510 | * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding. |
| | 511 | <c.andi>: Likewise. |
| | 512 | <c.addiw> Likewise. |
| | 513 | |
| | 514 | 2017-03-14 Kito Cheng <kito.cheng@gmail.com> |
| | 515 | |
| | 516 | * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode. |
| | 517 | |
| | 518 | 2017-03-13 Andrew Waterman <andrew@sifive.com> |
| | 519 | |
| | 520 | * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode. |
| | 521 | <srl> Likewise. |
| | 522 | <srai> Likewise. |
| | 523 | <sra> Likewise. |
| | 524 | |
| | 525 | 2017-03-09 H.J. Lu <hongjiu.lu@intel.com> |
| | 526 | |
| | 527 | * i386-gen.c (opcode_modifiers): Replace S with Load. |
| | 528 | * i386-opc.h (S): Removed. |
| | 529 | (Load): New. |
| | 530 | (i386_opcode_modifier): Replace s with load. |
| | 531 | * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3} |
| | 532 | and {evex}. Replace S with Load. |
| | 533 | * i386-tbl.h: Regenerated. |
| | 534 | |
| | 535 | 2017-03-09 H.J. Lu <hongjiu.lu@intel.com> |
| | 536 | |
| | 537 | * i386-opc.tbl: Use CpuCET on rdsspq. |
| | 538 | * i386-tbl.h: Regenerated. |
| | 539 | |
| | 540 | 2017-03-08 Peter Bergner <bergner@vnet.ibm.com> |
| | 541 | |
| | 542 | * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2; |
| | 543 | <vsx>: Do not use PPC_OPCODE_VSX3; |
| | 544 | |
| | 545 | 2017-03-08 Peter Bergner <bergner@vnet.ibm.com> |
| | 546 | |
| | 547 | * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic. |
| | 548 | |
| | 549 | 2017-03-06 H.J. Lu <hongjiu.lu@intel.com> |
| | 550 | |
| | 551 | * i386-dis.c (REG_0F1E_MOD_3): New enum. |
| | 552 | (MOD_0F1E_PREFIX_1): Likewise. |
| | 553 | (MOD_0F38F5_PREFIX_2): Likewise. |
| | 554 | (MOD_0F38F6_PREFIX_0): Likewise. |
| | 555 | (RM_0F1E_MOD_3_REG_7): Likewise. |
| | 556 | (PREFIX_MOD_0_0F01_REG_5): Likewise. |
| | 557 | (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise. |
| | 558 | (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise. |
| | 559 | (PREFIX_0F1E): Likewise. |
| | 560 | (PREFIX_MOD_0_0FAE_REG_5): Likewise. |
| | 561 | (PREFIX_0F38F5): Likewise. |
| | 562 | (dis386_twobyte): Use PREFIX_0F1E. |
| | 563 | (reg_table): Add REG_0F1E_MOD_3. |
| | 564 | (prefix_table): Add PREFIX_MOD_0_0F01_REG_5, |
| | 565 | PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2, |
| | 566 | PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update |
| | 567 | PREFIX_0FAE_REG_6 and PREFIX_0F38F6. |
| | 568 | (three_byte_table): Use PREFIX_0F38F5. |
| | 569 | (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5. |
| | 570 | Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0. |
| | 571 | (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0, |
| | 572 | RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and |
| | 573 | PREFIX_MOD_3_0F01_REG_5_RM_2. |
| | 574 | * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS. |
| | 575 | (cpu_flags): Add CpuCET. |
| | 576 | * i386-opc.h (CpuCET): New enum. |
| | 577 | (CpuUnused): Commented out. |
| | 578 | (i386_cpu_flags): Add cpucet. |
| | 579 | * i386-opc.tbl: Add Intel CET instructions. |
| | 580 | * i386-init.h: Regenerated. |
| | 581 | * i386-tbl.h: Likewise. |
| | 582 | |
| | 583 | 2017-03-06 Alan Modra <amodra@gmail.com> |
| | 584 | |
| | 585 | PR 21124 |
| | 586 | * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram) |
| | 587 | (extract_raq, extract_ras, extract_rbx): New functions. |
| | 588 | (powerpc_operands): Use opposite corresponding insert function. |
| | 589 | (Q_MASK): Define. |
| | 590 | (powerpc_opcodes): Apply Q_MASK to all quad insns with even |
| | 591 | register restriction. |
| | 592 | |
| | 593 | 2017-02-28 Peter Bergner <bergner@vnet.ibm.com> |
| | 594 | |
| | 595 | * disassemble.c Include "safe-ctype.h". |
| | 596 | (disassemble_init_for_target): Handle s390 init. |
| | 597 | (remove_whitespace_and_extra_commas): New function. |
| | 598 | (disassembler_options_cmp): Likewise. |
| | 599 | * arm-dis.c: Include "libiberty.h". |
| | 600 | (NUM_ELEM): Delete. |
| | 601 | (regnames): Use long disassembler style names. |
| | 602 | Add force-thumb and no-force-thumb options. |
| | 603 | (NUM_ARM_REGNAMES): Rename from this... |
| | 604 | (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE. |
| | 605 | (get_arm_regname_num_options): Delete. |
| | 606 | (set_arm_regname_option): Likewise. |
| | 607 | (get_arm_regnames): Likewise. |
| | 608 | (parse_disassembler_options): Likewise. |
| | 609 | (parse_arm_disassembler_option): Rename from this... |
| | 610 | (parse_arm_disassembler_options): ...to this. Make static. |
| | 611 | Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options. |
| | 612 | (print_insn): Use parse_arm_disassembler_options. |
| | 613 | (disassembler_options_arm): New function. |
| | 614 | (print_arm_disassembler_options): Handle updated regnames. |
| | 615 | * ppc-dis.c: Include "libiberty.h". |
| | 616 | (ppc_opts): Add "32" and "64" entries. |
| | 617 | (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp. |
| | 618 | (powerpc_init_dialect): Add break to switch statement. |
| | 619 | Use new FOR_EACH_DISASSEMBLER_OPTION macro. |
| | 620 | (disassembler_options_powerpc): New function. |
| | 621 | (print_ppc_disassembler_options): Use ARRAY_SIZE. |
| | 622 | Remove printing of "32" and "64". |
| | 623 | * s390-dis.c: Include "libiberty.h". |
| | 624 | (init_flag): Remove unneeded variable. |
| | 625 | (struct s390_options_t): New structure type. |
| | 626 | (options): New structure. |
| | 627 | (init_disasm): Rename from this... |
| | 628 | (disassemble_init_s390): ...to this. Add initializations for |
| | 629 | current_arch_mask and option_use_insn_len_bits_p. Remove init_flag. |
| | 630 | (print_insn_s390): Delete call to init_disasm. |
| | 631 | (disassembler_options_s390): New function. |
| | 632 | (print_s390_disassembler_options): Print using information from |
| | 633 | struct 'options'. |
| | 634 | * po/opcodes.pot: Regenerate. |
| | 635 | |
| | 636 | 2017-02-28 Jan Beulich <jbeulich@suse.com> |
| | 637 | |
| | 638 | * i386-dis.c (PCMPESTR_Fixup): New. |
| | 639 | (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete. |
| | 640 | (prefix_table): Use PCMPESTR_Fixup. |
| | 641 | (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use |
| | 642 | PCMPESTR_Fixup. |
| | 643 | (vex_w_table): Delete VPCMPESTR{I,M} entries. |
| | 644 | * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm): |
| | 645 | Split 64-bit and non-64-bit variants. |
| | 646 | * opcodes/i386-tbl.h: Re-generate. |
| | 647 | |
| | 648 | 2017-02-24 Richard Sandiford <richard.sandiford@arm.com> |
| | 649 | |
| | 650 | * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD) |
| | 651 | (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD) |
| | 652 | (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S) |
| | 653 | (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H) |
| | 654 | (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH) |
| | 655 | (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD) |
| | 656 | (OP_SVE_V_HSD): New macros. |
| | 657 | (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD) |
| | 658 | (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD) |
| | 659 | (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete. |
| | 660 | (aarch64_opcode_table): Add new SVE instructions. |
| | 661 | (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate |
| | 662 | for rotation operands. Add new SVE operands. |
| | 663 | * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter. |
| | 664 | (ins_sve_quad_index): Likewise. |
| | 665 | (ins_imm_rotate): Split into... |
| | 666 | (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters. |
| | 667 | * aarch64-asm.c (aarch64_ins_imm_rotate): Split into... |
| | 668 | (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two |
| | 669 | functions. |
| | 670 | (aarch64_ins_sve_addr_ri_s4): New function. |
| | 671 | (aarch64_ins_sve_quad_index): Likewise. |
| | 672 | (do_misc_encoding): Handle "MOV Zn.Q, Qm". |
| | 673 | * aarch64-asm-2.c: Regenerate. |
| | 674 | * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor. |
| | 675 | (ext_sve_quad_index): Likewise. |
| | 676 | (ext_imm_rotate): Split into... |
| | 677 | (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors. |
| | 678 | * aarch64-dis.c (aarch64_ext_imm_rotate): Split into... |
| | 679 | (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two |
| | 680 | functions. |
| | 681 | (aarch64_ext_sve_addr_ri_s4): New function. |
| | 682 | (aarch64_ext_sve_quad_index): Likewise. |
| | 683 | (aarch64_ext_sve_index): Allow quad indices. |
| | 684 | (do_misc_decoding): Likewise. |
| | 685 | * aarch64-dis-2.c: Regenerate. |
| | 686 | * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New |
| | 687 | aarch64_field_kinds. |
| | 688 | (OPD_F_OD_MASK): Widen by one bit. |
| | 689 | (OPD_F_NO_ZR): Bump accordingly. |
| | 690 | (get_operand_field_width): New function. |
| | 691 | * aarch64-opc.c (fields): Add new SVE fields. |
| | 692 | (operand_general_constraint_met_p): Handle new SVE operands. |
| | 693 | (aarch64_print_operand): Likewise. |
| | 694 | * aarch64-opc-2.c: Regenerate. |
| | 695 | |
| | 696 | 2017-02-24 Richard Sandiford <richard.sandiford@arm.com> |
| | 697 | |
| | 698 | * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with... |
| | 699 | (aarch64_feature_compnum): ...this. |
| | 700 | (SIMD_V8_3): Replace with... |
| | 701 | (COMPNUM): ...this. |
| | 702 | (CNUM_INSN): New macro. |
| | 703 | (aarch64_opcode_table): Use it for the complex number instructions. |
| | 704 | |
| | 705 | 2017-02-24 Jan Beulich <jbeulich@suse.com> |
| | 706 | |
| | 707 | * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST. |
| | 708 | |
| | 709 | 2017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com> |
| | 710 | |
| | 711 | Add support for associating SPARC ASIs with an architecture level. |
| | 712 | * include/opcode/sparc.h (sparc_asi): New sparc_asi struct. |
| | 713 | * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/ |
| | 714 | decoding of SPARC ASIs. |
| | 715 | |
| | 716 | 2017-02-23 Jan Beulich <jbeulich@suse.com> |
| | 717 | |
| | 718 | * i386-dis.c (get_valid_dis386): Don't special case VEX opcode |
| | 719 | 82. For 3-byte VEX only special case opcode 77 in VEX_0F space. |
| | 720 | |
| | 721 | 2017-02-21 Jan Beulich <jbeulich@suse.com> |
| | 722 | |
| | 723 | * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand |
| | 724 | 1 (instead of to itself). Correct typo. |
| | 725 | |
| | 726 | 2017-02-14 Andrew Waterman <andrew@sifive.com> |
| | 727 | |
| | 728 | * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and |
| | 729 | pseudoinstructions. |
| | 730 | |
| | 731 | 2017-02-15 Richard Sandiford <richard.sandiford@arm.com> |
| | 732 | |
| | 733 | * aarch64-opc.c (aarch64_sys_regs): Add SVE registers. |
| | 734 | (aarch64_sys_reg_supported_p): Handle them. |
| | 735 | |
| | 736 | 2017-02-15 Claudiu Zissulescu <claziss@synopsys.com> |
| | 737 | |
| | 738 | * arc-opc.c (UIMM6_20R): Define. |
| | 739 | (SIMM12_20): Use above. |
| | 740 | (SIMM12_20R): Define. |
| | 741 | (SIMM3_5_S): Use above. |
| | 742 | (UIMM7_A32_11R_S): Define. |
| | 743 | (UIMM7_9_S): Use above. |
| | 744 | (UIMM3_13R_S): Define. |
| | 745 | (SIMM11_A32_7_S): Use above. |
| | 746 | (SIMM9_8R): Define. |
| | 747 | (UIMM10_A32_8_S): Use above. |
| | 748 | (UIMM8_8R_S): Define. |
| | 749 | (W6): Use above. |
| | 750 | (arc_relax_opcodes): Use all above defines. |
| | 751 | |
| | 752 | 2017-02-15 Vineet Gupta <vgupta@synopsys.com> |
| | 753 | |
| | 754 | * arc-regs.h: Distinguish some of the registers different on |
| | 755 | ARC700 and HS38 cpus. |
| | 756 | |
| | 757 | 2017-02-14 Alan Modra <amodra@gmail.com> |
| | 758 | |
| | 759 | PR 21118 |
| | 760 | * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries |
| | 761 | with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR. |
| | 762 | |
| | 763 | 2017-02-11 Stafford Horne <shorne@gmail.com> |
| | 764 | Alan Modra <amodra@gmail.com> |
| | 765 | |
| | 766 | * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps. |
| | 767 | Use insn_bytes_value and insn_int_value directly instead. Don't |
| | 768 | free allocated memory until function exit. |
| | 769 | |
| | 770 | 2017-02-10 Nicholas Piggin <npiggin@gmail.com> |
| | 771 | |
| | 772 | * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics. |
| | 773 | |
| | 774 | 2017-02-03 Nick Clifton <nickc@redhat.com> |
| | 775 | |
| | 776 | PR 21096 |
| | 777 | * aarch64-opc.c (print_register_list): Ensure that the register |
| | 778 | list index will fir into the tb buffer. |
| | 779 | (print_register_offset_address): Likewise. |
| | 780 | * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf. |
| | 781 | |
| | 782 | 2017-01-27 Alexis Deruell <alexis.deruelle@gmail.com> |
| | 783 | |
| | 784 | PR 21056 |
| | 785 | * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel |
| | 786 | instructions when the previous fetch packet ends with a 32-bit |
| | 787 | instruction. |
| | 788 | |
| | 789 | 2017-01-24 Dimitar Dimitrov <dimitar@dinux.eu> |
| | 790 | |
| | 791 | * pru-opc.c: Remove vague reference to a future GDB port. |
| | 792 | |
| | 793 | 2017-01-20 Nick Clifton <nickc@redhat.com> |
| | 794 | |
| | 795 | * po/ga.po: Updated Irish translation. |
| | 796 | |
| | 797 | 2017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com> |
| | 798 | |
| | 799 | * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly. |
| | 800 | |
| | 801 | 2017-01-13 Yao Qi <yao.qi@linaro.org> |
| | 802 | |
| | 803 | * m68k-dis.c (match_insn_m68k): Extend comments. Return -1 |
| | 804 | if FETCH_DATA returns 0. |
| | 805 | (m68k_scan_mask): Likewise. |
| | 806 | (print_insn_m68k): Update code to handle -1 return value. |
| | 807 | |
| | 808 | 2017-01-13 Yao Qi <yao.qi@linaro.org> |
| | 809 | |
| | 810 | * m68k-dis.c (enum print_insn_arg_error): New. |
| | 811 | (NEXTBYTE): Replace -3 with |
| | 812 | PRINT_INSN_ARG_MEMORY_ERROR. |
| | 813 | (NEXTULONG): Likewise. |
| | 814 | (NEXTSINGLE): Likewise. |
| | 815 | (NEXTDOUBLE): Likewise. |
| | 816 | (NEXTDOUBLE): Likewise. |
| | 817 | (NEXTPACKED): Likewise. |
| | 818 | (FETCH_ARG): Likewise. |
| | 819 | (FETCH_DATA): Update comments. |
| | 820 | (print_insn_arg): Update comments. Replace magic numbers with |
| | 821 | enum. |
| | 822 | (match_insn_m68k): Likewise. |
| | 823 | |
| | 824 | 2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com> |
| | 825 | |
| | 826 | * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2. |
| | 827 | * i386-dis-evex.h (evex_table): Updated. |
| | 828 | * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS, |
| | 829 | CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS. |
| | 830 | (cpu_flags): Add CpuAVX512_VPOPCNTDQ. |
| | 831 | * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New. |
| | 832 | (i386_cpu_flags): Add cpuavx512_vpopcntdq. |
| | 833 | * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions. |
| | 834 | * i386-init.h: Regenerate. |
| | 835 | * i386-tbl.h: Ditto. |
| | 836 | |
| | 837 | 2017-01-12 Yao Qi <yao.qi@linaro.org> |
| | 838 | |
| | 839 | * msp430-dis.c (msp430_singleoperand): Return -1 if |
| | 840 | msp430dis_opcode_signed returns false. |
| | 841 | (msp430_doubleoperand): Likewise. |
| | 842 | (msp430_branchinstr): Return -1 if |
| | 843 | msp430dis_opcode_unsigned returns false. |
| | 844 | (msp430x_calla_instr): Likewise. |
| | 845 | (print_insn_msp430): Likewise. |
| | 846 | |
| | 847 | 2017-01-05 Nick Clifton <nickc@redhat.com> |
| | 848 | |
| | 849 | PR 20946 |
| | 850 | * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name |
| | 851 | could not be matched. |
| | 852 | (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning |
| | 853 | NULL. |
| | 854 | |
| | 855 | 2017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com> |
| | 856 | |
| | 857 | * aarch64-tbl.h (RCPC, RCPC_INSN): Define. |
| | 858 | (aarch64_opcode_table): Use RCPC_INSN. |
| | 859 | |
| | 860 | 2017-01-03 Kito Cheng <kito.cheng@gmail.com> |
| | 861 | |
| | 862 | * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA |
| | 863 | extension. |
| | 864 | * riscv-opcodes/all-opcodes: Likewise. |
| | 865 | |
| | 866 | 2017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org> |
| | 867 | |
| | 868 | * riscv-dis.c (print_insn_args): Add fall through comment. |
| | 869 | |
| | 870 | 2017-01-03 Nick Clifton <nickc@redhat.com> |
| | 871 | |
| | 872 | * po/sr.po: New Serbian translation. |
| | 873 | * configure.ac (ALL_LINGUAS): Add sr. |
| | 874 | * configure: Regenerate. |
| | 875 | |
| | 876 | 2017-01-02 Alan Modra <amodra@gmail.com> |
| | 877 | |
| | 878 | * epiphany-desc.h: Regenerate. |
| | 879 | * epiphany-opc.h: Regenerate. |
| | 880 | * fr30-desc.h: Regenerate. |
| | 881 | * fr30-opc.h: Regenerate. |
| | 882 | * frv-desc.h: Regenerate. |
| | 883 | * frv-opc.h: Regenerate. |
| | 884 | * ip2k-desc.h: Regenerate. |
| | 885 | * ip2k-opc.h: Regenerate. |
| | 886 | * iq2000-desc.h: Regenerate. |
| | 887 | * iq2000-opc.h: Regenerate. |
| | 888 | * lm32-desc.h: Regenerate. |
| | 889 | * lm32-opc.h: Regenerate. |
| | 890 | * m32c-desc.h: Regenerate. |
| | 891 | * m32c-opc.h: Regenerate. |
| | 892 | * m32r-desc.h: Regenerate. |
| | 893 | * m32r-opc.h: Regenerate. |
| | 894 | * mep-desc.h: Regenerate. |
| | 895 | * mep-opc.h: Regenerate. |
| | 896 | * mt-desc.h: Regenerate. |
| | 897 | * mt-opc.h: Regenerate. |
| | 898 | * or1k-desc.h: Regenerate. |
| | 899 | * or1k-opc.h: Regenerate. |
| | 900 | * xc16x-desc.h: Regenerate. |
| | 901 | * xc16x-opc.h: Regenerate. |
| | 902 | * xstormy16-desc.h: Regenerate. |
| | 903 | * xstormy16-opc.h: Regenerate. |
| | 904 | |
| | 905 | 2017-01-02 Alan Modra <amodra@gmail.com> |
| | 906 | |
| | 907 | Update year range in copyright notice of all files. |
| | 908 | |
| | 909 | For older changes see ChangeLog-2016 |
| | 910 | \f |
| | 911 | Copyright (C) 2017 Free Software Foundation, Inc. |
| | 912 | |
| | 913 | Copying and distribution of this file, with or without modification, |
| | 914 | are permitted in any medium without royalty provided the copyright |
| | 915 | notice and this notice are preserved. |
| | 916 | |
| | 917 | Local Variables: |
| | 918 | mode: change-log |
| | 919 | left-margin: 8 |
| | 920 | fill-column: 74 |
| | 921 | version-control: never |
| | 922 | End: |
projects / deliverable / binutils-gdb.git / blame_incremental