| 1 | 2019-06-25 Jan Beulich <jbeulich@suse.com> |
| 2 | |
| 3 | * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local |
| 4 | variables. |
| 5 | |
| 6 | 2019-06-25 Jan Beulich <jbeulich@suse.com> |
| 7 | |
| 8 | * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd. |
| 9 | Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and |
| 10 | movnti. |
| 11 | * i386-opc.tbl (movnti): Add IgnoreSize. |
| 12 | * i386-tbl.h: Re-generate. |
| 13 | |
| 14 | 2019-06-25 Jan Beulich <jbeulich@suse.com> |
| 15 | |
| 16 | * i386-opc.tbl (and): Mark Imm8S form for optimization. |
| 17 | * i386-tbl.h: Re-generate. |
| 18 | |
| 19 | 2019-06-21 H.J. Lu <hongjiu.lu@intel.com> |
| 20 | |
| 21 | * i386-dis-evex.h: Break into ... |
| 22 | * i386-dis-evex-len.h: New file. |
| 23 | * i386-dis-evex-mod.h: Likewise. |
| 24 | * i386-dis-evex-prefix.h: Likewise. |
| 25 | * i386-dis-evex-reg.h: Likewise. |
| 26 | * i386-dis-evex-w.h: Likewise. |
| 27 | * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h, |
| 28 | i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and |
| 29 | i386-dis-evex-mod.h. |
| 30 | |
| 31 | 2019-06-19 H.J. Lu <hongjiu.lu@intel.com> |
| 32 | |
| 33 | PR binutils/24700 |
| 34 | * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2, |
| 35 | EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and |
| 36 | EVEX_W_0F385B_P_2. |
| 37 | (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0, |
| 38 | EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0, |
| 39 | EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0, |
| 40 | EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0, |
| 41 | EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and |
| 42 | EVEX_LEN_0F385B_P_2_W_1. |
| 43 | * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum. |
| 44 | (EVEX_LEN_0F3819_P_2_W_1): Likewise. |
| 45 | (EVEX_LEN_0F381A_P_2_W_0): Likewise. |
| 46 | (EVEX_LEN_0F381A_P_2_W_1): Likewise. |
| 47 | (EVEX_LEN_0F381B_P_2_W_0): Likewise. |
| 48 | (EVEX_LEN_0F381B_P_2_W_1): Likewise. |
| 49 | (EVEX_LEN_0F385A_P_2_W_0): Likewise. |
| 50 | (EVEX_LEN_0F385A_P_2_W_1): Likewise. |
| 51 | (EVEX_LEN_0F385B_P_2_W_0): Likewise. |
| 52 | (EVEX_LEN_0F385B_P_2_W_1): Likewise. |
| 53 | |
| 54 | 2019-06-17 H.J. Lu <hongjiu.lu@intel.com> |
| 55 | |
| 56 | PR binutils/24691 |
| 57 | * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2, |
| 58 | EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, |
| 59 | EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2. |
| 60 | (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0, |
| 61 | EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0, |
| 62 | EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0, |
| 63 | EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0, |
| 64 | EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0, |
| 65 | EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and |
| 66 | EVEX_LEN_0F3A43_P_2_W_1. |
| 67 | * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum. |
| 68 | (EVEX_LEN_0F3A23_P_2_W_1): Likewise. |
| 69 | (EVEX_LEN_0F3A38_P_2_W_0): Likewise. |
| 70 | (EVEX_LEN_0F3A38_P_2_W_1): Likewise. |
| 71 | (EVEX_LEN_0F3A39_P_2_W_0): Likewise. |
| 72 | (EVEX_LEN_0F3A39_P_2_W_1): Likewise. |
| 73 | (EVEX_LEN_0F3A3A_P_2_W_0): Likewise. |
| 74 | (EVEX_LEN_0F3A3A_P_2_W_1): Likewise. |
| 75 | (EVEX_LEN_0F3A3B_P_2_W_0): Likewise. |
| 76 | (EVEX_LEN_0F3A3B_P_2_W_1): Likewise. |
| 77 | (EVEX_LEN_0F3A43_P_2_W_0): Likewise. |
| 78 | (EVEX_LEN_0F3A43_P_2_W_1): Likewise. |
| 79 | |
| 80 | 2019-06-14 Nick Clifton <nickc@redhat.com> |
| 81 | |
| 82 | * po/fr.po; Updated French translation. |
| 83 | |
| 84 | 2019-06-13 Stafford Horne <shorne@gmail.com> |
| 85 | |
| 86 | * or1k-asm.c: Regenerated. |
| 87 | * or1k-desc.c: Regenerated. |
| 88 | * or1k-desc.h: Regenerated. |
| 89 | * or1k-dis.c: Regenerated. |
| 90 | * or1k-ibld.c: Regenerated. |
| 91 | * or1k-opc.c: Regenerated. |
| 92 | * or1k-opc.h: Regenerated. |
| 93 | * or1k-opinst.c: Regenerated. |
| 94 | |
| 95 | 2019-06-12 Peter Bergner <bergner@linux.ibm.com> |
| 96 | |
| 97 | * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic. |
| 98 | |
| 99 | 2019-06-05 H.J. Lu <hongjiu.lu@intel.com> |
| 100 | |
| 101 | PR binutils/24633 |
| 102 | * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2, |
| 103 | EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2. |
| 104 | (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0, |
| 105 | EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0, |
| 106 | EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0, |
| 107 | EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0, |
| 108 | EVEX_LEN_0F3A1B_P_2_W_1. |
| 109 | * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum. |
| 110 | (EVEX_LEN_0F3A18_P_2_W_1): Likewise. |
| 111 | (EVEX_LEN_0F3A19_P_2_W_0): Likewise. |
| 112 | (EVEX_LEN_0F3A19_P_2_W_1): Likewise. |
| 113 | (EVEX_LEN_0F3A1A_P_2_W_0): Likewise. |
| 114 | (EVEX_LEN_0F3A1A_P_2_W_1): Likewise. |
| 115 | (EVEX_LEN_0F3A1B_P_2_W_0): Likewise. |
| 116 | (EVEX_LEN_0F3A1B_P_2_W_1): Likewise. |
| 117 | |
| 118 | 2019-06-04 H.J. Lu <hongjiu.lu@intel.com> |
| 119 | |
| 120 | PR binutils/24626 |
| 121 | * i386-dis.c (print_insn): Check for unused VEX.vvvv and |
| 122 | EVEX.vvvv when disassembling VEX and EVEX instructions. |
| 123 | (OP_VEX): Set vex.register_specifier to 0 after readding |
| 124 | vex.register_specifier. |
| 125 | (OP_Vex_2src_1): Likewise. |
| 126 | (OP_Vex_2src_2): Likewise. |
| 127 | (OP_LWP_E): Likewise. |
| 128 | (OP_EX_Vex): Don't check vex.register_specifier. |
| 129 | (OP_XMM_Vex): Likewise. |
| 130 | |
| 131 | 2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com> |
| 132 | Lili Cui <lili.cui@intel.com> |
| 133 | |
| 134 | * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3. |
| 135 | * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT |
| 136 | instructions. |
| 137 | * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS, |
| 138 | CPU_ANY_AVX512_VP2INTERSECT_FLAGS. |
| 139 | (cpu_flags): Add CpuAVX512_VP2INTERSECT. |
| 140 | * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT. |
| 141 | (i386_cpu_flags): Add cpuavx512_vp2intersect. |
| 142 | * i386-opc.tbl: Add AVX512_VP2INTERSECT insns. |
| 143 | * i386-init.h: Regenerated. |
| 144 | * i386-tbl.h: Likewise. |
| 145 | |
| 146 | 2019-06-04 Xuepeng Guo <xuepeng.guo@intel.com> |
| 147 | Lili Cui <lili.cui@intel.com> |
| 148 | |
| 149 | * doc/c-i386.texi: Document enqcmd. |
| 150 | * testsuite/gas/i386/enqcmd-intel.d: New file. |
| 151 | * testsuite/gas/i386/enqcmd-inval.l: Likewise. |
| 152 | * testsuite/gas/i386/enqcmd-inval.s: Likewise. |
| 153 | * testsuite/gas/i386/enqcmd.d: Likewise. |
| 154 | * testsuite/gas/i386/enqcmd.s: Likewise. |
| 155 | * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise. |
| 156 | * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise. |
| 157 | * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise. |
| 158 | * testsuite/gas/i386/x86-64-enqcmd.d: Likewise. |
| 159 | * testsuite/gas/i386/x86-64-enqcmd.s: Likewise. |
| 160 | * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval, |
| 161 | enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval, |
| 162 | and x86-64-enqcmd. |
| 163 | |
| 164 | 2019-06-04 Alan Hayward <alan.hayward@arm.com> |
| 165 | |
| 166 | * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis. |
| 167 | |
| 168 | 2019-06-03 Alan Modra <amodra@gmail.com> |
| 169 | |
| 170 | * ppc-dis.c (prefix_opcd_indices): Correct size. |
| 171 | |
| 172 | 2019-05-28 H.J. Lu <hongjiu.lu@intel.com> |
| 173 | |
| 174 | PR gas/24625 |
| 175 | * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with |
| 176 | Disp8ShiftVL. |
| 177 | * i386-tbl.h: Regenerated. |
| 178 | |
| 179 | 2019-05-24 Alan Modra <amodra@gmail.com> |
| 180 | |
| 181 | * po/POTFILES.in: Regenerate. |
| 182 | |
| 183 | 2019-05-24 Peter Bergner <bergner@linux.ibm.com> |
| 184 | Alan Modra <amodra@gmail.com> |
| 185 | |
| 186 | * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34), |
| 187 | (insert_pcrel, extract_pcrel, extract_pcrel0): New functions. |
| 188 | (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment. |
| 189 | (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0, |
| 190 | XTOP>): Define and add entries. |
| 191 | (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define. |
| 192 | (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw, |
| 193 | pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd, |
| 194 | plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq. |
| 195 | |
| 196 | 2019-05-24 Peter Bergner <bergner@linux.ibm.com> |
| 197 | Alan Modra <amodra@gmail.com> |
| 198 | |
| 199 | * ppc-dis.c (ppc_opts): Add "future" entry. |
| 200 | (PREFIX_OPCD_SEGS): Define. |
| 201 | (prefix_opcd_indices): New array. |
| 202 | (disassemble_init_powerpc): Initialize prefix_opcd_indices. |
| 203 | (lookup_prefix): New function. |
| 204 | (print_insn_powerpc): Handle 64-bit prefix instructions. |
| 205 | * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK), |
| 206 | (PMRR, POWERXX): Define. |
| 207 | (prefix_opcodes): New instruction table. |
| 208 | (prefix_num_opcodes): New constant. |
| 209 | |
| 210 | 2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com> |
| 211 | |
| 212 | * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch. |
| 213 | * configure: Regenerated. |
| 214 | * Makefile.am: Add rules for the files generated from cpu/bpf.cpu |
| 215 | and cpu/bpf.opc. |
| 216 | (HFILES): Add bpf-desc.h and bpf-opc.h. |
| 217 | (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c, |
| 218 | bpf-ibld.c and bpf-opc.c. |
| 219 | (BPF_DEPS): Define. |
| 220 | * Makefile.in: Regenerated. |
| 221 | * disassemble.c (ARCH_bpf): Define. |
| 222 | (disassembler): Add case for bfd_arch_bpf. |
| 223 | (disassemble_init_for_target): Likewise. |
| 224 | (enum epbf_isa_attr): Define. |
| 225 | * disassemble.h: extern print_insn_bpf. |
| 226 | * bpf-asm.c: Generated. |
| 227 | * bpf-opc.h: Likewise. |
| 228 | * bpf-opc.c: Likewise. |
| 229 | * bpf-ibld.c: Likewise. |
| 230 | * bpf-dis.c: Likewise. |
| 231 | * bpf-desc.h: Likewise. |
| 232 | * bpf-desc.c: Likewise. |
| 233 | |
| 234 | 2019-05-21 Sudakshina Das <sudi.das@arm.com> |
| 235 | |
| 236 | * arm-dis.c (coprocessor_opcodes): New instructions for VMRS |
| 237 | and VMSR with the new operands. |
| 238 | |
| 239 | 2019-05-21 Sudakshina Das <sudi.das@arm.com> |
| 240 | |
| 241 | * arm-dis.c (enum mve_instructions): New enum |
| 242 | for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv |
| 243 | and cneg. |
| 244 | (mve_opcodes): New instructions as above. |
| 245 | (is_mve_encoding_conflict): Add cases for csinc, csinv, |
| 246 | csneg and csel. |
| 247 | (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C. |
| 248 | |
| 249 | 2019-05-21 Sudakshina Das <sudi.das@arm.com> |
| 250 | |
| 251 | * arm-dis.c (emun mve_instructions): Updated for new instructions. |
| 252 | (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl, |
| 253 | sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll, |
| 254 | uqshl, urshrl and urshr. |
| 255 | (is_mve_okay_in_it): Add new instructions to TRUE list. |
| 256 | (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15. |
| 257 | (print_insn_mve): Updated to accept new %j, |
| 258 | %<bitfield>m and %<bitfield>n patterns. |
| 259 | |
| 260 | 2019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com> |
| 261 | |
| 262 | * mips-opc.c (mips_builtin_opcodes): Change source register |
| 263 | constraint for DAUI. |
| 264 | |
| 265 | 2019-05-20 Nick Clifton <nickc@redhat.com> |
| 266 | |
| 267 | * po/fr.po: Updated French translation. |
| 268 | |
| 269 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
| 270 | Michael Collison <michael.collison@arm.com> |
| 271 | |
| 272 | * arm-dis.c (thumb32_opcodes): Add new instructions. |
| 273 | (enum mve_instructions): Likewise. |
| 274 | (enum mve_undefined): Add new reasons. |
| 275 | (is_mve_encoding_conflict): Handle new instructions. |
| 276 | (is_mve_undefined): Likewise. |
| 277 | (is_mve_unpredictable): Likewise. |
| 278 | (print_mve_undefined): Likewise. |
| 279 | (print_mve_size): Likewise. |
| 280 | |
| 281 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
| 282 | Michael Collison <michael.collison@arm.com> |
| 283 | |
| 284 | * arm-dis.c (thumb32_opcodes): Add new instructions. |
| 285 | (enum mve_instructions): Likewise. |
| 286 | (is_mve_encoding_conflict): Handle new instructions. |
| 287 | (is_mve_undefined): Likewise. |
| 288 | (is_mve_unpredictable): Likewise. |
| 289 | (print_mve_size): Likewise. |
| 290 | |
| 291 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
| 292 | Michael Collison <michael.collison@arm.com> |
| 293 | |
| 294 | * arm-dis.c (thumb32_opcodes): Add new instructions. |
| 295 | (enum mve_instructions): Likewise. |
| 296 | (is_mve_encoding_conflict): Likewise. |
| 297 | (is_mve_unpredictable): Likewise. |
| 298 | (print_mve_size): Likewise. |
| 299 | |
| 300 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
| 301 | Michael Collison <michael.collison@arm.com> |
| 302 | |
| 303 | * arm-dis.c (thumb32_opcodes): Add new instructions. |
| 304 | (enum mve_instructions): Likewise. |
| 305 | (is_mve_encoding_conflict): Handle new instructions. |
| 306 | (is_mve_undefined): Likewise. |
| 307 | (is_mve_unpredictable): Likewise. |
| 308 | (print_mve_size): Likewise. |
| 309 | |
| 310 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
| 311 | Michael Collison <michael.collison@arm.com> |
| 312 | |
| 313 | * arm-dis.c (thumb32_opcodes): Add new instructions. |
| 314 | (enum mve_instructions): Likewise. |
| 315 | (is_mve_encoding_conflict): Handle new instructions. |
| 316 | (is_mve_undefined): Likewise. |
| 317 | (is_mve_unpredictable): Likewise. |
| 318 | (print_mve_size): Likewise. |
| 319 | (print_insn_mve): Likewise. |
| 320 | |
| 321 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
| 322 | Michael Collison <michael.collison@arm.com> |
| 323 | |
| 324 | * arm-dis.c (thumb32_opcodes): Add new instructions. |
| 325 | (print_insn_thumb32): Handle new instructions. |
| 326 | |
| 327 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
| 328 | Michael Collison <michael.collison@arm.com> |
| 329 | |
| 330 | * arm-dis.c (enum mve_instructions): Add new instructions. |
| 331 | (enum mve_undefined): Add new reasons. |
| 332 | (is_mve_encoding_conflict): Handle new instructions. |
| 333 | (is_mve_undefined): Likewise. |
| 334 | (is_mve_unpredictable): Likewise. |
| 335 | (print_mve_undefined): Likewise. |
| 336 | (print_mve_size): Likewise. |
| 337 | (print_mve_shift_n): Likewise. |
| 338 | (print_insn_mve): Likewise. |
| 339 | |
| 340 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
| 341 | Michael Collison <michael.collison@arm.com> |
| 342 | |
| 343 | * arm-dis.c (enum mve_instructions): Add new instructions. |
| 344 | (is_mve_encoding_conflict): Handle new instructions. |
| 345 | (is_mve_unpredictable): Likewise. |
| 346 | (print_mve_rotate): Likewise. |
| 347 | (print_mve_size): Likewise. |
| 348 | (print_insn_mve): Likewise. |
| 349 | |
| 350 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
| 351 | Michael Collison <michael.collison@arm.com> |
| 352 | |
| 353 | * arm-dis.c (enum mve_instructions): Add new instructions. |
| 354 | (is_mve_encoding_conflict): Handle new instructions. |
| 355 | (is_mve_unpredictable): Likewise. |
| 356 | (print_mve_size): Likewise. |
| 357 | (print_insn_mve): Likewise. |
| 358 | |
| 359 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
| 360 | Michael Collison <michael.collison@arm.com> |
| 361 | |
| 362 | * arm-dis.c (enum mve_instructions): Add new instructions. |
| 363 | (enum mve_undefined): Add new reasons. |
| 364 | (is_mve_encoding_conflict): Handle new instructions. |
| 365 | (is_mve_undefined): Likewise. |
| 366 | (is_mve_unpredictable): Likewise. |
| 367 | (print_mve_undefined): Likewise. |
| 368 | (print_mve_size): Likewise. |
| 369 | (print_insn_mve): Likewise. |
| 370 | |
| 371 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
| 372 | Michael Collison <michael.collison@arm.com> |
| 373 | |
| 374 | * arm-dis.c (enum mve_instructions): Add new instructions. |
| 375 | (is_mve_encoding_conflict): Handle new instructions. |
| 376 | (is_mve_undefined): Likewise. |
| 377 | (is_mve_unpredictable): Likewise. |
| 378 | (print_mve_size): Likewise. |
| 379 | (print_insn_mve): Likewise. |
| 380 | |
| 381 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
| 382 | Michael Collison <michael.collison@arm.com> |
| 383 | |
| 384 | * arm-dis.c (enum mve_instructions): Add new instructions. |
| 385 | (enum mve_unpredictable): Add new reasons. |
| 386 | (enum mve_undefined): Likewise. |
| 387 | (is_mve_okay_in_it): Handle new isntructions. |
| 388 | (is_mve_encoding_conflict): Likewise. |
| 389 | (is_mve_undefined): Likewise. |
| 390 | (is_mve_unpredictable): Likewise. |
| 391 | (print_mve_vmov_index): Likewise. |
| 392 | (print_simd_imm8): Likewise. |
| 393 | (print_mve_undefined): Likewise. |
| 394 | (print_mve_unpredictable): Likewise. |
| 395 | (print_mve_size): Likewise. |
| 396 | (print_insn_mve): Likewise. |
| 397 | |
| 398 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
| 399 | Michael Collison <michael.collison@arm.com> |
| 400 | |
| 401 | * arm-dis.c (enum mve_instructions): Add new instructions. |
| 402 | (enum mve_unpredictable): Add new reasons. |
| 403 | (enum mve_undefined): Likewise. |
| 404 | (is_mve_encoding_conflict): Handle new instructions. |
| 405 | (is_mve_undefined): Likewise. |
| 406 | (is_mve_unpredictable): Likewise. |
| 407 | (print_mve_undefined): Likewise. |
| 408 | (print_mve_unpredictable): Likewise. |
| 409 | (print_mve_rounding_mode): Likewise. |
| 410 | (print_mve_vcvt_size): Likewise. |
| 411 | (print_mve_size): Likewise. |
| 412 | (print_insn_mve): Likewise. |
| 413 | |
| 414 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
| 415 | Michael Collison <michael.collison@arm.com> |
| 416 | |
| 417 | * arm-dis.c (enum mve_instructions): Add new instructions. |
| 418 | (enum mve_unpredictable): Add new reasons. |
| 419 | (enum mve_undefined): Likewise. |
| 420 | (is_mve_undefined): Handle new instructions. |
| 421 | (is_mve_unpredictable): Likewise. |
| 422 | (print_mve_undefined): Likewise. |
| 423 | (print_mve_unpredictable): Likewise. |
| 424 | (print_mve_size): Likewise. |
| 425 | (print_insn_mve): Likewise. |
| 426 | |
| 427 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
| 428 | Michael Collison <michael.collison@arm.com> |
| 429 | |
| 430 | * arm-dis.c (enum mve_instructions): Add new instructions. |
| 431 | (enum mve_undefined): Add new reasons. |
| 432 | (insns): Add new instructions. |
| 433 | (is_mve_encoding_conflict): |
| 434 | (print_mve_vld_str_addr): New print function. |
| 435 | (is_mve_undefined): Handle new instructions. |
| 436 | (is_mve_unpredictable): Likewise. |
| 437 | (print_mve_undefined): Likewise. |
| 438 | (print_mve_size): Likewise. |
| 439 | (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions. |
| 440 | (print_insn_mve): Handle new operands. |
| 441 | |
| 442 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
| 443 | Michael Collison <michael.collison@arm.com> |
| 444 | |
| 445 | * arm-dis.c (enum mve_instructions): Add new instructions. |
| 446 | (enum mve_unpredictable): Add new reasons. |
| 447 | (is_mve_encoding_conflict): Handle new instructions. |
| 448 | (is_mve_unpredictable): Likewise. |
| 449 | (mve_opcodes): Add new instructions. |
| 450 | (print_mve_unpredictable): Handle new reasons. |
| 451 | (print_mve_register_blocks): New print function. |
| 452 | (print_mve_size): Handle new instructions. |
| 453 | (print_insn_mve): Likewise. |
| 454 | |
| 455 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
| 456 | Michael Collison <michael.collison@arm.com> |
| 457 | |
| 458 | * arm-dis.c (enum mve_instructions): Add new instructions. |
| 459 | (enum mve_unpredictable): Add new reasons. |
| 460 | (enum mve_undefined): Likewise. |
| 461 | (is_mve_encoding_conflict): Handle new instructions. |
| 462 | (is_mve_undefined): Likewise. |
| 463 | (is_mve_unpredictable): Likewise. |
| 464 | (coprocessor_opcodes): Move NEON VDUP from here... |
| 465 | (neon_opcodes): ... to here. |
| 466 | (mve_opcodes): Add new instructions. |
| 467 | (print_mve_undefined): Handle new reasons. |
| 468 | (print_mve_unpredictable): Likewise. |
| 469 | (print_mve_size): Handle new instructions. |
| 470 | (print_insn_neon): Handle vdup. |
| 471 | (print_insn_mve): Handle new operands. |
| 472 | |
| 473 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
| 474 | Michael Collison <michael.collison@arm.com> |
| 475 | |
| 476 | * arm-dis.c (enum mve_instructions): Add new instructions. |
| 477 | (enum mve_unpredictable): Add new values. |
| 478 | (mve_opcodes): Add new instructions. |
| 479 | (vec_condnames): New array with vector conditions. |
| 480 | (mve_predicatenames): New array with predicate suffixes. |
| 481 | (mve_vec_sizename): New array with vector sizes. |
| 482 | (enum vpt_pred_state): New enum with vector predication states. |
| 483 | (struct vpt_block): New struct type for vpt blocks. |
| 484 | (vpt_block_state): Global struct to keep track of state. |
| 485 | (mve_extract_pred_mask): New helper function. |
| 486 | (num_instructions_vpt_block): Likewise. |
| 487 | (mark_outside_vpt_block): Likewise. |
| 488 | (mark_inside_vpt_block): Likewise. |
| 489 | (invert_next_predicate_state): Likewise. |
| 490 | (update_next_predicate_state): Likewise. |
| 491 | (update_vpt_block_state): Likewise. |
| 492 | (is_vpt_instruction): Likewise. |
| 493 | (is_mve_encoding_conflict): Add entries for new instructions. |
| 494 | (is_mve_unpredictable): Likewise. |
| 495 | (print_mve_unpredictable): Handle new cases. |
| 496 | (print_instruction_predicate): Likewise. |
| 497 | (print_mve_size): New function. |
| 498 | (print_vec_condition): New function. |
| 499 | (print_insn_mve): Handle vpt blocks and new print operands. |
| 500 | |
| 501 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
| 502 | |
| 503 | * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors |
| 504 | 8, 14 and 15 for Armv8.1-M Mainline. |
| 505 | |
| 506 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
| 507 | Michael Collison <michael.collison@arm.com> |
| 508 | |
| 509 | * arm-dis.c (enum mve_instructions): New enum. |
| 510 | (enum mve_unpredictable): Likewise. |
| 511 | (enum mve_undefined): Likewise. |
| 512 | (struct mopcode32): New struct. |
| 513 | (is_mve_okay_in_it): New function. |
| 514 | (is_mve_architecture): Likewise. |
| 515 | (arm_decode_field): Likewise. |
| 516 | (arm_decode_field_multiple): Likewise. |
| 517 | (is_mve_encoding_conflict): Likewise. |
| 518 | (is_mve_undefined): Likewise. |
| 519 | (is_mve_unpredictable): Likewise. |
| 520 | (print_mve_undefined): Likewise. |
| 521 | (print_mve_unpredictable): Likewise. |
| 522 | (print_insn_coprocessor_1): Use arm_decode_field_multiple. |
| 523 | (print_insn_mve): New function. |
| 524 | (print_insn_thumb32): Handle MVE architecture. |
| 525 | (select_arm_features): Force thumb for Armv8.1-m Mainline. |
| 526 | |
| 527 | 2019-05-10 Nick Clifton <nickc@redhat.com> |
| 528 | |
| 529 | PR 24538 |
| 530 | * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the |
| 531 | end of the table prematurely. |
| 532 | |
| 533 | 2019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com> |
| 534 | |
| 535 | * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB |
| 536 | macros for R6. |
| 537 | |
| 538 | 2019-05-11 Alan Modra <amodra@gmail.com> |
| 539 | |
| 540 | * ppc-dis.c (print_insn_powerpc) Don't skip optional operands |
| 541 | when -Mraw is in effect. |
| 542 | |
| 543 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
| 544 | |
| 545 | * aarch64-dis-2.c: Regenerate. |
| 546 | * aarch64-tbl.h (OP_SVE_BBU): New variant set. |
| 547 | (OP_SVE_BBB): New variant set. |
| 548 | (OP_SVE_DDDD): New variant set. |
| 549 | (OP_SVE_HHH): New variant set. |
| 550 | (OP_SVE_HHHU): New variant set. |
| 551 | (OP_SVE_SSS): New variant set. |
| 552 | (OP_SVE_SSSU): New variant set. |
| 553 | (OP_SVE_SHH): New variant set. |
| 554 | (OP_SVE_SBBU): New variant set. |
| 555 | (OP_SVE_DSS): New variant set. |
| 556 | (OP_SVE_DHHU): New variant set. |
| 557 | (OP_SVE_VMV_HSD_BHS): New variant set. |
| 558 | (OP_SVE_VVU_HSD_BHS): New variant set. |
| 559 | (OP_SVE_VVVU_SD_BH): New variant set. |
| 560 | (OP_SVE_VVVU_BHSD): New variant set. |
| 561 | (OP_SVE_VVV_QHD_DBS): New variant set. |
| 562 | (OP_SVE_VVV_HSD_BHS): New variant set. |
| 563 | (OP_SVE_VVV_HSD_BHS2): New variant set. |
| 564 | (OP_SVE_VVV_BHS_HSD): New variant set. |
| 565 | (OP_SVE_VV_BHS_HSD): New variant set. |
| 566 | (OP_SVE_VVV_SD): New variant set. |
| 567 | (OP_SVE_VVU_BHS_HSD): New variant set. |
| 568 | (OP_SVE_VZVV_SD): New variant set. |
| 569 | (OP_SVE_VZVV_BH): New variant set. |
| 570 | (OP_SVE_VZV_SD): New variant set. |
| 571 | (aarch64_opcode_table): Add sve2 instructions. |
| 572 | |
| 573 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
| 574 | |
| 575 | * aarch64-asm-2.c: Regenerated. |
| 576 | * aarch64-dis-2.c: Regenerated. |
| 577 | * aarch64-opc-2.c: Regenerated. |
| 578 | * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking |
| 579 | for SVE_SHLIMM_UNPRED_22. |
| 580 | (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22. |
| 581 | * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22 |
| 582 | operand. |
| 583 | |
| 584 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
| 585 | |
| 586 | * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle |
| 587 | sve_size_tsz_bhs iclass encode. |
| 588 | * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle |
| 589 | sve_size_tsz_bhs iclass decode. |
| 590 | |
| 591 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
| 592 | |
| 593 | * aarch64-asm-2.c: Regenerated. |
| 594 | * aarch64-dis-2.c: Regenerated. |
| 595 | * aarch64-opc-2.c: Regenerated. |
| 596 | * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking |
| 597 | for SVE_Zm4_11_INDEX. |
| 598 | (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX. |
| 599 | (fields): Handle SVE_i2h field. |
| 600 | * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field. |
| 601 | * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand. |
| 602 | |
| 603 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
| 604 | |
| 605 | * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle |
| 606 | sve_shift_tsz_bhsd iclass encode. |
| 607 | * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle |
| 608 | sve_shift_tsz_bhsd iclass decode. |
| 609 | |
| 610 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
| 611 | |
| 612 | * aarch64-asm-2.c: Regenerated. |
| 613 | * aarch64-dis-2.c: Regenerated. |
| 614 | * aarch64-opc-2.c: Regenerated. |
| 615 | * aarch64-asm.c (aarch64_ins_sve_shrimm): |
| 616 | (aarch64_encode_variant_using_iclass): Handle |
| 617 | sve_shift_tsz_hsd iclass encode. |
| 618 | * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle |
| 619 | sve_shift_tsz_hsd iclass decode. |
| 620 | * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking |
| 621 | for SVE_SHRIMM_UNPRED_22. |
| 622 | (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22. |
| 623 | * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22 |
| 624 | operand. |
| 625 | |
| 626 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
| 627 | |
| 628 | * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle |
| 629 | sve_size_013 iclass encode. |
| 630 | * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle |
| 631 | sve_size_013 iclass decode. |
| 632 | |
| 633 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
| 634 | |
| 635 | * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle |
| 636 | sve_size_bh iclass encode. |
| 637 | * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle |
| 638 | sve_size_bh iclass decode. |
| 639 | |
| 640 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
| 641 | |
| 642 | * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle |
| 643 | sve_size_sd2 iclass encode. |
| 644 | * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle |
| 645 | sve_size_sd2 iclass decode. |
| 646 | * aarch64-opc.c (fields): Handle SVE_sz2 field. |
| 647 | * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field. |
| 648 | |
| 649 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
| 650 | |
| 651 | * aarch64-asm-2.c: Regenerated. |
| 652 | * aarch64-dis-2.c: Regenerated. |
| 653 | * aarch64-opc-2.c: Regenerated. |
| 654 | * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking |
| 655 | for SVE_ADDR_ZX. |
| 656 | (aarch64_print_operand): Add printing for SVE_ADDR_ZX. |
| 657 | * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand. |
| 658 | |
| 659 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
| 660 | |
| 661 | * aarch64-asm-2.c: Regenerated. |
| 662 | * aarch64-dis-2.c: Regenerated. |
| 663 | * aarch64-opc-2.c: Regenerated. |
| 664 | * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking |
| 665 | for SVE_Zm3_11_INDEX. |
| 666 | (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX. |
| 667 | (fields): Handle SVE_i3l and SVE_i3h2 fields. |
| 668 | * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2 |
| 669 | fields. |
| 670 | * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand. |
| 671 | |
| 672 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
| 673 | |
| 674 | * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle |
| 675 | sve_size_hsd2 iclass encode. |
| 676 | * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle |
| 677 | sve_size_hsd2 iclass decode. |
| 678 | * aarch64-opc.c (fields): Handle SVE_size field. |
| 679 | * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field. |
| 680 | |
| 681 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
| 682 | |
| 683 | * aarch64-asm-2.c: Regenerated. |
| 684 | * aarch64-dis-2.c: Regenerated. |
| 685 | * aarch64-opc-2.c: Regenerated. |
| 686 | * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking |
| 687 | for SVE_IMM_ROT3. |
| 688 | (aarch64_print_operand): Add printing for SVE_IMM_ROT3. |
| 689 | (fields): Handle SVE_rot3 field. |
| 690 | * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field. |
| 691 | * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand. |
| 692 | |
| 693 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
| 694 | |
| 695 | * aarch64-opc.c (verify_constraints): Check for movprfx for sve2 |
| 696 | instructions. |
| 697 | |
| 698 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
| 699 | |
| 700 | * aarch64-tbl.h |
| 701 | (aarch64_feature_sve2, aarch64_feature_sve2aes, |
| 702 | aarch64_feature_sve2sha3, aarch64_feature_sve2sm4, |
| 703 | aarch64_feature_sve2bitperm): New feature sets. |
| 704 | (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros |
| 705 | for feature set addresses. |
| 706 | (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN, |
| 707 | SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros. |
| 708 | |
| 709 | 2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com> |
| 710 | Faraz Shahbazker <fshahbazker@wavecomp.com> |
| 711 | |
| 712 | * mips-dis.c (mips_calculate_combination_ases): Add ISA |
| 713 | argument and set ASE_EVA_R6 appropriately. |
| 714 | (set_default_mips_dis_options): Pass ISA to above. |
| 715 | (parse_mips_dis_option): Likewise. |
| 716 | * mips-opc.c (EVAR6): New macro. |
| 717 | (mips_builtin_opcodes): Add llwpe, scwpe. |
| 718 | |
| 719 | 2019-05-01 Sudakshina Das <sudi.das@arm.com> |
| 720 | |
| 721 | * aarch64-asm-2.c: Regenerated. |
| 722 | * aarch64-dis-2.c: Regenerated. |
| 723 | * aarch64-opc-2.c: Regenerated. |
| 724 | * aarch64-opc.c (operand_general_constraint_met_p): Add case for |
| 725 | AARCH64_OPND_TME_UIMM16. |
| 726 | (aarch64_print_operand): Likewise. |
| 727 | * aarch64-tbl.h (QL_IMM_NIL): New. |
| 728 | (TME): New. |
| 729 | (_TME_INSN): New. |
| 730 | (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel. |
| 731 | |
| 732 | 2019-04-29 John Darrington <john@darrington.wattle.id.au> |
| 733 | |
| 734 | * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails. |
| 735 | |
| 736 | 2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com> |
| 737 | Faraz Shahbazker <fshahbazker@wavecomp.com> |
| 738 | |
| 739 | * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp. |
| 740 | |
| 741 | 2019-04-24 John Darrington <john@darrington.wattle.id.au> |
| 742 | |
| 743 | * s12z-opc.h: Add extern "C" bracketing to help |
| 744 | users who wish to use this interface in c++ code. |
| 745 | |
| 746 | 2019-04-24 John Darrington <john@darrington.wattle.id.au> |
| 747 | |
| 748 | * s12z-opc.c (bm_decode): Handle bit map operations with the |
| 749 | "reserved0" mode. |
| 750 | |
| 751 | 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> |
| 752 | |
| 753 | * arm-dis.c (coprocessor_opcodes): Document new %J and %K format |
| 754 | specifier. Add entries for VLDR and VSTR of system registers. |
| 755 | (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in |
| 756 | coprocessor instructions on Armv8.1-M Mainline targets. Add handling |
| 757 | of %J and %K format specifier. |
| 758 | |
| 759 | 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> |
| 760 | |
| 761 | * arm-dis.c (coprocessor_opcodes): Document new %C format control code. |
| 762 | Add new entries for VSCCLRM instruction. |
| 763 | (print_insn_coprocessor): Handle new %C format control code. |
| 764 | |
| 765 | 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> |
| 766 | |
| 767 | * arm-dis.c (enum isa): New enum. |
| 768 | (struct sopcode32): New structure. |
| 769 | (coprocessor_opcodes): change type of entries to struct sopcode32 and |
| 770 | set isa field of all current entries to ANY. |
| 771 | (print_insn_coprocessor): Change type of insn to struct sopcode32. |
| 772 | Only match an entry if its isa field allows the current mode. |
| 773 | |
| 774 | 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> |
| 775 | |
| 776 | * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for |
| 777 | CLRM. |
| 778 | (print_insn_thumb32): Add logic to print %n CLRM register list. |
| 779 | |
| 780 | 2019-04-15 Sudakshina Das <sudi.das@arm.com> |
| 781 | |
| 782 | * arm-dis.c (print_insn_thumb32): Updated to accept new %P |
| 783 | and %Q patterns. |
| 784 | |
| 785 | 2019-04-15 Sudakshina Das <sudi.das@arm.com> |
| 786 | |
| 787 | * arm-dis.c (thumb32_opcodes): New instruction bfcsel. |
| 788 | (print_insn_thumb32): Edit the switch case for %Z. |
| 789 | |
| 790 | 2019-04-15 Sudakshina Das <sudi.das@arm.com> |
| 791 | |
| 792 | * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern. |
| 793 | |
| 794 | 2019-04-15 Sudakshina Das <sudi.das@arm.com> |
| 795 | |
| 796 | * arm-dis.c (thumb32_opcodes): New instruction bfl. |
| 797 | |
| 798 | 2019-04-15 Sudakshina Das <sudi.das@arm.com> |
| 799 | |
| 800 | * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern. |
| 801 | |
| 802 | 2019-04-15 Sudakshina Das <sudi.das@arm.com> |
| 803 | |
| 804 | * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an |
| 805 | Arm register with r13 and r15 unpredictable. |
| 806 | (thumb32_opcodes): New instructions for bfx and bflx. |
| 807 | |
| 808 | 2019-04-15 Sudakshina Das <sudi.das@arm.com> |
| 809 | |
| 810 | * arm-dis.c (thumb32_opcodes): New instructions for bf. |
| 811 | |
| 812 | 2019-04-15 Sudakshina Das <sudi.das@arm.com> |
| 813 | |
| 814 | * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern. |
| 815 | |
| 816 | 2019-04-15 Sudakshina Das <sudi.das@arm.com> |
| 817 | |
| 818 | * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern. |
| 819 | |
| 820 | 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> |
| 821 | |
| 822 | * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline. |
| 823 | |
| 824 | 2019-04-12 John Darrington <john@darrington.wattle.id.au> |
| 825 | |
| 826 | s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with |
| 827 | "optr". ("operator" is a reserved word in c++). |
| 828 | |
| 829 | 2019-04-11 Sudakshina Das <sudi.das@arm.com> |
| 830 | |
| 831 | * aarch64-opc.c (aarch64_print_operand): Add case for |
| 832 | AARCH64_OPND_Rt_SP. |
| 833 | (verify_constraints): Likewise. |
| 834 | * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier. |
| 835 | (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions |
| 836 | to accept Rt|SP as first operand. |
| 837 | (AARCH64_OPERANDS): Add new Rt_SP. |
| 838 | * aarch64-asm-2.c: Regenerated. |
| 839 | * aarch64-dis-2.c: Regenerated. |
| 840 | * aarch64-opc-2.c: Regenerated. |
| 841 | |
| 842 | 2019-04-11 Sudakshina Das <sudi.das@arm.com> |
| 843 | |
| 844 | * aarch64-asm-2.c: Regenerated. |
| 845 | * aarch64-dis-2.c: Likewise. |
| 846 | * aarch64-opc-2.c: Likewise. |
| 847 | * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm. |
| 848 | |
| 849 | 2019-04-09 Robert Suchanek <robert.suchanek@mips.com> |
| 850 | |
| 851 | * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel. |
| 852 | |
| 853 | 2019-04-08 H.J. Lu <hongjiu.lu@intel.com> |
| 854 | |
| 855 | * i386-opc.tbl: Consolidate AVX512 BF16 entries. |
| 856 | * i386-init.h: Regenerated. |
| 857 | |
| 858 | 2019-04-07 Alan Modra <amodra@gmail.com> |
| 859 | |
| 860 | * ppc-dis.c (print_insn_powerpc): Use a tiny state machine |
| 861 | op_separator to control printing of spaces, comma and parens |
| 862 | rather than need_comma, need_paren and spaces vars. |
| 863 | |
| 864 | 2019-04-07 Alan Modra <amodra@gmail.com> |
| 865 | |
| 866 | PR 24421 |
| 867 | * arm-dis.c (print_insn_coprocessor): Correct bracket placement. |
| 868 | (print_insn_neon, print_insn_arm): Likewise. |
| 869 | |
| 870 | 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com> |
| 871 | |
| 872 | * i386-dis-evex.h (evex_table): Updated to support BF16 |
| 873 | instructions. |
| 874 | * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1 |
| 875 | and EVEX_W_0F3872_P_3. |
| 876 | * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS. |
| 877 | (cpu_flags): Add bitfield for CpuAVX512_BF16. |
| 878 | * i386-opc.h (enum): Add CpuAVX512_BF16. |
| 879 | (i386_cpu_flags): Add bitfield for cpuavx512_bf16. |
| 880 | * i386-opc.tbl: Add AVX512 BF16 instructions. |
| 881 | * i386-init.h: Regenerated. |
| 882 | * i386-tbl.h: Likewise. |
| 883 | |
| 884 | 2019-04-05 Alan Modra <amodra@gmail.com> |
| 885 | |
| 886 | * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK. |
| 887 | (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics |
| 888 | to favour printing of "-" branch hint when using the "y" bit. |
| 889 | Allow BH field on bc{ctr,lr,tar}{,l}{-,+}. |
| 890 | |
| 891 | 2019-04-05 Alan Modra <amodra@gmail.com> |
| 892 | |
| 893 | * ppc-dis.c (print_insn_powerpc): Delay printing spaces after |
| 894 | opcode until first operand is output. |
| 895 | |
| 896 | 2019-04-04 Peter Bergner <bergner@linux.ibm.com> |
| 897 | |
| 898 | PR gas/24349 |
| 899 | * ppc-opc.c (valid_bo_pre_v2): Add comments. |
| 900 | (valid_bo_post_v2): Add support for 'at' branch hints. |
| 901 | (insert_bo): Only error on branch on ctr. |
| 902 | (get_bo_hint_mask): New function. |
| 903 | (insert_boe): Add new 'branch_taken' formal argument. Add support |
| 904 | for inserting 'at' branch hints. |
| 905 | (extract_boe): Add new 'branch_taken' formal argument. Add support |
| 906 | for extracting 'at' branch hints. |
| 907 | (insert_bom, extract_bom, insert_bop, extract_bop): New functions. |
| 908 | (BOE): Delete operand. |
| 909 | (BOM, BOP): New operands. |
| 910 | (RM): Update value. |
| 911 | (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete. |
| 912 | (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-, |
| 913 | bcctrl-, bctar-, bctarl->: Replace BOE with BOM. |
| 914 | (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+, |
| 915 | bcctrl+, bctar+, bctarl+>: Replace BOE with BOP. |
| 916 | <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-, |
| 917 | bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar, |
| 918 | bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar, |
| 919 | bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-, |
| 920 | bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-, |
| 921 | bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+, |
| 922 | bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+, |
| 923 | bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl, |
| 924 | beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-, |
| 925 | bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-, |
| 926 | buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+, |
| 927 | bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar, |
| 928 | bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar, |
| 929 | bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+, |
| 930 | bttarl+>: New extended mnemonics. |
| 931 | |
| 932 | 2019-03-28 Alan Modra <amodra@gmail.com> |
| 933 | |
| 934 | PR 24390 |
| 935 | * ppc-opc.c (BTF): Define. |
| 936 | (powerpc_opcodes): Use for mtfsb*. |
| 937 | * ppc-dis.c (print_insn_powerpc): Print fields with both |
| 938 | PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number. |
| 939 | |
| 940 | 2019-03-25 Tamar Christina <tamar.christina@arm.com> |
| 941 | |
| 942 | * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols. |
| 943 | (mapping_symbol_for_insn): Implement new algorithm. |
| 944 | (print_insn): Remove duplicate code. |
| 945 | |
| 946 | 2019-03-25 Tamar Christina <tamar.christina@arm.com> |
| 947 | |
| 948 | * aarch64-dis.c (print_insn_aarch64): |
| 949 | Implement override. |
| 950 | |
| 951 | 2019-03-25 Tamar Christina <tamar.christina@arm.com> |
| 952 | |
| 953 | * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search |
| 954 | order. |
| 955 | |
| 956 | 2019-03-25 Tamar Christina <tamar.christina@arm.com> |
| 957 | |
| 958 | * aarch64-dis.c (last_stop_offset): New. |
| 959 | (print_insn_aarch64): Use stop_offset. |
| 960 | |
| 961 | 2019-03-19 H.J. Lu <hongjiu.lu@intel.com> |
| 962 | |
| 963 | PR gas/24359 |
| 964 | * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to |
| 965 | CPU_ANY_AVX2_FLAGS. |
| 966 | * i386-init.h: Regenerated. |
| 967 | |
| 968 | 2019-03-18 H.J. Lu <hongjiu.lu@intel.com> |
| 969 | |
| 970 | PR gas/24348 |
| 971 | * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8, |
| 972 | vmovdqu16, vmovdqu32 and vmovdqu64. |
| 973 | * i386-tbl.h: Regenerated. |
| 974 | |
| 975 | 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com> |
| 976 | |
| 977 | * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand |
| 978 | from vstrszb, vstrszh, and vstrszf. |
| 979 | |
| 980 | 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com> |
| 981 | |
| 982 | * s390-opc.txt: Add instruction descriptions. |
| 983 | |
| 984 | 2019-02-08 Jim Wilson <jimw@sifive.com> |
| 985 | |
| 986 | * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form. |
| 987 | <bne>: Likewise. |
| 988 | |
| 989 | 2019-02-07 Tamar Christina <tamar.christina@arm.com> |
| 990 | |
| 991 | * arm-dis.c (arm_opcodes): Redefine hlt to armv1. |
| 992 | |
| 993 | 2019-02-07 Tamar Christina <tamar.christina@arm.com> |
| 994 | |
| 995 | PR binutils/23212 |
| 996 | * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz. |
| 997 | * aarch64-opc.c (verify_elem_sd): New. |
| 998 | (fields): Add FLD_sz entr. |
| 999 | * aarch64-tbl.h (_SIMD_INSN): New. |
| 1000 | (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and |
| 1001 | fmulx scalar and vector by element isns. |
| 1002 | |
| 1003 | 2019-02-07 Nick Clifton <nickc@redhat.com> |
| 1004 | |
| 1005 | * po/sv.po: Updated Swedish translation. |
| 1006 | |
| 1007 | 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com> |
| 1008 | |
| 1009 | * s390-mkopc.c (main): Accept arch13 as cpu string. |
| 1010 | * s390-opc.c: Add new instruction formats and instruction opcode |
| 1011 | masks. |
| 1012 | * s390-opc.txt: Add new arch13 instructions. |
| 1013 | |
| 1014 | 2019-01-25 Sudakshina Das <sudi.das@arm.com> |
| 1015 | |
| 1016 | * aarch64-tbl.h (QL_LDST_AT): Update macro. |
| 1017 | (aarch64_opcode): Change encoding for stg, stzg |
| 1018 | st2g and st2zg. |
| 1019 | * aarch64-asm-2.c: Regenerated. |
| 1020 | * aarch64-dis-2.c: Regenerated. |
| 1021 | * aarch64-opc-2.c: Regenerated. |
| 1022 | |
| 1023 | 2019-01-25 Sudakshina Das <sudi.das@arm.com> |
| 1024 | |
| 1025 | * aarch64-asm-2.c: Regenerated. |
| 1026 | * aarch64-dis-2.c: Likewise. |
| 1027 | * aarch64-opc-2.c: Likewise. |
| 1028 | * aarch64-tbl.h (aarch64_opcode): Add new stzgm. |
| 1029 | |
| 1030 | 2019-01-25 Sudakshina Das <sudi.das@arm.com> |
| 1031 | Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> |
| 1032 | |
| 1033 | * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove. |
| 1034 | * aarch64-asm.h (ins_addr_simple_2): Likeiwse. |
| 1035 | * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise. |
| 1036 | * aarch64-dis.h (ext_addr_simple_2): Likewise. |
| 1037 | * aarch64-opc.c (operand_general_constraint_met_p): Remove |
| 1038 | case for ldstgv_indexed. |
| 1039 | (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2. |
| 1040 | * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv. |
| 1041 | (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2. |
| 1042 | * aarch64-asm-2.c: Regenerated. |
| 1043 | * aarch64-dis-2.c: Regenerated. |
| 1044 | * aarch64-opc-2.c: Regenerated. |
| 1045 | |
| 1046 | 2019-01-23 Nick Clifton <nickc@redhat.com> |
| 1047 | |
| 1048 | * po/pt_BR.po: Updated Brazilian Portuguese translation. |
| 1049 | |
| 1050 | 2019-01-21 Nick Clifton <nickc@redhat.com> |
| 1051 | |
| 1052 | * po/de.po: Updated German translation. |
| 1053 | * po/uk.po: Updated Ukranian translation. |
| 1054 | |
| 1055 | 2019-01-20 Chenghua Xu <paul.hua.gm@gmail.com> |
| 1056 | * mips-dis.c (mips_arch_choices): Fix typo in |
| 1057 | gs464, gs464e and gs264e descriptors. |
| 1058 | |
| 1059 | 2019-01-19 Nick Clifton <nickc@redhat.com> |
| 1060 | |
| 1061 | * configure: Regenerate. |
| 1062 | * po/opcodes.pot: Regenerate. |
| 1063 | |
| 1064 | 2018-06-24 Nick Clifton <nickc@redhat.com> |
| 1065 | |
| 1066 | 2.32 branch created. |
| 1067 | |
| 1068 | 2019-01-09 John Darrington <john@darrington.wattle.id.au> |
| 1069 | |
| 1070 | * s12z-dis.c (print_insn_s12z): Do not dereference an operand |
| 1071 | if it is null. |
| 1072 | -dis.c (opr_emit_disassembly): Do not omit an index if it is |
| 1073 | zero. |
| 1074 | |
| 1075 | 2019-01-09 Andrew Paprocki <andrew@ishiboo.com> |
| 1076 | |
| 1077 | * configure: Regenerate. |
| 1078 | |
| 1079 | 2019-01-07 Alan Modra <amodra@gmail.com> |
| 1080 | |
| 1081 | * configure: Regenerate. |
| 1082 | * po/POTFILES.in: Regenerate. |
| 1083 | |
| 1084 | 2019-01-03 John Darrington <john@darrington.wattle.id.au> |
| 1085 | |
| 1086 | * s12z-opc.c: New file. |
| 1087 | * s12z-opc.h: New file. |
| 1088 | * s12z-dis.c: Removed all code not directly related to display |
| 1089 | of instructions. Used the interface provided by the new files |
| 1090 | instead. |
| 1091 | * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c. |
| 1092 | * Makefile.in: Regenerate. |
| 1093 | * configure.ac (bfd_s12z_arch): Correct the dependencies. |
| 1094 | * configure: Regenerate. |
| 1095 | |
| 1096 | 2019-01-01 Alan Modra <amodra@gmail.com> |
| 1097 | |
| 1098 | Update year range in copyright notice of all files. |
| 1099 | |
| 1100 | For older changes see ChangeLog-2018 |
| 1101 | \f |
| 1102 | Copyright (C) 2019 Free Software Foundation, Inc. |
| 1103 | |
| 1104 | Copying and distribution of this file, with or without modification, |
| 1105 | are permitted in any medium without royalty provided the copyright |
| 1106 | notice and this notice are preserved. |
| 1107 | |
| 1108 | Local Variables: |
| 1109 | mode: change-log |
| 1110 | left-margin: 8 |
| 1111 | fill-column: 74 |
| 1112 | version-control: never |
| 1113 | End: |