| 1 | 2017-05-12 Maciej W. Rozycki <macro@imgtec.com> |
| 2 | |
| 3 | * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand |
| 4 | type to hexadecimal. |
| 5 | (mips16_opcodes): Add operandless "break" and "sdbbp" entries. |
| 6 | |
| 7 | 2017-05-11 Maciej W. Rozycki <macro@imgtec.com> |
| 8 | |
| 9 | * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs", |
| 10 | "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release", |
| 11 | "sync_rmb" and "sync_wmb" as aliases. |
| 12 | * micromips-opc.c (micromips_opcodes): Mark "sync_acquire", |
| 13 | "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases. |
| 14 | |
| 15 | 2017-05-10 Claudiu Zissulescu <claziss@synopsys.com> |
| 16 | |
| 17 | * arc-dis.c (parse_option): Update quarkse_em option.. |
| 18 | * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to |
| 19 | QUARKSE1. |
| 20 | (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2. |
| 21 | |
| 22 | 2017-05-03 Kito Cheng <kito.cheng@gmail.com> |
| 23 | |
| 24 | * riscv-dis.c (print_insn_args): Handle 'Co' operands. |
| 25 | |
| 26 | 2017-05-01 Michael Clark <michaeljclark@mac.com> |
| 27 | |
| 28 | * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary |
| 29 | register. |
| 30 | |
| 31 | 2017-05-02 Maciej W. Rozycki <macro@imgtec.com> |
| 32 | |
| 33 | * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps |
| 34 | and branches and not synthetic data instructions. |
| 35 | |
| 36 | 2017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de> |
| 37 | |
| 38 | * arm-dis.c (print_insn_thumb32): Fix value_in_comment. |
| 39 | |
| 40 | 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com> |
| 41 | |
| 42 | * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics. |
| 43 | * arc-opc.c (insert_r13el): New function. |
| 44 | (R13_EL): Define. |
| 45 | * arc-tbl.h: Add new enter/leave variants. |
| 46 | |
| 47 | 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com> |
| 48 | |
| 49 | * arc-tbl.h: Reorder NOP entry to be before MOV instructions. |
| 50 | |
| 51 | 2017-04-25 Maciej W. Rozycki <macro@imgtec.com> |
| 52 | |
| 53 | * mips-dis.c (print_mips_disassembler_options): Add |
| 54 | `no-aliases'. |
| 55 | |
| 56 | 2017-04-25 Maciej W. Rozycki <macro@imgtec.com> |
| 57 | |
| 58 | * mips16-opc.c (AL): New macro. |
| 59 | (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms |
| 60 | of "ld" and "lw" as aliases. |
| 61 | |
| 62 | 2017-04-24 Tamar Christina <tamar.christina@arm.com> |
| 63 | |
| 64 | * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE |
| 65 | arguments. |
| 66 | |
| 67 | 2017-04-22 Alexander Fedotov <alfedotov@gmail.com> |
| 68 | Alan Modra <amodra@gmail.com> |
| 69 | |
| 70 | * ppc-opc.c (ELEV): Define. |
| 71 | (vle_opcodes): Add se_rfgi and e_sc. |
| 72 | (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx |
| 73 | for E200Z4. |
| 74 | |
| 75 | 2017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com> |
| 76 | |
| 77 | * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9. |
| 78 | |
| 79 | 2017-04-21 Nick Clifton <nickc@redhat.com> |
| 80 | |
| 81 | PR binutils/21380 |
| 82 | * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R, |
| 83 | LD3R and LD4R. |
| 84 | |
| 85 | 2017-04-13 Alan Modra <amodra@gmail.com> |
| 86 | |
| 87 | * epiphany-desc.c: Regenerate. |
| 88 | * fr30-desc.c: Regenerate. |
| 89 | * frv-desc.c: Regenerate. |
| 90 | * ip2k-desc.c: Regenerate. |
| 91 | * iq2000-desc.c: Regenerate. |
| 92 | * lm32-desc.c: Regenerate. |
| 93 | * m32c-desc.c: Regenerate. |
| 94 | * m32r-desc.c: Regenerate. |
| 95 | * mep-desc.c: Regenerate. |
| 96 | * mt-desc.c: Regenerate. |
| 97 | * or1k-desc.c: Regenerate. |
| 98 | * xc16x-desc.c: Regenerate. |
| 99 | * xstormy16-desc.c: Regenerate. |
| 100 | |
| 101 | 2017-04-11 Alan Modra <amodra@gmail.com> |
| 102 | |
| 103 | * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2, |
| 104 | PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set |
| 105 | PPC_OPCODE_TMR for e6500. |
| 106 | * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500. |
| 107 | (PPCVEC3): Define as PPC_OPCODE_POWER9. |
| 108 | (PPCVSX2): Define as PPC_OPCODE_POWER8. |
| 109 | (PPCVSX3): Define as PPC_OPCODE_POWER9. |
| 110 | (PPCHTM): Define as PPC_OPCODE_POWER8. |
| 111 | (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500. |
| 112 | |
| 113 | 2017-04-10 Alan Modra <amodra@gmail.com> |
| 114 | |
| 115 | * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440. |
| 116 | * ppc-opc.c (MULHW): Add PPC_OPCODE_476. |
| 117 | (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit |
| 118 | removal of PPC_OPCODE_440 from ppc476 cpu selection bits. |
| 119 | |
| 120 | 2017-04-09 Pip Cet <pipcet@gmail.com> |
| 121 | |
| 122 | * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify |
| 123 | appropriate floating-point precision directly. |
| 124 | |
| 125 | 2017-04-07 Alan Modra <amodra@gmail.com> |
| 126 | |
| 127 | * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl, |
| 128 | lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx, |
| 129 | lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx, |
| 130 | lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only |
| 131 | vector instructions with E6500 not PPCVEC2. |
| 132 | |
| 133 | 2017-04-06 Pip Cet <pipcet@gmail.com> |
| 134 | |
| 135 | * Makefile.am: Add wasm32-dis.c. |
| 136 | * configure.ac: Add wasm32-dis.c to wasm32 target. |
| 137 | * disassemble.c: Add wasm32 disassembler code. |
| 138 | * wasm32-dis.c: New file. |
| 139 | * Makefile.in: Regenerate. |
| 140 | * configure: Regenerate. |
| 141 | * po/POTFILES.in: Regenerate. |
| 142 | * po/opcodes.pot: Regenerate. |
| 143 | |
| 144 | 2017-04-05 Pedro Alves <palves@redhat.com> |
| 145 | |
| 146 | * arc-dis.c (parse_option, parse_disassembler_options): Constify. |
| 147 | * arm-dis.c (parse_arm_disassembler_options): Constify. |
| 148 | * ppc-dis.c (powerpc_init_dialect): Constify local. |
| 149 | * vax-dis.c (parse_disassembler_options): Constify. |
| 150 | |
| 151 | 2017-04-03 Palmer Dabbelt <palmer@dabbelt.com> |
| 152 | |
| 153 | * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to |
| 154 | RISCV_GP_SYMBOL. |
| 155 | |
| 156 | 2017-03-30 Pip Cet <pipcet@gmail.com> |
| 157 | |
| 158 | * configure.ac: Add (empty) bfd_wasm32_arch target. |
| 159 | * configure: Regenerate |
| 160 | * po/opcodes.pot: Regenerate. |
| 161 | |
| 162 | 2017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com> |
| 163 | |
| 164 | Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, & |
| 165 | OSA2015. |
| 166 | * opcodes/sparc-opc.c (asi_table): New ASIs. |
| 167 | |
| 168 | 2017-03-29 Alan Modra <amodra@gmail.com> |
| 169 | |
| 170 | * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add |
| 171 | "raw" option. |
| 172 | (lookup_powerpc): Don't special case -1 dialect. Handle |
| 173 | PPC_OPCODE_RAW. |
| 174 | (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first |
| 175 | lookup_powerpc call, pass it on second. |
| 176 | |
| 177 | 2017-03-27 Alan Modra <amodra@gmail.com> |
| 178 | |
| 179 | PR 21303 |
| 180 | * ppc-dis.c (struct ppc_mopt): Comment. |
| 181 | (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu. |
| 182 | |
| 183 | 2017-03-27 Rinat Zelig <rinat@mellanox.com> |
| 184 | |
| 185 | * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format. |
| 186 | * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR, |
| 187 | F_NPS_M, F_NPS_CORE, F_NPS_ALL. |
| 188 | (insert_nps_misc_imm_offset): New function. |
| 189 | (extract_nps_misc imm_offset): New function. |
| 190 | (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T. |
| 191 | (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T. |
| 192 | |
| 193 | 2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com> |
| 194 | |
| 195 | * s390-mkopc.c (main): Remove vx2 check. |
| 196 | * s390-opc.txt: Remove vx2 instruction flags. |
| 197 | |
| 198 | 2017-03-21 Rinat Zelig <rinat@mellanox.com> |
| 199 | |
| 200 | * arc-nps400-tbl.h: Add cp32/cp16 instructions format. |
| 201 | * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET. |
| 202 | (insert_nps_imm_offset): New function. |
| 203 | (extract_nps_imm_offset): New function. |
| 204 | (insert_nps_imm_entry): New function. |
| 205 | (extract_nps_imm_entry): New function. |
| 206 | |
| 207 | 2017-03-17 Alan Modra <amodra@gmail.com> |
| 208 | |
| 209 | PR 21248 |
| 210 | * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33, |
| 211 | mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after |
| 212 | those spr mnemonics they alias. Similarly for mtibatl, mtibatu. |
| 213 | |
| 214 | 2017-03-14 Kito Cheng <kito.cheng@gmail.com> |
| 215 | |
| 216 | * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding. |
| 217 | <c.andi>: Likewise. |
| 218 | <c.addiw> Likewise. |
| 219 | |
| 220 | 2017-03-14 Kito Cheng <kito.cheng@gmail.com> |
| 221 | |
| 222 | * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode. |
| 223 | |
| 224 | 2017-03-13 Andrew Waterman <andrew@sifive.com> |
| 225 | |
| 226 | * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode. |
| 227 | <srl> Likewise. |
| 228 | <srai> Likewise. |
| 229 | <sra> Likewise. |
| 230 | |
| 231 | 2017-03-09 H.J. Lu <hongjiu.lu@intel.com> |
| 232 | |
| 233 | * i386-gen.c (opcode_modifiers): Replace S with Load. |
| 234 | * i386-opc.h (S): Removed. |
| 235 | (Load): New. |
| 236 | (i386_opcode_modifier): Replace s with load. |
| 237 | * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3} |
| 238 | and {evex}. Replace S with Load. |
| 239 | * i386-tbl.h: Regenerated. |
| 240 | |
| 241 | 2017-03-09 H.J. Lu <hongjiu.lu@intel.com> |
| 242 | |
| 243 | * i386-opc.tbl: Use CpuCET on rdsspq. |
| 244 | * i386-tbl.h: Regenerated. |
| 245 | |
| 246 | 2017-03-08 Peter Bergner <bergner@vnet.ibm.com> |
| 247 | |
| 248 | * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2; |
| 249 | <vsx>: Do not use PPC_OPCODE_VSX3; |
| 250 | |
| 251 | 2017-03-08 Peter Bergner <bergner@vnet.ibm.com> |
| 252 | |
| 253 | * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic. |
| 254 | |
| 255 | 2017-03-06 H.J. Lu <hongjiu.lu@intel.com> |
| 256 | |
| 257 | * i386-dis.c (REG_0F1E_MOD_3): New enum. |
| 258 | (MOD_0F1E_PREFIX_1): Likewise. |
| 259 | (MOD_0F38F5_PREFIX_2): Likewise. |
| 260 | (MOD_0F38F6_PREFIX_0): Likewise. |
| 261 | (RM_0F1E_MOD_3_REG_7): Likewise. |
| 262 | (PREFIX_MOD_0_0F01_REG_5): Likewise. |
| 263 | (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise. |
| 264 | (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise. |
| 265 | (PREFIX_0F1E): Likewise. |
| 266 | (PREFIX_MOD_0_0FAE_REG_5): Likewise. |
| 267 | (PREFIX_0F38F5): Likewise. |
| 268 | (dis386_twobyte): Use PREFIX_0F1E. |
| 269 | (reg_table): Add REG_0F1E_MOD_3. |
| 270 | (prefix_table): Add PREFIX_MOD_0_0F01_REG_5, |
| 271 | PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2, |
| 272 | PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update |
| 273 | PREFIX_0FAE_REG_6 and PREFIX_0F38F6. |
| 274 | (three_byte_table): Use PREFIX_0F38F5. |
| 275 | (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5. |
| 276 | Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0. |
| 277 | (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0, |
| 278 | RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and |
| 279 | PREFIX_MOD_3_0F01_REG_5_RM_2. |
| 280 | * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS. |
| 281 | (cpu_flags): Add CpuCET. |
| 282 | * i386-opc.h (CpuCET): New enum. |
| 283 | (CpuUnused): Commented out. |
| 284 | (i386_cpu_flags): Add cpucet. |
| 285 | * i386-opc.tbl: Add Intel CET instructions. |
| 286 | * i386-init.h: Regenerated. |
| 287 | * i386-tbl.h: Likewise. |
| 288 | |
| 289 | 2017-03-06 Alan Modra <amodra@gmail.com> |
| 290 | |
| 291 | PR 21124 |
| 292 | * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram) |
| 293 | (extract_raq, extract_ras, extract_rbx): New functions. |
| 294 | (powerpc_operands): Use opposite corresponding insert function. |
| 295 | (Q_MASK): Define. |
| 296 | (powerpc_opcodes): Apply Q_MASK to all quad insns with even |
| 297 | register restriction. |
| 298 | |
| 299 | 2017-02-28 Peter Bergner <bergner@vnet.ibm.com> |
| 300 | |
| 301 | * disassemble.c Include "safe-ctype.h". |
| 302 | (disassemble_init_for_target): Handle s390 init. |
| 303 | (remove_whitespace_and_extra_commas): New function. |
| 304 | (disassembler_options_cmp): Likewise. |
| 305 | * arm-dis.c: Include "libiberty.h". |
| 306 | (NUM_ELEM): Delete. |
| 307 | (regnames): Use long disassembler style names. |
| 308 | Add force-thumb and no-force-thumb options. |
| 309 | (NUM_ARM_REGNAMES): Rename from this... |
| 310 | (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE. |
| 311 | (get_arm_regname_num_options): Delete. |
| 312 | (set_arm_regname_option): Likewise. |
| 313 | (get_arm_regnames): Likewise. |
| 314 | (parse_disassembler_options): Likewise. |
| 315 | (parse_arm_disassembler_option): Rename from this... |
| 316 | (parse_arm_disassembler_options): ...to this. Make static. |
| 317 | Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options. |
| 318 | (print_insn): Use parse_arm_disassembler_options. |
| 319 | (disassembler_options_arm): New function. |
| 320 | (print_arm_disassembler_options): Handle updated regnames. |
| 321 | * ppc-dis.c: Include "libiberty.h". |
| 322 | (ppc_opts): Add "32" and "64" entries. |
| 323 | (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp. |
| 324 | (powerpc_init_dialect): Add break to switch statement. |
| 325 | Use new FOR_EACH_DISASSEMBLER_OPTION macro. |
| 326 | (disassembler_options_powerpc): New function. |
| 327 | (print_ppc_disassembler_options): Use ARRAY_SIZE. |
| 328 | Remove printing of "32" and "64". |
| 329 | * s390-dis.c: Include "libiberty.h". |
| 330 | (init_flag): Remove unneeded variable. |
| 331 | (struct s390_options_t): New structure type. |
| 332 | (options): New structure. |
| 333 | (init_disasm): Rename from this... |
| 334 | (disassemble_init_s390): ...to this. Add initializations for |
| 335 | current_arch_mask and option_use_insn_len_bits_p. Remove init_flag. |
| 336 | (print_insn_s390): Delete call to init_disasm. |
| 337 | (disassembler_options_s390): New function. |
| 338 | (print_s390_disassembler_options): Print using information from |
| 339 | struct 'options'. |
| 340 | * po/opcodes.pot: Regenerate. |
| 341 | |
| 342 | 2017-02-28 Jan Beulich <jbeulich@suse.com> |
| 343 | |
| 344 | * i386-dis.c (PCMPESTR_Fixup): New. |
| 345 | (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete. |
| 346 | (prefix_table): Use PCMPESTR_Fixup. |
| 347 | (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use |
| 348 | PCMPESTR_Fixup. |
| 349 | (vex_w_table): Delete VPCMPESTR{I,M} entries. |
| 350 | * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm): |
| 351 | Split 64-bit and non-64-bit variants. |
| 352 | * opcodes/i386-tbl.h: Re-generate. |
| 353 | |
| 354 | 2017-02-24 Richard Sandiford <richard.sandiford@arm.com> |
| 355 | |
| 356 | * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD) |
| 357 | (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD) |
| 358 | (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S) |
| 359 | (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H) |
| 360 | (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH) |
| 361 | (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD) |
| 362 | (OP_SVE_V_HSD): New macros. |
| 363 | (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD) |
| 364 | (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD) |
| 365 | (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete. |
| 366 | (aarch64_opcode_table): Add new SVE instructions. |
| 367 | (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate |
| 368 | for rotation operands. Add new SVE operands. |
| 369 | * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter. |
| 370 | (ins_sve_quad_index): Likewise. |
| 371 | (ins_imm_rotate): Split into... |
| 372 | (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters. |
| 373 | * aarch64-asm.c (aarch64_ins_imm_rotate): Split into... |
| 374 | (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two |
| 375 | functions. |
| 376 | (aarch64_ins_sve_addr_ri_s4): New function. |
| 377 | (aarch64_ins_sve_quad_index): Likewise. |
| 378 | (do_misc_encoding): Handle "MOV Zn.Q, Qm". |
| 379 | * aarch64-asm-2.c: Regenerate. |
| 380 | * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor. |
| 381 | (ext_sve_quad_index): Likewise. |
| 382 | (ext_imm_rotate): Split into... |
| 383 | (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors. |
| 384 | * aarch64-dis.c (aarch64_ext_imm_rotate): Split into... |
| 385 | (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two |
| 386 | functions. |
| 387 | (aarch64_ext_sve_addr_ri_s4): New function. |
| 388 | (aarch64_ext_sve_quad_index): Likewise. |
| 389 | (aarch64_ext_sve_index): Allow quad indices. |
| 390 | (do_misc_decoding): Likewise. |
| 391 | * aarch64-dis-2.c: Regenerate. |
| 392 | * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New |
| 393 | aarch64_field_kinds. |
| 394 | (OPD_F_OD_MASK): Widen by one bit. |
| 395 | (OPD_F_NO_ZR): Bump accordingly. |
| 396 | (get_operand_field_width): New function. |
| 397 | * aarch64-opc.c (fields): Add new SVE fields. |
| 398 | (operand_general_constraint_met_p): Handle new SVE operands. |
| 399 | (aarch64_print_operand): Likewise. |
| 400 | * aarch64-opc-2.c: Regenerate. |
| 401 | |
| 402 | 2017-02-24 Richard Sandiford <richard.sandiford@arm.com> |
| 403 | |
| 404 | * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with... |
| 405 | (aarch64_feature_compnum): ...this. |
| 406 | (SIMD_V8_3): Replace with... |
| 407 | (COMPNUM): ...this. |
| 408 | (CNUM_INSN): New macro. |
| 409 | (aarch64_opcode_table): Use it for the complex number instructions. |
| 410 | |
| 411 | 2017-02-24 Jan Beulich <jbeulich@suse.com> |
| 412 | |
| 413 | * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST. |
| 414 | |
| 415 | 2017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com> |
| 416 | |
| 417 | Add support for associating SPARC ASIs with an architecture level. |
| 418 | * include/opcode/sparc.h (sparc_asi): New sparc_asi struct. |
| 419 | * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/ |
| 420 | decoding of SPARC ASIs. |
| 421 | |
| 422 | 2017-02-23 Jan Beulich <jbeulich@suse.com> |
| 423 | |
| 424 | * i386-dis.c (get_valid_dis386): Don't special case VEX opcode |
| 425 | 82. For 3-byte VEX only special case opcode 77 in VEX_0F space. |
| 426 | |
| 427 | 2017-02-21 Jan Beulich <jbeulich@suse.com> |
| 428 | |
| 429 | * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand |
| 430 | 1 (instead of to itself). Correct typo. |
| 431 | |
| 432 | 2017-02-14 Andrew Waterman <andrew@sifive.com> |
| 433 | |
| 434 | * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and |
| 435 | pseudoinstructions. |
| 436 | |
| 437 | 2017-02-15 Richard Sandiford <richard.sandiford@arm.com> |
| 438 | |
| 439 | * aarch64-opc.c (aarch64_sys_regs): Add SVE registers. |
| 440 | (aarch64_sys_reg_supported_p): Handle them. |
| 441 | |
| 442 | 2017-02-15 Claudiu Zissulescu <claziss@synopsys.com> |
| 443 | |
| 444 | * arc-opc.c (UIMM6_20R): Define. |
| 445 | (SIMM12_20): Use above. |
| 446 | (SIMM12_20R): Define. |
| 447 | (SIMM3_5_S): Use above. |
| 448 | (UIMM7_A32_11R_S): Define. |
| 449 | (UIMM7_9_S): Use above. |
| 450 | (UIMM3_13R_S): Define. |
| 451 | (SIMM11_A32_7_S): Use above. |
| 452 | (SIMM9_8R): Define. |
| 453 | (UIMM10_A32_8_S): Use above. |
| 454 | (UIMM8_8R_S): Define. |
| 455 | (W6): Use above. |
| 456 | (arc_relax_opcodes): Use all above defines. |
| 457 | |
| 458 | 2017-02-15 Vineet Gupta <vgupta@synopsys.com> |
| 459 | |
| 460 | * arc-regs.h: Distinguish some of the registers different on |
| 461 | ARC700 and HS38 cpus. |
| 462 | |
| 463 | 2017-02-14 Alan Modra <amodra@gmail.com> |
| 464 | |
| 465 | PR 21118 |
| 466 | * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries |
| 467 | with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR. |
| 468 | |
| 469 | 2017-02-11 Stafford Horne <shorne@gmail.com> |
| 470 | Alan Modra <amodra@gmail.com> |
| 471 | |
| 472 | * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps. |
| 473 | Use insn_bytes_value and insn_int_value directly instead. Don't |
| 474 | free allocated memory until function exit. |
| 475 | |
| 476 | 2017-02-10 Nicholas Piggin <npiggin@gmail.com> |
| 477 | |
| 478 | * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics. |
| 479 | |
| 480 | 2017-02-03 Nick Clifton <nickc@redhat.com> |
| 481 | |
| 482 | PR 21096 |
| 483 | * aarch64-opc.c (print_register_list): Ensure that the register |
| 484 | list index will fir into the tb buffer. |
| 485 | (print_register_offset_address): Likewise. |
| 486 | * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf. |
| 487 | |
| 488 | 2017-01-27 Alexis Deruell <alexis.deruelle@gmail.com> |
| 489 | |
| 490 | PR 21056 |
| 491 | * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel |
| 492 | instructions when the previous fetch packet ends with a 32-bit |
| 493 | instruction. |
| 494 | |
| 495 | 2017-01-24 Dimitar Dimitrov <dimitar@dinux.eu> |
| 496 | |
| 497 | * pru-opc.c: Remove vague reference to a future GDB port. |
| 498 | |
| 499 | 2017-01-20 Nick Clifton <nickc@redhat.com> |
| 500 | |
| 501 | * po/ga.po: Updated Irish translation. |
| 502 | |
| 503 | 2017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com> |
| 504 | |
| 505 | * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly. |
| 506 | |
| 507 | 2017-01-13 Yao Qi <yao.qi@linaro.org> |
| 508 | |
| 509 | * m68k-dis.c (match_insn_m68k): Extend comments. Return -1 |
| 510 | if FETCH_DATA returns 0. |
| 511 | (m68k_scan_mask): Likewise. |
| 512 | (print_insn_m68k): Update code to handle -1 return value. |
| 513 | |
| 514 | 2017-01-13 Yao Qi <yao.qi@linaro.org> |
| 515 | |
| 516 | * m68k-dis.c (enum print_insn_arg_error): New. |
| 517 | (NEXTBYTE): Replace -3 with |
| 518 | PRINT_INSN_ARG_MEMORY_ERROR. |
| 519 | (NEXTULONG): Likewise. |
| 520 | (NEXTSINGLE): Likewise. |
| 521 | (NEXTDOUBLE): Likewise. |
| 522 | (NEXTDOUBLE): Likewise. |
| 523 | (NEXTPACKED): Likewise. |
| 524 | (FETCH_ARG): Likewise. |
| 525 | (FETCH_DATA): Update comments. |
| 526 | (print_insn_arg): Update comments. Replace magic numbers with |
| 527 | enum. |
| 528 | (match_insn_m68k): Likewise. |
| 529 | |
| 530 | 2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com> |
| 531 | |
| 532 | * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2. |
| 533 | * i386-dis-evex.h (evex_table): Updated. |
| 534 | * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS, |
| 535 | CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS. |
| 536 | (cpu_flags): Add CpuAVX512_VPOPCNTDQ. |
| 537 | * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New. |
| 538 | (i386_cpu_flags): Add cpuavx512_vpopcntdq. |
| 539 | * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions. |
| 540 | * i386-init.h: Regenerate. |
| 541 | * i386-tbl.h: Ditto. |
| 542 | |
| 543 | 2017-01-12 Yao Qi <yao.qi@linaro.org> |
| 544 | |
| 545 | * msp430-dis.c (msp430_singleoperand): Return -1 if |
| 546 | msp430dis_opcode_signed returns false. |
| 547 | (msp430_doubleoperand): Likewise. |
| 548 | (msp430_branchinstr): Return -1 if |
| 549 | msp430dis_opcode_unsigned returns false. |
| 550 | (msp430x_calla_instr): Likewise. |
| 551 | (print_insn_msp430): Likewise. |
| 552 | |
| 553 | 2017-01-05 Nick Clifton <nickc@redhat.com> |
| 554 | |
| 555 | PR 20946 |
| 556 | * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name |
| 557 | could not be matched. |
| 558 | (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning |
| 559 | NULL. |
| 560 | |
| 561 | 2017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com> |
| 562 | |
| 563 | * aarch64-tbl.h (RCPC, RCPC_INSN): Define. |
| 564 | (aarch64_opcode_table): Use RCPC_INSN. |
| 565 | |
| 566 | 2017-01-03 Kito Cheng <kito.cheng@gmail.com> |
| 567 | |
| 568 | * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA |
| 569 | extension. |
| 570 | * riscv-opcodes/all-opcodes: Likewise. |
| 571 | |
| 572 | 2017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org> |
| 573 | |
| 574 | * riscv-dis.c (print_insn_args): Add fall through comment. |
| 575 | |
| 576 | 2017-01-03 Nick Clifton <nickc@redhat.com> |
| 577 | |
| 578 | * po/sr.po: New Serbian translation. |
| 579 | * configure.ac (ALL_LINGUAS): Add sr. |
| 580 | * configure: Regenerate. |
| 581 | |
| 582 | 2017-01-02 Alan Modra <amodra@gmail.com> |
| 583 | |
| 584 | * epiphany-desc.h: Regenerate. |
| 585 | * epiphany-opc.h: Regenerate. |
| 586 | * fr30-desc.h: Regenerate. |
| 587 | * fr30-opc.h: Regenerate. |
| 588 | * frv-desc.h: Regenerate. |
| 589 | * frv-opc.h: Regenerate. |
| 590 | * ip2k-desc.h: Regenerate. |
| 591 | * ip2k-opc.h: Regenerate. |
| 592 | * iq2000-desc.h: Regenerate. |
| 593 | * iq2000-opc.h: Regenerate. |
| 594 | * lm32-desc.h: Regenerate. |
| 595 | * lm32-opc.h: Regenerate. |
| 596 | * m32c-desc.h: Regenerate. |
| 597 | * m32c-opc.h: Regenerate. |
| 598 | * m32r-desc.h: Regenerate. |
| 599 | * m32r-opc.h: Regenerate. |
| 600 | * mep-desc.h: Regenerate. |
| 601 | * mep-opc.h: Regenerate. |
| 602 | * mt-desc.h: Regenerate. |
| 603 | * mt-opc.h: Regenerate. |
| 604 | * or1k-desc.h: Regenerate. |
| 605 | * or1k-opc.h: Regenerate. |
| 606 | * xc16x-desc.h: Regenerate. |
| 607 | * xc16x-opc.h: Regenerate. |
| 608 | * xstormy16-desc.h: Regenerate. |
| 609 | * xstormy16-opc.h: Regenerate. |
| 610 | |
| 611 | 2017-01-02 Alan Modra <amodra@gmail.com> |
| 612 | |
| 613 | Update year range in copyright notice of all files. |
| 614 | |
| 615 | For older changes see ChangeLog-2016 |
| 616 | \f |
| 617 | Copyright (C) 2017 Free Software Foundation, Inc. |
| 618 | |
| 619 | Copying and distribution of this file, with or without modification, |
| 620 | are permitted in any medium without royalty provided the copyright |
| 621 | notice and this notice are preserved. |
| 622 | |
| 623 | Local Variables: |
| 624 | mode: change-log |
| 625 | left-margin: 8 |
| 626 | fill-column: 74 |
| 627 | version-control: never |
| 628 | End: |