projects / deliverable / binutils-gdb.git / blame_incremental
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (non-incremental) | history | HEAD
[PATCH 42/57][Arm][OBJDUMP] Add support for MVE instructions: vldr[bhw] and vstr...
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
... / ...
CommitLineData
12019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
2 Michael Collison <michael.collison@arm.com>
3
4 * arm-dis.c (enum mve_instructions): Add new instructions.
5 (enum mve_undefined): Add new reasons.
6 (insns): Add new instructions.
7 (is_mve_encoding_conflict):
8 (print_mve_vld_str_addr): New print function.
9 (is_mve_undefined): Handle new instructions.
10 (is_mve_unpredictable): Likewise.
11 (print_mve_undefined): Likewise.
12 (print_mve_size): Likewise.
13 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
14 (print_insn_mve): Handle new operands.
15
162019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
17 Michael Collison <michael.collison@arm.com>
18
19 * arm-dis.c (enum mve_instructions): Add new instructions.
20 (enum mve_unpredictable): Add new reasons.
21 (is_mve_encoding_conflict): Handle new instructions.
22 (is_mve_unpredictable): Likewise.
23 (mve_opcodes): Add new instructions.
24 (print_mve_unpredictable): Handle new reasons.
25 (print_mve_register_blocks): New print function.
26 (print_mve_size): Handle new instructions.
27 (print_insn_mve): Likewise.
28
292019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
30 Michael Collison <michael.collison@arm.com>
31
32 * arm-dis.c (enum mve_instructions): Add new instructions.
33 (enum mve_unpredictable): Add new reasons.
34 (enum mve_undefined): Likewise.
35 (is_mve_encoding_conflict): Handle new instructions.
36 (is_mve_undefined): Likewise.
37 (is_mve_unpredictable): Likewise.
38 (coprocessor_opcodes): Move NEON VDUP from here...
39 (neon_opcodes): ... to here.
40 (mve_opcodes): Add new instructions.
41 (print_mve_undefined): Handle new reasons.
42 (print_mve_unpredictable): Likewise.
43 (print_mve_size): Handle new instructions.
44 (print_insn_neon): Handle vdup.
45 (print_insn_mve): Handle new operands.
46
472019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
48 Michael Collison <michael.collison@arm.com>
49
50 * arm-dis.c (enum mve_instructions): Add new instructions.
51 (enum mve_unpredictable): Add new values.
52 (mve_opcodes): Add new instructions.
53 (vec_condnames): New array with vector conditions.
54 (mve_predicatenames): New array with predicate suffixes.
55 (mve_vec_sizename): New array with vector sizes.
56 (enum vpt_pred_state): New enum with vector predication states.
57 (struct vpt_block): New struct type for vpt blocks.
58 (vpt_block_state): Global struct to keep track of state.
59 (mve_extract_pred_mask): New helper function.
60 (num_instructions_vpt_block): Likewise.
61 (mark_outside_vpt_block): Likewise.
62 (mark_inside_vpt_block): Likewise.
63 (invert_next_predicate_state): Likewise.
64 (update_next_predicate_state): Likewise.
65 (update_vpt_block_state): Likewise.
66 (is_vpt_instruction): Likewise.
67 (is_mve_encoding_conflict): Add entries for new instructions.
68 (is_mve_unpredictable): Likewise.
69 (print_mve_unpredictable): Handle new cases.
70 (print_instruction_predicate): Likewise.
71 (print_mve_size): New function.
72 (print_vec_condition): New function.
73 (print_insn_mve): Handle vpt blocks and new print operands.
74
752019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
76
77 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
78 8, 14 and 15 for Armv8.1-M Mainline.
79
802019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
81 Michael Collison <michael.collison@arm.com>
82
83 * arm-dis.c (enum mve_instructions): New enum.
84 (enum mve_unpredictable): Likewise.
85 (enum mve_undefined): Likewise.
86 (struct mopcode32): New struct.
87 (is_mve_okay_in_it): New function.
88 (is_mve_architecture): Likewise.
89 (arm_decode_field): Likewise.
90 (arm_decode_field_multiple): Likewise.
91 (is_mve_encoding_conflict): Likewise.
92 (is_mve_undefined): Likewise.
93 (is_mve_unpredictable): Likewise.
94 (print_mve_undefined): Likewise.
95 (print_mve_unpredictable): Likewise.
96 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
97 (print_insn_mve): New function.
98 (print_insn_thumb32): Handle MVE architecture.
99 (select_arm_features): Force thumb for Armv8.1-m Mainline.
100
1012019-05-10 Nick Clifton <nickc@redhat.com>
102
103 PR 24538
104 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
105 end of the table prematurely.
106
1072019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
108
109 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
110 macros for R6.
111
1122019-05-11 Alan Modra <amodra@gmail.com>
113
114 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
115 when -Mraw is in effect.
116
1172019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
118
119 * aarch64-dis-2.c: Regenerate.
120 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
121 (OP_SVE_BBB): New variant set.
122 (OP_SVE_DDDD): New variant set.
123 (OP_SVE_HHH): New variant set.
124 (OP_SVE_HHHU): New variant set.
125 (OP_SVE_SSS): New variant set.
126 (OP_SVE_SSSU): New variant set.
127 (OP_SVE_SHH): New variant set.
128 (OP_SVE_SBBU): New variant set.
129 (OP_SVE_DSS): New variant set.
130 (OP_SVE_DHHU): New variant set.
131 (OP_SVE_VMV_HSD_BHS): New variant set.
132 (OP_SVE_VVU_HSD_BHS): New variant set.
133 (OP_SVE_VVVU_SD_BH): New variant set.
134 (OP_SVE_VVVU_BHSD): New variant set.
135 (OP_SVE_VVV_QHD_DBS): New variant set.
136 (OP_SVE_VVV_HSD_BHS): New variant set.
137 (OP_SVE_VVV_HSD_BHS2): New variant set.
138 (OP_SVE_VVV_BHS_HSD): New variant set.
139 (OP_SVE_VV_BHS_HSD): New variant set.
140 (OP_SVE_VVV_SD): New variant set.
141 (OP_SVE_VVU_BHS_HSD): New variant set.
142 (OP_SVE_VZVV_SD): New variant set.
143 (OP_SVE_VZVV_BH): New variant set.
144 (OP_SVE_VZV_SD): New variant set.
145 (aarch64_opcode_table): Add sve2 instructions.
146
1472019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
148
149 * aarch64-asm-2.c: Regenerated.
150 * aarch64-dis-2.c: Regenerated.
151 * aarch64-opc-2.c: Regenerated.
152 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
153 for SVE_SHLIMM_UNPRED_22.
154 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
155 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
156 operand.
157
1582019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
159
160 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
161 sve_size_tsz_bhs iclass encode.
162 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
163 sve_size_tsz_bhs iclass decode.
164
1652019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
166
167 * aarch64-asm-2.c: Regenerated.
168 * aarch64-dis-2.c: Regenerated.
169 * aarch64-opc-2.c: Regenerated.
170 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
171 for SVE_Zm4_11_INDEX.
172 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
173 (fields): Handle SVE_i2h field.
174 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
175 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
176
1772019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
178
179 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
180 sve_shift_tsz_bhsd iclass encode.
181 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
182 sve_shift_tsz_bhsd iclass decode.
183
1842019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
185
186 * aarch64-asm-2.c: Regenerated.
187 * aarch64-dis-2.c: Regenerated.
188 * aarch64-opc-2.c: Regenerated.
189 * aarch64-asm.c (aarch64_ins_sve_shrimm):
190 (aarch64_encode_variant_using_iclass): Handle
191 sve_shift_tsz_hsd iclass encode.
192 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
193 sve_shift_tsz_hsd iclass decode.
194 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
195 for SVE_SHRIMM_UNPRED_22.
196 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
197 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
198 operand.
199
2002019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
201
202 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
203 sve_size_013 iclass encode.
204 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
205 sve_size_013 iclass decode.
206
2072019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
208
209 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
210 sve_size_bh iclass encode.
211 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
212 sve_size_bh iclass decode.
213
2142019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
215
216 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
217 sve_size_sd2 iclass encode.
218 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
219 sve_size_sd2 iclass decode.
220 * aarch64-opc.c (fields): Handle SVE_sz2 field.
221 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
222
2232019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
224
225 * aarch64-asm-2.c: Regenerated.
226 * aarch64-dis-2.c: Regenerated.
227 * aarch64-opc-2.c: Regenerated.
228 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
229 for SVE_ADDR_ZX.
230 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
231 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
232
2332019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
234
235 * aarch64-asm-2.c: Regenerated.
236 * aarch64-dis-2.c: Regenerated.
237 * aarch64-opc-2.c: Regenerated.
238 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
239 for SVE_Zm3_11_INDEX.
240 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
241 (fields): Handle SVE_i3l and SVE_i3h2 fields.
242 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
243 fields.
244 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
245
2462019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
247
248 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
249 sve_size_hsd2 iclass encode.
250 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
251 sve_size_hsd2 iclass decode.
252 * aarch64-opc.c (fields): Handle SVE_size field.
253 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
254
2552019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
256
257 * aarch64-asm-2.c: Regenerated.
258 * aarch64-dis-2.c: Regenerated.
259 * aarch64-opc-2.c: Regenerated.
260 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
261 for SVE_IMM_ROT3.
262 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
263 (fields): Handle SVE_rot3 field.
264 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
265 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
266
2672019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
268
269 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
270 instructions.
271
2722019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
273
274 * aarch64-tbl.h
275 (aarch64_feature_sve2, aarch64_feature_sve2aes,
276 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
277 aarch64_feature_sve2bitperm): New feature sets.
278 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
279 for feature set addresses.
280 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
281 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
282
2832019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
284 Faraz Shahbazker <fshahbazker@wavecomp.com>
285
286 * mips-dis.c (mips_calculate_combination_ases): Add ISA
287 argument and set ASE_EVA_R6 appropriately.
288 (set_default_mips_dis_options): Pass ISA to above.
289 (parse_mips_dis_option): Likewise.
290 * mips-opc.c (EVAR6): New macro.
291 (mips_builtin_opcodes): Add llwpe, scwpe.
292
2932019-05-01 Sudakshina Das <sudi.das@arm.com>
294
295 * aarch64-asm-2.c: Regenerated.
296 * aarch64-dis-2.c: Regenerated.
297 * aarch64-opc-2.c: Regenerated.
298 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
299 AARCH64_OPND_TME_UIMM16.
300 (aarch64_print_operand): Likewise.
301 * aarch64-tbl.h (QL_IMM_NIL): New.
302 (TME): New.
303 (_TME_INSN): New.
304 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
305
3062019-04-29 John Darrington <john@darrington.wattle.id.au>
307
308 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
309
3102019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
311 Faraz Shahbazker <fshahbazker@wavecomp.com>
312
313 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
314
3152019-04-24 John Darrington <john@darrington.wattle.id.au>
316
317 * s12z-opc.h: Add extern "C" bracketing to help
318 users who wish to use this interface in c++ code.
319
3202019-04-24 John Darrington <john@darrington.wattle.id.au>
321
322 * s12z-opc.c (bm_decode): Handle bit map operations with the
323 "reserved0" mode.
324
3252019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
326
327 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
328 specifier. Add entries for VLDR and VSTR of system registers.
329 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
330 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
331 of %J and %K format specifier.
332
3332019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
334
335 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
336 Add new entries for VSCCLRM instruction.
337 (print_insn_coprocessor): Handle new %C format control code.
338
3392019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
340
341 * arm-dis.c (enum isa): New enum.
342 (struct sopcode32): New structure.
343 (coprocessor_opcodes): change type of entries to struct sopcode32 and
344 set isa field of all current entries to ANY.
345 (print_insn_coprocessor): Change type of insn to struct sopcode32.
346 Only match an entry if its isa field allows the current mode.
347
3482019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
349
350 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
351 CLRM.
352 (print_insn_thumb32): Add logic to print %n CLRM register list.
353
3542019-04-15 Sudakshina Das <sudi.das@arm.com>
355
356 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
357 and %Q patterns.
358
3592019-04-15 Sudakshina Das <sudi.das@arm.com>
360
361 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
362 (print_insn_thumb32): Edit the switch case for %Z.
363
3642019-04-15 Sudakshina Das <sudi.das@arm.com>
365
366 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
367
3682019-04-15 Sudakshina Das <sudi.das@arm.com>
369
370 * arm-dis.c (thumb32_opcodes): New instruction bfl.
371
3722019-04-15 Sudakshina Das <sudi.das@arm.com>
373
374 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
375
3762019-04-15 Sudakshina Das <sudi.das@arm.com>
377
378 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
379 Arm register with r13 and r15 unpredictable.
380 (thumb32_opcodes): New instructions for bfx and bflx.
381
3822019-04-15 Sudakshina Das <sudi.das@arm.com>
383
384 * arm-dis.c (thumb32_opcodes): New instructions for bf.
385
3862019-04-15 Sudakshina Das <sudi.das@arm.com>
387
388 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
389
3902019-04-15 Sudakshina Das <sudi.das@arm.com>
391
392 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
393
3942019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
395
396 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
397
3982019-04-12 John Darrington <john@darrington.wattle.id.au>
399
400 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
401 "optr". ("operator" is a reserved word in c++).
402
4032019-04-11 Sudakshina Das <sudi.das@arm.com>
404
405 * aarch64-opc.c (aarch64_print_operand): Add case for
406 AARCH64_OPND_Rt_SP.
407 (verify_constraints): Likewise.
408 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
409 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
410 to accept Rt|SP as first operand.
411 (AARCH64_OPERANDS): Add new Rt_SP.
412 * aarch64-asm-2.c: Regenerated.
413 * aarch64-dis-2.c: Regenerated.
414 * aarch64-opc-2.c: Regenerated.
415
4162019-04-11 Sudakshina Das <sudi.das@arm.com>
417
418 * aarch64-asm-2.c: Regenerated.
419 * aarch64-dis-2.c: Likewise.
420 * aarch64-opc-2.c: Likewise.
421 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
422
4232019-04-09 Robert Suchanek <robert.suchanek@mips.com>
424
425 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
426
4272019-04-08 H.J. Lu <hongjiu.lu@intel.com>
428
429 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
430 * i386-init.h: Regenerated.
431
4322019-04-07 Alan Modra <amodra@gmail.com>
433
434 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
435 op_separator to control printing of spaces, comma and parens
436 rather than need_comma, need_paren and spaces vars.
437
4382019-04-07 Alan Modra <amodra@gmail.com>
439
440 PR 24421
441 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
442 (print_insn_neon, print_insn_arm): Likewise.
443
4442019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
445
446 * i386-dis-evex.h (evex_table): Updated to support BF16
447 instructions.
448 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
449 and EVEX_W_0F3872_P_3.
450 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
451 (cpu_flags): Add bitfield for CpuAVX512_BF16.
452 * i386-opc.h (enum): Add CpuAVX512_BF16.
453 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
454 * i386-opc.tbl: Add AVX512 BF16 instructions.
455 * i386-init.h: Regenerated.
456 * i386-tbl.h: Likewise.
457
4582019-04-05 Alan Modra <amodra@gmail.com>
459
460 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
461 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
462 to favour printing of "-" branch hint when using the "y" bit.
463 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
464
4652019-04-05 Alan Modra <amodra@gmail.com>
466
467 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
468 opcode until first operand is output.
469
4702019-04-04 Peter Bergner <bergner@linux.ibm.com>
471
472 PR gas/24349
473 * ppc-opc.c (valid_bo_pre_v2): Add comments.
474 (valid_bo_post_v2): Add support for 'at' branch hints.
475 (insert_bo): Only error on branch on ctr.
476 (get_bo_hint_mask): New function.
477 (insert_boe): Add new 'branch_taken' formal argument. Add support
478 for inserting 'at' branch hints.
479 (extract_boe): Add new 'branch_taken' formal argument. Add support
480 for extracting 'at' branch hints.
481 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
482 (BOE): Delete operand.
483 (BOM, BOP): New operands.
484 (RM): Update value.
485 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
486 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
487 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
488 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
489 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
490 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
491 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
492 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
493 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
494 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
495 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
496 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
497 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
498 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
499 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
500 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
501 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
502 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
503 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
504 bttarl+>: New extended mnemonics.
505
5062019-03-28 Alan Modra <amodra@gmail.com>
507
508 PR 24390
509 * ppc-opc.c (BTF): Define.
510 (powerpc_opcodes): Use for mtfsb*.
511 * ppc-dis.c (print_insn_powerpc): Print fields with both
512 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
513
5142019-03-25 Tamar Christina <tamar.christina@arm.com>
515
516 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
517 (mapping_symbol_for_insn): Implement new algorithm.
518 (print_insn): Remove duplicate code.
519
5202019-03-25 Tamar Christina <tamar.christina@arm.com>
521
522 * aarch64-dis.c (print_insn_aarch64):
523 Implement override.
524
5252019-03-25 Tamar Christina <tamar.christina@arm.com>
526
527 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
528 order.
529
5302019-03-25 Tamar Christina <tamar.christina@arm.com>
531
532 * aarch64-dis.c (last_stop_offset): New.
533 (print_insn_aarch64): Use stop_offset.
534
5352019-03-19 H.J. Lu <hongjiu.lu@intel.com>
536
537 PR gas/24359
538 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
539 CPU_ANY_AVX2_FLAGS.
540 * i386-init.h: Regenerated.
541
5422019-03-18 H.J. Lu <hongjiu.lu@intel.com>
543
544 PR gas/24348
545 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
546 vmovdqu16, vmovdqu32 and vmovdqu64.
547 * i386-tbl.h: Regenerated.
548
5492019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
550
551 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
552 from vstrszb, vstrszh, and vstrszf.
553
5542019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
555
556 * s390-opc.txt: Add instruction descriptions.
557
5582019-02-08 Jim Wilson <jimw@sifive.com>
559
560 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
561 <bne>: Likewise.
562
5632019-02-07 Tamar Christina <tamar.christina@arm.com>
564
565 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
566
5672019-02-07 Tamar Christina <tamar.christina@arm.com>
568
569 PR binutils/23212
570 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
571 * aarch64-opc.c (verify_elem_sd): New.
572 (fields): Add FLD_sz entr.
573 * aarch64-tbl.h (_SIMD_INSN): New.
574 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
575 fmulx scalar and vector by element isns.
576
5772019-02-07 Nick Clifton <nickc@redhat.com>
578
579 * po/sv.po: Updated Swedish translation.
580
5812019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
582
583 * s390-mkopc.c (main): Accept arch13 as cpu string.
584 * s390-opc.c: Add new instruction formats and instruction opcode
585 masks.
586 * s390-opc.txt: Add new arch13 instructions.
587
5882019-01-25 Sudakshina Das <sudi.das@arm.com>
589
590 * aarch64-tbl.h (QL_LDST_AT): Update macro.
591 (aarch64_opcode): Change encoding for stg, stzg
592 st2g and st2zg.
593 * aarch64-asm-2.c: Regenerated.
594 * aarch64-dis-2.c: Regenerated.
595 * aarch64-opc-2.c: Regenerated.
596
5972019-01-25 Sudakshina Das <sudi.das@arm.com>
598
599 * aarch64-asm-2.c: Regenerated.
600 * aarch64-dis-2.c: Likewise.
601 * aarch64-opc-2.c: Likewise.
602 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
603
6042019-01-25 Sudakshina Das <sudi.das@arm.com>
605 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
606
607 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
608 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
609 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
610 * aarch64-dis.h (ext_addr_simple_2): Likewise.
611 * aarch64-opc.c (operand_general_constraint_met_p): Remove
612 case for ldstgv_indexed.
613 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
614 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
615 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
616 * aarch64-asm-2.c: Regenerated.
617 * aarch64-dis-2.c: Regenerated.
618 * aarch64-opc-2.c: Regenerated.
619
6202019-01-23 Nick Clifton <nickc@redhat.com>
621
622 * po/pt_BR.po: Updated Brazilian Portuguese translation.
623
6242019-01-21 Nick Clifton <nickc@redhat.com>
625
626 * po/de.po: Updated German translation.
627 * po/uk.po: Updated Ukranian translation.
628
6292019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
630 * mips-dis.c (mips_arch_choices): Fix typo in
631 gs464, gs464e and gs264e descriptors.
632
6332019-01-19 Nick Clifton <nickc@redhat.com>
634
635 * configure: Regenerate.
636 * po/opcodes.pot: Regenerate.
637
6382018-06-24 Nick Clifton <nickc@redhat.com>
639
640 2.32 branch created.
641
6422019-01-09 John Darrington <john@darrington.wattle.id.au>
643
644 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
645 if it is null.
646 -dis.c (opr_emit_disassembly): Do not omit an index if it is
647 zero.
648
6492019-01-09 Andrew Paprocki <andrew@ishiboo.com>
650
651 * configure: Regenerate.
652
6532019-01-07 Alan Modra <amodra@gmail.com>
654
655 * configure: Regenerate.
656 * po/POTFILES.in: Regenerate.
657
6582019-01-03 John Darrington <john@darrington.wattle.id.au>
659
660 * s12z-opc.c: New file.
661 * s12z-opc.h: New file.
662 * s12z-dis.c: Removed all code not directly related to display
663 of instructions. Used the interface provided by the new files
664 instead.
665 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
666 * Makefile.in: Regenerate.
667 * configure.ac (bfd_s12z_arch): Correct the dependencies.
668 * configure: Regenerate.
669
6702019-01-01 Alan Modra <amodra@gmail.com>
671
672 Update year range in copyright notice of all files.
673
674For older changes see ChangeLog-2018
675\f
676Copyright (C) 2019 Free Software Foundation, Inc.
677
678Copying and distribution of this file, with or without modification,
679are permitted in any medium without royalty provided the copyright
680notice and this notice are preserved.
681
682Local Variables:
683mode: change-log
684left-margin: 8
685fill-column: 74
686version-control: never
687End:
GDB Binutils - Deliverables
This page took 0.025417 seconds and 4 git commands to generate.