Add support for .extInstruction pseudo-op.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
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CommitLineData
12016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
2
3 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
4 Initialize.
5 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
6 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
7 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
8 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
9 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
10 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
11 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
12 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
13 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
14 (arc_opcode arc_opcodes): Null terminate the array.
15 (arc_num_opcodes): Remove.
16 * arc-ext.h (INSERT_XOP): Define.
17 (extInstruction_t): Likewise.
18 (arcExtMap_instName): Delete.
19 (arcExtMap_insn): New function.
20 (arcExtMap_genOpcode): Likewise.
21 * arc-ext.c (ExtInstruction): Remove.
22 (create_map): Zero initialize instruction fields.
23 (arcExtMap_instName): Remove.
24 (arcExtMap_insn): New function.
25 (dump_ARC_extmap): More info while debuging.
26 (arcExtMap_genOpcode): New function.
27 * arc-dis.c (find_format): New function.
28 (print_insn_arc): Use find_format.
29 (arc_get_disassembler): Enable dump_ARC_extmap only when
30 debugging.
31
322016-04-11 Maciej W. Rozycki <macro@imgtec.com>
33
34 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
35 instruction bits out.
36
372016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
38
39 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
40 * arc-opc.c (arc_flag_operands): Add new flags.
41 (arc_flag_classes): Add new classes.
42
432016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
44
45 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
46
472016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
48
49 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
50 encode1, rflt, crc16, and crc32 instructions.
51 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
52 (arc_flag_classes): Add C_NPS_R.
53 (insert_nps_bitop_size_2b): New function.
54 (extract_nps_bitop_size_2b): Likewise.
55 (insert_nps_bitop_uimm8): Likewise.
56 (extract_nps_bitop_uimm8): Likewise.
57 (arc_operands): Add new operand entries.
58
592016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
60
61 * arc-regs.h: Add a new subclass field. Add double assist
62 accumulator register values.
63 * arc-tbl.h: Use DPA subclass to mark the double assist
64 instructions. Use DPX/SPX subclas to mark the FPX instructions.
65 * arc-opc.c (RSP): Define instead of SP.
66 (arc_aux_regs): Add the subclass field.
67
682016-04-05 Jiong Wang <jiong.wang@arm.com>
69
70 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
71
722016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
73
74 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
75 NPS_R_SRC1.
76
772016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
78
79 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
80 issues. No functional changes.
81
822016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
83
84 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
85 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
86 (RTT): Remove duplicate.
87 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
88 (PCT_CONFIG*): Remove.
89 (D1L, D1H, D2H, D2L): Define.
90
912016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
92
93 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
94
952016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
96
97 * arc-tbl.h (invld07): Remove.
98 * arc-ext-tbl.h: New file.
99 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
100 * arc-opc.c (arc_opcodes): Add ext-tbl include.
101
1022016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
103
104 Fix -Wstack-usage warnings.
105 * aarch64-dis.c (print_operands): Substitute size.
106 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
107
1082016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
109
110 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
111 to get a proper diagnostic when an invalid ASR register is used.
112
1132016-03-22 Nick Clifton <nickc@redhat.com>
114
115 * configure: Regenerate.
116
1172016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
118
119 * arc-nps400-tbl.h: New file.
120 * arc-opc.c: Add top level comment.
121 (insert_nps_3bit_dst): New function.
122 (extract_nps_3bit_dst): New function.
123 (insert_nps_3bit_src2): New function.
124 (extract_nps_3bit_src2): New function.
125 (insert_nps_bitop_size): New function.
126 (extract_nps_bitop_size): New function.
127 (arc_flag_operands): Add nps400 entries.
128 (arc_flag_classes): Add nps400 entries.
129 (arc_operands): Add nps400 entries.
130 (arc_opcodes): Add nps400 include.
131
1322016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
133
134 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
135 the new class enum values.
136
1372016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
138
139 * arc-dis.c (print_insn_arc): Handle nps400.
140
1412016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
142
143 * arc-opc.c (BASE): Delete.
144
1452016-03-18 Nick Clifton <nickc@redhat.com>
146
147 PR target/19721
148 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
149 of MOV insn that aliases an ORR insn.
150
1512016-03-16 Jiong Wang <jiong.wang@arm.com>
152
153 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
154
1552016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
156
157 * mcore-opc.h: Add const qualifiers.
158 * microblaze-opc.h (struct op_code_struct): Likewise.
159 * sh-opc.h: Likewise.
160 * tic4x-dis.c (tic4x_print_indirect): Likewise.
161 (tic4x_print_op): Likewise.
162
1632016-03-02 Alan Modra <amodra@gmail.com>
164
165 * or1k-desc.h: Regenerate.
166 * fr30-ibld.c: Regenerate.
167 * rl78-decode.c: Regenerate.
168
1692016-03-01 Nick Clifton <nickc@redhat.com>
170
171 PR target/19747
172 * rl78-dis.c (print_insn_rl78_common): Fix typo.
173
1742016-02-24 Renlin Li <renlin.li@arm.com>
175
176 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
177 (print_insn_coprocessor): Support fp16 instructions.
178
1792016-02-24 Renlin Li <renlin.li@arm.com>
180
181 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
182 vminnm, vrint(mpna).
183
1842016-02-24 Renlin Li <renlin.li@arm.com>
185
186 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
187 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
188
1892016-02-15 H.J. Lu <hongjiu.lu@intel.com>
190
191 * i386-dis.c (print_insn): Parenthesize expression to prevent
192 truncated addresses.
193 (OP_J): Likewise.
194
1952016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
196 Janek van Oirschot <jvanoirs@synopsys.com>
197
198 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
199 variable.
200
2012016-02-04 Nick Clifton <nickc@redhat.com>
202
203 PR target/19561
204 * msp430-dis.c (print_insn_msp430): Add a special case for
205 decoding an RRC instruction with the ZC bit set in the extension
206 word.
207
2082016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
209
210 * cgen-ibld.in (insert_normal): Rework calculation of shift.
211 * epiphany-ibld.c: Regenerate.
212 * fr30-ibld.c: Regenerate.
213 * frv-ibld.c: Regenerate.
214 * ip2k-ibld.c: Regenerate.
215 * iq2000-ibld.c: Regenerate.
216 * lm32-ibld.c: Regenerate.
217 * m32c-ibld.c: Regenerate.
218 * m32r-ibld.c: Regenerate.
219 * mep-ibld.c: Regenerate.
220 * mt-ibld.c: Regenerate.
221 * or1k-ibld.c: Regenerate.
222 * xc16x-ibld.c: Regenerate.
223 * xstormy16-ibld.c: Regenerate.
224
2252016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
226
227 * epiphany-dis.c: Regenerated from latest cpu files.
228
2292016-02-01 Michael McConville <mmcco@mykolab.com>
230
231 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
232 test bit.
233
2342016-01-25 Renlin Li <renlin.li@arm.com>
235
236 * arm-dis.c (mapping_symbol_for_insn): New function.
237 (find_ifthen_state): Call mapping_symbol_for_insn().
238
2392016-01-20 Matthew Wahab <matthew.wahab@arm.com>
240
241 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
242 of MSR UAO immediate operand.
243
2442016-01-18 Maciej W. Rozycki <macro@imgtec.com>
245
246 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
247 instruction support.
248
2492016-01-17 Alan Modra <amodra@gmail.com>
250
251 * configure: Regenerate.
252
2532016-01-14 Nick Clifton <nickc@redhat.com>
254
255 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
256 instructions that can support stack pointer operations.
257 * rl78-decode.c: Regenerate.
258 * rl78-dis.c: Fix display of stack pointer in MOVW based
259 instructions.
260
2612016-01-14 Matthew Wahab <matthew.wahab@arm.com>
262
263 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
264 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
265 erxtatus_el1 and erxaddr_el1.
266
2672016-01-12 Matthew Wahab <matthew.wahab@arm.com>
268
269 * arm-dis.c (arm_opcodes): Add "esb".
270 (thumb_opcodes): Likewise.
271
2722016-01-11 Peter Bergner <bergner@vnet.ibm.com>
273
274 * ppc-opc.c <xscmpnedp>: Delete.
275 <xvcmpnedp>: Likewise.
276 <xvcmpnedp.>: Likewise.
277 <xvcmpnesp>: Likewise.
278 <xvcmpnesp.>: Likewise.
279
2802016-01-08 Andreas Schwab <schwab@linux-m68k.org>
281
282 PR gas/13050
283 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
284 addition to ISA_A.
285
2862016-01-01 Alan Modra <amodra@gmail.com>
287
288 Update year range in copyright notice of all files.
289
290For older changes see ChangeLog-2015
291\f
292Copyright (C) 2016 Free Software Foundation, Inc.
293
294Copying and distribution of this file, with or without modification,
295are permitted in any medium without royalty provided the copyright
296notice and this notice are preserved.
297
298Local Variables:
299mode: change-log
300left-margin: 8
301fill-column: 74
302version-control: never
303End:
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