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x86: Don't disable SSE3 when disabling SSE4a
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
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CommitLineData
12020-02-16 H.J. Lu <hongjiu.lu@intel.com>
2
3 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
4 CPU_ANY_SSE4A_FLAGS.
5
62020-02-17 Alan Modra <amodra@gmail.com>
7
8 * i386-gen.c (cpu_flag_init): Correct last change.
9
102020-02-16 H.J. Lu <hongjiu.lu@intel.com>
11
12 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
13 CPU_ANY_SSE4_FLAGS.
14
152020-02-14 H.J. Lu <hongjiu.lu@intel.com>
16
17 * i386-opc.tbl (movsx): Remove Intel syntax comments.
18 (movzx): Likewise.
19
202020-02-14 Jan Beulich <jbeulich@suse.com>
21
22 PR gas/25438
23 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
24 destination for Cpu64-only variant.
25 (movzx): Fold patterns.
26 * i386-tbl.h: Re-generate.
27
282020-02-13 Jan Beulich <jbeulich@suse.com>
29
30 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
31 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
32 CPU_ANY_SSE4_FLAGS entry.
33 * i386-init.h: Re-generate.
34
352020-02-12 Jan Beulich <jbeulich@suse.com>
36
37 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
38 with Unspecified, making the present one AT&T syntax only.
39 * i386-tbl.h: Re-generate.
40
412020-02-12 Jan Beulich <jbeulich@suse.com>
42
43 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
44 * i386-tbl.h: Re-generate.
45
462020-02-12 Jan Beulich <jbeulich@suse.com>
47
48 PR gas/24546
49 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
50 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
51 Amd64 and Intel64 templates.
52 (call, jmp): Likewise for far indirect variants. Dro
53 Unspecified.
54 * i386-tbl.h: Re-generate.
55
562020-02-11 Jan Beulich <jbeulich@suse.com>
57
58 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
59 * i386-opc.h (ShortForm): Delete.
60 (struct i386_opcode_modifier): Remove shortform field.
61 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
62 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
63 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
64 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
65 Drop ShortForm.
66 * i386-tbl.h: Re-generate.
67
682020-02-11 Jan Beulich <jbeulich@suse.com>
69
70 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
71 fucompi): Drop ShortForm from operand-less templates.
72 * i386-tbl.h: Re-generate.
73
742020-02-11 Alan Modra <amodra@gmail.com>
75
76 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
77 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
78 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
79 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
80 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
81
822020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
83
84 * arm-dis.c (print_insn_cde): Define 'V' parse character.
85 (cde_opcodes): Add VCX* instructions.
86
872020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
88 Matthew Malcomson <matthew.malcomson@arm.com>
89
90 * arm-dis.c (struct cdeopcode32): New.
91 (CDE_OPCODE): New macro.
92 (cde_opcodes): New disassembly table.
93 (regnames): New option to table.
94 (cde_coprocs): New global variable.
95 (print_insn_cde): New
96 (print_insn_thumb32): Use print_insn_cde.
97 (parse_arm_disassembler_options): Parse coprocN args.
98
992020-02-10 H.J. Lu <hongjiu.lu@intel.com>
100
101 PR gas/25516
102 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
103 with ISA64.
104 * i386-opc.h (AMD64): Removed.
105 (Intel64): Likewose.
106 (AMD64): New.
107 (INTEL64): Likewise.
108 (INTEL64ONLY): Likewise.
109 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
110 * i386-opc.tbl (Amd64): New.
111 (Intel64): Likewise.
112 (Intel64Only): Likewise.
113 Replace AMD64 with Amd64. Update sysenter/sysenter with
114 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
115 * i386-tbl.h: Regenerated.
116
1172020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
118
119 PR 25469
120 * z80-dis.c: Add support for GBZ80 opcodes.
121
1222020-02-04 Alan Modra <amodra@gmail.com>
123
124 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
125
1262020-02-03 Alan Modra <amodra@gmail.com>
127
128 * m32c-ibld.c: Regenerate.
129
1302020-02-01 Alan Modra <amodra@gmail.com>
131
132 * frv-ibld.c: Regenerate.
133
1342020-01-31 Jan Beulich <jbeulich@suse.com>
135
136 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
137 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
138 (OP_E_memory): Replace xmm_mdq_mode case label by
139 vex_scalar_w_dq_mode one.
140 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
141
1422020-01-31 Jan Beulich <jbeulich@suse.com>
143
144 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
145 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
146 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
147 (intel_operand_size): Drop vex_w_dq_mode case label.
148
1492020-01-31 Richard Sandiford <richard.sandiford@arm.com>
150
151 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
152 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
153
1542020-01-30 Alan Modra <amodra@gmail.com>
155
156 * m32c-ibld.c: Regenerate.
157
1582020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
159
160 * bpf-opc.c: Regenerate.
161
1622020-01-30 Jan Beulich <jbeulich@suse.com>
163
164 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
165 (dis386): Use them to replace C2/C3 table entries.
166 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
167 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
168 ones. Use Size64 instead of DefaultSize on Intel64 ones.
169 * i386-tbl.h: Re-generate.
170
1712020-01-30 Jan Beulich <jbeulich@suse.com>
172
173 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
174 forms.
175 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
176 DefaultSize.
177 * i386-tbl.h: Re-generate.
178
1792020-01-30 Alan Modra <amodra@gmail.com>
180
181 * tic4x-dis.c (tic4x_dp): Make unsigned.
182
1832020-01-27 H.J. Lu <hongjiu.lu@intel.com>
184 Jan Beulich <jbeulich@suse.com>
185
186 PR binutils/25445
187 * i386-dis.c (MOVSXD_Fixup): New function.
188 (movsxd_mode): New enum.
189 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
190 (intel_operand_size): Handle movsxd_mode.
191 (OP_E_register): Likewise.
192 (OP_G): Likewise.
193 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
194 register on movsxd. Add movsxd with 16-bit destination register
195 for AMD64 and Intel64 ISAs.
196 * i386-tbl.h: Regenerated.
197
1982020-01-27 Tamar Christina <tamar.christina@arm.com>
199
200 PR 25403
201 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
202 * aarch64-asm-2.c: Regenerate
203 * aarch64-dis-2.c: Likewise.
204 * aarch64-opc-2.c: Likewise.
205
2062020-01-21 Jan Beulich <jbeulich@suse.com>
207
208 * i386-opc.tbl (sysret): Drop DefaultSize.
209 * i386-tbl.h: Re-generate.
210
2112020-01-21 Jan Beulich <jbeulich@suse.com>
212
213 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
214 Dword.
215 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
216 * i386-tbl.h: Re-generate.
217
2182020-01-20 Nick Clifton <nickc@redhat.com>
219
220 * po/de.po: Updated German translation.
221 * po/pt_BR.po: Updated Brazilian Portuguese translation.
222 * po/uk.po: Updated Ukranian translation.
223
2242020-01-20 Alan Modra <amodra@gmail.com>
225
226 * hppa-dis.c (fput_const): Remove useless cast.
227
2282020-01-20 Alan Modra <amodra@gmail.com>
229
230 * arm-dis.c (print_insn_arm): Wrap 'T' value.
231
2322020-01-18 Nick Clifton <nickc@redhat.com>
233
234 * configure: Regenerate.
235 * po/opcodes.pot: Regenerate.
236
2372020-01-18 Nick Clifton <nickc@redhat.com>
238
239 Binutils 2.34 branch created.
240
2412020-01-17 Christian Biesinger <cbiesinger@google.com>
242
243 * opintl.h: Fix spelling error (seperate).
244
2452020-01-17 H.J. Lu <hongjiu.lu@intel.com>
246
247 * i386-opc.tbl: Add {vex} pseudo prefix.
248 * i386-tbl.h: Regenerated.
249
2502020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
251
252 PR 25376
253 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
254 (neon_opcodes): Likewise.
255 (select_arm_features): Make sure we enable MVE bits when selecting
256 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
257 any architecture.
258
2592020-01-16 Jan Beulich <jbeulich@suse.com>
260
261 * i386-opc.tbl: Drop stale comment from XOP section.
262
2632020-01-16 Jan Beulich <jbeulich@suse.com>
264
265 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
266 (extractps): Add VexWIG to SSE2AVX forms.
267 * i386-tbl.h: Re-generate.
268
2692020-01-16 Jan Beulich <jbeulich@suse.com>
270
271 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
272 Size64 from and use VexW1 on SSE2AVX forms.
273 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
274 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
275 * i386-tbl.h: Re-generate.
276
2772020-01-15 Alan Modra <amodra@gmail.com>
278
279 * tic4x-dis.c (tic4x_version): Make unsigned long.
280 (optab, optab_special, registernames): New file scope vars.
281 (tic4x_print_register): Set up registernames rather than
282 malloc'd registertable.
283 (tic4x_disassemble): Delete optable and optable_special. Use
284 optab and optab_special instead. Throw away old optab,
285 optab_special and registernames when info->mach changes.
286
2872020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
288
289 PR 25377
290 * z80-dis.c (suffix): Use .db instruction to generate double
291 prefix.
292
2932020-01-14 Alan Modra <amodra@gmail.com>
294
295 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
296 values to unsigned before shifting.
297
2982020-01-13 Thomas Troeger <tstroege@gmx.de>
299
300 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
301 flow instructions.
302 (print_insn_thumb16, print_insn_thumb32): Likewise.
303 (print_insn): Initialize the insn info.
304 * i386-dis.c (print_insn): Initialize the insn info fields, and
305 detect jumps.
306
3072012-01-13 Claudiu Zissulescu <claziss@gmail.com>
308
309 * arc-opc.c (C_NE): Make it required.
310
3112012-01-13 Claudiu Zissulescu <claziss@gmail.com>
312
313 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
314 reserved register name.
315
3162020-01-13 Alan Modra <amodra@gmail.com>
317
318 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
319 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
320
3212020-01-13 Alan Modra <amodra@gmail.com>
322
323 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
324 result of wasm_read_leb128 in a uint64_t and check that bits
325 are not lost when copying to other locals. Use uint32_t for
326 most locals. Use PRId64 when printing int64_t.
327
3282020-01-13 Alan Modra <amodra@gmail.com>
329
330 * score-dis.c: Formatting.
331 * score7-dis.c: Formatting.
332
3332020-01-13 Alan Modra <amodra@gmail.com>
334
335 * score-dis.c (print_insn_score48): Use unsigned variables for
336 unsigned values. Don't left shift negative values.
337 (print_insn_score32): Likewise.
338 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
339
3402020-01-13 Alan Modra <amodra@gmail.com>
341
342 * tic4x-dis.c (tic4x_print_register): Remove dead code.
343
3442020-01-13 Alan Modra <amodra@gmail.com>
345
346 * fr30-ibld.c: Regenerate.
347
3482020-01-13 Alan Modra <amodra@gmail.com>
349
350 * xgate-dis.c (print_insn): Don't left shift signed value.
351 (ripBits): Formatting, use 1u.
352
3532020-01-10 Alan Modra <amodra@gmail.com>
354
355 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
356 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
357
3582020-01-10 Alan Modra <amodra@gmail.com>
359
360 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
361 and XRREG value earlier to avoid a shift with negative exponent.
362 * m10200-dis.c (disassemble): Similarly.
363
3642020-01-09 Nick Clifton <nickc@redhat.com>
365
366 PR 25224
367 * z80-dis.c (ld_ii_ii): Use correct cast.
368
3692020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
370
371 PR 25224
372 * z80-dis.c (ld_ii_ii): Use character constant when checking
373 opcode byte value.
374
3752020-01-09 Jan Beulich <jbeulich@suse.com>
376
377 * i386-dis.c (SEP_Fixup): New.
378 (SEP): Define.
379 (dis386_twobyte): Use it for sysenter/sysexit.
380 (enum x86_64_isa): Change amd64 enumerator to value 1.
381 (OP_J): Compare isa64 against intel64 instead of amd64.
382 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
383 forms.
384 * i386-tbl.h: Re-generate.
385
3862020-01-08 Alan Modra <amodra@gmail.com>
387
388 * z8k-dis.c: Include libiberty.h
389 (instr_data_s): Make max_fetched unsigned.
390 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
391 Don't exceed byte_info bounds.
392 (output_instr): Make num_bytes unsigned.
393 (unpack_instr): Likewise for nibl_count and loop.
394 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
395 idx unsigned.
396 * z8k-opc.h: Regenerate.
397
3982020-01-07 Shahab Vahedi <shahab@synopsys.com>
399
400 * arc-tbl.h (llock): Use 'LLOCK' as class.
401 (llockd): Likewise.
402 (scond): Use 'SCOND' as class.
403 (scondd): Likewise.
404 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
405 (scondd): Likewise.
406
4072020-01-06 Alan Modra <amodra@gmail.com>
408
409 * m32c-ibld.c: Regenerate.
410
4112020-01-06 Alan Modra <amodra@gmail.com>
412
413 PR 25344
414 * z80-dis.c (suffix): Don't use a local struct buffer copy.
415 Peek at next byte to prevent recursion on repeated prefix bytes.
416 Ensure uninitialised "mybuf" is not accessed.
417 (print_insn_z80): Don't zero n_fetch and n_used here,..
418 (print_insn_z80_buf): ..do it here instead.
419
4202020-01-04 Alan Modra <amodra@gmail.com>
421
422 * m32r-ibld.c: Regenerate.
423
4242020-01-04 Alan Modra <amodra@gmail.com>
425
426 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
427
4282020-01-04 Alan Modra <amodra@gmail.com>
429
430 * crx-dis.c (match_opcode): Avoid shift left of signed value.
431
4322020-01-04 Alan Modra <amodra@gmail.com>
433
434 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
435
4362020-01-03 Jan Beulich <jbeulich@suse.com>
437
438 * aarch64-tbl.h (aarch64_opcode_table): Use
439 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
440
4412020-01-03 Jan Beulich <jbeulich@suse.com>
442
443 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
444 forms of SUDOT and USDOT.
445
4462020-01-03 Jan Beulich <jbeulich@suse.com>
447
448 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
449 uzip{1,2}.
450 * opcodes/aarch64-dis-2.c: Re-generate.
451
4522020-01-03 Jan Beulich <jbeulich@suse.com>
453
454 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
455 FMMLA encoding.
456 * opcodes/aarch64-dis-2.c: Re-generate.
457
4582020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
459
460 * z80-dis.c: Add support for eZ80 and Z80 instructions.
461
4622020-01-01 Alan Modra <amodra@gmail.com>
463
464 Update year range in copyright notice of all files.
465
466For older changes see ChangeLog-2019
467\f
468Copyright (C) 2020 Free Software Foundation, Inc.
469
470Copying and distribution of this file, with or without modification,
471are permitted in any medium without royalty provided the copyright
472notice and this notice are preserved.
473
474Local Variables:
475mode: change-log
476left-margin: 8
477fill-column: 74
478version-control: never
479End:
GDB Binutils - Deliverables
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