| 1 | /* cris-opc.c -- Table of opcodes for the CRIS processor. |
| 2 | Copyright 2000 Free Software Foundation, Inc. |
| 3 | Contributed by Axis Communications AB, Lund, Sweden. |
| 4 | Originally written for GAS 1.38.1 by Mikael Asker. |
| 5 | Reorganized by Hans-Peter Nilsson. |
| 6 | |
| 7 | This file is part of GAS, GDB and the GNU binutils. |
| 8 | |
| 9 | GAS, GDB, and GNU binutils is free software; you can redistribute it |
| 10 | and/or modify it under the terms of the GNU General Public License as |
| 11 | published by the Free Software Foundation; either version 2, or (at your |
| 12 | option) any later version. |
| 13 | |
| 14 | GAS, GDB, and GNU binutils are distributed in the hope that they will be |
| 15 | useful, but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | GNU General Public License for more details. |
| 18 | |
| 19 | You should have received a copy of the GNU General Public License |
| 20 | along with this program; if not, write to the Free Software |
| 21 | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ |
| 22 | |
| 23 | #include "opcode/cris.h" |
| 24 | |
| 25 | #ifndef NULL |
| 26 | #define NULL (0) |
| 27 | #endif |
| 28 | |
| 29 | const struct cris_spec_reg |
| 30 | cris_spec_regs[] = |
| 31 | { |
| 32 | {"p0", 0, 1, 0, NULL}, |
| 33 | {"vr", 1, 1, 0, NULL}, |
| 34 | {"p1", 1, 1, 0, NULL}, |
| 35 | {"p2", 2, 1, cris_ver_warning, NULL}, |
| 36 | {"p3", 3, 1, cris_ver_warning, NULL}, |
| 37 | {"p4", 4, 2, 0, NULL}, |
| 38 | {"ccr", 5, 2, 0, NULL}, |
| 39 | {"p5", 5, 2, 0, NULL}, |
| 40 | {"dcr0",6, 2, cris_ver_v0_3, NULL}, |
| 41 | {"p6", 6, 2, cris_ver_v0_3, NULL}, |
| 42 | {"dcr1/mof", 7, 4, cris_ver_v10p, |
| 43 | "Register `dcr1/mof' with ambiguous size specified. Guessing 4 bytes"}, |
| 44 | {"dcr1/mof", 7, 2, cris_ver_v0_3, |
| 45 | "Register `dcr1/mof' with ambiguous size specified. Guessing 2 bytes"}, |
| 46 | {"mof", 7, 4, cris_ver_v10p, NULL}, |
| 47 | {"dcr1",7, 2, cris_ver_v0_3, NULL}, |
| 48 | {"p7", 7, 4, cris_ver_v10p, NULL}, |
| 49 | {"p7", 7, 2, cris_ver_v0_3, NULL}, |
| 50 | {"p8", 8, 4, 0, NULL}, |
| 51 | {"ibr", 9, 4, 0, NULL}, |
| 52 | {"p9", 9, 4, 0, NULL}, |
| 53 | {"irp", 10, 4, 0, NULL}, |
| 54 | {"p10", 10, 4, 0, NULL}, |
| 55 | {"srp", 11, 4, 0, NULL}, |
| 56 | {"p11", 11, 4, 0, NULL}, |
| 57 | /* For disassembly use only. Accept at assembly with a warning. */ |
| 58 | {"bar/dtp0", 12, 4, cris_ver_warning, |
| 59 | "Ambiguous register `bar/dtp0' specified"}, |
| 60 | {"bar", 12, 4, cris_ver_v8p, NULL}, |
| 61 | {"dtp0",12, 4, cris_ver_v0_3, NULL}, |
| 62 | {"p12", 12, 4, 0, NULL}, |
| 63 | /* For disassembly use only. Accept at assembly with a warning. */ |
| 64 | {"dccr/dtp1",13, 4, cris_ver_warning, |
| 65 | "Ambiguous register `dccr/dtp1' specified"}, |
| 66 | {"dccr",13, 4, cris_ver_v8p, NULL}, |
| 67 | {"dtp1",13, 4, cris_ver_v0_3, NULL}, |
| 68 | {"p13", 13, 4, 0, NULL}, |
| 69 | {"brp", 14, 4, cris_ver_v3p, NULL}, |
| 70 | {"p14", 14, 4, cris_ver_v3p, NULL}, |
| 71 | {"usp", 15, 4, cris_ver_v10p, NULL}, |
| 72 | {"p15", 15, 4, cris_ver_v10p, NULL}, |
| 73 | {NULL, 0, 0, cris_ver_version_all, NULL} |
| 74 | }; |
| 75 | |
| 76 | /* All CRIS opcodes are 16 bits. |
| 77 | |
| 78 | - The match component is a mask saying which bits must match a |
| 79 | particular opcode in order for an instruction to be an instance |
| 80 | of that opcode. |
| 81 | |
| 82 | - The args component is a string containing characters symbolically |
| 83 | matching the operands of an instruction. Used for both assembly |
| 84 | and disassembly. |
| 85 | |
| 86 | Operand-matching characters: |
| 87 | B Not really an operand. It causes a "BDAP -size,SP" prefix to be |
| 88 | output for the PUSH alias-instructions and recognizes a |
| 89 | push-prefix at disassembly. Must be followed by a R or P letter. |
| 90 | ! Non-match pattern, will not match if there's a prefix insn. |
| 91 | b Non-matching operand, used for branches with 16-bit |
| 92 | displacement. Only recognized by the disassembler. |
| 93 | c 5-bit unsigned immediate in bits <4:0>. |
| 94 | C 4-bit unsigned immediate in bits <3:0>. |
| 95 | D General register in bits <15:12> and <3:0>. |
| 96 | f List of flags in bits <15:12> and <3:0>. |
| 97 | i 6-bit signed immediate in bits <5:0>. |
| 98 | I 6-bit unsigned immediate in bits <5:0>. |
| 99 | M Size modifier (B, W or D) for CLEAR instructions. |
| 100 | m Size modifier (B, W or D) in bits <5:4> |
| 101 | o [-128..127] word offset in bits <7:1> and <0>. Used by 8-bit |
| 102 | branch instructions. |
| 103 | O [-128..127] offset in bits <7:0>. Also matches a comma and a |
| 104 | general register after the expression. Used only for the BDAP |
| 105 | prefix insn. |
| 106 | P Special register in bits <15:12>. |
| 107 | p Indicates that the insn is a prefix insn. Must be first |
| 108 | character. |
| 109 | R General register in bits <15:12>. |
| 110 | r General register in bits <3:0>. |
| 111 | S Source operand in bit <10> and a prefix; a 3-operand prefix |
| 112 | without side-effect. |
| 113 | s Source operand in bits <10> and <3:0>, optionally with a |
| 114 | side-effect prefix. |
| 115 | x Register-dot-modifier, for example "r5.w" in bits <15:12> and <5:4>. |
| 116 | y Like 's' but do not allow an integer at assembly. |
| 117 | z Size modifier (B or W) in bit <4>. */ |
| 118 | |
| 119 | |
| 120 | /* Please note the order of the opcodes in this table is significant. |
| 121 | The assembler requires that all instances of the same mnemonic must |
| 122 | be consecutive. If they aren't, the assembler might not recognize |
| 123 | them, or may indicate and internal error. |
| 124 | |
| 125 | The disassembler should not normally care about the order of the |
| 126 | opcodes, but will prefer an earlier alternative if the "match-score" |
| 127 | (see cris-dis.c) is computed as equal. |
| 128 | |
| 129 | It should not be significant for proper execution that this table is |
| 130 | in alphabetical order, but please follow that convention for an easy |
| 131 | overview. */ |
| 132 | |
| 133 | const struct cris_opcode |
| 134 | cris_opcodes[] = |
| 135 | { |
| 136 | {"abs", 0x06B0, 0x0940, "r,R", 0, SIZE_NONE, 0, |
| 137 | cris_abs_op}, |
| 138 | |
| 139 | {"add", 0x0600, 0x09c0, "m r,R", 0, SIZE_NONE, 0, |
| 140 | cris_reg_mode_add_sub_cmp_and_or_move_op}, |
| 141 | |
| 142 | {"add", 0x0A00, 0x01c0, "m s,R", 0, SIZE_FIELD, 0, |
| 143 | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
| 144 | |
| 145 | {"add", 0x0A00, 0x01c0, "m S,D", 0, SIZE_NONE, 0, |
| 146 | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
| 147 | |
| 148 | {"add", 0x0a00, 0x05c0, "m S,R,r", 0, SIZE_NONE, 0, |
| 149 | cris_three_operand_add_sub_cmp_and_or_op}, |
| 150 | |
| 151 | {"addi", 0x0500, 0x0Ac0, "x,r", 0, SIZE_NONE, 0, |
| 152 | cris_addi_op}, |
| 153 | |
| 154 | {"addq", 0x0200, 0x0Dc0, "I,R", 0, SIZE_NONE, 0, |
| 155 | cris_quick_mode_add_sub_op}, |
| 156 | |
| 157 | {"adds", 0x0420, 0x0Bc0, "z r,R", 0, SIZE_NONE, 0, |
| 158 | cris_reg_mode_add_sub_cmp_and_or_move_op}, |
| 159 | |
| 160 | {"adds", 0x0820, 0x03c0, "z s,R", 0, SIZE_FIELD, 0, |
| 161 | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
| 162 | |
| 163 | {"adds", 0x0820, 0x03c0, "z S,D", 0, SIZE_NONE, 0, |
| 164 | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
| 165 | |
| 166 | {"adds", 0x0820, 0x07c0, "z S,R,r", 0, SIZE_NONE, 0, |
| 167 | cris_three_operand_add_sub_cmp_and_or_op}, |
| 168 | |
| 169 | {"addu", 0x0400, 0x0be0, "z r,R", 0, SIZE_NONE, 0, |
| 170 | cris_reg_mode_add_sub_cmp_and_or_move_op}, |
| 171 | |
| 172 | {"addu", 0x0800, 0x03e0, "z s,R", 0, SIZE_FIELD, 0, |
| 173 | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
| 174 | |
| 175 | {"addu", 0x0800, 0x03e0, "z S,D", 0, SIZE_NONE, 0, |
| 176 | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
| 177 | |
| 178 | {"addu", 0x0800, 0x07e0, "z S,R,r", 0, SIZE_NONE, 0, |
| 179 | cris_three_operand_add_sub_cmp_and_or_op}, |
| 180 | |
| 181 | {"and", 0x0700, 0x08C0, "m r,R", 0, SIZE_NONE, 0, |
| 182 | cris_reg_mode_add_sub_cmp_and_or_move_op}, |
| 183 | |
| 184 | {"and", 0x0B00, 0x00C0, "m s,R", 0, SIZE_FIELD, 0, |
| 185 | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
| 186 | |
| 187 | {"and", 0x0B00, 0x00C0, "m S,D", 0, SIZE_NONE, 0, |
| 188 | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
| 189 | |
| 190 | {"and", 0x0B00, 0x04C0, "m S,R,r", 0, SIZE_NONE, 0, |
| 191 | cris_three_operand_add_sub_cmp_and_or_op}, |
| 192 | |
| 193 | {"andq", 0x0300, 0x0CC0, "i,R", 0, SIZE_NONE, 0, |
| 194 | cris_quick_mode_and_cmp_move_or_op}, |
| 195 | |
| 196 | {"asr", 0x0780, 0x0840, "m r,R", 0, SIZE_NONE, 0, |
| 197 | cris_asr_op}, |
| 198 | |
| 199 | {"asrq", 0x03a0, 0x0c40, "c,R", 0, SIZE_NONE, 0, |
| 200 | cris_asrq_op}, |
| 201 | |
| 202 | {"ax", 0x15B0, 0xEA4F, "", 0, SIZE_NONE, 0, |
| 203 | cris_ax_ei_setf_op}, |
| 204 | |
| 205 | /* FIXME: Should use branch #defines. */ |
| 206 | {"b", 0x0dff, 0x0200, "b", 1, SIZE_NONE, 0, |
| 207 | cris_sixteen_bit_offset_branch_op}, |
| 208 | |
| 209 | {"ba", |
| 210 | BA_QUICK_OPCODE, |
| 211 | 0x0F00+(0xF-CC_A)*0x1000, "o", 1, SIZE_NONE, 0, |
| 212 | cris_eight_bit_offset_branch_op}, |
| 213 | |
| 214 | {"bcc", |
| 215 | BRANCH_QUICK_OPCODE+CC_CC*0x1000, |
| 216 | 0x0f00+(0xF-CC_CC)*0x1000, "o", 1, SIZE_NONE, 0, |
| 217 | cris_eight_bit_offset_branch_op}, |
| 218 | |
| 219 | {"bcs", |
| 220 | BRANCH_QUICK_OPCODE+CC_CS*0x1000, |
| 221 | 0x0f00+(0xF-CC_CS)*0x1000, "o", 1, SIZE_NONE, 0, |
| 222 | cris_eight_bit_offset_branch_op}, |
| 223 | |
| 224 | {"bdap", |
| 225 | BDAP_INDIR_OPCODE, BDAP_INDIR_Z_BITS, "pm s,R", 0, SIZE_FIELD, 0, |
| 226 | cris_bdap_prefix}, |
| 227 | |
| 228 | {"bdap", |
| 229 | BDAP_QUICK_OPCODE, BDAP_QUICK_Z_BITS, "pO", 0, SIZE_NONE, 0, |
| 230 | cris_quick_mode_bdap_prefix}, |
| 231 | |
| 232 | {"beq", |
| 233 | BRANCH_QUICK_OPCODE+CC_EQ*0x1000, |
| 234 | 0x0f00+(0xF-CC_EQ)*0x1000, "o", 1, SIZE_NONE, 0, |
| 235 | cris_eight_bit_offset_branch_op}, |
| 236 | |
| 237 | /* This is deliberately put before "bext" to trump it, even though not |
| 238 | in alphabetical order. */ |
| 239 | {"bwf", |
| 240 | BRANCH_QUICK_OPCODE+CC_EXT*0x1000, |
| 241 | 0x0f00+(0xF-CC_EXT)*0x1000, "o", 1, SIZE_NONE, |
| 242 | cris_ver_v10p, |
| 243 | cris_eight_bit_offset_branch_op}, |
| 244 | |
| 245 | {"bext", |
| 246 | BRANCH_QUICK_OPCODE+CC_EXT*0x1000, |
| 247 | 0x0f00+(0xF-CC_EXT)*0x1000, "o", 1, SIZE_NONE, |
| 248 | cris_ver_v0_3, |
| 249 | cris_eight_bit_offset_branch_op}, |
| 250 | |
| 251 | {"bge", |
| 252 | BRANCH_QUICK_OPCODE+CC_GE*0x1000, |
| 253 | 0x0f00+(0xF-CC_GE)*0x1000, "o", 1, SIZE_NONE, 0, |
| 254 | cris_eight_bit_offset_branch_op}, |
| 255 | |
| 256 | {"bgt", |
| 257 | BRANCH_QUICK_OPCODE+CC_GT*0x1000, |
| 258 | 0x0f00+(0xF-CC_GT)*0x1000, "o", 1, SIZE_NONE, 0, |
| 259 | cris_eight_bit_offset_branch_op}, |
| 260 | |
| 261 | {"bhi", |
| 262 | BRANCH_QUICK_OPCODE+CC_HI*0x1000, |
| 263 | 0x0f00+(0xF-CC_HI)*0x1000, "o", 1, SIZE_NONE, 0, |
| 264 | cris_eight_bit_offset_branch_op}, |
| 265 | |
| 266 | {"bhs", |
| 267 | BRANCH_QUICK_OPCODE+CC_HS*0x1000, |
| 268 | 0x0f00+(0xF-CC_HS)*0x1000, "o", 1, SIZE_NONE, 0, |
| 269 | cris_eight_bit_offset_branch_op}, |
| 270 | |
| 271 | {"biap", BIAP_OPCODE, BIAP_Z_BITS, "pm r,R", 0, SIZE_NONE, 0, |
| 272 | cris_biap_prefix}, |
| 273 | |
| 274 | {"ble", |
| 275 | BRANCH_QUICK_OPCODE+CC_LE*0x1000, |
| 276 | 0x0f00+(0xF-CC_LE)*0x1000, "o", 1, SIZE_NONE, 0, |
| 277 | cris_eight_bit_offset_branch_op}, |
| 278 | |
| 279 | {"blo", |
| 280 | BRANCH_QUICK_OPCODE+CC_LO*0x1000, |
| 281 | 0x0f00+(0xF-CC_LO)*0x1000, "o", 1, SIZE_NONE, 0, |
| 282 | cris_eight_bit_offset_branch_op}, |
| 283 | |
| 284 | {"bls", |
| 285 | BRANCH_QUICK_OPCODE+CC_LS*0x1000, |
| 286 | 0x0f00+(0xF-CC_LS)*0x1000, "o", 1, SIZE_NONE, 0, |
| 287 | cris_eight_bit_offset_branch_op}, |
| 288 | |
| 289 | {"blt", |
| 290 | BRANCH_QUICK_OPCODE+CC_LT*0x1000, |
| 291 | 0x0f00+(0xF-CC_LT)*0x1000, "o", 1, SIZE_NONE, 0, |
| 292 | cris_eight_bit_offset_branch_op}, |
| 293 | |
| 294 | {"bmi", |
| 295 | BRANCH_QUICK_OPCODE+CC_MI*0x1000, |
| 296 | 0x0f00+(0xF-CC_MI)*0x1000, "o", 1, SIZE_NONE, 0, |
| 297 | cris_eight_bit_offset_branch_op}, |
| 298 | |
| 299 | {"bmod", 0x0ab0, 0x0140, "s,R", 0, SIZE_FIX_32, |
| 300 | cris_ver_sim, |
| 301 | cris_not_implemented_op}, |
| 302 | |
| 303 | {"bmod", 0x0ab0, 0x0140, "S,D", 0, SIZE_NONE, |
| 304 | cris_ver_sim, |
| 305 | cris_not_implemented_op}, |
| 306 | |
| 307 | {"bmod", 0x0ab0, 0x0540, "S,R,r", 0, SIZE_NONE, |
| 308 | cris_ver_sim, |
| 309 | cris_not_implemented_op}, |
| 310 | |
| 311 | {"bne", |
| 312 | BRANCH_QUICK_OPCODE+CC_NE*0x1000, |
| 313 | 0x0f00+(0xF-CC_NE)*0x1000, "o", 1, SIZE_NONE, 0, |
| 314 | cris_eight_bit_offset_branch_op}, |
| 315 | |
| 316 | {"bound", 0x05c0, 0x0A00, "m r,R", 0, SIZE_NONE, 0, |
| 317 | cris_two_operand_bound_op}, |
| 318 | {"bound", 0x09c0, 0x0200, "m s,R", 0, SIZE_FIELD, 0, |
| 319 | cris_two_operand_bound_op}, |
| 320 | {"bound", 0x09c0, 0x0200, "m S,D", 0, SIZE_NONE, 0, |
| 321 | cris_two_operand_bound_op}, |
| 322 | {"bound", 0x09c0, 0x0600, "m S,R,r", 0, SIZE_NONE, 0, |
| 323 | cris_three_operand_bound_op}, |
| 324 | {"bpl", |
| 325 | BRANCH_QUICK_OPCODE+CC_PL*0x1000, |
| 326 | 0x0f00+(0xF-CC_PL)*0x1000, "o", 1, SIZE_NONE, 0, |
| 327 | cris_eight_bit_offset_branch_op}, |
| 328 | |
| 329 | {"break", 0xe930, 0x16c0, "C", 0, SIZE_NONE, |
| 330 | cris_ver_v3p, |
| 331 | cris_break_op}, |
| 332 | |
| 333 | {"bstore", 0x0af0, 0x0100, "s,R", 0, SIZE_FIX_32, |
| 334 | cris_ver_warning, |
| 335 | cris_not_implemented_op}, |
| 336 | |
| 337 | {"bstore", 0x0af0, 0x0100, "S,D", 0, SIZE_NONE, |
| 338 | cris_ver_warning, |
| 339 | cris_not_implemented_op}, |
| 340 | |
| 341 | {"bstore", 0x0af0, 0x0500, "S,R,r", 0, SIZE_NONE, |
| 342 | cris_ver_warning, |
| 343 | cris_not_implemented_op}, |
| 344 | |
| 345 | {"btst", 0x04F0, 0x0B00, "r,R", 0, SIZE_NONE, 0, |
| 346 | cris_btst_nop_op}, |
| 347 | {"btstq", 0x0380, 0x0C60, "c,R", 0, SIZE_NONE, 0, |
| 348 | cris_btst_nop_op}, |
| 349 | {"bvc", |
| 350 | BRANCH_QUICK_OPCODE+CC_VC*0x1000, |
| 351 | 0x0f00+(0xF-CC_VC)*0x1000, "o", 1, SIZE_NONE, 0, |
| 352 | cris_eight_bit_offset_branch_op}, |
| 353 | |
| 354 | {"bvs", |
| 355 | BRANCH_QUICK_OPCODE+CC_VS*0x1000, |
| 356 | 0x0f00+(0xF-CC_VS)*0x1000, "o", 1, SIZE_NONE, 0, |
| 357 | cris_eight_bit_offset_branch_op}, |
| 358 | |
| 359 | {"clear", 0x0670, 0x3980, "M r", 0, SIZE_NONE, 0, |
| 360 | cris_reg_mode_clear_op}, |
| 361 | |
| 362 | {"clear", 0x0A70, 0x3180, "M y", 0, SIZE_NONE, 0, |
| 363 | cris_none_reg_mode_clear_test_op}, |
| 364 | |
| 365 | {"clear", 0x0A70, 0x3180, "M S", 0, SIZE_NONE, 0, |
| 366 | cris_none_reg_mode_clear_test_op}, |
| 367 | |
| 368 | {"clearf", 0x05F0, 0x0A00, "f", 0, SIZE_NONE, 0, |
| 369 | cris_clearf_di_op}, |
| 370 | |
| 371 | {"cmp", 0x06C0, 0x0900, "m r,R", 0, SIZE_NONE, 0, |
| 372 | cris_reg_mode_add_sub_cmp_and_or_move_op}, |
| 373 | |
| 374 | {"cmp", 0x0Ac0, 0x0100, "m s,R", 0, SIZE_FIELD, 0, |
| 375 | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
| 376 | |
| 377 | {"cmp", 0x0Ac0, 0x0100, "m S,D", 0, SIZE_NONE, 0, |
| 378 | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
| 379 | |
| 380 | {"cmpq", 0x02C0, 0x0D00, "i,R", 0, SIZE_NONE, 0, |
| 381 | cris_quick_mode_and_cmp_move_or_op}, |
| 382 | |
| 383 | {"cmps", 0x08e0, 0x0300, "z s,R", 0, SIZE_FIELD, 0, |
| 384 | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
| 385 | |
| 386 | {"cmps", 0x08e0, 0x0300, "z S,D", 0, SIZE_NONE, 0, |
| 387 | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
| 388 | |
| 389 | {"cmpu", 0x08c0, 0x0320, "z s,R" , 0, SIZE_FIELD, 0, |
| 390 | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
| 391 | |
| 392 | {"cmpu", 0x08c0, 0x0320, "z S,D", 0, SIZE_NONE, 0, |
| 393 | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
| 394 | |
| 395 | {"di", 0x25F0, 0xDA0F, "", 0, SIZE_NONE, 0, |
| 396 | cris_clearf_di_op}, |
| 397 | |
| 398 | {"dip", DIP_OPCODE, DIP_Z_BITS, "ps", 0, SIZE_FIX_32, 0, |
| 399 | cris_dip_prefix}, |
| 400 | |
| 401 | {"div", 0x0980, 0x0640, "m R,r", 0, SIZE_FIELD, 0, |
| 402 | cris_not_implemented_op}, |
| 403 | |
| 404 | {"dstep", 0x06f0, 0x0900, "r,R", 0, SIZE_NONE, 0, |
| 405 | cris_dstep_logshift_mstep_neg_not_op}, |
| 406 | |
| 407 | {"ei", 0x25B0, 0xDA4F, "", 0, SIZE_NONE, 0, |
| 408 | cris_ax_ei_setf_op}, |
| 409 | |
| 410 | {"jbrc", 0x69b0, 0x9640, "r", 0, SIZE_NONE, |
| 411 | cris_ver_v8p, |
| 412 | cris_reg_mode_jump_op}, |
| 413 | |
| 414 | {"jbrc", 0x6930, 0x92c0, "s", 0, SIZE_FIX_32, |
| 415 | cris_ver_v8p, |
| 416 | cris_none_reg_mode_jump_op}, |
| 417 | |
| 418 | {"jbrc", 0x6930, 0x92c0, "S", 0, SIZE_NONE, |
| 419 | cris_ver_v8p, |
| 420 | cris_none_reg_mode_jump_op}, |
| 421 | |
| 422 | {"jir", 0xA9b0, 0x5640, "r", 0, SIZE_NONE, 0, |
| 423 | cris_reg_mode_jump_op}, |
| 424 | |
| 425 | {"jir", 0xA930, 0x52c0, "s", 0, SIZE_FIX_32, 0, |
| 426 | cris_none_reg_mode_jump_op}, |
| 427 | |
| 428 | {"jir", 0xA930, 0x52c0, "S", 0, SIZE_NONE, 0, |
| 429 | cris_none_reg_mode_jump_op}, |
| 430 | |
| 431 | {"jirc", 0x29b0, 0xd640, "r", 0, SIZE_NONE, |
| 432 | cris_ver_v8p, |
| 433 | cris_reg_mode_jump_op}, |
| 434 | |
| 435 | {"jirc", 0x2930, 0xd2c0, "s", 0, SIZE_FIX_32, |
| 436 | cris_ver_v8p, |
| 437 | cris_none_reg_mode_jump_op}, |
| 438 | |
| 439 | {"jirc", 0x2930, 0xd2c0, "S", 0, SIZE_NONE, |
| 440 | cris_ver_v8p, |
| 441 | cris_none_reg_mode_jump_op}, |
| 442 | |
| 443 | {"jsr", 0xB9b0, 0x4640, "r", 0, SIZE_NONE, 0, |
| 444 | cris_reg_mode_jump_op}, |
| 445 | |
| 446 | {"jsr", 0xB930, 0x42c0, "s", 0, SIZE_FIX_32, 0, |
| 447 | cris_none_reg_mode_jump_op}, |
| 448 | |
| 449 | {"jsr", 0xB930, 0x42c0, "S", 0, SIZE_NONE, 0, |
| 450 | cris_none_reg_mode_jump_op}, |
| 451 | |
| 452 | {"jsrc", 0x39b0, 0xc640, "r", 0, SIZE_NONE, |
| 453 | cris_ver_v8p, |
| 454 | cris_reg_mode_jump_op}, |
| 455 | |
| 456 | {"jsrc", 0x3930, 0xc2c0, "s", 0, SIZE_FIX_32, |
| 457 | cris_ver_v8p, |
| 458 | cris_none_reg_mode_jump_op}, |
| 459 | |
| 460 | {"jsrc", 0x3930, 0xc2c0, "S", 0, SIZE_NONE, |
| 461 | cris_ver_v8p, |
| 462 | cris_none_reg_mode_jump_op}, |
| 463 | |
| 464 | {"jump", 0x09b0, 0xF640, "r", 0, SIZE_NONE, 0, |
| 465 | cris_reg_mode_jump_op}, |
| 466 | |
| 467 | {"jump", |
| 468 | JUMP_INDIR_OPCODE, JUMP_INDIR_Z_BITS, "s", 0, SIZE_FIX_32, 0, |
| 469 | cris_none_reg_mode_jump_op}, |
| 470 | |
| 471 | {"jump", |
| 472 | JUMP_INDIR_OPCODE, JUMP_INDIR_Z_BITS, "S", 0, SIZE_NONE, 0, |
| 473 | cris_none_reg_mode_jump_op}, |
| 474 | |
| 475 | {"jmpu", 0x8930, 0x72c0, "s", 0, SIZE_FIX_32, |
| 476 | cris_ver_v10p, |
| 477 | cris_none_reg_mode_jump_op}, |
| 478 | |
| 479 | {"jmpu", 0x8930, 0x72c0, "S", 0, SIZE_NONE, |
| 480 | cris_ver_v10p, |
| 481 | cris_none_reg_mode_jump_op}, |
| 482 | |
| 483 | {"lsl", 0x04C0, 0x0B00, "m r,R", 0, SIZE_NONE, 0, |
| 484 | cris_dstep_logshift_mstep_neg_not_op}, |
| 485 | |
| 486 | {"lslq", 0x03c0, 0x0C20, "c,R", 0, SIZE_NONE, 0, |
| 487 | cris_dstep_logshift_mstep_neg_not_op}, |
| 488 | |
| 489 | {"lsr", 0x07C0, 0x0800, "m r,R", 0, SIZE_NONE, 0, |
| 490 | cris_dstep_logshift_mstep_neg_not_op}, |
| 491 | |
| 492 | {"lsrq", 0x03e0, 0x0C00, "c,R", 0, SIZE_NONE, 0, |
| 493 | cris_dstep_logshift_mstep_neg_not_op}, |
| 494 | |
| 495 | {"lz", 0x0730, 0x08C0, "r,R", 0, SIZE_NONE, |
| 496 | cris_ver_v3p, |
| 497 | cris_not_implemented_op}, |
| 498 | |
| 499 | {"move", 0x0640, 0x0980, "m r,R", 0, SIZE_NONE, 0, |
| 500 | cris_reg_mode_add_sub_cmp_and_or_move_op}, |
| 501 | |
| 502 | {"move", 0x0630, 0x09c0, "r,P", 0, SIZE_NONE, 0, |
| 503 | cris_move_to_preg_op}, |
| 504 | |
| 505 | {"move", 0x0670, 0x0980, "P,r", 0, SIZE_NONE, 0, |
| 506 | cris_reg_mode_move_from_preg_op}, |
| 507 | |
| 508 | {"move", 0x0BC0, 0x0000, "m R,y", 0, SIZE_FIELD, 0, |
| 509 | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
| 510 | |
| 511 | {"move", 0x0BC0, 0x0000, "m D,S", 0, SIZE_NONE, 0, |
| 512 | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
| 513 | |
| 514 | {"move", 0x0A40, 0x0180, "m s,R", 0, SIZE_FIELD, 0, |
| 515 | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
| 516 | |
| 517 | {"move", 0x0A40, 0x0180, "m S,D", 0, SIZE_NONE, 0, |
| 518 | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
| 519 | |
| 520 | {"move", 0x0A30, 0x01c0, "s,P", 0, SIZE_SPEC_REG, 0, |
| 521 | cris_move_to_preg_op}, |
| 522 | |
| 523 | {"move", 0x0A30, 0x01c0, "S,P", 0, SIZE_NONE, 0, |
| 524 | cris_move_to_preg_op}, |
| 525 | |
| 526 | {"move", 0x0A70, 0x0180, "P,y", 0, SIZE_SPEC_REG, 0, |
| 527 | cris_none_reg_mode_move_from_preg_op}, |
| 528 | |
| 529 | {"move", 0x0A70, 0x0180, "P,S", 0, SIZE_NONE, 0, |
| 530 | cris_none_reg_mode_move_from_preg_op}, |
| 531 | |
| 532 | {"movem", 0x0BF0, 0x0000, "R,y", 0, SIZE_FIX_32, 0, |
| 533 | cris_move_reg_to_mem_movem_op}, |
| 534 | |
| 535 | {"movem", 0x0BF0, 0x0000, "D,S", 0, SIZE_NONE, 0, |
| 536 | cris_move_reg_to_mem_movem_op}, |
| 537 | |
| 538 | {"movem", 0x0BB0, 0x0040, "s,R", 0, SIZE_FIX_32, 0, |
| 539 | cris_move_mem_to_reg_movem_op}, |
| 540 | |
| 541 | {"movem", 0x0BB0, 0x0040, "S,D", 0, SIZE_NONE, 0, |
| 542 | cris_move_mem_to_reg_movem_op}, |
| 543 | |
| 544 | {"moveq", 0x0240, 0x0D80, "i,R", 0, SIZE_NONE, 0, |
| 545 | cris_quick_mode_and_cmp_move_or_op}, |
| 546 | |
| 547 | {"movs", 0x0460, 0x0B80, "z r,R", 0, SIZE_NONE, 0, |
| 548 | cris_reg_mode_add_sub_cmp_and_or_move_op}, |
| 549 | |
| 550 | {"movs", 0x0860, 0x0380, "z s,R", 0, SIZE_FIELD, 0, |
| 551 | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
| 552 | |
| 553 | {"movs", 0x0860, 0x0380, "z S,D", 0, SIZE_NONE, 0, |
| 554 | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
| 555 | |
| 556 | {"movu", 0x0440, 0x0Ba0, "z r,R", 0, SIZE_NONE, 0, |
| 557 | cris_reg_mode_add_sub_cmp_and_or_move_op}, |
| 558 | |
| 559 | {"movu", 0x0840, 0x03a0, "z s,R", 0, SIZE_FIELD, 0, |
| 560 | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
| 561 | |
| 562 | {"movu", 0x0840, 0x03a0, "z S,D", 0, SIZE_NONE, 0, |
| 563 | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
| 564 | |
| 565 | {"mstep", 0x07f0, 0x0800, "r,R", 0, SIZE_NONE, 0, |
| 566 | cris_dstep_logshift_mstep_neg_not_op}, |
| 567 | |
| 568 | {"muls", 0x0d00, 0x02c0, "m r,R", 0, SIZE_NONE, |
| 569 | cris_ver_v10p, |
| 570 | cris_muls_op}, |
| 571 | |
| 572 | {"mulu", 0x0900, 0x06c0, "m r,R", 0, SIZE_NONE, |
| 573 | cris_ver_v10p, |
| 574 | cris_mulu_op}, |
| 575 | |
| 576 | {"neg", 0x0580, 0x0A40, "m r,R", 0, SIZE_NONE, 0, |
| 577 | cris_dstep_logshift_mstep_neg_not_op}, |
| 578 | |
| 579 | {"nop", NOP_OPCODE, NOP_Z_BITS, "", 0, SIZE_NONE, 0, |
| 580 | cris_btst_nop_op}, |
| 581 | |
| 582 | {"not", 0x8770, 0x7880, "r", 0, SIZE_NONE, 0, |
| 583 | cris_dstep_logshift_mstep_neg_not_op}, |
| 584 | |
| 585 | {"or", 0x0740, 0x0880, "m r,R", 0, SIZE_NONE, 0, |
| 586 | cris_reg_mode_add_sub_cmp_and_or_move_op}, |
| 587 | |
| 588 | {"or", 0x0B40, 0x0080, "m s,R", 0, SIZE_FIELD, 0, |
| 589 | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
| 590 | |
| 591 | {"or", 0x0B40, 0x0080, "m S,D", 0, SIZE_NONE, 0, |
| 592 | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
| 593 | |
| 594 | {"or", 0x0B40, 0x0480, "m S,R,r", 0, SIZE_NONE, 0, |
| 595 | cris_three_operand_add_sub_cmp_and_or_op}, |
| 596 | |
| 597 | {"orq", 0x0340, 0x0C80, "i,R", 0, SIZE_NONE, 0, |
| 598 | cris_quick_mode_and_cmp_move_or_op}, |
| 599 | |
| 600 | {"pop", 0x0E6E, 0x0191, "!R", 0, SIZE_NONE, 0, |
| 601 | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
| 602 | |
| 603 | {"pop", 0x0e3e, 0x01c1, "!P", 0, SIZE_NONE, 0, |
| 604 | cris_none_reg_mode_move_from_preg_op}, |
| 605 | |
| 606 | {"push", 0x0FEE, 0x0011, "BR", 0, SIZE_NONE, 0, |
| 607 | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
| 608 | |
| 609 | {"push", 0x0E7E, 0x0181, "BP", 0, SIZE_NONE, 0, |
| 610 | cris_move_to_preg_op}, |
| 611 | |
| 612 | {"rbf", 0x3b30, 0xc0c0, "y", 0, SIZE_NONE, |
| 613 | cris_ver_v10p, |
| 614 | cris_not_implemented_op}, |
| 615 | |
| 616 | {"rbf", 0x3b30, 0xc0c0, "S", 0, SIZE_NONE, |
| 617 | cris_ver_v10p, |
| 618 | cris_not_implemented_op}, |
| 619 | |
| 620 | {"ret", 0xB67F, 0x4980, "", 1, SIZE_NONE, 0, |
| 621 | cris_reg_mode_move_from_preg_op}, |
| 622 | |
| 623 | {"retb", 0xe67f, 0x1980, "", 1, SIZE_NONE, 0, |
| 624 | cris_reg_mode_move_from_preg_op}, |
| 625 | |
| 626 | {"reti", 0xA67F, 0x5980, "", 1, SIZE_NONE, 0, |
| 627 | cris_reg_mode_move_from_preg_op}, |
| 628 | |
| 629 | {"sbfs", 0x3b70, 0xc080, "y", 0, SIZE_NONE, |
| 630 | cris_ver_v10p, |
| 631 | cris_not_implemented_op}, |
| 632 | |
| 633 | {"sbfs", 0x3b70, 0xc080, "S", 0, SIZE_NONE, |
| 634 | cris_ver_v10p, |
| 635 | cris_not_implemented_op}, |
| 636 | |
| 637 | {"sa", |
| 638 | 0x0530+CC_A*0x1000, |
| 639 | 0x0AC0+(0xf-CC_A)*0x1000, "r", 0, SIZE_NONE, 0, |
| 640 | cris_scc_op}, |
| 641 | |
| 642 | {"scc", |
| 643 | 0x0530+CC_CC*0x1000, |
| 644 | 0x0AC0+(0xf-CC_CC)*0x1000, "r", 0, SIZE_NONE, 0, |
| 645 | cris_scc_op}, |
| 646 | |
| 647 | {"scs", |
| 648 | 0x0530+CC_CS*0x1000, |
| 649 | 0x0AC0+(0xf-CC_CS)*0x1000, "r", 0, SIZE_NONE, 0, |
| 650 | cris_scc_op}, |
| 651 | |
| 652 | {"seq", |
| 653 | 0x0530+CC_EQ*0x1000, |
| 654 | 0x0AC0+(0xf-CC_EQ)*0x1000, "r", 0, SIZE_NONE, 0, |
| 655 | cris_scc_op}, |
| 656 | |
| 657 | {"setf", 0x05b0, 0x0A40, "f", 0, SIZE_NONE, 0, |
| 658 | cris_ax_ei_setf_op}, |
| 659 | |
| 660 | /* Need to have "swf" in front of "sext" so it is the one displayed in |
| 661 | disassembly. */ |
| 662 | {"swf", |
| 663 | 0x0530+CC_EXT*0x1000, |
| 664 | 0x0AC0+(0xf-CC_EXT)*0x1000, "r", 0, SIZE_NONE, |
| 665 | cris_ver_v10p, |
| 666 | cris_scc_op}, |
| 667 | |
| 668 | {"sext", |
| 669 | 0x0530+CC_EXT*0x1000, |
| 670 | 0x0AC0+(0xf-CC_EXT)*0x1000, "r", 0, SIZE_NONE, |
| 671 | cris_ver_v0_3, |
| 672 | cris_scc_op}, |
| 673 | |
| 674 | {"sge", |
| 675 | 0x0530+CC_GE*0x1000, |
| 676 | 0x0AC0+(0xf-CC_GE)*0x1000, "r", 0, SIZE_NONE, 0, |
| 677 | cris_scc_op}, |
| 678 | |
| 679 | {"sgt", |
| 680 | 0x0530+CC_GT*0x1000, |
| 681 | 0x0AC0+(0xf-CC_GT)*0x1000, "r", 0, SIZE_NONE, 0, |
| 682 | cris_scc_op}, |
| 683 | |
| 684 | {"shi", |
| 685 | 0x0530+CC_HI*0x1000, |
| 686 | 0x0AC0+(0xf-CC_HI)*0x1000, "r", 0, SIZE_NONE, 0, |
| 687 | cris_scc_op}, |
| 688 | |
| 689 | {"shs", |
| 690 | 0x0530+CC_HS*0x1000, |
| 691 | 0x0AC0+(0xf-CC_HS)*0x1000, "r", 0, SIZE_NONE, 0, |
| 692 | cris_scc_op}, |
| 693 | |
| 694 | {"sle", |
| 695 | 0x0530+CC_LE*0x1000, |
| 696 | 0x0AC0+(0xf-CC_LE)*0x1000, "r", 0, SIZE_NONE, 0, |
| 697 | cris_scc_op}, |
| 698 | |
| 699 | {"slo", |
| 700 | 0x0530+CC_LO*0x1000, |
| 701 | 0x0AC0+(0xf-CC_LO)*0x1000, "r", 0, SIZE_NONE, 0, |
| 702 | cris_scc_op}, |
| 703 | |
| 704 | {"sls", |
| 705 | 0x0530+CC_LS*0x1000, |
| 706 | 0x0AC0+(0xf-CC_LS)*0x1000, "r", 0, SIZE_NONE, 0, |
| 707 | cris_scc_op}, |
| 708 | |
| 709 | {"slt", |
| 710 | 0x0530+CC_LT*0x1000, |
| 711 | 0x0AC0+(0xf-CC_LT)*0x1000, "r", 0, SIZE_NONE, 0, |
| 712 | cris_scc_op}, |
| 713 | |
| 714 | {"smi", |
| 715 | 0x0530+CC_MI*0x1000, |
| 716 | 0x0AC0+(0xf-CC_MI)*0x1000, "r", 0, SIZE_NONE, 0, |
| 717 | cris_scc_op}, |
| 718 | |
| 719 | {"sne", |
| 720 | 0x0530+CC_NE*0x1000, |
| 721 | 0x0AC0+(0xf-CC_NE)*0x1000, "r", 0, SIZE_NONE, 0, |
| 722 | cris_scc_op}, |
| 723 | |
| 724 | {"spl", |
| 725 | 0x0530+CC_PL*0x1000, |
| 726 | 0x0AC0+(0xf-CC_PL)*0x1000, "r", 0, SIZE_NONE, 0, |
| 727 | cris_scc_op}, |
| 728 | |
| 729 | {"sub", 0x0680, 0x0940, "m r,R", 0, SIZE_NONE, 0, |
| 730 | cris_reg_mode_add_sub_cmp_and_or_move_op}, |
| 731 | |
| 732 | {"sub", 0x0a80, 0x0140, "m s,R", 0, SIZE_FIELD, 0, |
| 733 | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
| 734 | |
| 735 | {"sub", 0x0a80, 0x0140, "m S,D", 0, SIZE_NONE, 0, |
| 736 | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
| 737 | |
| 738 | {"sub", 0x0a80, 0x0540, "m S,R,r", 0, SIZE_NONE, 0, |
| 739 | cris_three_operand_add_sub_cmp_and_or_op}, |
| 740 | |
| 741 | {"subq", 0x0280, 0x0d40, "I,R", 0, SIZE_NONE, 0, |
| 742 | cris_quick_mode_add_sub_op}, |
| 743 | |
| 744 | {"subs", 0x04a0, 0x0b40, "z r,R", 0, SIZE_NONE, 0, |
| 745 | cris_reg_mode_add_sub_cmp_and_or_move_op}, |
| 746 | |
| 747 | {"subs", 0x08a0, 0x0340, "z s,R", 0, SIZE_FIELD, 0, |
| 748 | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
| 749 | |
| 750 | {"subs", 0x08a0, 0x0340, "z S,D", 0, SIZE_NONE, 0, |
| 751 | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
| 752 | |
| 753 | {"subs", 0x08a0, 0x0740, "z S,R,r", 0, SIZE_NONE, 0, |
| 754 | cris_three_operand_add_sub_cmp_and_or_op}, |
| 755 | |
| 756 | {"subu", 0x0480, 0x0b60, "z r,R", 0, SIZE_NONE, 0, |
| 757 | cris_reg_mode_add_sub_cmp_and_or_move_op}, |
| 758 | |
| 759 | {"subu", 0x0880, 0x0360, "z s,R", 0, SIZE_FIELD, 0, |
| 760 | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
| 761 | |
| 762 | {"subu", 0x0880, 0x0360, "z S,D", 0, SIZE_NONE, 0, |
| 763 | cris_none_reg_mode_add_sub_cmp_and_or_move_op}, |
| 764 | |
| 765 | {"subu", 0x0880, 0x0760, "z S,R,r", 0, SIZE_NONE, 0, |
| 766 | cris_three_operand_add_sub_cmp_and_or_op}, |
| 767 | |
| 768 | {"svc", |
| 769 | 0x0530+CC_VC*0x1000, |
| 770 | 0x0AC0+(0xf-CC_VC)*0x1000, "r", 0, SIZE_NONE, 0, |
| 771 | cris_scc_op}, |
| 772 | |
| 773 | {"svs", |
| 774 | 0x0530+CC_VS*0x1000, |
| 775 | 0x0AC0+(0xf-CC_VS)*0x1000, "r", 0, SIZE_NONE, 0, |
| 776 | cris_scc_op}, |
| 777 | |
| 778 | /* The insn "swapn" is the same as "not" and will be disassembled as |
| 779 | such, but the swap* family of mnmonics are generally v8-and-higher |
| 780 | only, so count it in. */ |
| 781 | {"swapn", 0x8770, 0x7880, "r", 0, SIZE_NONE, |
| 782 | cris_ver_v8p, |
| 783 | cris_not_implemented_op}, |
| 784 | |
| 785 | {"swapw", 0x4770, 0xb880, "r", 0, SIZE_NONE, |
| 786 | cris_ver_v8p, |
| 787 | cris_not_implemented_op}, |
| 788 | |
| 789 | {"swapnw", 0xc770, 0x3880, "r", 0, SIZE_NONE, |
| 790 | cris_ver_v8p, |
| 791 | cris_not_implemented_op}, |
| 792 | |
| 793 | {"swapb", 0x2770, 0xd880, "r", 0, SIZE_NONE, |
| 794 | cris_ver_v8p, |
| 795 | cris_not_implemented_op}, |
| 796 | |
| 797 | {"swapnb", 0xA770, 0x5880, "r", 0, SIZE_NONE, |
| 798 | cris_ver_v8p, |
| 799 | cris_not_implemented_op}, |
| 800 | |
| 801 | {"swapwb", 0x6770, 0x9880, "r", 0, SIZE_NONE, |
| 802 | cris_ver_v8p, |
| 803 | cris_not_implemented_op}, |
| 804 | |
| 805 | {"swapnwb", 0xE770, 0x1880, "r", 0, SIZE_NONE, |
| 806 | cris_ver_v8p, |
| 807 | cris_not_implemented_op}, |
| 808 | |
| 809 | {"swapr", 0x1770, 0xe880, "r", 0, SIZE_NONE, |
| 810 | cris_ver_v8p, |
| 811 | cris_not_implemented_op}, |
| 812 | |
| 813 | {"swapnr", 0x9770, 0x6880, "r", 0, SIZE_NONE, |
| 814 | cris_ver_v8p, |
| 815 | cris_not_implemented_op}, |
| 816 | |
| 817 | {"swapwr", 0x5770, 0xa880, "r", 0, SIZE_NONE, |
| 818 | cris_ver_v8p, |
| 819 | cris_not_implemented_op}, |
| 820 | |
| 821 | {"swapnwr", 0xd770, 0x2880, "r", 0, SIZE_NONE, |
| 822 | cris_ver_v8p, |
| 823 | cris_not_implemented_op}, |
| 824 | |
| 825 | {"swapbr", 0x3770, 0xc880, "r", 0, SIZE_NONE, |
| 826 | cris_ver_v8p, |
| 827 | cris_not_implemented_op}, |
| 828 | |
| 829 | {"swapnbr", 0xb770, 0x4880, "r", 0, SIZE_NONE, |
| 830 | cris_ver_v8p, |
| 831 | cris_not_implemented_op}, |
| 832 | |
| 833 | {"swapwbr", 0x7770, 0x8880, "r", 0, SIZE_NONE, |
| 834 | cris_ver_v8p, |
| 835 | cris_not_implemented_op}, |
| 836 | |
| 837 | {"swapnwbr", 0xf770, 0x0880, "r", 0, SIZE_NONE, |
| 838 | cris_ver_v8p, |
| 839 | cris_not_implemented_op}, |
| 840 | |
| 841 | {"test", 0x0640, 0x0980, "m D", 0, SIZE_NONE, 0, |
| 842 | cris_reg_mode_test_op}, |
| 843 | |
| 844 | {"test", 0x0b80, 0xf040, "m s", 0, SIZE_FIELD, 0, |
| 845 | cris_none_reg_mode_clear_test_op}, |
| 846 | |
| 847 | {"test", 0x0b80, 0xf040, "m S", 0, SIZE_NONE, 0, |
| 848 | cris_none_reg_mode_clear_test_op}, |
| 849 | |
| 850 | {"xor", 0x07B0, 0x0840, "r,R", 0, SIZE_NONE, 0, |
| 851 | cris_xor_op}, |
| 852 | |
| 853 | {NULL, 0, 0, NULL, 0, 0, 0, cris_not_implemented_op} |
| 854 | }; |
| 855 | |
| 856 | /* Condition-names, indexed by the CC_* numbers as found in cris.h. */ |
| 857 | const char * const |
| 858 | cris_cc_strings[] = |
| 859 | { |
| 860 | "hs", |
| 861 | "lo", |
| 862 | "ne", |
| 863 | "eq", |
| 864 | "vc", |
| 865 | "vs", |
| 866 | "pl", |
| 867 | "mi", |
| 868 | "ls", |
| 869 | "hi", |
| 870 | "ge", |
| 871 | "lt", |
| 872 | "gt", |
| 873 | "le", |
| 874 | "a", |
| 875 | /* In v0, this would be "ext". */ |
| 876 | "wf", |
| 877 | }; |
| 878 | |
| 879 | |
| 880 | /* |
| 881 | * Local variables: |
| 882 | * eval: (c-set-style "gnu") |
| 883 | * indent-tabs-mode: t |
| 884 | * End: |
| 885 | */ |