| 1 | /* Declarations for C-SKY opcode table |
| 2 | Copyright (C) 2007-2020 Free Software Foundation, Inc. |
| 3 | Contributed by C-SKY Microsystems and Mentor Graphics. |
| 4 | |
| 5 | This file is part of the GNU opcodes library. |
| 6 | |
| 7 | This library is free software; you can redistribute it and/or modify |
| 8 | it under the terms of the GNU General Public License as published by |
| 9 | the Free Software Foundation; either version 3, or (at your option) |
| 10 | any later version. |
| 11 | |
| 12 | It is distributed in the hope that it will be useful, but WITHOUT |
| 13 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
| 14 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public |
| 15 | License for more details. |
| 16 | |
| 17 | You should have received a copy of the GNU General Public License |
| 18 | along with GAS; see the file COPYING. If not, write to the Free |
| 19 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
| 20 | 02110-1301, USA. */ |
| 21 | |
| 22 | #include "opcode/csky.h" |
| 23 | |
| 24 | #define OP_TABLE_NUM 2 |
| 25 | #define MAX_OPRND_NUM 4 |
| 26 | |
| 27 | enum operand_type |
| 28 | { |
| 29 | OPRND_TYPE_NONE = 0, |
| 30 | /* Control register. */ |
| 31 | OPRND_TYPE_CTRLREG, |
| 32 | /* r0 - r7. */ |
| 33 | OPRND_TYPE_GREG0_7, |
| 34 | /* r0 - r15. */ |
| 35 | OPRND_TYPE_GREG0_15, |
| 36 | /* r16 - r31. */ |
| 37 | OPRND_TYPE_GREG16_31, |
| 38 | /* r0 - r31. */ |
| 39 | OPRND_TYPE_AREG, |
| 40 | /* (rx). */ |
| 41 | OPRND_TYPE_AREG_WITH_BRACKET, |
| 42 | OPRND_TYPE_AREG_WITH_LSHIFT, |
| 43 | OPRND_TYPE_AREG_WITH_LSHIFT_FPU, |
| 44 | |
| 45 | OPRND_TYPE_FREG_WITH_INDEX, |
| 46 | /* r1 only, for xtrb0(1)(2)(3) in csky v1 ISA. */ |
| 47 | OPRND_TYPE_REG_r1a, |
| 48 | /* r1 only, for divs/divu in csky v1 ISA. */ |
| 49 | OPRND_TYPE_REG_r1b, |
| 50 | /* r28. */ |
| 51 | OPRND_TYPE_REG_r28, |
| 52 | OPRND_TYPE_REGr4_r7, |
| 53 | /* sp register with bracket. */ |
| 54 | OPRND_TYPE_REGbsp, |
| 55 | /* sp register. */ |
| 56 | OPRND_TYPE_REGsp, |
| 57 | /* Register with bracket. */ |
| 58 | OPRND_TYPE_REGnr4_r7, |
| 59 | /* Not sp register. */ |
| 60 | OPRND_TYPE_REGnsp, |
| 61 | /* Not lr register. */ |
| 62 | OPRND_TYPE_REGnlr, |
| 63 | /* Not sp/lr register. */ |
| 64 | OPRND_TYPE_REGnsplr, |
| 65 | /* hi/lo register. */ |
| 66 | OPRND_TYPE_REGhilo, |
| 67 | /* VDSP register. */ |
| 68 | OPRND_TYPE_VREG, |
| 69 | |
| 70 | /* cp index. */ |
| 71 | OPRND_TYPE_CPIDX, |
| 72 | /* cp regs. */ |
| 73 | OPRND_TYPE_CPREG, |
| 74 | /* cp cregs. */ |
| 75 | OPRND_TYPE_CPCREG, |
| 76 | /* fpu regs. */ |
| 77 | OPRND_TYPE_FREG, |
| 78 | /* fpu even regs. */ |
| 79 | OPRND_TYPE_FEREG, |
| 80 | /* Float round mode. */ |
| 81 | OPRND_TYPE_RM, |
| 82 | /* PSR bits. */ |
| 83 | OPRND_TYPE_PSR_BITS_LIST, |
| 84 | |
| 85 | /* Constant. */ |
| 86 | OPRND_TYPE_CONSTANT, |
| 87 | /* Floating Constant. */ |
| 88 | OPRND_TYPE_FCONSTANT, |
| 89 | /* Extern lrw constant. */ |
| 90 | OPRND_TYPE_ELRW_CONSTANT, |
| 91 | /* [label]. */ |
| 92 | OPRND_TYPE_LABEL_WITH_BRACKET, |
| 93 | /* The operand is the same as first reg. It is a dummy reg that doesn't |
| 94 | appear in the binary code of the instruction. It is also used by |
| 95 | the disassembler. |
| 96 | For example: bclri rz, rz, imm5 -> bclri rz, imm5. */ |
| 97 | OPRND_TYPE_DUMMY_REG, |
| 98 | /* The type of the operand is same as the first operand. If the value |
| 99 | of the operand is same as the first operand, we can use a 16-bit |
| 100 | instruction to represent the opcode. |
| 101 | For example: addc r1, r1, r2 -> addc16 r1, r2. */ |
| 102 | OPRND_TYPE_2IN1_DUMMY, |
| 103 | /* Output a reg same as the first reg. |
| 104 | For example: addc r17, r1 -> addc32 r17, r17, r1. |
| 105 | The old "addc" cannot be represented by a 16-bit instruction because |
| 106 | 16-bit "addc" only supports regs from r0 to r15. So we use "addc32" |
| 107 | which has 3 operands, and duplicate the first operand to the second. */ |
| 108 | OPRND_TYPE_DUP_GREG0_7, |
| 109 | OPRND_TYPE_DUP_GREG0_15, |
| 110 | OPRND_TYPE_DUP_AREG, |
| 111 | /* Immediate. */ |
| 112 | OPRND_TYPE_IMM1b, |
| 113 | OPRND_TYPE_IMM2b, |
| 114 | OPRND_TYPE_IMM3b, |
| 115 | OPRND_TYPE_IMM4b, |
| 116 | OPRND_TYPE_IMM5b, |
| 117 | OPRND_TYPE_IMM7b, |
| 118 | OPRND_TYPE_IMM8b, |
| 119 | OPRND_TYPE_IMM12b, |
| 120 | OPRND_TYPE_IMM15b, |
| 121 | OPRND_TYPE_IMM16b, |
| 122 | OPRND_TYPE_IMM18b, |
| 123 | OPRND_TYPE_IMM32b, |
| 124 | /* Immediate left shift 2 bits. */ |
| 125 | OPRND_TYPE_IMM7b_LS2, |
| 126 | OPRND_TYPE_IMM8b_LS2, |
| 127 | /* OPRND_TYPE_IMM5b_a_b means: Immediate in (a, b). */ |
| 128 | OPRND_TYPE_IMM5b_1_31, |
| 129 | OPRND_TYPE_IMM5b_7_31, |
| 130 | /* Operand type for rori and rotri. */ |
| 131 | OPRND_TYPE_IMM5b_RORI, |
| 132 | OPRND_TYPE_IMM5b_POWER, |
| 133 | OPRND_TYPE_IMM5b_7_31_POWER, |
| 134 | OPRND_TYPE_IMM5b_BMASKI, |
| 135 | OPRND_TYPE_IMM8b_BMASKI, |
| 136 | /* For v2 movih. */ |
| 137 | OPRND_TYPE_IMM16b_MOVIH, |
| 138 | /* For v2 ori. */ |
| 139 | OPRND_TYPE_IMM16b_ORI, |
| 140 | /* For v2 ld/st. */ |
| 141 | OPRND_TYPE_IMM_LDST, |
| 142 | OPRND_TYPE_IMM_FLDST, |
| 143 | OPRND_TYPE_IMM2b_JMPIX, |
| 144 | /* Offset for bloop. */ |
| 145 | OPRND_TYPE_BLOOP_OFF4b, |
| 146 | OPRND_TYPE_BLOOP_OFF12b, |
| 147 | /* Offset for jump. */ |
| 148 | OPRND_TYPE_OFF8b, |
| 149 | OPRND_TYPE_OFF10b, |
| 150 | OPRND_TYPE_OFF11b, |
| 151 | OPRND_TYPE_OFF16b, |
| 152 | OPRND_TYPE_OFF16b_LSL1, |
| 153 | OPRND_TYPE_OFF26b, |
| 154 | /* An immediate or label. */ |
| 155 | OPRND_TYPE_IMM_OFF18b, |
| 156 | /* Offset immediate. */ |
| 157 | OPRND_TYPE_OIMM3b, |
| 158 | OPRND_TYPE_OIMM4b, |
| 159 | OPRND_TYPE_OIMM5b, |
| 160 | OPRND_TYPE_OIMM8b, |
| 161 | OPRND_TYPE_OIMM12b, |
| 162 | OPRND_TYPE_OIMM16b, |
| 163 | OPRND_TYPE_OIMM18b, |
| 164 | /* For csky v2 idly. */ |
| 165 | OPRND_TYPE_OIMM5b_IDLY, |
| 166 | /* For v2 bmaski. */ |
| 167 | OPRND_TYPE_OIMM5b_BMASKI, |
| 168 | /* Constants. */ |
| 169 | OPRND_TYPE_CONST1, |
| 170 | /* PC relative offset. */ |
| 171 | OPRND_TYPE_PCR_OFFSET_16K, |
| 172 | OPRND_TYPE_PCR_OFFSET_64K, |
| 173 | OPRND_TYPE_PCR_OFFSET_64M, |
| 174 | OPRND_TYPE_CPFUNC, |
| 175 | OPRND_TYPE_GOT_PLT, |
| 176 | OPRND_TYPE_REGLIST_LDM, |
| 177 | OPRND_TYPE_REGLIST_DASH, |
| 178 | OPRND_TYPE_FREGLIST_DASH, |
| 179 | OPRND_TYPE_REGLIST_COMMA, |
| 180 | OPRND_TYPE_REGLIST_DASH_COMMA, |
| 181 | OPRND_TYPE_BRACKET, |
| 182 | OPRND_TYPE_ABRACKET, |
| 183 | OPRND_TYPE_JBTF, |
| 184 | OPRND_TYPE_JBR, |
| 185 | OPRND_TYPE_JBSR, |
| 186 | OPRND_TYPE_UNCOND10b, |
| 187 | OPRND_TYPE_UNCOND16b, |
| 188 | OPRND_TYPE_COND10b, |
| 189 | OPRND_TYPE_COND16b, |
| 190 | OPRND_TYPE_JCOMPZ, |
| 191 | OPRND_TYPE_LSB2SIZE, |
| 192 | OPRND_TYPE_MSB2SIZE, |
| 193 | OPRND_TYPE_LSB, |
| 194 | OPRND_TYPE_MSB, |
| 195 | /* Single float and double float. */ |
| 196 | OPRND_TYPE_SFLOAT, |
| 197 | OPRND_TYPE_DFLOAT, |
| 198 | }; |
| 199 | |
| 200 | /* Operand descriptors. */ |
| 201 | struct operand |
| 202 | { |
| 203 | /* Mask for suboperand. */ |
| 204 | unsigned int mask; |
| 205 | /* Suboperand type. */ |
| 206 | enum operand_type type; |
| 207 | /* Operand shift. */ |
| 208 | int shift; |
| 209 | }; |
| 210 | |
| 211 | struct soperand |
| 212 | { |
| 213 | /* Mask for operand. */ |
| 214 | unsigned int mask; |
| 215 | /* Operand type. */ |
| 216 | enum operand_type type; |
| 217 | /* Operand shift. */ |
| 218 | int shift; |
| 219 | /* Suboperand. */ |
| 220 | struct operand subs[3]; |
| 221 | }; |
| 222 | |
| 223 | union csky_operand |
| 224 | { |
| 225 | struct operand oprnds[5]; |
| 226 | struct suboperand1 |
| 227 | { |
| 228 | struct operand oprnd; |
| 229 | struct soperand soprnd; |
| 230 | } soprnd1; |
| 231 | struct suboperand2 |
| 232 | { |
| 233 | struct soperand soprnd; |
| 234 | struct operand oprnd; |
| 235 | } soprnd2; |
| 236 | }; |
| 237 | |
| 238 | /* Describe a single instruction encoding. */ |
| 239 | struct csky_opcode_info |
| 240 | { |
| 241 | /* How many operands. */ |
| 242 | long operand_num; |
| 243 | /* The instruction opcode. */ |
| 244 | unsigned int opcode; |
| 245 | /* Operand information. */ |
| 246 | union csky_operand oprnd; |
| 247 | }; |
| 248 | |
| 249 | /* C-SKY instruction description. Each mnemonic can have multiple |
| 250 | 16-bit and 32-bit encodings. */ |
| 251 | struct csky_opcode |
| 252 | { |
| 253 | /* The instruction name. */ |
| 254 | const char *mnemonic; |
| 255 | /* Whether this is an unconditional control transfer instruction, |
| 256 | for the purposes of placing literal pools after it. |
| 257 | 0 = no, 1 = within function, 2 = end of function. |
| 258 | See check_literals in gas/config/tc-csky.c. */ |
| 259 | int transfer; |
| 260 | /* Encodings for 16-bit opcodes. */ |
| 261 | struct csky_opcode_info op16[OP_TABLE_NUM]; |
| 262 | /* Encodings for 32-bit opcodes. */ |
| 263 | struct csky_opcode_info op32[OP_TABLE_NUM]; |
| 264 | /* Instruction set flag. */ |
| 265 | unsigned int isa_flag16; |
| 266 | unsigned int isa_flag32; |
| 267 | /* Whether this insn needs relocation, 0: no, !=0: yes. */ |
| 268 | signed int reloc16; |
| 269 | signed int reloc32; |
| 270 | /* Whether this insn needs relaxation, 0: no, != 0: yes. */ |
| 271 | signed int relax; |
| 272 | /* Worker function to call when this instruction needs special assembler |
| 273 | handling. */ |
| 274 | bfd_boolean (*work)(void); |
| 275 | }; |
| 276 | |
| 277 | /* The following are the opcodes used in relax/fix process. */ |
| 278 | #define CSKYV1_INST_JMPI 0x7000 |
| 279 | #define CSKYV1_INST_ADDI 0x2000 |
| 280 | #define CSKYV1_INST_SUBI 0x2400 |
| 281 | #define CSKYV1_INST_LDW 0x8000 |
| 282 | #define CSKYV1_INST_STW 0x9000 |
| 283 | #define CSKYV1_INST_BSR 0xf800 |
| 284 | #define CSKYV1_INST_LRW 0x7000 |
| 285 | #define CSKYV1_INST_ADDU 0x1c00 |
| 286 | #define CSKYV1_INST_JMP 0x00c0 |
| 287 | #define CSKYV1_INST_MOV_R1_RX 0x1201 |
| 288 | #define CSKYV1_INST_MOV_RX_R1 0x1210 |
| 289 | |
| 290 | #define CSKYV2_INST_BT16 0x0800 |
| 291 | #define CSKYV2_INST_BF16 0x0c00 |
| 292 | #define CSKYV2_INST_BT32 0xe8600000 |
| 293 | #define CSKYV2_INST_BF32 0xe8400000 |
| 294 | #define CSKYV2_INST_BR32 0xe8000000 |
| 295 | #define CSKYV2_INST_NOP 0x6c03 |
| 296 | #define CSKYV2_INST_MOVI16 0x3000 |
| 297 | #define CSKYV2_INST_MOVI32 0xea000000 |
| 298 | #define CSKYV2_INST_MOVIH 0xea200000 |
| 299 | #define CSKYV2_INST_LRW16 0x1000 |
| 300 | #define CSKYV2_INST_LRW32 0xea800000 |
| 301 | #define CSKYV2_INST_BSR32 0xe0000000 |
| 302 | #define CSKYV2_INST_BR32 0xe8000000 |
| 303 | #define CSKYV2_INST_FLRW 0xf4003800 |
| 304 | #define CSKYV2_INST_JMPI32 0xeac00000 |
| 305 | #define CSKYV2_INST_JSRI32 0xeae00000 |
| 306 | #define CSKYV2_INST_JSRI_TO_LRW 0xea9a0000 |
| 307 | #define CSKYV2_INST_JSR_R26 0xe8fa0000 |
| 308 | #define CSKYV2_INST_MOV_R0_R0 0xc4004820 |
| 309 | |
| 310 | #define OPRND_SHIFT_0_BIT 0 |
| 311 | #define OPRND_SHIFT_1_BIT 1 |
| 312 | #define OPRND_SHIFT_2_BIT 2 |
| 313 | #define OPRND_SHIFT_3_BIT 3 |
| 314 | #define OPRND_SHIFT_4_BIT 4 |
| 315 | |
| 316 | #define OPRND_MASK_NONE 0x0 |
| 317 | #define OPRND_MASK_0_1 0x3 |
| 318 | #define OPRND_MASK_0_2 0x7 |
| 319 | #define OPRND_MASK_0_3 0xf |
| 320 | #define OPRND_MASK_0_4 0x1f |
| 321 | #define OPRND_MASK_0_7 0xff |
| 322 | #define OPRND_MASK_0_8 0x1ff |
| 323 | #define OPRND_MASK_0_9 0x3ff |
| 324 | #define OPRND_MASK_0_10 0x7ff |
| 325 | #define OPRND_MASK_0_11 0xfff |
| 326 | #define OPRND_MASK_0_14 0x7fff |
| 327 | #define OPRND_MASK_0_15 0xffff |
| 328 | #define OPRND_MASK_0_17 0x3ffff |
| 329 | #define OPRND_MASK_0_25 0x3ffffff |
| 330 | #define OPRND_MASK_2_4 0x1c |
| 331 | #define OPRND_MASK_2_5 0x3c |
| 332 | #define OPRND_MASK_3_7 0xf8 |
| 333 | #define OPRND_MASK_4 0x10 |
| 334 | #define OPRND_MASK_4_6 0x70 |
| 335 | #define OPRND_MASK_4_7 0xf0 |
| 336 | #define OPRND_MASK_4_8 0x1f0 |
| 337 | #define OPRND_MASK_4_10 0x7f0 |
| 338 | #define OPRND_MASK_5 0x20 |
| 339 | #define OPRND_MASK_5_6 0x60 |
| 340 | #define OPRND_MASK_5_7 0xe0 |
| 341 | #define OPRND_MASK_5_8 0x1e0 |
| 342 | #define OPRND_MASK_5_9 0x3e0 |
| 343 | #define OPRND_MASK_6_9 0x3c0 |
| 344 | #define OPRND_MASK_6_10 0x7c0 |
| 345 | #define OPRND_MASK_8_9 0x300 |
| 346 | #define OPRND_MASK_8_10 0x700 |
| 347 | #define OPRND_MASK_8_11 0xf00 |
| 348 | #define OPRND_MASK_9_10 0x600 |
| 349 | #define OPRND_MASK_9_12 0x1e00 |
| 350 | #define OPRND_MASK_10_11 0xc00 |
| 351 | #define OPRND_MASK_10_14 0x7c00 |
| 352 | #define OPRND_MASK_12_15 0xf000 |
| 353 | #define OPRND_MASK_13_17 0x3e000 |
| 354 | #define OPRND_MASK_16_19 0xf0000 |
| 355 | #define OPRND_MASK_16_20 0x1f0000 |
| 356 | #define OPRND_MASK_16_25 0x3ff0000 |
| 357 | #define OPRND_MASK_21_24 0x1e00000 |
| 358 | #define OPRND_MASK_21_25 0x3e00000 |
| 359 | #define OPRND_MASK_25 0x2000000 |
| 360 | #define OPRND_MASK_RSV 0xffffffff |
| 361 | #define OPRND_MASK_0_3or21_24 OPRND_MASK_0_3 | OPRND_MASK_21_24 |
| 362 | #define OPRND_MASK_0_4or21_25 OPRND_MASK_0_4 | OPRND_MASK_21_25 |
| 363 | #define OPRND_MASK_0_4or16_20 OPRND_MASK_0_4 | OPRND_MASK_16_20 |
| 364 | #define OPRND_MASK_0_4or8_10 OPRND_MASK_0_4 | OPRND_MASK_8_10 |
| 365 | #define OPRND_MASK_0_4or8_9 OPRND_MASK_0_4 | OPRND_MASK_8_9 |
| 366 | #define OPRND_MASK_0_14or16_20 OPRND_MASK_0_14 | OPRND_MASK_16_20 |
| 367 | #define OPRND_MASK_4or5_8 OPRND_MASK_4 | OPRND_MASK_5_8 |
| 368 | #define OPRND_MASK_5or21_24 OPRND_MASK_5 | OPRND_MASK_21_24 |
| 369 | #define OPRND_MASK_2_5or6_9 OPRND_MASK_2_5 | OPRND_MASK_6_9 |
| 370 | #define OPRND_MASK_4_6or21_25 OPRND_MASK_4_6 | OPRND_MASK_21_25 |
| 371 | #define OPRND_MASK_4_7or21_24 OPRND_MASK_4_7 | OPRND_MASK_21_24 |
| 372 | #define OPRND_MASK_5_6or21_25 OPRND_MASK_5_6 | OPRND_MASK_21_25 |
| 373 | #define OPRND_MASK_5_7or8_10 OPRND_MASK_5_7 | OPRND_MASK_8_10 |
| 374 | #define OPRND_MASK_5_9or21_25 OPRND_MASK_5_9 | OPRND_MASK_21_25 |
| 375 | #define OPRND_MASK_16_19or21_24 OPRND_MASK_16_19 | OPRND_MASK_21_24 |
| 376 | #define OPRND_MASK_16_20or21_25 OPRND_MASK_16_20 | OPRND_MASK_21_25 |
| 377 | #define OPRND_MASK_4or9_10or25 OPRND_MASK_4 | OPRND_MASK_9_10 | OPRND_MASK_25 |
| 378 | #define OPRND_MASK_4_7or16_24 OPRND_MASK_4_7 | OPRND_MASK_16_20 | OPRND_MASK_21_24 |
| 379 | |
| 380 | #define OPERAND_INFO(mask, type, shift) \ |
| 381 | {OPRND_MASK_##mask, OPRND_TYPE_##type, shift} |
| 382 | |
| 383 | #define OPCODE_INFO_NONE() \ |
| 384 | {-2, 0, \ |
| 385 | {{OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ |
| 386 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ |
| 387 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ |
| 388 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ |
| 389 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT)}}} |
| 390 | |
| 391 | /* Here and in subsequent macros, the "oprnd" arguments are the |
| 392 | parenthesized arglist to the OPERAND_INFO macro above. */ |
| 393 | #define OPCODE_INFO(num, op, oprnd1, oprnd2, oprnd3, oprnd4, oprnd5) \ |
| 394 | {num, op, \ |
| 395 | {OPERAND_INFO oprnd1, OPERAND_INFO oprnd2, OPERAND_INFO oprnd3, \ |
| 396 | OPERAND_INFO oprnd4, OPERAND_INFO oprnd5}} |
| 397 | |
| 398 | #define OPCODE_INFO0(op) \ |
| 399 | {0, op, \ |
| 400 | {{OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ |
| 401 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ |
| 402 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ |
| 403 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ |
| 404 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT)}}} |
| 405 | #define OPCODE_INFO1(op, oprnd) \ |
| 406 | {1, op, \ |
| 407 | {{OPERAND_INFO oprnd, \ |
| 408 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ |
| 409 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ |
| 410 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ |
| 411 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT)}}} |
| 412 | #define OPCODE_INFO2(op, oprnd1, oprnd2) \ |
| 413 | {2, op, \ |
| 414 | {{OPERAND_INFO oprnd1, \ |
| 415 | OPERAND_INFO oprnd2, \ |
| 416 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ |
| 417 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ |
| 418 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT)}}} |
| 419 | #define OPCODE_INFO3(op, oprnd1, oprnd2, oprnd3) \ |
| 420 | {3, op, \ |
| 421 | {{OPERAND_INFO oprnd1, \ |
| 422 | OPERAND_INFO oprnd2, \ |
| 423 | OPERAND_INFO oprnd3, \ |
| 424 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ |
| 425 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT)}}} |
| 426 | #define OPCODE_INFO4(op, oprnd1, oprnd2, oprnd3, oprnd4) \ |
| 427 | {4, op, \ |
| 428 | {{OPERAND_INFO oprnd1, \ |
| 429 | OPERAND_INFO oprnd2, \ |
| 430 | OPERAND_INFO oprnd3, \ |
| 431 | OPERAND_INFO oprnd4, \ |
| 432 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT)}}} |
| 433 | #define OPCODE_INFO_LIST(op, oprnd) \ |
| 434 | {-1, op, \ |
| 435 | {{OPERAND_INFO oprnd, \ |
| 436 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ |
| 437 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT) , \ |
| 438 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ |
| 439 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT)}}} |
| 440 | #define OPCODE_INFO5(op, oprnd1, oprnd2, oprnd3, oprnd4, oprnd5) \ |
| 441 | {5, op, \ |
| 442 | {{OPERAND_INFO oprnd1, \ |
| 443 | OPERAND_INFO oprnd2, \ |
| 444 | OPERAND_INFO oprnd3, \ |
| 445 | OPERAND_INFO oprnd4, \ |
| 446 | OPERAND_INFO oprnd5}}} |
| 447 | |
| 448 | #define BRACKET_OPRND(oprnd1, oprnd2) \ |
| 449 | OPERAND_INFO (RSV, BRACKET, OPRND_SHIFT_0_BIT), \ |
| 450 | OPERAND_INFO oprnd1, \ |
| 451 | OPERAND_INFO oprnd2, \ |
| 452 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT) |
| 453 | #define ABRACKET_OPRND(oprnd1, oprnd2) \ |
| 454 | OPERAND_INFO (RSV, ABRACKET, OPRND_SHIFT_0_BIT), \ |
| 455 | OPERAND_INFO oprnd1, \ |
| 456 | OPERAND_INFO oprnd2, \ |
| 457 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT) |
| 458 | |
| 459 | #define SOPCODE_INFO1(op, soprnd) \ |
| 460 | {1, op, \ |
| 461 | {{soprnd, \ |
| 462 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT)}}} |
| 463 | #define SOPCODE_INFO2(op, oprnd, soprnd) \ |
| 464 | {2, op, \ |
| 465 | {{OPERAND_INFO oprnd, soprnd}}} |
| 466 | |
| 467 | |
| 468 | /* Before using the opcode-defining macros, there need to be |
| 469 | #defines for _TRANSFER, _RELOC16, _RELOC32, and _RELAX. See |
| 470 | below. */ |
| 471 | /* FIXME: it is a wart that these parameters are not explicit. */ |
| 472 | |
| 473 | #define OP16(mnem, opcode16, isa) \ |
| 474 | {mnem, _TRANSFER, \ |
| 475 | {opcode16, OPCODE_INFO_NONE ()}, \ |
| 476 | {OPCODE_INFO_NONE (), OPCODE_INFO_NONE ()}, \ |
| 477 | isa, 0, _RELOC16, 0, _RELAX, NULL} |
| 478 | |
| 479 | #ifdef BUILD_AS |
| 480 | |
| 481 | #define OP16_WITH_WORK(mnem, opcode16, isa, work) \ |
| 482 | {mnem, _TRANSFER, \ |
| 483 | {opcode16, OPCODE_INFO_NONE ()}, \ |
| 484 | {OPCODE_INFO_NONE (), OPCODE_INFO_NONE ()}, \ |
| 485 | isa, 0, _RELOC16, 0, _RELAX, work} |
| 486 | #define OP32_WITH_WORK(mnem, opcode32, isa, work) \ |
| 487 | {mnem, _TRANSFER, \ |
| 488 | {OPCODE_INFO_NONE (), OPCODE_INFO_NONE ()}, \ |
| 489 | {opcode32, OPCODE_INFO_NONE ()}, \ |
| 490 | 0, isa, 0, _RELOC32, _RELAX, work} |
| 491 | #define OP16_OP32_WITH_WORK(mnem, opcode16, isa16, opcode32, isa32, work) \ |
| 492 | {mnem, _TRANSFER, \ |
| 493 | {opcode16, OPCODE_INFO_NONE ()}, \ |
| 494 | {opcode32, OPCODE_INFO_NONE ()}, \ |
| 495 | isa16, isa32, _RELOC16, _RELOC32, _RELAX, work} |
| 496 | #define DOP16_OP32_WITH_WORK(mnem, opcode16a, opcode16b, isa16, opcode32, isa32, work) \ |
| 497 | {mnem, _TRANSFER, \ |
| 498 | {opcode16a, opcode16b}, \ |
| 499 | {opcode32, OPCODE_INFO_NONE ()}, \ |
| 500 | isa16, isa32, _RELOC16, _RELOC32, _RELAX, work} |
| 501 | #define DOP16_DOP32_WITH_WORK(mnem, opcode16a, opcode16b, isa16, opcode32a, opcode32b, isa32, work) \ |
| 502 | {mnem, _TRANSFER, \ |
| 503 | {opcode16a, opcode16b}, \ |
| 504 | {opcode32a, opcode32b}, \ |
| 505 | isa16, isa32, _RELOC16, _RELOC32, _RELAX, work} |
| 506 | #define DOP32_WITH_WORK(mnem, opcode32a, opcode32b, isa, work) \ |
| 507 | {mnem, _TRANSFER, \ |
| 508 | {OPCODE_INFO_NONE (), OPCODE_INFO_NONE ()}, \ |
| 509 | {opcode32a, opcode32b}, \ |
| 510 | 0, isa, 0, _RELOC32, _RELAX, work} |
| 511 | |
| 512 | #else /* ifdef BUILD_AS */ |
| 513 | |
| 514 | #define OP16_WITH_WORK(mnem, opcode16, isa, work) \ |
| 515 | {mnem, _TRANSFER, \ |
| 516 | {opcode16, OPCODE_INFO_NONE ()}, \ |
| 517 | {OPCODE_INFO_NONE (), OPCODE_INFO_NONE ()}, \ |
| 518 | isa, 0, _RELOC16, 0, _RELAX, NULL} |
| 519 | #define OP32_WITH_WORK(mnem, opcode32, isa, work) \ |
| 520 | {mnem, _TRANSFER, \ |
| 521 | {OPCODE_INFO_NONE (), OPCODE_INFO_NONE ()}, \ |
| 522 | {opcode32, OPCODE_INFO_NONE ()}, \ |
| 523 | 0, isa, 0, _RELOC32, _RELAX, NULL} |
| 524 | #define OP16_OP32_WITH_WORK(mnem, opcode16, isa16, opcode32, isa32, work) \ |
| 525 | {mnem, _TRANSFER, \ |
| 526 | {opcode16, OPCODE_INFO_NONE ()}, \ |
| 527 | {opcode32, OPCODE_INFO_NONE ()}, \ |
| 528 | isa16, isa32, _RELOC16, _RELOC32, _RELAX, NULL} |
| 529 | #define DOP16_OP32_WITH_WORK(mnem, opcode16a, opcode16b, isa16, opcode32, isa32, work) \ |
| 530 | {mnem, _TRANSFER, \ |
| 531 | {opcode16a, opcode16b}, \ |
| 532 | {opcode32, OPCODE_INFO_NONE ()}, \ |
| 533 | isa16, isa32, _RELOC16, _RELOC32, _RELAX, NULL} |
| 534 | #define DOP16_DOP32_WITH_WORK(mnem, opcode16a, opcode16b, isa16, opcode32a, opcode32b, isa32, work) \ |
| 535 | {mnem, _TRANSFER, \ |
| 536 | {opcode16a, opcode16b}, \ |
| 537 | {opcode32a, opcode32b}, \ |
| 538 | isa16, isa32, _RELOC16, _RELOC32, _RELAX, NULL} |
| 539 | #define DOP32_WITH_WORK(mnem, opcode32a, opcode32b, isa, work) \ |
| 540 | {mnem, _TRANSFER, \ |
| 541 | {OPCODE_INFO_NONE (), OPCODE_INFO_NONE ()}, \ |
| 542 | {opcode32a, opcode32b}, \ |
| 543 | 0, isa, 0, _RELOC32, _RELAX, NULL} |
| 544 | |
| 545 | #endif /* ifdef BUILD_AS */ |
| 546 | |
| 547 | #define DOP16(mnem, opcode16_1, opcode16_2, isa) \ |
| 548 | {mnem, _TRANSFER, \ |
| 549 | {opcode16_1, opcode16_2}, \ |
| 550 | {OPCODE_INFO_NONE (), OPCODE_INFO_NONE ()}, \ |
| 551 | isa, 0, _RELOC16, 0, _RELAX, NULL} |
| 552 | #define OP32(mnem, opcode32, isa) \ |
| 553 | {mnem, _TRANSFER, \ |
| 554 | {OPCODE_INFO_NONE (), OPCODE_INFO_NONE ()}, \ |
| 555 | {opcode32, OPCODE_INFO_NONE ()}, \ |
| 556 | 0, isa, 0, _RELOC32, _RELAX, NULL} |
| 557 | #define DOP32(mnem, opcode32a, opcode32b, isa) \ |
| 558 | {mnem, _TRANSFER, \ |
| 559 | {OPCODE_INFO_NONE (), OPCODE_INFO_NONE ()}, \ |
| 560 | {opcode32a, opcode32b}, \ |
| 561 | 0, isa, 0, _RELOC32, _RELAX, NULL} |
| 562 | #define OP16_OP32(mnem, opcode16, isa16, opcode32, isa32) \ |
| 563 | {mnem, _TRANSFER, \ |
| 564 | {opcode16, OPCODE_INFO_NONE ()}, \ |
| 565 | {opcode32, OPCODE_INFO_NONE ()}, \ |
| 566 | isa16, isa32, _RELOC16, _RELOC32, _RELAX, NULL} |
| 567 | #define DOP16_OP32(mnem, opcode16a, opcode16b, isa16, opcode32, isa32) \ |
| 568 | {mnem, _TRANSFER, \ |
| 569 | {opcode16a, opcode16b}, \ |
| 570 | {opcode32, OPCODE_INFO_NONE ()}, \ |
| 571 | isa16, isa32, _RELOC16, _RELOC32, _RELAX, NULL} |
| 572 | #define OP16_DOP32(mnem, opcode16, isa16, opcode32a, opcode32b, isa32) \ |
| 573 | {mnem, _TRANSFER, \ |
| 574 | {opcode16, OPCODE_INFO_NONE ()}, \ |
| 575 | {opcode32a, opcode32b}, \ |
| 576 | isa16, isa32, _RELOC16, _RELOC32, _RELAX, NULL} |
| 577 | #define DOP16_DOP32(mnem, opcode16a, opcode16b, isa16, opcode32a, opcode32b, isa32) \ |
| 578 | {mnem, _TRANSFER, \ |
| 579 | {opcode16a, opcode16b}, \ |
| 580 | {opcode32a, opcode32b}, \ |
| 581 | isa16, isa32, _RELOC16, _RELOC32, _RELAX, NULL} |
| 582 | |
| 583 | |
| 584 | /* Register names and numbers. */ |
| 585 | #define V1_REG_SP 0 |
| 586 | #define V1_REG_LR 15 |
| 587 | |
| 588 | struct csky_reg |
| 589 | { |
| 590 | const char *name; |
| 591 | int index; |
| 592 | int flag; |
| 593 | }; |
| 594 | |
| 595 | const char *csky_general_reg[] = |
| 596 | { |
| 597 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
| 598 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", |
| 599 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", |
| 600 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", |
| 601 | NULL, |
| 602 | }; |
| 603 | |
| 604 | /* TODO: optimize. */ |
| 605 | const char *cskyv2_general_alias_reg[] = |
| 606 | { |
| 607 | "a0", "a1", "a2", "a3", "l0", "l1", "l2", "l3", |
| 608 | "l4", "l5", "l6", "l7", "t0", "t1", "sp", "lr", |
| 609 | "l8", "l9", "t2", "t3", "t4", "t5", "t6", "t7", |
| 610 | "t8", "t9", "r26", "r27", "rdb", "gb", "r30", "r31", |
| 611 | NULL, |
| 612 | }; |
| 613 | |
| 614 | /* TODO: optimize. */ |
| 615 | const char *cskyv1_general_alias_reg[] = |
| 616 | { |
| 617 | "sp", "r1", "a0", "a1", "a2", "a3", "a4", "a5", |
| 618 | "fp", "l0", "l1", "l2", "l3", "l4", "gb", "lr", |
| 619 | NULL, |
| 620 | }; |
| 621 | |
| 622 | /* TODO: optimize. */ |
| 623 | const char *csky_fpu_reg[] = |
| 624 | { |
| 625 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", |
| 626 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", |
| 627 | "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", |
| 628 | "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31", |
| 629 | NULL, |
| 630 | }; |
| 631 | |
| 632 | /* Control Registers. */ |
| 633 | struct csky_reg csky_ctrl_regs[] = |
| 634 | { |
| 635 | {"psr", 0, 0}, {"vbr", 1, 0}, {"epsr", 2, 0}, {"fpsr", 3, 0}, |
| 636 | {"epc", 4, 0}, {"fpc", 5, 0}, {"ss0", 6, 0}, {"ss1", 7, 0}, |
| 637 | {"ss2", 8, 0}, {"ss3", 9, 0}, {"ss4", 10, 0}, {"gcr", 11, 0}, |
| 638 | {"gsr", 12, 0}, {"cpuidr", 13, 0}, {"dcsr", 14, 0}, {"cwr", 15, 0}, |
| 639 | {"cfr", 16, 0}, {"ccr", 17, 0}, {"capr", 19, 0}, {"pacr", 20, 0}, |
| 640 | {"rid", 21, 0}, {"sedcr", 8, CSKY_ISA_TRUST}, {"sepcr", 9, CSKY_ISA_TRUST}, |
| 641 | {NULL, 0, 0} |
| 642 | }; |
| 643 | |
| 644 | const char *csky_cp_idx[] = |
| 645 | { |
| 646 | "cp0", "cp1", "cp2", "cp3", "cp4", "cp5", "cp6", "cp7", |
| 647 | "cp8", "cp9", "cp10", "cp11", "cp12", "cp13", "cp14", "cp15", |
| 648 | "cp16", "cp17", "cp18", "cp19", "cp20", |
| 649 | NULL, |
| 650 | }; |
| 651 | |
| 652 | const char *csky_cp_reg[] = |
| 653 | { |
| 654 | "cpr0", "cpr1", "cpr2", "cpr3", "cpr4", "cpr5", "cpr6", "cpr7", |
| 655 | "cpr8", "cpr9", "cpr10", "cpr11", "cpr12", "cpr13", "cpr14", "cpr15", |
| 656 | "cpr16", "cpr17", "cpr18", "cpr19", "cpr20", "cpr21", "cpr22", "cpr23", |
| 657 | "cpr24", "cpr25", "cpr26", "cpr27", "cpr28", "cpr29", "cpr30", "cpr31", |
| 658 | "cpr32", "cpr33", "cpr34", "cpr35", "cpr36", "cpr37", "cpr38", "cpr39", |
| 659 | "cpr40", "cpr41", "cpr42", "cpr43", "cpr44", "cpr45", "cpr46", "cpr47", |
| 660 | "cpr48", "cpr49", "cpr50", "cpr51", "cpr52", "cpr53", "cpr54", "cpr55", |
| 661 | "cpr56", "cpr57", "cpr58", "cpr59", "cpr60", "cpr61", "cpr62", "cpr63", |
| 662 | NULL, |
| 663 | }; |
| 664 | |
| 665 | const char *csky_cp_creg[] = |
| 666 | { |
| 667 | "cpcr0", "cpcr1", "cpcr2", "cpcr3", |
| 668 | "cpcr4", "cpcr5", "cpcr6", "cpcr7", |
| 669 | "cpcr8", "cpcr9", "cpcr10", "cpcr11", |
| 670 | "cpcr12", "cpcr13", "cpcr14", "cpcr15", |
| 671 | "cpcr16", "cpcr17", "cpcr18", "cpcr19", |
| 672 | "cpcr20", "cpcr21", "cpcr22", "cpcr23", |
| 673 | "cpcr24", "cpcr25", "cpcr26", "cpcr27", |
| 674 | "cpcr28", "cpcr29", "cpcr30", "cpcr31", |
| 675 | "cpcr32", "cpcr33", "cpcr34", "cpcr35", |
| 676 | "cpcr36", "cpcr37", "cpcr38", "cpcr39", |
| 677 | "cpcr40", "cpcr41", "cpcr42", "cpcr43", |
| 678 | "cpcr44", "cpcr45", "cpcr46", "cpcr47", |
| 679 | "cpcr48", "cpcr49", "cpcr50", "cpcr51", |
| 680 | "cpcr52", "cpcr53", "cpcr54", "cpcr55", |
| 681 | "cpcr56", "cpcr57", "cpcr58", "cpcr59", |
| 682 | "cpcr60", "cpcr61", "cpcr62", "cpcr63", |
| 683 | NULL, |
| 684 | }; |
| 685 | |
| 686 | struct psrbit |
| 687 | { |
| 688 | int value; |
| 689 | int isa; |
| 690 | const char *name; |
| 691 | }; |
| 692 | const struct psrbit cskyv1_psr_bits[] = |
| 693 | { |
| 694 | {1, 0, "ie"}, |
| 695 | {2, 0, "fe"}, |
| 696 | {4, 0, "ee"}, |
| 697 | {8, 0, "af"}, |
| 698 | {0, 0, NULL}, |
| 699 | }; |
| 700 | const struct psrbit cskyv2_psr_bits[] = |
| 701 | { |
| 702 | {8, 0, "ee"}, |
| 703 | {4, 0, "ie"}, |
| 704 | {2, 0, "fe"}, |
| 705 | {1, 0, "af"}, |
| 706 | {0x10, CSKY_ISA_TRUST, "sie"}, |
| 707 | {0, 0, NULL}, |
| 708 | }; |
| 709 | |
| 710 | |
| 711 | /* C-SKY V1 opcodes. */ |
| 712 | const struct csky_opcode csky_v1_opcodes[] = |
| 713 | { |
| 714 | #define _TRANSFER 0 |
| 715 | #define _RELOC16 0 |
| 716 | #define _RELOC32 0 |
| 717 | #define _RELAX 0 |
| 718 | OP16 ("bkpt", |
| 719 | OPCODE_INFO0 (0x0000), |
| 720 | CSKYV1_ISA_E1), |
| 721 | OP16 ("sync", |
| 722 | OPCODE_INFO0 (0x0001), |
| 723 | CSKYV1_ISA_E1), |
| 724 | #undef _TRANSFER |
| 725 | #define _TRANSFER 2 |
| 726 | OP16 ("rfi", |
| 727 | OPCODE_INFO0 (0x0003), |
| 728 | CSKYV1_ISA_E1), |
| 729 | #undef _TRANSFER |
| 730 | #define _TRANSFER 0 |
| 731 | OP16 ("stop", |
| 732 | OPCODE_INFO0 (0x0004), |
| 733 | CSKYV1_ISA_E1), |
| 734 | OP16 ("wait", |
| 735 | OPCODE_INFO0 (0x0005), |
| 736 | CSKYV1_ISA_E1), |
| 737 | OP16 ("doze", |
| 738 | OPCODE_INFO0 (0x0006), |
| 739 | CSKYV1_ISA_E1), |
| 740 | OP16 ("idly4", |
| 741 | OPCODE_INFO0 (0x0007), |
| 742 | CSKYV1_ISA_E1), |
| 743 | OP16 ("trap", |
| 744 | OPCODE_INFO1 (0x0008, |
| 745 | (0_1, IMM2b, OPRND_SHIFT_0_BIT)), |
| 746 | CSKYV1_ISA_E1), |
| 747 | OP16 ("mvtc", |
| 748 | OPCODE_INFO0 (0x000c), |
| 749 | CSKY_ISA_DSP), |
| 750 | OP16 ("cprc", |
| 751 | OPCODE_INFO0 (0x000d), |
| 752 | CSKY_ISA_CP), |
| 753 | OP16 ("cpseti", |
| 754 | OPCODE_INFO1 (0x0010, |
| 755 | (0_3, CPIDX, OPRND_SHIFT_0_BIT)), |
| 756 | CSKY_ISA_CP), |
| 757 | OP16 ("mvc", |
| 758 | OPCODE_INFO1 (0x0020, |
| 759 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 760 | CSKYV1_ISA_E1), |
| 761 | OP16 ("mvcv", |
| 762 | OPCODE_INFO1 (0x0030, |
| 763 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 764 | CSKYV1_ISA_E1), |
| 765 | OP16 ("ldq", |
| 766 | OPCODE_INFO2 (0x0040, |
| 767 | (NONE, REGr4_r7, OPRND_SHIFT_0_BIT), |
| 768 | (0_3, REGnr4_r7, OPRND_SHIFT_0_BIT)), |
| 769 | CSKYV1_ISA_E1), |
| 770 | OP16 ("stq", |
| 771 | OPCODE_INFO2 (0x0050, |
| 772 | (NONE, REGr4_r7, OPRND_SHIFT_0_BIT), |
| 773 | (0_3, REGnr4_r7, OPRND_SHIFT_0_BIT)), |
| 774 | CSKYV1_ISA_E1), |
| 775 | OP16 ("ldm", |
| 776 | OPCODE_INFO2 (0x0060, |
| 777 | (0_3, REGLIST_DASH, OPRND_SHIFT_0_BIT), |
| 778 | (NONE, REGbsp, OPRND_SHIFT_0_BIT)), |
| 779 | CSKYV1_ISA_E1), |
| 780 | OP16 ("stm", |
| 781 | OPCODE_INFO2 (0x0070, |
| 782 | (0_3, REGLIST_DASH, OPRND_SHIFT_0_BIT), |
| 783 | (NONE, REGbsp, OPRND_SHIFT_0_BIT)), |
| 784 | CSKYV1_ISA_E1), |
| 785 | DOP16 ("dect", |
| 786 | OPCODE_INFO3 (0x0080, |
| 787 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 788 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), |
| 789 | (NONE, CONST1, OPRND_SHIFT_0_BIT)), |
| 790 | OPCODE_INFO1 (0x0080, |
| 791 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 792 | CSKYV1_ISA_E1), |
| 793 | DOP16 ("decf", |
| 794 | OPCODE_INFO3 (0x0090, |
| 795 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 796 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), |
| 797 | (NONE, CONST1, OPRND_SHIFT_0_BIT)), |
| 798 | OPCODE_INFO1 (0x0090, |
| 799 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 800 | CSKYV1_ISA_E1), |
| 801 | DOP16 ("inct", |
| 802 | OPCODE_INFO3 (0x00a0, |
| 803 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 804 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), |
| 805 | (NONE, CONST1, OPRND_SHIFT_0_BIT)), |
| 806 | OPCODE_INFO1 (0x00a0, |
| 807 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 808 | CSKYV1_ISA_E1), |
| 809 | DOP16 ("incf", |
| 810 | OPCODE_INFO3 (0x00b0, |
| 811 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 812 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), |
| 813 | (NONE, CONST1, OPRND_SHIFT_0_BIT)), |
| 814 | OPCODE_INFO1 (0x00b0, |
| 815 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 816 | CSKYV1_ISA_E1), |
| 817 | #undef _TRANSFER |
| 818 | #define _TRANSFER 2 |
| 819 | OP16 ("jmp", |
| 820 | OPCODE_INFO1 (0x00c0, |
| 821 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 822 | CSKYV1_ISA_E1), |
| 823 | #undef _TRANSFER |
| 824 | #define _TRANSFER 0 |
| 825 | OP16 ("jsr", |
| 826 | OPCODE_INFO1 (0x00d0, |
| 827 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 828 | CSKYV1_ISA_E1), |
| 829 | DOP16 ("ff1", |
| 830 | OPCODE_INFO2 (0x00e0, |
| 831 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 832 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT)), |
| 833 | OPCODE_INFO1 (0x00e0, |
| 834 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 835 | CSKYV1_ISA_E1), |
| 836 | DOP16 ("brev", |
| 837 | OPCODE_INFO2 (0x00f0, |
| 838 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 839 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT)), |
| 840 | OPCODE_INFO1 (0x00f0, |
| 841 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 842 | CSKYV1_ISA_E1), |
| 843 | DOP16 ("xtrb3", |
| 844 | OPCODE_INFO2 (0x0100, |
| 845 | (NONE, REG_r1a, OPRND_SHIFT_0_BIT), |
| 846 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 847 | OPCODE_INFO1 (0x0100, |
| 848 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 849 | CSKYV1_ISA_E1), |
| 850 | DOP16 ("xtrb2", |
| 851 | OPCODE_INFO2 (0x0110, |
| 852 | (NONE, REG_r1a, OPRND_SHIFT_0_BIT), |
| 853 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 854 | OPCODE_INFO1 (0x0110, |
| 855 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 856 | CSKYV1_ISA_E1), |
| 857 | DOP16 ("xtrb1", |
| 858 | OPCODE_INFO2 (0x0120, |
| 859 | (NONE, REG_r1a, OPRND_SHIFT_0_BIT), |
| 860 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 861 | OPCODE_INFO1 (0x0120, |
| 862 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 863 | CSKYV1_ISA_E1), |
| 864 | DOP16 ("xtrb0", |
| 865 | OPCODE_INFO2 (0x0130, |
| 866 | (NONE, REG_r1a, OPRND_SHIFT_0_BIT), |
| 867 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 868 | OPCODE_INFO1 (0x0130, |
| 869 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 870 | CSKYV1_ISA_E1), |
| 871 | DOP16 ("zextb", |
| 872 | OPCODE_INFO2 (0x0140, |
| 873 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 874 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT)), |
| 875 | OPCODE_INFO1 (0x0140, |
| 876 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 877 | CSKYV1_ISA_E1), |
| 878 | DOP16 ("sextb", |
| 879 | OPCODE_INFO2 (0x0150, |
| 880 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 881 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT)), |
| 882 | OPCODE_INFO1 (0x0150, |
| 883 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 884 | CSKYV1_ISA_E1), |
| 885 | DOP16 ("zexth", |
| 886 | OPCODE_INFO2 (0x0160, |
| 887 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 888 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT)), |
| 889 | OPCODE_INFO1 (0x0160, |
| 890 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 891 | CSKYV1_ISA_E1), |
| 892 | DOP16 ("sexth", |
| 893 | OPCODE_INFO2 (0x0170, |
| 894 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 895 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT)), |
| 896 | OPCODE_INFO1 (0x0170, |
| 897 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 898 | CSKYV1_ISA_E1), |
| 899 | DOP16 ("declt", |
| 900 | OPCODE_INFO3 (0x0180, |
| 901 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 902 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), |
| 903 | (NONE, CONST1, OPRND_SHIFT_0_BIT)), |
| 904 | OPCODE_INFO1 (0x0180, |
| 905 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 906 | CSKYV1_ISA_E1), |
| 907 | OP16 ("tstnbz", |
| 908 | OPCODE_INFO1 (0x0190, |
| 909 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 910 | CSKYV1_ISA_E1), |
| 911 | DOP16 ("decgt", |
| 912 | OPCODE_INFO3 (0x01a0, |
| 913 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 914 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), |
| 915 | (NONE, CONST1, OPRND_SHIFT_0_BIT)), |
| 916 | OPCODE_INFO1 (0x01a0, |
| 917 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 918 | CSKYV1_ISA_E1), |
| 919 | DOP16 ("decne", |
| 920 | OPCODE_INFO3 (0x01b0, |
| 921 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 922 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), |
| 923 | (NONE, CONST1, OPRND_SHIFT_0_BIT)), |
| 924 | OPCODE_INFO1 (0x01b0, |
| 925 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 926 | CSKYV1_ISA_E1), |
| 927 | OP16 ("clrt", |
| 928 | OPCODE_INFO1 (0x01c0, |
| 929 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 930 | CSKYV1_ISA_E1), |
| 931 | OP16 ("clrf", |
| 932 | OPCODE_INFO1 (0x01d0, |
| 933 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 934 | CSKYV1_ISA_E1), |
| 935 | DOP16 ("abs", |
| 936 | OPCODE_INFO2 (0x01e0, |
| 937 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 938 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT)), |
| 939 | OPCODE_INFO1 (0x01e0, |
| 940 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 941 | CSKYV1_ISA_E1), |
| 942 | DOP16 ("not", |
| 943 | OPCODE_INFO2 (0x01f0, |
| 944 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 945 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT)), |
| 946 | OPCODE_INFO1 (0x01f0, |
| 947 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 948 | CSKYV1_ISA_E1), |
| 949 | OP16 ("movt", |
| 950 | OPCODE_INFO2 (0x0200, |
| 951 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 952 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 953 | CSKYV1_ISA_E1), |
| 954 | DOP16 ("mult", |
| 955 | OPCODE_INFO3 (0x0300, |
| 956 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 957 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), |
| 958 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 959 | OPCODE_INFO2 (0x0300, |
| 960 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 961 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 962 | CSKYV1_ISA_E1), |
| 963 | OP16 ("mac", |
| 964 | OPCODE_INFO2 (0x0400, |
| 965 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 966 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 967 | CSKY_ISA_MAC), |
| 968 | DOP16 ("subu", |
| 969 | OPCODE_INFO3 (0x0500, |
| 970 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 971 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), |
| 972 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 973 | OPCODE_INFO2 (0x0500, |
| 974 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 975 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 976 | CSKYV1_ISA_E1), |
| 977 | DOP16 ("sub", |
| 978 | OPCODE_INFO3 (0x0500, |
| 979 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 980 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), |
| 981 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 982 | OPCODE_INFO2 (0x0500, |
| 983 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 984 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 985 | CSKYV1_ISA_E1), |
| 986 | DOP16 ("addc", |
| 987 | OPCODE_INFO3 (0x0600, |
| 988 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 989 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), |
| 990 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 991 | OPCODE_INFO2 (0x0600, |
| 992 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 993 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 994 | CSKYV1_ISA_E1), |
| 995 | DOP16 ("subc", |
| 996 | OPCODE_INFO3 (0x0700, |
| 997 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 998 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), |
| 999 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1000 | OPCODE_INFO2 (0x0700, |
| 1001 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1002 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1003 | CSKYV1_ISA_E1), |
| 1004 | OP16 ("cprgr", |
| 1005 | OPCODE_INFO2 (0x0800, |
| 1006 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1007 | (4_8, CPREG, OPRND_SHIFT_0_BIT)), |
| 1008 | CSKY_ISA_CP), |
| 1009 | OP16 ("movf", |
| 1010 | OPCODE_INFO2 (0x0a00, |
| 1011 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1012 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1013 | CSKYV1_ISA_E1), |
| 1014 | DOP16 ("lsr", |
| 1015 | OPCODE_INFO3 (0x0b00, |
| 1016 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1017 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), |
| 1018 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1019 | OPCODE_INFO2 (0x0b00, |
| 1020 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1021 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1022 | CSKYV1_ISA_E1), |
| 1023 | OP16 ("cmphs", |
| 1024 | OPCODE_INFO2 (0x0c00, |
| 1025 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1026 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1027 | CSKYV1_ISA_E1), |
| 1028 | OP16 ("cmplt", |
| 1029 | OPCODE_INFO2 (0x0d00, |
| 1030 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1031 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1032 | CSKYV1_ISA_E1), |
| 1033 | OP16 ("tst", |
| 1034 | OPCODE_INFO2 (0x0e00, |
| 1035 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1036 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1037 | CSKYV1_ISA_E1), |
| 1038 | OP16 ("cmpne", |
| 1039 | OPCODE_INFO2 (0x0f00, |
| 1040 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1041 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1042 | CSKYV1_ISA_E1), |
| 1043 | OP16 ("mfcr", |
| 1044 | OPCODE_INFO2 (0x1000, |
| 1045 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1046 | (4_8, CTRLREG, OPRND_SHIFT_0_BIT)), |
| 1047 | CSKYV1_ISA_E1), |
| 1048 | OP16 ("psrclr", |
| 1049 | OPCODE_INFO_LIST (0x11f0, |
| 1050 | (0_2, PSR_BITS_LIST, OPRND_SHIFT_0_BIT)), |
| 1051 | CSKYV1_ISA_E1), |
| 1052 | OP16 ("psrset", |
| 1053 | OPCODE_INFO_LIST (0x11f8, |
| 1054 | (0_2, PSR_BITS_LIST, OPRND_SHIFT_0_BIT)), |
| 1055 | CSKYV1_ISA_E1), |
| 1056 | OP16 ("mov", |
| 1057 | OPCODE_INFO2 (0x1200, |
| 1058 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1059 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1060 | CSKYV1_ISA_E1), |
| 1061 | OP16 ("bgenr", |
| 1062 | OPCODE_INFO2 (0x1300, |
| 1063 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1064 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1065 | CSKYV1_ISA_E1), |
| 1066 | DOP16 ("rsub", |
| 1067 | OPCODE_INFO3 (0x1400, |
| 1068 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1069 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), |
| 1070 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1071 | OPCODE_INFO2 (0x1400, |
| 1072 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1073 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1074 | CSKYV1_ISA_E1), |
| 1075 | DOP16 ("ixw", |
| 1076 | OPCODE_INFO3 (0x1500, |
| 1077 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1078 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), |
| 1079 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1080 | OPCODE_INFO2 (0x1500, |
| 1081 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1082 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1083 | CSKYV1_ISA_E1), |
| 1084 | DOP16 ("and", |
| 1085 | OPCODE_INFO3 (0x1600, |
| 1086 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1087 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), |
| 1088 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1089 | OPCODE_INFO2 (0x1600, |
| 1090 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1091 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1092 | CSKYV1_ISA_E1), |
| 1093 | DOP16 ("xor", |
| 1094 | OPCODE_INFO3 (0x1700, |
| 1095 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1096 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), |
| 1097 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1098 | OPCODE_INFO2 (0x1700, |
| 1099 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1100 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1101 | CSKYV1_ISA_E1), |
| 1102 | OP16 ("mtcr", |
| 1103 | OPCODE_INFO2 (0x1800, |
| 1104 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1105 | (4_8, CTRLREG, OPRND_SHIFT_0_BIT)), |
| 1106 | CSKYV1_ISA_E1), |
| 1107 | DOP16 ("asr", |
| 1108 | OPCODE_INFO3 (0x1a00, |
| 1109 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1110 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), |
| 1111 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1112 | OPCODE_INFO2 (0x1a00, |
| 1113 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1114 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1115 | CSKYV1_ISA_E1), |
| 1116 | DOP16 ("lsl", |
| 1117 | OPCODE_INFO3 (0x1b00, |
| 1118 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1119 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), |
| 1120 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1121 | OPCODE_INFO2 (0x1b00, |
| 1122 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1123 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1124 | CSKYV1_ISA_E1), |
| 1125 | DOP16 ("addu", |
| 1126 | OPCODE_INFO3 (0x1c00, |
| 1127 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1128 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), |
| 1129 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1130 | OPCODE_INFO2 (0x1c00, |
| 1131 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1132 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1133 | CSKYV1_ISA_E1), |
| 1134 | OP16 ("add", |
| 1135 | OPCODE_INFO2 (0x1c00, |
| 1136 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1137 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1138 | CSKYV1_ISA_E1), |
| 1139 | DOP16 ("ixh", |
| 1140 | OPCODE_INFO3 (0x1d00, |
| 1141 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1142 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), |
| 1143 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1144 | OPCODE_INFO2 (0x1d00, |
| 1145 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1146 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1147 | CSKYV1_ISA_E1), |
| 1148 | DOP16 ("or", |
| 1149 | OPCODE_INFO3 (0x1e00, |
| 1150 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1151 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), |
| 1152 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1153 | OPCODE_INFO2 (0x1e00, |
| 1154 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1155 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1156 | CSKYV1_ISA_E1), |
| 1157 | DOP16 ("andn", |
| 1158 | OPCODE_INFO3 (0x1f00, |
| 1159 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1160 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), |
| 1161 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1162 | OPCODE_INFO2 (0x1f00, |
| 1163 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1164 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1165 | CSKYV1_ISA_E1), |
| 1166 | DOP16 ("addi", |
| 1167 | OPCODE_INFO3 (0x2000, |
| 1168 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1169 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), |
| 1170 | (4_8, OIMM5b, OPRND_SHIFT_0_BIT)), |
| 1171 | OPCODE_INFO2 (0x2000, |
| 1172 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1173 | (4_8, OIMM5b, OPRND_SHIFT_0_BIT)), |
| 1174 | CSKYV1_ISA_E1), |
| 1175 | OP16 ("cmplti", |
| 1176 | OPCODE_INFO2 (0x2200, |
| 1177 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1178 | (4_8, OIMM5b, OPRND_SHIFT_0_BIT)), |
| 1179 | CSKYV1_ISA_E1), |
| 1180 | DOP16 ("subi", |
| 1181 | OPCODE_INFO3 (0x2400, |
| 1182 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1183 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), |
| 1184 | (4_8, OIMM5b, OPRND_SHIFT_0_BIT)), |
| 1185 | OPCODE_INFO2 (0x2400, |
| 1186 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1187 | (4_8, OIMM5b, OPRND_SHIFT_0_BIT)), |
| 1188 | CSKYV1_ISA_E1), |
| 1189 | OP16 ("cpwgr", |
| 1190 | OPCODE_INFO2 (0x2600, |
| 1191 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1192 | (4_8, CPREG, OPRND_SHIFT_0_BIT)), |
| 1193 | CSKY_ISA_CP), |
| 1194 | DOP16 ("rsubi", |
| 1195 | OPCODE_INFO3 (0x2800, |
| 1196 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1197 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), |
| 1198 | (4_8, IMM5b, OPRND_SHIFT_0_BIT)), |
| 1199 | OPCODE_INFO2 (0x2800, |
| 1200 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1201 | (4_8, IMM5b, OPRND_SHIFT_0_BIT)), |
| 1202 | CSKYV1_ISA_E1), |
| 1203 | OP16 ("cmpnei", |
| 1204 | OPCODE_INFO2 (0x2a00, |
| 1205 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1206 | (4_8, IMM5b, OPRND_SHIFT_0_BIT)), |
| 1207 | CSKYV1_ISA_E1), |
| 1208 | OP16 ("bmaski", |
| 1209 | OPCODE_INFO2 (0x2c00, |
| 1210 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1211 | (4_8, IMM5b_BMASKI, OPRND_SHIFT_0_BIT)), |
| 1212 | CSKYV1_ISA_E1), |
| 1213 | DOP16 ("divu", |
| 1214 | OPCODE_INFO3 (0x2c10, |
| 1215 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1216 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), |
| 1217 | (NONE, REG_r1b, OPRND_SHIFT_0_BIT)), |
| 1218 | OPCODE_INFO2 (0x2c10, |
| 1219 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1220 | (NONE, REG_r1b, OPRND_SHIFT_0_BIT)), |
| 1221 | CSKYV1_ISA_E1), |
| 1222 | OP16 ("mflos", |
| 1223 | OPCODE_INFO1 (0x2c20, |
| 1224 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1225 | CSKY_ISA_MAC_DSP), |
| 1226 | OP16 ("mfhis", |
| 1227 | OPCODE_INFO1 (0x2c30, |
| 1228 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1229 | CSKY_ISA_MAC_DSP), |
| 1230 | OP16 ("mtlo", |
| 1231 | OPCODE_INFO1 (0x2c40, |
| 1232 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1233 | CSKY_ISA_MAC_DSP), |
| 1234 | OP16 ("mthi", |
| 1235 | OPCODE_INFO1 (0x2c50, |
| 1236 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1237 | CSKY_ISA_MAC_DSP), |
| 1238 | OP16 ("mflo", |
| 1239 | OPCODE_INFO1 (0x2c60, |
| 1240 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1241 | CSKY_ISA_MAC_DSP), |
| 1242 | OP16 ("mfhi", |
| 1243 | OPCODE_INFO1 (0x2c70, |
| 1244 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1245 | CSKY_ISA_MAC_DSP), |
| 1246 | DOP16 ("andi", |
| 1247 | OPCODE_INFO3 (0x2e00, |
| 1248 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1249 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), |
| 1250 | (4_8, IMM5b, OPRND_SHIFT_0_BIT)), |
| 1251 | OPCODE_INFO2 (0x2e00, |
| 1252 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1253 | (4_8, IMM5b, OPRND_SHIFT_0_BIT)), |
| 1254 | CSKYV1_ISA_E1), |
| 1255 | DOP16 ("bclri", |
| 1256 | OPCODE_INFO3 (0x3000, |
| 1257 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1258 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), |
| 1259 | (4_8, IMM5b, OPRND_SHIFT_0_BIT)), |
| 1260 | OPCODE_INFO2 (0x3000, |
| 1261 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1262 | (4_8, IMM5b, OPRND_SHIFT_0_BIT)), |
| 1263 | CSKYV1_ISA_E1), |
| 1264 | OP16 ("bgeni", |
| 1265 | OPCODE_INFO2 (0x3200, |
| 1266 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1267 | (4_8, IMM5b_7_31, OPRND_SHIFT_0_BIT)), |
| 1268 | CSKYV1_ISA_E1), |
| 1269 | OP16 ("cpwir", |
| 1270 | OPCODE_INFO1 (0x3200, |
| 1271 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1272 | CSKY_ISA_CP), |
| 1273 | DOP16 ("divs", |
| 1274 | OPCODE_INFO3 (0x3210, |
| 1275 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1276 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), |
| 1277 | (NONE, REG_r1b, OPRND_SHIFT_0_BIT)), |
| 1278 | OPCODE_INFO2 (0x3210, |
| 1279 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1280 | (NONE, REG_r1b, OPRND_SHIFT_0_BIT)), |
| 1281 | CSKYV1_ISA_E1), |
| 1282 | OP16 ("cprsr", |
| 1283 | OPCODE_INFO1 (0x3220, |
| 1284 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1285 | CSKY_ISA_CP), |
| 1286 | OP16 ("cpwsr", |
| 1287 | OPCODE_INFO1 (0x3230, |
| 1288 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1289 | CSKY_ISA_CP), |
| 1290 | DOP16 ("bseti", |
| 1291 | OPCODE_INFO3 (0x3400, |
| 1292 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1293 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), |
| 1294 | (4_8, IMM5b, OPRND_SHIFT_0_BIT)), |
| 1295 | OPCODE_INFO2 (0x3400, |
| 1296 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1297 | (4_8, IMM5b, OPRND_SHIFT_0_BIT)), |
| 1298 | CSKYV1_ISA_E1), |
| 1299 | OP16 ("btsti", |
| 1300 | OPCODE_INFO2 (0x3600, |
| 1301 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1302 | (4_8, IMM5b, OPRND_SHIFT_0_BIT)), |
| 1303 | CSKYV1_ISA_E1), |
| 1304 | DOP16 ("rotli", |
| 1305 | OPCODE_INFO3 (0x3800, |
| 1306 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1307 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), |
| 1308 | (4_8, IMM5b_1_31, OPRND_SHIFT_0_BIT)), |
| 1309 | OPCODE_INFO2 (0x3800, |
| 1310 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1311 | (4_8, IMM5b_1_31, OPRND_SHIFT_0_BIT)), |
| 1312 | CSKYV1_ISA_E1), |
| 1313 | DOP16 ("xsr", |
| 1314 | OPCODE_INFO3 (0x3800, |
| 1315 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1316 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), |
| 1317 | (NONE, CONST1, OPRND_SHIFT_0_BIT)), |
| 1318 | OPCODE_INFO1 (0x3800, |
| 1319 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1320 | CSKYV1_ISA_E1), |
| 1321 | DOP16 ("asrc", |
| 1322 | OPCODE_INFO3 (0x3a00, |
| 1323 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1324 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), |
| 1325 | (NONE, CONST1, OPRND_SHIFT_0_BIT)), |
| 1326 | OPCODE_INFO1 (0x3a00, |
| 1327 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1328 | CSKYV1_ISA_E1), |
| 1329 | DOP16 ("asri", |
| 1330 | OPCODE_INFO3 (0x3a00, |
| 1331 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1332 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), |
| 1333 | (4_8, IMM5b_1_31, OPRND_SHIFT_0_BIT)), |
| 1334 | OPCODE_INFO2 (0x3a00, |
| 1335 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1336 | (4_8, IMM5b_1_31, OPRND_SHIFT_0_BIT)), |
| 1337 | CSKYV1_ISA_E1), |
| 1338 | DOP16 ("lslc", |
| 1339 | OPCODE_INFO3 (0x3c00, |
| 1340 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1341 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), |
| 1342 | (NONE, CONST1, OPRND_SHIFT_0_BIT)), |
| 1343 | OPCODE_INFO1 (0x3c00, |
| 1344 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1345 | CSKYV1_ISA_E1), |
| 1346 | DOP16 ("lsli", |
| 1347 | OPCODE_INFO3 (0x3c00, |
| 1348 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1349 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), |
| 1350 | (4_8, IMM5b_1_31, OPRND_SHIFT_0_BIT)), |
| 1351 | OPCODE_INFO2 (0x3c00, |
| 1352 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1353 | (4_8, IMM5b_1_31, OPRND_SHIFT_0_BIT)), |
| 1354 | CSKYV1_ISA_E1), |
| 1355 | DOP16 ("lsrc", |
| 1356 | OPCODE_INFO3 (0x3e00, |
| 1357 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1358 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), |
| 1359 | (NONE, CONST1, OPRND_SHIFT_0_BIT)), |
| 1360 | OPCODE_INFO1 (0x3e00, |
| 1361 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1362 | CSKYV1_ISA_E1), |
| 1363 | DOP16 ("lsri", |
| 1364 | OPCODE_INFO3 (0x3e00, |
| 1365 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1366 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), |
| 1367 | (4_8, IMM5b_1_31, OPRND_SHIFT_0_BIT)), |
| 1368 | OPCODE_INFO2 (0x3e00, |
| 1369 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1370 | (4_8, IMM5b_1_31, OPRND_SHIFT_0_BIT)), |
| 1371 | CSKYV1_ISA_E1), |
| 1372 | OP16 ("ldex", |
| 1373 | SOPCODE_INFO2 (0x4000, |
| 1374 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1375 | BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1376 | (4_7, IMM_LDST, OPRND_SHIFT_0_BIT))), |
| 1377 | CSKY_ISA_MP), |
| 1378 | OP16 ("ldex.w", |
| 1379 | SOPCODE_INFO2 (0x4000, |
| 1380 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1381 | BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1382 | (4_7, IMM_LDST, OPRND_SHIFT_0_BIT))), |
| 1383 | CSKY_ISA_MP), |
| 1384 | OP16 ("ldwex", |
| 1385 | SOPCODE_INFO2 (0x4000, |
| 1386 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1387 | BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1388 | (4_7, IMM_LDST, OPRND_SHIFT_0_BIT))), |
| 1389 | CSKY_ISA_MP), |
| 1390 | OP16 ("stex", |
| 1391 | SOPCODE_INFO2 (0x5000, |
| 1392 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1393 | BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1394 | (4_7, IMM_LDST, OPRND_SHIFT_0_BIT))), |
| 1395 | CSKY_ISA_MP), |
| 1396 | OP16 ("stex.w", |
| 1397 | SOPCODE_INFO2 (0x5000, |
| 1398 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1399 | BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1400 | (4_7, IMM_LDST, OPRND_SHIFT_0_BIT))), |
| 1401 | CSKY_ISA_MP), |
| 1402 | OP16 ("stwex", |
| 1403 | SOPCODE_INFO2 (0x5000, |
| 1404 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1405 | BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1406 | (4_7, IMM_LDST, OPRND_SHIFT_0_BIT))), |
| 1407 | CSKY_ISA_MP), |
| 1408 | OP16 ("omflip0", |
| 1409 | OPCODE_INFO2 (0x4000, |
| 1410 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1411 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1412 | CSKY_ISA_MAC), |
| 1413 | OP16 ("omflip1", |
| 1414 | OPCODE_INFO2 (0x4100, |
| 1415 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1416 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1417 | CSKY_ISA_MAC), |
| 1418 | OP16 ("omflip2", |
| 1419 | OPCODE_INFO2 (0x4200, |
| 1420 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1421 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1422 | CSKY_ISA_MAC), |
| 1423 | OP16 ("omflip3", |
| 1424 | OPCODE_INFO2 (0x4300, |
| 1425 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1426 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1427 | CSKY_ISA_MAC), |
| 1428 | OP16 ("muls", |
| 1429 | OPCODE_INFO2 (0x5000, |
| 1430 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1431 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1432 | CSKY_ISA_DSP), |
| 1433 | OP16 ("mulsa", |
| 1434 | OPCODE_INFO2 (0x5100, |
| 1435 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1436 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1437 | CSKY_ISA_DSP), |
| 1438 | OP16 ("mulss", |
| 1439 | OPCODE_INFO2 (0x5200, |
| 1440 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1441 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1442 | CSKY_ISA_DSP), |
| 1443 | OP16 ("mulu", |
| 1444 | OPCODE_INFO2 (0x5400, |
| 1445 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1446 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1447 | CSKY_ISA_DSP), |
| 1448 | OP16 ("mulua", |
| 1449 | OPCODE_INFO2 (0x5500, |
| 1450 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1451 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1452 | CSKY_ISA_DSP), |
| 1453 | OP16 ("mulus", |
| 1454 | OPCODE_INFO2 (0x5600, |
| 1455 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1456 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1457 | CSKY_ISA_DSP), |
| 1458 | OP16 ("vmulsh", |
| 1459 | OPCODE_INFO2 (0x5800, |
| 1460 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1461 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1462 | CSKY_ISA_DSP), |
| 1463 | OP16 ("vmulsha", |
| 1464 | OPCODE_INFO2 (0x5900, |
| 1465 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1466 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1467 | CSKY_ISA_DSP), |
| 1468 | OP16 ("vmulshs", |
| 1469 | OPCODE_INFO2 (0x5a00, |
| 1470 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1471 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1472 | CSKY_ISA_DSP), |
| 1473 | OP16 ("vmulsw", |
| 1474 | OPCODE_INFO2 (0x5c00, |
| 1475 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1476 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1477 | CSKY_ISA_DSP), |
| 1478 | OP16 ("vmulswa", |
| 1479 | OPCODE_INFO2 (0x5d00, |
| 1480 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1481 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1482 | CSKY_ISA_DSP), |
| 1483 | OP16 ("vmulsws", |
| 1484 | OPCODE_INFO2 (0x5e00, |
| 1485 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1486 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1487 | CSKY_ISA_DSP), |
| 1488 | OP16 ("movi", |
| 1489 | OPCODE_INFO2 (0x6000, |
| 1490 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1491 | (4_10, IMM7b, OPRND_SHIFT_0_BIT)), |
| 1492 | CSKYV1_ISA_E1), |
| 1493 | DOP16 ("mulsh", |
| 1494 | OPCODE_INFO3 (0x6800, |
| 1495 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1496 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), |
| 1497 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1498 | OPCODE_INFO2 (0x6800, |
| 1499 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1500 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1501 | CSKYV1_ISA_E1), |
| 1502 | DOP16 ("mulsh.h", |
| 1503 | OPCODE_INFO3 (0x6800, |
| 1504 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1505 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), |
| 1506 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1507 | OPCODE_INFO2 (0x6800, |
| 1508 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1509 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1510 | CSKYV1_ISA_E1), |
| 1511 | OP16 ("mulsha", |
| 1512 | OPCODE_INFO2 (0x6900, |
| 1513 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1514 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1515 | CSKY_ISA_DSP), |
| 1516 | OP16 ("mulshs", |
| 1517 | OPCODE_INFO2 (0x6a00, |
| 1518 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1519 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1520 | CSKY_ISA_DSP), |
| 1521 | OP16 ("cprcr", |
| 1522 | OPCODE_INFO2 (0x6b00, |
| 1523 | (0_2, GREG0_7, OPRND_SHIFT_0_BIT), |
| 1524 | (3_7, CPCREG, OPRND_SHIFT_0_BIT)), |
| 1525 | CSKY_ISA_CP), |
| 1526 | OP16 ("mulsw", |
| 1527 | OPCODE_INFO2 (0x6c00, |
| 1528 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1529 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1530 | CSKY_ISA_DSP), |
| 1531 | OP16 ("mulswa", |
| 1532 | OPCODE_INFO2 (0x6d00, |
| 1533 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1534 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1535 | CSKY_ISA_DSP), |
| 1536 | OP16 ("mulsws", |
| 1537 | OPCODE_INFO2 (0x6e00, |
| 1538 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1539 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1540 | CSKY_ISA_DSP), |
| 1541 | OP16 ("cpwcr", |
| 1542 | OPCODE_INFO2 (0x6f00, |
| 1543 | (0_2, GREG0_7, OPRND_SHIFT_0_BIT), |
| 1544 | (3_7, CPCREG, OPRND_SHIFT_0_BIT)), |
| 1545 | CSKY_ISA_CP), |
| 1546 | #undef _RELOC16 |
| 1547 | #define _RELOC16 BFD_RELOC_CKCORE_PCREL_IMM8BY4 |
| 1548 | #undef _TRANSFER |
| 1549 | #define _TRANSFER 1 |
| 1550 | OP16 ("jmpi", |
| 1551 | OPCODE_INFO1 (0x7000, |
| 1552 | (0_7, OFF8b, OPRND_SHIFT_2_BIT)), |
| 1553 | CSKYV1_ISA_E1), |
| 1554 | #undef _TRANSFER |
| 1555 | #define _TRANSFER 0 |
| 1556 | OP16 ("jsri", |
| 1557 | OPCODE_INFO1 (0x7f00, |
| 1558 | (0_7, OFF8b, OPRND_SHIFT_2_BIT)), |
| 1559 | CSKYV1_ISA_E1), |
| 1560 | OP16_WITH_WORK ("lrw", |
| 1561 | OPCODE_INFO2 (0x7000, |
| 1562 | (8_11, REGnsplr, OPRND_SHIFT_0_BIT), |
| 1563 | (0_7, CONSTANT, OPRND_SHIFT_2_BIT)), |
| 1564 | CSKYV1_ISA_E1, |
| 1565 | v1_work_lrw), |
| 1566 | #undef _RELOC16 |
| 1567 | #define _RELOC16 0 |
| 1568 | DOP16 ("ld.w", |
| 1569 | SOPCODE_INFO2 (0x8000, |
| 1570 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1571 | BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1572 | (4_7, IMM_LDST, OPRND_SHIFT_2_BIT))), |
| 1573 | OPCODE_INFO2 (0x8000, |
| 1574 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1575 | (0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), |
| 1576 | CSKYV1_ISA_E1), |
| 1577 | DOP16 ("ldw", |
| 1578 | SOPCODE_INFO2 (0x8000, |
| 1579 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1580 | BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1581 | (4_7, IMM_LDST, OPRND_SHIFT_2_BIT))), |
| 1582 | OPCODE_INFO2 (0x8000, |
| 1583 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1584 | (0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), |
| 1585 | CSKYV1_ISA_E1), |
| 1586 | DOP16 ("ld", |
| 1587 | SOPCODE_INFO2 (0x8000, |
| 1588 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1589 | BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1590 | (4_7, IMM_LDST, OPRND_SHIFT_2_BIT))), |
| 1591 | OPCODE_INFO2 (0x8000, |
| 1592 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1593 | (0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), |
| 1594 | CSKYV1_ISA_E1), |
| 1595 | DOP16 ("st.w", |
| 1596 | SOPCODE_INFO2 (0x9000, |
| 1597 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1598 | BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1599 | (4_7, IMM_LDST, OPRND_SHIFT_2_BIT))), |
| 1600 | OPCODE_INFO2 (0x9000, |
| 1601 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1602 | (0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), |
| 1603 | CSKYV1_ISA_E1), |
| 1604 | DOP16 ("stw", |
| 1605 | SOPCODE_INFO2 (0x9000, |
| 1606 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1607 | BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1608 | (4_7, IMM_LDST, OPRND_SHIFT_2_BIT))), |
| 1609 | OPCODE_INFO2 (0x9000, |
| 1610 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1611 | (0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), |
| 1612 | CSKYV1_ISA_E1), |
| 1613 | DOP16 ("st", |
| 1614 | SOPCODE_INFO2 (0x9000, |
| 1615 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1616 | BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1617 | (4_7, IMM_LDST, OPRND_SHIFT_2_BIT))), |
| 1618 | OPCODE_INFO2 (0x9000, |
| 1619 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1620 | (0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), |
| 1621 | CSKYV1_ISA_E1), |
| 1622 | DOP16 ("ld.b", |
| 1623 | SOPCODE_INFO2 (0xa000, |
| 1624 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1625 | BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1626 | (4_7, IMM_LDST, OPRND_SHIFT_0_BIT))), |
| 1627 | OPCODE_INFO2 (0xa000, |
| 1628 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1629 | (0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), |
| 1630 | CSKYV1_ISA_E1), |
| 1631 | DOP16 ("ldb", |
| 1632 | SOPCODE_INFO2 (0xa000, |
| 1633 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1634 | BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1635 | (4_7, IMM_LDST, OPRND_SHIFT_0_BIT))), |
| 1636 | OPCODE_INFO2 (0xa000, |
| 1637 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1638 | (0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), |
| 1639 | CSKYV1_ISA_E1), |
| 1640 | DOP16 ("st.b", |
| 1641 | SOPCODE_INFO2 (0xb000, |
| 1642 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1643 | BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1644 | (4_7, IMM_LDST, OPRND_SHIFT_0_BIT))), |
| 1645 | OPCODE_INFO2 (0xb000, |
| 1646 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1647 | (0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), |
| 1648 | CSKYV1_ISA_E1), |
| 1649 | DOP16 ("stb", |
| 1650 | SOPCODE_INFO2 (0xb000, |
| 1651 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1652 | BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1653 | (4_7, IMM_LDST, OPRND_SHIFT_0_BIT))), |
| 1654 | OPCODE_INFO2 (0xb000, |
| 1655 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1656 | (0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), |
| 1657 | CSKYV1_ISA_E1), |
| 1658 | DOP16 ("ld.h", |
| 1659 | SOPCODE_INFO2 (0xc000, |
| 1660 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1661 | BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1662 | (4_7, IMM_LDST, OPRND_SHIFT_1_BIT))), |
| 1663 | OPCODE_INFO2 (0xc000, |
| 1664 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1665 | (0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), |
| 1666 | CSKYV1_ISA_E1), |
| 1667 | DOP16 ("ldh", |
| 1668 | SOPCODE_INFO2 (0xc000, |
| 1669 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1670 | BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1671 | (4_7, IMM_LDST, OPRND_SHIFT_1_BIT))), |
| 1672 | OPCODE_INFO2 (0xc000, |
| 1673 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1674 | (0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), |
| 1675 | CSKYV1_ISA_E1), |
| 1676 | DOP16 ("st.h", |
| 1677 | SOPCODE_INFO2 (0xd000, |
| 1678 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1679 | BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1680 | (4_7, IMM_LDST, OPRND_SHIFT_1_BIT))), |
| 1681 | OPCODE_INFO2 (0xd000, |
| 1682 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1683 | (0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), |
| 1684 | CSKYV1_ISA_E1), |
| 1685 | DOP16 ("sth", |
| 1686 | SOPCODE_INFO2 (0xd000, |
| 1687 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1688 | BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1689 | (4_7, IMM_LDST, OPRND_SHIFT_1_BIT))), |
| 1690 | OPCODE_INFO2 (0xd000, |
| 1691 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1692 | (0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), |
| 1693 | CSKYV1_ISA_E1), |
| 1694 | |
| 1695 | #undef _RELOC16 |
| 1696 | #define _RELOC16 BFD_RELOC_CKCORE_PCREL_IMM11BY2 |
| 1697 | OP16 ("bt", |
| 1698 | OPCODE_INFO1 (0xe000, |
| 1699 | (0_10, OFF11b, OPRND_SHIFT_1_BIT)), |
| 1700 | CSKYV1_ISA_E1), |
| 1701 | OP16 ("bf", |
| 1702 | OPCODE_INFO1 (0xe800, |
| 1703 | (0_10, OFF11b, OPRND_SHIFT_1_BIT)), |
| 1704 | CSKYV1_ISA_E1), |
| 1705 | #undef _TRANSFER |
| 1706 | #define _TRANSFER 1 |
| 1707 | OP16 ("br", |
| 1708 | OPCODE_INFO1 (0xf000, |
| 1709 | (0_10, OFF11b, OPRND_SHIFT_1_BIT)), |
| 1710 | CSKYV1_ISA_E1), |
| 1711 | #undef _TRANSFER |
| 1712 | #define _TRANSFER 0 |
| 1713 | OP16 ("bsr", |
| 1714 | OPCODE_INFO1 (0xf800, |
| 1715 | (0_10, OFF11b, OPRND_SHIFT_1_BIT)), |
| 1716 | CSKYV1_ISA_E1), |
| 1717 | #undef _RELOC16 |
| 1718 | #define _RELOC16 0 |
| 1719 | |
| 1720 | #undef _RELAX |
| 1721 | #define _RELAX 1 |
| 1722 | OP16 ("jbt", |
| 1723 | OPCODE_INFO1 (0xe000, |
| 1724 | (0_10, JBTF, OPRND_SHIFT_0_BIT)), |
| 1725 | CSKYV1_ISA_E1), |
| 1726 | OP16 ("jbf", |
| 1727 | OPCODE_INFO1 (0xe800, |
| 1728 | (0_10, JBTF, OPRND_SHIFT_0_BIT)), |
| 1729 | CSKYV1_ISA_E1), |
| 1730 | #undef _TRANSFER |
| 1731 | #define _TRANSFER 1 |
| 1732 | OP16 ("jbr", |
| 1733 | OPCODE_INFO1 (0xf000, |
| 1734 | (0_10, JBR, OPRND_SHIFT_0_BIT)), |
| 1735 | CSKYV1_ISA_E1), |
| 1736 | #undef _TRANSFER |
| 1737 | #define _TRANSFER 0 |
| 1738 | #undef _RELAX |
| 1739 | #define _RELAX 0 |
| 1740 | |
| 1741 | OP16_WITH_WORK ("jbsr", |
| 1742 | OPCODE_INFO1 (0xf800, |
| 1743 | (0_10, JBSR, OPRND_SHIFT_0_BIT)), |
| 1744 | CSKYV1_ISA_E1, |
| 1745 | v1_work_jbsr), |
| 1746 | |
| 1747 | /* The following are aliases for other instructions. */ |
| 1748 | /* rts -> jmp r15. */ |
| 1749 | #undef _TRANSFER |
| 1750 | #define _TRANSFER 2 |
| 1751 | OP16 ("rts", |
| 1752 | OPCODE_INFO0 (0x00CF), |
| 1753 | CSKYV1_ISA_E1), |
| 1754 | OP16 ("rte", |
| 1755 | OPCODE_INFO0 (0x0002), |
| 1756 | CSKYV1_ISA_E1), |
| 1757 | OP16 ("rfe", |
| 1758 | OPCODE_INFO0 (0x0002), |
| 1759 | CSKYV1_ISA_E1), |
| 1760 | #undef _TRANSFER |
| 1761 | #define _TRANSFER 0 |
| 1762 | |
| 1763 | /* cmphs r0,r0 */ |
| 1764 | OP16 ("setc", |
| 1765 | OPCODE_INFO0 (0x0c00), |
| 1766 | CSKYV1_ISA_E1), |
| 1767 | /* cmpne r0,r0 */ |
| 1768 | OP16 ("clrc", |
| 1769 | OPCODE_INFO0 (0x0f00), |
| 1770 | CSKYV1_ISA_E1), |
| 1771 | /* cmplti rd,1 */ |
| 1772 | OP16 ("tstle", |
| 1773 | OPCODE_INFO1 (0x2200, |
| 1774 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1775 | CSKYV1_ISA_E1), |
| 1776 | /* cmplei rd,X -> cmplti rd,X+1 */ |
| 1777 | OP16 ("cmplei", |
| 1778 | OPCODE_INFO2 (0x2200, |
| 1779 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1780 | (4_8, IMM5b, OPRND_SHIFT_0_BIT)), |
| 1781 | CSKYV1_ISA_E1), |
| 1782 | /* rsubi rd,0 */ |
| 1783 | OP16 ("neg", |
| 1784 | OPCODE_INFO1 (0x2800, |
| 1785 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1786 | CSKYV1_ISA_E1), |
| 1787 | /* cmpnei rd,0. */ |
| 1788 | OP16 ("tstne", |
| 1789 | OPCODE_INFO1 (0x2a00, |
| 1790 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1791 | CSKYV1_ISA_E1), |
| 1792 | /* btsti rx,31. */ |
| 1793 | OP16 ("tstlt", |
| 1794 | OPCODE_INFO1 (0x37f0, |
| 1795 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1796 | CSKYV1_ISA_E1), |
| 1797 | /* bclri rx,log2(imm). */ |
| 1798 | OP16 ("mclri", |
| 1799 | OPCODE_INFO2 (0x3000, |
| 1800 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1801 | (4_8, IMM5b_POWER, OPRND_SHIFT_0_BIT)), |
| 1802 | CSKYV1_ISA_E1), |
| 1803 | /* bgeni rx,log2(imm). */ |
| 1804 | OP16 ("mgeni", |
| 1805 | OPCODE_INFO2 (0x3200, |
| 1806 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1807 | (4_8, IMM5b_7_31_POWER, OPRND_SHIFT_0_BIT)), |
| 1808 | CSKYV1_ISA_E1), |
| 1809 | /* bseti rx,log2(imm). */ |
| 1810 | OP16 ("mseti", |
| 1811 | OPCODE_INFO2 (0x3400, |
| 1812 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1813 | (4_8, IMM5b_POWER, OPRND_SHIFT_0_BIT)), |
| 1814 | CSKYV1_ISA_E1), |
| 1815 | /* btsti rx,log2(imm). */ |
| 1816 | OP16 ("mtsti", |
| 1817 | OPCODE_INFO2 (0x3600, |
| 1818 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1819 | (4_8, IMM5b_POWER, OPRND_SHIFT_0_BIT)), |
| 1820 | CSKYV1_ISA_E1), |
| 1821 | OP16 ("rori", |
| 1822 | OPCODE_INFO2 (0x3800, |
| 1823 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1824 | (4_8, IMM5b_RORI, OPRND_SHIFT_0_BIT)), |
| 1825 | CSKYV1_ISA_E1), |
| 1826 | OP16 ("rotri", |
| 1827 | OPCODE_INFO2 (0x3800, |
| 1828 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), |
| 1829 | (4_8, IMM5b_RORI, OPRND_SHIFT_0_BIT)), |
| 1830 | CSKYV1_ISA_E1), |
| 1831 | /* mov r0, r0. */ |
| 1832 | OP16 ("nop", |
| 1833 | OPCODE_INFO0 (0x1200), |
| 1834 | CSKYV1_ISA_E1), |
| 1835 | |
| 1836 | /* Float instruction with work. */ |
| 1837 | OP16_WITH_WORK ("fabss", |
| 1838 | OPCODE_INFO3 (0xffe04400, |
| 1839 | (5_9, FREG, OPRND_SHIFT_0_BIT), |
| 1840 | (0_4, FREG, OPRND_SHIFT_0_BIT), |
| 1841 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1842 | CSKY_ISA_FLOAT_E1, |
| 1843 | v1_work_fpu_fo), |
| 1844 | OP16_WITH_WORK ("fnegs", |
| 1845 | OPCODE_INFO3 (0xffe04c00, |
| 1846 | (5_9, FREG, OPRND_SHIFT_0_BIT), |
| 1847 | (0_4, FREG, OPRND_SHIFT_0_BIT), |
| 1848 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1849 | CSKY_ISA_FLOAT_E1, |
| 1850 | v1_work_fpu_fo), |
| 1851 | OP16_WITH_WORK ("fsqrts", |
| 1852 | OPCODE_INFO3 (0xffe05400, |
| 1853 | (5_9, FREG, OPRND_SHIFT_0_BIT), |
| 1854 | (0_4, FREG, OPRND_SHIFT_0_BIT), |
| 1855 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1856 | CSKY_ISA_FLOAT_E1, |
| 1857 | v1_work_fpu_fo), |
| 1858 | OP16_WITH_WORK ("frecips", |
| 1859 | OPCODE_INFO3 (0xffe05c00, |
| 1860 | (5_9, FREG, OPRND_SHIFT_0_BIT), |
| 1861 | (0_4, FREG, OPRND_SHIFT_0_BIT), |
| 1862 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1863 | CSKY_ISA_FLOAT_E1, |
| 1864 | v1_work_fpu_fo), |
| 1865 | OP16_WITH_WORK ("fadds", |
| 1866 | OPCODE_INFO4 (0xffe38000, |
| 1867 | (5_9, FREG, OPRND_SHIFT_0_BIT), |
| 1868 | (0_4, FREG, OPRND_SHIFT_0_BIT), |
| 1869 | (10_14, FREG, OPRND_SHIFT_0_BIT), |
| 1870 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1871 | CSKY_ISA_FLOAT_E1, |
| 1872 | v1_work_fpu_fo), |
| 1873 | OP16_WITH_WORK ("fsubs", |
| 1874 | OPCODE_INFO4 (0xffe48000, |
| 1875 | (5_9, FREG, OPRND_SHIFT_0_BIT), |
| 1876 | (0_4, FREG, OPRND_SHIFT_0_BIT), |
| 1877 | (10_14, FREG, OPRND_SHIFT_0_BIT), |
| 1878 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1879 | CSKY_ISA_FLOAT_E1, v1_work_fpu_fo), |
| 1880 | OP16_WITH_WORK ("fmacs", |
| 1881 | OPCODE_INFO4 (0xffe58000, |
| 1882 | (5_9, FREG, OPRND_SHIFT_0_BIT), |
| 1883 | (0_4, FREG, OPRND_SHIFT_0_BIT), |
| 1884 | (10_14, FREG, OPRND_SHIFT_0_BIT), |
| 1885 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1886 | CSKY_ISA_FLOAT_E1, |
| 1887 | v1_work_fpu_fo), |
| 1888 | OP16_WITH_WORK ("fmscs", |
| 1889 | OPCODE_INFO4 (0xffe68000, |
| 1890 | (5_9, FREG, OPRND_SHIFT_0_BIT), |
| 1891 | (0_4, FREG, OPRND_SHIFT_0_BIT), |
| 1892 | (10_14, FREG, OPRND_SHIFT_0_BIT), |
| 1893 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1894 | CSKY_ISA_FLOAT_E1, |
| 1895 | v1_work_fpu_fo), |
| 1896 | OP16_WITH_WORK ("fmuls", |
| 1897 | OPCODE_INFO4 (0xffe78000, |
| 1898 | (5_9, FREG, OPRND_SHIFT_0_BIT), |
| 1899 | (0_4, FREG, OPRND_SHIFT_0_BIT), |
| 1900 | (10_14, FREG, OPRND_SHIFT_0_BIT), |
| 1901 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1902 | CSKY_ISA_FLOAT_E1, |
| 1903 | v1_work_fpu_fo), |
| 1904 | OP16_WITH_WORK ("fdivs", |
| 1905 | OPCODE_INFO4 (0xffe88000, |
| 1906 | (5_9, FREG, OPRND_SHIFT_0_BIT), |
| 1907 | (0_4, FREG, OPRND_SHIFT_0_BIT), |
| 1908 | (10_14, FREG, OPRND_SHIFT_0_BIT), |
| 1909 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1910 | CSKY_ISA_FLOAT_E1, |
| 1911 | v1_work_fpu_fo), |
| 1912 | OP16_WITH_WORK ("fnmacs", |
| 1913 | OPCODE_INFO4 (0xffe98000, |
| 1914 | (5_9, FREG, OPRND_SHIFT_0_BIT), |
| 1915 | (0_4, FREG, OPRND_SHIFT_0_BIT), |
| 1916 | (10_14, FREG, OPRND_SHIFT_0_BIT), |
| 1917 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1918 | CSKY_ISA_FLOAT_E1, |
| 1919 | v1_work_fpu_fo), |
| 1920 | OP16_WITH_WORK ("fnmscs", |
| 1921 | OPCODE_INFO4 (0xffea8000, |
| 1922 | (5_9, FREG, OPRND_SHIFT_0_BIT), |
| 1923 | (0_4, FREG, OPRND_SHIFT_0_BIT), |
| 1924 | (10_14, FREG, OPRND_SHIFT_0_BIT), |
| 1925 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1926 | CSKY_ISA_FLOAT_E1, |
| 1927 | v1_work_fpu_fo), |
| 1928 | OP16_WITH_WORK ("fnmuls", |
| 1929 | OPCODE_INFO4 (0xffeb8000, |
| 1930 | (5_9, FREG, OPRND_SHIFT_0_BIT), |
| 1931 | (0_4, FREG, OPRND_SHIFT_0_BIT), |
| 1932 | (10_14, FREG, OPRND_SHIFT_0_BIT), |
| 1933 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1934 | CSKY_ISA_FLOAT_E1, |
| 1935 | v1_work_fpu_fo), |
| 1936 | OP16_WITH_WORK ("fabsd", |
| 1937 | OPCODE_INFO3 (0xffe04000, |
| 1938 | (5_9, FEREG, OPRND_SHIFT_0_BIT), |
| 1939 | (0_4, FEREG, OPRND_SHIFT_0_BIT), |
| 1940 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1941 | CSKY_ISA_FLOAT_E1, |
| 1942 | v1_work_fpu_fo), |
| 1943 | OP16_WITH_WORK ("fnegd", |
| 1944 | OPCODE_INFO3 (0xffe04800, |
| 1945 | (5_9, FEREG, OPRND_SHIFT_0_BIT), |
| 1946 | (0_4, FEREG, OPRND_SHIFT_0_BIT), |
| 1947 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1948 | CSKY_ISA_FLOAT_E1, |
| 1949 | v1_work_fpu_fo), |
| 1950 | OP16_WITH_WORK ("fsqrtd", |
| 1951 | OPCODE_INFO3 (0xffe05000, |
| 1952 | (5_9, FEREG, OPRND_SHIFT_0_BIT), |
| 1953 | (0_4, FEREG, OPRND_SHIFT_0_BIT), |
| 1954 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1955 | CSKY_ISA_FLOAT_E1, |
| 1956 | v1_work_fpu_fo), |
| 1957 | OP16_WITH_WORK ("frecipd", |
| 1958 | OPCODE_INFO3 (0xffe05800, |
| 1959 | (5_9, FEREG, OPRND_SHIFT_0_BIT), |
| 1960 | (0_4, FEREG, OPRND_SHIFT_0_BIT), |
| 1961 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1962 | CSKY_ISA_FLOAT_E1, |
| 1963 | v1_work_fpu_fo), |
| 1964 | OP16_WITH_WORK ("faddd", |
| 1965 | OPCODE_INFO4 (0xffe30000, |
| 1966 | (5_9, FEREG, OPRND_SHIFT_0_BIT), |
| 1967 | (0_4, FEREG, OPRND_SHIFT_0_BIT), |
| 1968 | (10_14, FEREG, OPRND_SHIFT_0_BIT), |
| 1969 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1970 | CSKY_ISA_FLOAT_E1, |
| 1971 | v1_work_fpu_fo), |
| 1972 | OP16_WITH_WORK ("fsubd", |
| 1973 | OPCODE_INFO4 (0xffe40000, |
| 1974 | (5_9, FEREG, OPRND_SHIFT_0_BIT), |
| 1975 | (0_4, FEREG, OPRND_SHIFT_0_BIT), |
| 1976 | (10_14, FEREG, OPRND_SHIFT_0_BIT), |
| 1977 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1978 | CSKY_ISA_FLOAT_E1, |
| 1979 | v1_work_fpu_fo), |
| 1980 | OP16_WITH_WORK ("fmacd", |
| 1981 | OPCODE_INFO4 (0xffe50000, |
| 1982 | (5_9, FEREG, OPRND_SHIFT_0_BIT), |
| 1983 | (0_4, FEREG, OPRND_SHIFT_0_BIT), |
| 1984 | (10_14, FEREG, OPRND_SHIFT_0_BIT), |
| 1985 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1986 | CSKY_ISA_FLOAT_E1, |
| 1987 | v1_work_fpu_fo), |
| 1988 | OP16_WITH_WORK ("fmscd", |
| 1989 | OPCODE_INFO4 (0xffe60000, |
| 1990 | (5_9, FEREG, OPRND_SHIFT_0_BIT), |
| 1991 | (0_4, FEREG, OPRND_SHIFT_0_BIT), |
| 1992 | (10_14, FEREG, OPRND_SHIFT_0_BIT), |
| 1993 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 1994 | CSKY_ISA_FLOAT_E1, |
| 1995 | v1_work_fpu_fo), |
| 1996 | OP16_WITH_WORK ("fmuld", |
| 1997 | OPCODE_INFO4 (0xffe70000, |
| 1998 | (5_9, FEREG, OPRND_SHIFT_0_BIT), |
| 1999 | (0_4, FEREG, OPRND_SHIFT_0_BIT), |
| 2000 | (10_14, FEREG, OPRND_SHIFT_0_BIT), |
| 2001 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 2002 | CSKY_ISA_FLOAT_E1, |
| 2003 | v1_work_fpu_fo), |
| 2004 | OP16_WITH_WORK ("fdivd", |
| 2005 | OPCODE_INFO4 (0xffe80000, |
| 2006 | (5_9, FEREG, OPRND_SHIFT_0_BIT), |
| 2007 | (0_4, FEREG, OPRND_SHIFT_0_BIT), |
| 2008 | (10_14, FEREG, OPRND_SHIFT_0_BIT), |
| 2009 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 2010 | CSKY_ISA_FLOAT_E1, |
| 2011 | v1_work_fpu_fo), |
| 2012 | OP16_WITH_WORK ("fnmacd", |
| 2013 | OPCODE_INFO4 (0xffe90000, |
| 2014 | (5_9, FEREG, OPRND_SHIFT_0_BIT), |
| 2015 | (0_4, FEREG, OPRND_SHIFT_0_BIT), |
| 2016 | (10_14, FEREG, OPRND_SHIFT_0_BIT), |
| 2017 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 2018 | CSKY_ISA_FLOAT_E1, |
| 2019 | v1_work_fpu_fo), |
| 2020 | OP16_WITH_WORK ("fnmscd", |
| 2021 | OPCODE_INFO4 (0xffea0000, |
| 2022 | (5_9, FEREG, OPRND_SHIFT_0_BIT), |
| 2023 | (0_4, FEREG, OPRND_SHIFT_0_BIT), |
| 2024 | (10_14, FEREG, OPRND_SHIFT_0_BIT), |
| 2025 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 2026 | CSKY_ISA_FLOAT_E1, |
| 2027 | v1_work_fpu_fo), |
| 2028 | OP16_WITH_WORK ("fnmuld", |
| 2029 | OPCODE_INFO4 (0xffeb0000, |
| 2030 | (5_9, FEREG, OPRND_SHIFT_0_BIT), |
| 2031 | (0_4, FEREG, OPRND_SHIFT_0_BIT), |
| 2032 | (10_14, FEREG, OPRND_SHIFT_0_BIT), |
| 2033 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 2034 | CSKY_ISA_FLOAT_E1, |
| 2035 | v1_work_fpu_fo), |
| 2036 | OP16_WITH_WORK ("fabsm", |
| 2037 | OPCODE_INFO3 (0xffe06000, |
| 2038 | (5_9, FEREG, OPRND_SHIFT_0_BIT), |
| 2039 | (0_4, FEREG, OPRND_SHIFT_0_BIT), |
| 2040 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 2041 | CSKY_ISA_FLOAT_E1, |
| 2042 | v1_work_fpu_fo), |
| 2043 | OP16_WITH_WORK ("fnegm", |
| 2044 | OPCODE_INFO3 (0xffe06400, |
| 2045 | (5_9, FEREG, OPRND_SHIFT_0_BIT), |
| 2046 | (0_4, FEREG, OPRND_SHIFT_0_BIT), |
| 2047 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 2048 | CSKY_ISA_FLOAT_E1, |
| 2049 | v1_work_fpu_fo), |
| 2050 | OP16_WITH_WORK ("faddm", |
| 2051 | OPCODE_INFO4 (0xffec0000, |
| 2052 | (5_9, FEREG, OPRND_SHIFT_0_BIT), |
| 2053 | (0_4, FEREG, OPRND_SHIFT_0_BIT), |
| 2054 | (10_14, FEREG, OPRND_SHIFT_0_BIT), |
| 2055 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 2056 | CSKY_ISA_FLOAT_E1, |
| 2057 | v1_work_fpu_fo), |
| 2058 | OP16_WITH_WORK ("fsubm", |
| 2059 | OPCODE_INFO4 (0xffec8000, |
| 2060 | (5_9, FEREG, OPRND_SHIFT_0_BIT), |
| 2061 | (0_4, FEREG, OPRND_SHIFT_0_BIT), |
| 2062 | (10_14, FEREG, OPRND_SHIFT_0_BIT), |
| 2063 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 2064 | CSKY_ISA_FLOAT_E1, |
| 2065 | v1_work_fpu_fo), |
| 2066 | OP16_WITH_WORK ("fmacm", |
| 2067 | OPCODE_INFO4 (0xffed8000, |
| 2068 | (5_9, FEREG, OPRND_SHIFT_0_BIT), |
| 2069 | (0_4, FEREG, OPRND_SHIFT_0_BIT), |
| 2070 | (10_14, FEREG, OPRND_SHIFT_0_BIT), |
| 2071 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 2072 | CSKY_ISA_FLOAT_E1, |
| 2073 | v1_work_fpu_fo), |
| 2074 | OP16_WITH_WORK ("fmscm", |
| 2075 | OPCODE_INFO4 (0xffee0000, |
| 2076 | (5_9, FEREG, OPRND_SHIFT_0_BIT), |
| 2077 | (0_4, FEREG, OPRND_SHIFT_0_BIT), |
| 2078 | (10_14, FEREG, OPRND_SHIFT_0_BIT), |
| 2079 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 2080 | CSKY_ISA_FLOAT_E1, |
| 2081 | v1_work_fpu_fo), |
| 2082 | OP16_WITH_WORK ("fmulm", |
| 2083 | OPCODE_INFO4 (0xffed0000, |
| 2084 | (5_9, FEREG, OPRND_SHIFT_0_BIT), |
| 2085 | (0_4, FEREG, OPRND_SHIFT_0_BIT), |
| 2086 | (10_14, FEREG, OPRND_SHIFT_0_BIT), |
| 2087 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 2088 | CSKY_ISA_FLOAT_E1, |
| 2089 | v1_work_fpu_fo), |
| 2090 | OP16_WITH_WORK ("fnmacm", |
| 2091 | OPCODE_INFO4 (0xffee8000, |
| 2092 | (5_9, FEREG, OPRND_SHIFT_0_BIT), |
| 2093 | (0_4, FEREG, OPRND_SHIFT_0_BIT), |
| 2094 | (10_14, FEREG, OPRND_SHIFT_0_BIT), |
| 2095 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 2096 | CSKY_ISA_FLOAT_E1, |
| 2097 | v1_work_fpu_fo), |
| 2098 | OP16_WITH_WORK ("fnmscm", |
| 2099 | OPCODE_INFO4 (0xffef0000, |
| 2100 | (5_9, FEREG, OPRND_SHIFT_0_BIT), |
| 2101 | (0_4, FEREG, OPRND_SHIFT_0_BIT), |
| 2102 | (10_14, FEREG, OPRND_SHIFT_0_BIT), |
| 2103 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 2104 | CSKY_ISA_FLOAT_E1, |
| 2105 | v1_work_fpu_fo), |
| 2106 | OP16_WITH_WORK ("fnmulm", |
| 2107 | OPCODE_INFO4 (0xffef8000, |
| 2108 | (5_9, FEREG, OPRND_SHIFT_0_BIT), |
| 2109 | (0_4, FEREG, OPRND_SHIFT_0_BIT), |
| 2110 | (10_14, FEREG, OPRND_SHIFT_0_BIT), |
| 2111 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 2112 | CSKY_ISA_FLOAT_E1, |
| 2113 | v1_work_fpu_fo), |
| 2114 | OP16_WITH_WORK ("fcmphsd", |
| 2115 | OPCODE_INFO3 (0xffe00800, |
| 2116 | (0_4, FEREG, OPRND_SHIFT_0_BIT), |
| 2117 | (5_9, FEREG, OPRND_SHIFT_0_BIT), |
| 2118 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 2119 | CSKY_ISA_FLOAT_E1, |
| 2120 | v1_work_fpu_fo_fc), |
| 2121 | OP16_WITH_WORK ("fcmpltd", |
| 2122 | OPCODE_INFO3 (0xffe00c00, |
| 2123 | (0_4, FEREG, OPRND_SHIFT_0_BIT), |
| 2124 | (5_9, FEREG, OPRND_SHIFT_0_BIT), |
| 2125 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 2126 | CSKY_ISA_FLOAT_E1, |
| 2127 | v1_work_fpu_fo_fc), |
| 2128 | OP16_WITH_WORK ("fcmpned", |
| 2129 | OPCODE_INFO3 (0xffe01000, |
| 2130 | (0_4, FEREG, OPRND_SHIFT_0_BIT), |
| 2131 | (5_9, FEREG, OPRND_SHIFT_0_BIT), |
| 2132 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 2133 | CSKY_ISA_FLOAT_E1, |
| 2134 | v1_work_fpu_fo_fc), |
| 2135 | OP16_WITH_WORK ("fcmpuod", |
| 2136 | OPCODE_INFO3 (0xffe01400, |
| 2137 | (0_4, FEREG, OPRND_SHIFT_0_BIT), |
| 2138 | (5_9, FEREG, OPRND_SHIFT_0_BIT), |
| 2139 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 2140 | CSKY_ISA_FLOAT_E1, |
| 2141 | v1_work_fpu_fo_fc), |
| 2142 | OP16_WITH_WORK ("fcmphss", |
| 2143 | OPCODE_INFO3 (0xffe01800, |
| 2144 | (0_4, FREG, OPRND_SHIFT_0_BIT), |
| 2145 | (5_9, FREG, OPRND_SHIFT_0_BIT), |
| 2146 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 2147 | CSKY_ISA_FLOAT_E1, |
| 2148 | v1_work_fpu_fo_fc), |
| 2149 | OP16_WITH_WORK ("fcmplts", |
| 2150 | OPCODE_INFO3 (0xffe01c00, |
| 2151 | (0_4, FREG, OPRND_SHIFT_0_BIT), |
| 2152 | (5_9, FREG, OPRND_SHIFT_0_BIT), |
| 2153 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 2154 | CSKY_ISA_FLOAT_E1, |
| 2155 | v1_work_fpu_fo_fc), |
| 2156 | OP16_WITH_WORK ("fcmpnes", |
| 2157 | OPCODE_INFO3 (0xffe02000, |
| 2158 | (0_4, FREG, OPRND_SHIFT_0_BIT), |
| 2159 | (5_9, FREG, OPRND_SHIFT_0_BIT), |
| 2160 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 2161 | CSKY_ISA_FLOAT_E1, |
| 2162 | v1_work_fpu_fo_fc), |
| 2163 | OP16_WITH_WORK ("fcmpuos", |
| 2164 | OPCODE_INFO3 (0xffe02400, |
| 2165 | (0_4, FREG, OPRND_SHIFT_0_BIT), |
| 2166 | (5_9, FREG, OPRND_SHIFT_0_BIT), |
| 2167 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 2168 | CSKY_ISA_FLOAT_E1, |
| 2169 | v1_work_fpu_fo_fc), |
| 2170 | OP16_WITH_WORK ("fcmpzhsd", |
| 2171 | OPCODE_INFO2 (0xffe00400, |
| 2172 | (0_4, FEREG, OPRND_SHIFT_0_BIT), |
| 2173 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 2174 | CSKY_ISA_FLOAT_E1, |
| 2175 | v1_work_fpu_fo_fc), |
| 2176 | OP16_WITH_WORK ("fcmpzltd", |
| 2177 | OPCODE_INFO2 (0xffe00480, |
| 2178 | (0_4, FEREG, OPRND_SHIFT_0_BIT), |
| 2179 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 2180 | CSKY_ISA_FLOAT_E1, |
| 2181 | v1_work_fpu_fo_fc), |
| 2182 | OP16_WITH_WORK ("fcmpzned", |
| 2183 | OPCODE_INFO2 (0xffe00500, |
| 2184 | (0_4, FEREG, OPRND_SHIFT_0_BIT), |
| 2185 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 2186 | CSKY_ISA_FLOAT_E1, |
| 2187 | v1_work_fpu_fo_fc), |
| 2188 | OP16_WITH_WORK ("fcmpzuod", |
| 2189 | OPCODE_INFO2 (0xffe00580, |
| 2190 | (0_4, FEREG, OPRND_SHIFT_0_BIT), |
| 2191 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 2192 | CSKY_ISA_FLOAT_E1, |
| 2193 | v1_work_fpu_fo_fc), |
| 2194 | OP16_WITH_WORK ("fcmpzhss", |
| 2195 | OPCODE_INFO2 (0xffe00600, |
| 2196 | (0_4, FREG, OPRND_SHIFT_0_BIT), |
| 2197 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 2198 | CSKY_ISA_FLOAT_E1, |
| 2199 | v1_work_fpu_fo_fc), |
| 2200 | OP16_WITH_WORK ("fcmpzlts", |
| 2201 | OPCODE_INFO2 (0xffe00680, |
| 2202 | (0_4, FREG, OPRND_SHIFT_0_BIT), |
| 2203 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 2204 | CSKY_ISA_FLOAT_E1, |
| 2205 | v1_work_fpu_fo_fc), |
| 2206 | OP16_WITH_WORK ("fcmpznes", |
| 2207 | OPCODE_INFO2 (0xffe00700, |
| 2208 | (0_4, FREG, OPRND_SHIFT_0_BIT), |
| 2209 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 2210 | CSKY_ISA_FLOAT_E1, |
| 2211 | v1_work_fpu_fo_fc), |
| 2212 | OP16_WITH_WORK ("fcmpzuos", |
| 2213 | OPCODE_INFO2 (0xffe00780, |
| 2214 | (0_4, FREG, OPRND_SHIFT_0_BIT), |
| 2215 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 2216 | CSKY_ISA_FLOAT_E1, |
| 2217 | v1_work_fpu_fo_fc), |
| 2218 | OP16_WITH_WORK ("fstod", |
| 2219 | OPCODE_INFO3 (0xffe02800, |
| 2220 | (5_9, FEREG, OPRND_SHIFT_0_BIT), |
| 2221 | (0_4, FREG, OPRND_SHIFT_0_BIT), |
| 2222 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 2223 | CSKY_ISA_FLOAT_E1, |
| 2224 | v1_work_fpu_fo), |
| 2225 | OP16_WITH_WORK ("fdtos", |
| 2226 | OPCODE_INFO3 (0xffe02c00, |
| 2227 | (5_9, FREG, OPRND_SHIFT_0_BIT), |
| 2228 | (0_4, FEREG, OPRND_SHIFT_0_BIT), |
| 2229 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 2230 | CSKY_ISA_FLOAT_E1, |
| 2231 | v1_work_fpu_fo), |
| 2232 | OP16_WITH_WORK ("fsitos", |
| 2233 | OPCODE_INFO3 (0xffe03400, |
| 2234 | (5_9, FREG, OPRND_SHIFT_0_BIT), |
| 2235 | (0_4, FREG, OPRND_SHIFT_0_BIT), |
| 2236 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 2237 | CSKY_ISA_FLOAT_E1, |
| 2238 | v1_work_fpu_fo), |
| 2239 | OP16_WITH_WORK ("fsitod", |
| 2240 | OPCODE_INFO3 (0xffe03000, |
| 2241 | (5_9, FEREG, OPRND_SHIFT_0_BIT), |
| 2242 | (0_4, FREG, OPRND_SHIFT_0_BIT), |
| 2243 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 2244 | CSKY_ISA_FLOAT_E1, |
| 2245 | v1_work_fpu_fo), |
| 2246 | OP16_WITH_WORK ("fuitos", |
| 2247 | OPCODE_INFO3 (0xffe03c00, |
| 2248 | (5_9, FREG, OPRND_SHIFT_0_BIT), |
| 2249 | (0_4, FREG, OPRND_SHIFT_0_BIT), |
| 2250 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 2251 | CSKY_ISA_FLOAT_E1, |
| 2252 | v1_work_fpu_fo), |
| 2253 | OP16_WITH_WORK ("fuitod", |
| 2254 | OPCODE_INFO3 (0xffe03800, |
| 2255 | (5_9, FEREG, OPRND_SHIFT_0_BIT), |
| 2256 | (0_4, FREG, OPRND_SHIFT_0_BIT), |
| 2257 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 2258 | CSKY_ISA_FLOAT_E1, |
| 2259 | v1_work_fpu_fo), |
| 2260 | OP16_WITH_WORK ("fstosi", |
| 2261 | OPCODE_INFO4 (0xffe10000, |
| 2262 | (5_9, FREG, OPRND_SHIFT_0_BIT), |
| 2263 | (0_4, FREG, OPRND_SHIFT_0_BIT), |
| 2264 | (13_17, RM, OPRND_SHIFT_0_BIT), |
| 2265 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 2266 | CSKY_ISA_FLOAT_E1, |
| 2267 | v1_work_fpu_fo), |
| 2268 | OP16_WITH_WORK ("fdtosi", |
| 2269 | OPCODE_INFO4 (0xffe08000, |
| 2270 | (5_9, FREG, OPRND_SHIFT_0_BIT), |
| 2271 | (0_4, FEREG, OPRND_SHIFT_0_BIT), |
| 2272 | (13_17, RM, OPRND_SHIFT_0_BIT), |
| 2273 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 2274 | CSKY_ISA_FLOAT_E1, |
| 2275 | v1_work_fpu_fo), |
| 2276 | OP16_WITH_WORK ("fstoui", |
| 2277 | OPCODE_INFO4 (0xffe20000, |
| 2278 | (5_9, FREG, OPRND_SHIFT_0_BIT), |
| 2279 | (0_4, FREG, OPRND_SHIFT_0_BIT), |
| 2280 | (13_17, RM, OPRND_SHIFT_0_BIT), |
| 2281 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 2282 | CSKY_ISA_FLOAT_E1, |
| 2283 | v1_work_fpu_fo), |
| 2284 | OP16_WITH_WORK ("fdtoui", |
| 2285 | OPCODE_INFO4 (0xffe18000, |
| 2286 | (5_9, FREG, OPRND_SHIFT_0_BIT), |
| 2287 | (0_4, FEREG, OPRND_SHIFT_0_BIT), |
| 2288 | (13_17, RM, OPRND_SHIFT_0_BIT), |
| 2289 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 2290 | CSKY_ISA_FLOAT_E1, |
| 2291 | v1_work_fpu_fo), |
| 2292 | OP16_WITH_WORK ("fmovd", |
| 2293 | OPCODE_INFO3 (0xffe06800, |
| 2294 | (5_9, FEREG, OPRND_SHIFT_0_BIT), |
| 2295 | (0_4, FREG, OPRND_SHIFT_0_BIT), |
| 2296 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 2297 | CSKY_ISA_FLOAT_E1, |
| 2298 | v1_work_fpu_fo), |
| 2299 | OP16_WITH_WORK ("fmovs", |
| 2300 | OPCODE_INFO3 (0xffe06c00, |
| 2301 | (5_9, FREG, OPRND_SHIFT_0_BIT), |
| 2302 | (0_4, FREG, OPRND_SHIFT_0_BIT), |
| 2303 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 2304 | CSKY_ISA_FLOAT_E1, |
| 2305 | v1_work_fpu_fo), |
| 2306 | OP16_WITH_WORK ("fmts", |
| 2307 | OPCODE_INFO2 (0x00000000, |
| 2308 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT), |
| 2309 | (NONE, FREG, OPRND_SHIFT_0_BIT)), |
| 2310 | CSKY_ISA_FLOAT_E1, |
| 2311 | v1_work_fpu_write), |
| 2312 | OP16_WITH_WORK ("fmfs", |
| 2313 | OPCODE_INFO2 (0x00000000, |
| 2314 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT), |
| 2315 | (NONE, FREG, OPRND_SHIFT_0_BIT)), |
| 2316 | CSKY_ISA_FLOAT_E1, |
| 2317 | v1_work_fpu_read), |
| 2318 | OP16_WITH_WORK ("fmtd", |
| 2319 | OPCODE_INFO2 (0x00000000, |
| 2320 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT), |
| 2321 | (NONE, FEREG, OPRND_SHIFT_0_BIT)), |
| 2322 | CSKY_ISA_FLOAT_E1, |
| 2323 | v1_work_fpu_writed), |
| 2324 | OP16_WITH_WORK ("fmfd", |
| 2325 | OPCODE_INFO2 (0x00000000, |
| 2326 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT), |
| 2327 | (NONE, FEREG, OPRND_SHIFT_0_BIT)), |
| 2328 | CSKY_ISA_FLOAT_E1, |
| 2329 | v1_work_fpu_readd), |
| 2330 | {NULL, 0, {}, {}, 0, 0, 0, 0, 0, NULL} |
| 2331 | }; |
| 2332 | |
| 2333 | #undef _TRANSFER |
| 2334 | #undef _RELOC16 |
| 2335 | #undef _RELOC32 |
| 2336 | #undef _RELAX |
| 2337 | |
| 2338 | /* C-SKY v2 opcodes. */ |
| 2339 | const struct csky_opcode csky_v2_opcodes[] = |
| 2340 | { |
| 2341 | #define _TRANSFER 0 |
| 2342 | #define _RELOC16 0 |
| 2343 | #define _RELOC32 0 |
| 2344 | #define _RELAX 0 |
| 2345 | OP16 ("bkpt", |
| 2346 | OPCODE_INFO0 (0x0000), |
| 2347 | CSKYV2_ISA_E1), |
| 2348 | OP16_WITH_WORK ("nie", |
| 2349 | OPCODE_INFO0 (0x1460), |
| 2350 | CSKYV2_ISA_E1, |
| 2351 | v2_work_istack), |
| 2352 | OP16_WITH_WORK ("nir", |
| 2353 | OPCODE_INFO0 (0x1461), |
| 2354 | CSKYV2_ISA_E1, |
| 2355 | v2_work_istack), |
| 2356 | OP16_WITH_WORK ("ipush", |
| 2357 | OPCODE_INFO0 (0x1462), |
| 2358 | CSKYV2_ISA_E1, |
| 2359 | v2_work_istack), |
| 2360 | OP16_WITH_WORK ("ipop", |
| 2361 | OPCODE_INFO0 (0x1463), |
| 2362 | CSKYV2_ISA_E1, |
| 2363 | v2_work_istack), |
| 2364 | OP16 ("bpop.h", |
| 2365 | OPCODE_INFO1 (0x14a0, |
| 2366 | (2_4, GREG0_7, OPRND_SHIFT_0_BIT)), |
| 2367 | CSKY_ISA_JAVA), |
| 2368 | OP16 ("bpop.w", |
| 2369 | OPCODE_INFO1 (0x14a2, |
| 2370 | (2_4, GREG0_7, OPRND_SHIFT_0_BIT)), |
| 2371 | CSKY_ISA_JAVA), |
| 2372 | OP16 ("bpush.h", |
| 2373 | OPCODE_INFO1 (0x14e0, |
| 2374 | (2_4, GREG0_7, OPRND_SHIFT_0_BIT)), |
| 2375 | CSKY_ISA_JAVA), |
| 2376 | OP16 ("bpush.w", |
| 2377 | OPCODE_INFO1 (0x14e2, |
| 2378 | (2_4, GREG0_7, OPRND_SHIFT_0_BIT)), |
| 2379 | CSKY_ISA_JAVA), |
| 2380 | OP32 ("bmset", |
| 2381 | OPCODE_INFO0 (0xc0001020), |
| 2382 | CSKY_ISA_JAVA), |
| 2383 | OP32 ("bmclr", |
| 2384 | OPCODE_INFO0 (0xc0001420), |
| 2385 | CSKY_ISA_JAVA), |
| 2386 | OP32 ("sce", |
| 2387 | OPCODE_INFO1 (0xc0001820, |
| 2388 | (21_24, IMM4b, OPRND_SHIFT_0_BIT)), |
| 2389 | CSKY_ISA_MP), |
| 2390 | OP32 ("trap", |
| 2391 | OPCODE_INFO1 (0xc0002020, |
| 2392 | (10_11, IMM2b, OPRND_SHIFT_0_BIT)), |
| 2393 | CSKYV2_ISA_E1), |
| 2394 | /* Secure/nsecure world switch. */ |
| 2395 | OP32 ("wsc", |
| 2396 | OPCODE_INFO0 (0xc0003c20), |
| 2397 | CSKY_ISA_TRUST), |
| 2398 | OP32 ("mtcr", |
| 2399 | OPCODE_INFO2 (0xc0006420, |
| 2400 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 2401 | (0_4or21_25, CTRLREG, OPRND_SHIFT_0_BIT)), |
| 2402 | CSKYV2_ISA_E1), |
| 2403 | OP32 ("mfcr", |
| 2404 | OPCODE_INFO2 (0xc0006020, |
| 2405 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 2406 | (16_20or21_25, CTRLREG, OPRND_SHIFT_0_BIT)), |
| 2407 | CSKYV2_ISA_E1), |
| 2408 | #undef _TRANSFER |
| 2409 | #define _TRANSFER 2 |
| 2410 | OP32 ("rte", |
| 2411 | OPCODE_INFO0 (0xc0004020), |
| 2412 | CSKYV2_ISA_E1), |
| 2413 | OP32 ("rfi", |
| 2414 | OPCODE_INFO0 (0xc0004420), |
| 2415 | CSKYV2_ISA_2E3), |
| 2416 | #undef _TRANSFER |
| 2417 | #define _TRANSFER 0 |
| 2418 | OP32 ("stop", |
| 2419 | OPCODE_INFO0 (0xc0004820), |
| 2420 | CSKYV2_ISA_E1), |
| 2421 | OP32 ("wait", |
| 2422 | OPCODE_INFO0 (0xc0004c20), |
| 2423 | CSKYV2_ISA_E1), |
| 2424 | OP32 ("doze", |
| 2425 | OPCODE_INFO0 (0xc0005020), |
| 2426 | CSKYV2_ISA_E1), |
| 2427 | OP32 ("we", |
| 2428 | OPCODE_INFO0 (0xc0005420), |
| 2429 | CSKY_ISA_MP_1E2), |
| 2430 | OP32 ("se", |
| 2431 | OPCODE_INFO0 (0xc0005820), |
| 2432 | CSKY_ISA_MP_1E2), |
| 2433 | OP32 ("psrclr", |
| 2434 | OPCODE_INFO_LIST (0xc0007020, |
| 2435 | (21_25, PSR_BITS_LIST, OPRND_SHIFT_0_BIT)), |
| 2436 | CSKYV2_ISA_E1), |
| 2437 | OP32 ("psrset", |
| 2438 | OPCODE_INFO_LIST (0xc0007420, |
| 2439 | (21_25, PSR_BITS_LIST, OPRND_SHIFT_0_BIT)), |
| 2440 | CSKYV2_ISA_E1), |
| 2441 | DOP32 ("abs", |
| 2442 | OPCODE_INFO2 (0xc4000200, |
| 2443 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 2444 | (16_20, AREG, OPRND_SHIFT_0_BIT)), |
| 2445 | OPCODE_INFO1 (0xc4000200, |
| 2446 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT)), |
| 2447 | CSKYV2_ISA_2E3), |
| 2448 | OP32 ("mvc", |
| 2449 | OPCODE_INFO1 (0xc4000500, |
| 2450 | (0_4, AREG, OPRND_SHIFT_0_BIT)), |
| 2451 | CSKYV2_ISA_1E2), |
| 2452 | OP32 ("incf", |
| 2453 | OPCODE_INFO3 (0xc4000c20, |
| 2454 | (21_25, AREG, OPRND_SHIFT_0_BIT), |
| 2455 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 2456 | (0_4, IMM5b, OPRND_SHIFT_0_BIT)), |
| 2457 | CSKYV2_ISA_1E2), |
| 2458 | OP32 ("movf", |
| 2459 | OPCODE_INFO2 (0xc4000c20, |
| 2460 | (21_25, AREG, OPRND_SHIFT_0_BIT), |
| 2461 | (16_20, AREG, OPRND_SHIFT_0_BIT)), |
| 2462 | CSKYV2_ISA_1E2), |
| 2463 | OP32 ("inct", |
| 2464 | OPCODE_INFO3 (0xc4000c40, |
| 2465 | (21_25, AREG, OPRND_SHIFT_0_BIT), |
| 2466 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 2467 | (0_4, IMM5b, OPRND_SHIFT_0_BIT)), |
| 2468 | CSKYV2_ISA_1E2), |
| 2469 | OP32 ("movt", |
| 2470 | OPCODE_INFO2 (0xc4000c40, |
| 2471 | (21_25, AREG, OPRND_SHIFT_0_BIT), |
| 2472 | (16_20, AREG, OPRND_SHIFT_0_BIT)), |
| 2473 | CSKYV2_ISA_1E2), |
| 2474 | OP32 ("decf", |
| 2475 | OPCODE_INFO3 (0xc4000c80, |
| 2476 | (21_25, AREG, OPRND_SHIFT_0_BIT), |
| 2477 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 2478 | (0_4, IMM5b, OPRND_SHIFT_0_BIT)), |
| 2479 | CSKYV2_ISA_1E2), |
| 2480 | OP32 ("dect", |
| 2481 | OPCODE_INFO3 (0xc4000d00, |
| 2482 | (21_25, AREG, OPRND_SHIFT_0_BIT), |
| 2483 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 2484 | (0_4, IMM5b, OPRND_SHIFT_0_BIT)), |
| 2485 | CSKYV2_ISA_1E2), |
| 2486 | OP32 ("decgt", |
| 2487 | OPCODE_INFO3 (0xc4001020, |
| 2488 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 2489 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 2490 | (21_25, IMM5b, OPRND_SHIFT_0_BIT)), |
| 2491 | CSKYV2_ISA_2E3), |
| 2492 | OP32 ("declt", |
| 2493 | OPCODE_INFO3 (0xc4001040, |
| 2494 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 2495 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 2496 | (21_25, IMM5b, OPRND_SHIFT_0_BIT)), |
| 2497 | CSKYV2_ISA_2E3), |
| 2498 | OP32 ("decne", |
| 2499 | OPCODE_INFO3 (0xc4001080, |
| 2500 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 2501 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 2502 | (21_25, IMM5b, OPRND_SHIFT_0_BIT)), |
| 2503 | CSKYV2_ISA_2E3), |
| 2504 | OP32 ("clrf", |
| 2505 | OPCODE_INFO1 (0xc4002c20, |
| 2506 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 2507 | CSKYV2_ISA_2E3), |
| 2508 | OP32 ("clrt", |
| 2509 | OPCODE_INFO1 (0xc4002c40, |
| 2510 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 2511 | CSKYV2_ISA_2E3), |
| 2512 | DOP32 ("rotli", |
| 2513 | OPCODE_INFO3 (0xc4004900, |
| 2514 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 2515 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 2516 | (21_25, IMM5b, OPRND_SHIFT_0_BIT)), |
| 2517 | OPCODE_INFO2 (0xc4004900, |
| 2518 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), |
| 2519 | (21_25, IMM5b, OPRND_SHIFT_0_BIT)), |
| 2520 | CSKYV2_ISA_1E2), |
| 2521 | OP32 ("lslc", |
| 2522 | OPCODE_INFO3 (0xc4004c20, |
| 2523 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 2524 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 2525 | (21_25, OIMM5b, OPRND_SHIFT_0_BIT)), |
| 2526 | CSKYV2_ISA_1E2), |
| 2527 | OP32 ("lsrc", |
| 2528 | OPCODE_INFO3 (0xc4004c40, |
| 2529 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 2530 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 2531 | (21_25, OIMM5b, OPRND_SHIFT_0_BIT)), |
| 2532 | CSKYV2_ISA_1E2), |
| 2533 | DOP32 ("asrc", |
| 2534 | OPCODE_INFO3 (0xc4004c80, |
| 2535 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 2536 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 2537 | (21_25, OIMM5b, OPRND_SHIFT_0_BIT)), |
| 2538 | OPCODE_INFO1 (0xc4004c80, |
| 2539 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT)), |
| 2540 | CSKYV2_ISA_1E2), |
| 2541 | OP32 ("xsr", |
| 2542 | OPCODE_INFO3 (0xc4004d00, |
| 2543 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 2544 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 2545 | (21_25, OIMM5b, OPRND_SHIFT_0_BIT)), |
| 2546 | CSKYV2_ISA_1E2), |
| 2547 | OP32 ("bgenr", |
| 2548 | OPCODE_INFO2 (0xc4005040, |
| 2549 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 2550 | (16_20, AREG, OPRND_SHIFT_0_BIT)), |
| 2551 | CSKYV2_ISA_2E3), |
| 2552 | DOP32 ("brev", |
| 2553 | OPCODE_INFO2 (0xc4006200, |
| 2554 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 2555 | (16_20, AREG, OPRND_SHIFT_0_BIT)), |
| 2556 | OPCODE_INFO1 (0xc4006200, |
| 2557 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT)), |
| 2558 | CSKYV2_ISA_2E3), |
| 2559 | OP32 ("xtrb0", |
| 2560 | OPCODE_INFO2 (0xc4007020, |
| 2561 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 2562 | (16_20, AREG, OPRND_SHIFT_0_BIT)), |
| 2563 | CSKYV2_ISA_1E2), |
| 2564 | OP32 ("xtrb1", |
| 2565 | OPCODE_INFO2 (0xc4007040, |
| 2566 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 2567 | (16_20, AREG, OPRND_SHIFT_0_BIT)), |
| 2568 | CSKYV2_ISA_1E2), |
| 2569 | OP32 ("xtrb2", |
| 2570 | OPCODE_INFO2 (0xc4007080, |
| 2571 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 2572 | (16_20, AREG, OPRND_SHIFT_0_BIT)), |
| 2573 | CSKYV2_ISA_1E2), |
| 2574 | OP32 ("xtrb3", |
| 2575 | OPCODE_INFO2 (0xc4007100, |
| 2576 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 2577 | (16_20, AREG, OPRND_SHIFT_0_BIT)), |
| 2578 | CSKYV2_ISA_1E2), |
| 2579 | OP32 ("ff0", |
| 2580 | OPCODE_INFO2 (0xc4007c20, |
| 2581 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 2582 | (16_20, AREG, OPRND_SHIFT_0_BIT)), |
| 2583 | CSKYV2_ISA_1E2), |
| 2584 | DOP32 ("ff1", |
| 2585 | OPCODE_INFO2 (0xc4007c40, |
| 2586 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 2587 | (16_20, AREG, OPRND_SHIFT_0_BIT)), |
| 2588 | OPCODE_INFO1 (0xc4007c40, |
| 2589 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT)), |
| 2590 | CSKYV2_ISA_1E2), |
| 2591 | OP32 ("mulu", |
| 2592 | OPCODE_INFO2 (0xc4008820, |
| 2593 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 2594 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 2595 | CSKY_ISA_DSP), |
| 2596 | OP32 ("mulua", |
| 2597 | OPCODE_INFO2 (0xc4008840, |
| 2598 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 2599 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 2600 | CSKY_ISA_DSP), |
| 2601 | OP32 ("mulus", |
| 2602 | OPCODE_INFO2 (0xc4008880, |
| 2603 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 2604 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 2605 | CSKY_ISA_DSP), |
| 2606 | OP32 ("muls", |
| 2607 | OPCODE_INFO2 (0xc4008c20, |
| 2608 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 2609 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 2610 | CSKY_ISA_DSP), |
| 2611 | OP32 ("mulsa", |
| 2612 | OPCODE_INFO2 (0xc4008c40, |
| 2613 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 2614 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 2615 | CSKY_ISA_DSP), |
| 2616 | OP32 ("mulss", |
| 2617 | OPCODE_INFO2 (0xc4008c80, |
| 2618 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 2619 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 2620 | CSKY_ISA_DSP), |
| 2621 | OP32 ("mulsha", |
| 2622 | OPCODE_INFO2 (0xc4009040, |
| 2623 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 2624 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 2625 | CSKY_ISA_DSP), |
| 2626 | OP32 ("mulshs", |
| 2627 | OPCODE_INFO2 (0xc4009080, |
| 2628 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 2629 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 2630 | CSKY_ISA_DSP), |
| 2631 | OP32 ("mulswa", |
| 2632 | OPCODE_INFO2 (0xc4009440, |
| 2633 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 2634 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 2635 | CSKY_ISA_DSP), |
| 2636 | OP32 ("mulsws", |
| 2637 | OPCODE_INFO2 (0xc4009480, |
| 2638 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 2639 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 2640 | CSKY_ISA_DSP), |
| 2641 | OP32 ("mfhis", |
| 2642 | OPCODE_INFO1 (0xc4009820, |
| 2643 | (0_4, AREG, OPRND_SHIFT_0_BIT)), |
| 2644 | CSKY_ISA_DSP), |
| 2645 | OP32 ("mflos", |
| 2646 | OPCODE_INFO1 (0xc4009880, |
| 2647 | (0_4, AREG, OPRND_SHIFT_0_BIT)), |
| 2648 | CSKY_ISA_DSP), |
| 2649 | OP32 ("mvtc", |
| 2650 | OPCODE_INFO0 (0xc4009a00), |
| 2651 | CSKY_ISA_DSP), |
| 2652 | OP32 ("mfhi", |
| 2653 | OPCODE_INFO1 (0xc4009c20, |
| 2654 | (0_4, AREG, OPRND_SHIFT_0_BIT)), |
| 2655 | CSKY_ISA_DSP), |
| 2656 | OP32 ("mthi", |
| 2657 | OPCODE_INFO1 (0xc4009c40, |
| 2658 | (16_20, AREG, OPRND_SHIFT_0_BIT)), |
| 2659 | CSKY_ISA_DSP), |
| 2660 | OP32 ("mflo", |
| 2661 | OPCODE_INFO1 (0xc4009c80, |
| 2662 | (0_4, AREG, OPRND_SHIFT_0_BIT)), |
| 2663 | CSKY_ISA_DSP), |
| 2664 | OP32 ("mtlo", |
| 2665 | OPCODE_INFO1 (0xc4009d00, |
| 2666 | (16_20, AREG, OPRND_SHIFT_0_BIT)), |
| 2667 | CSKY_ISA_DSP), |
| 2668 | OP32 ("vmulsh", |
| 2669 | OPCODE_INFO2 (0xc400b020, |
| 2670 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 2671 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 2672 | CSKY_ISA_DSP_1E2), |
| 2673 | OP32 ("vmulsha", |
| 2674 | OPCODE_INFO2 (0xc400b040, |
| 2675 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 2676 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 2677 | CSKY_ISA_DSP_1E2), |
| 2678 | OP32 ("vmulshs", |
| 2679 | OPCODE_INFO2 (0xc400b080, |
| 2680 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 2681 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 2682 | CSKY_ISA_DSP_1E2), |
| 2683 | OP32 ("vmulsw", |
| 2684 | OPCODE_INFO2 (0xc400b420, |
| 2685 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 2686 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 2687 | CSKY_ISA_DSP_1E2), |
| 2688 | OP32 ("vmulswa", |
| 2689 | OPCODE_INFO2 (0xc400b440, |
| 2690 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 2691 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 2692 | CSKY_ISA_DSP_1E2), |
| 2693 | OP32 ("vmulsws", |
| 2694 | OPCODE_INFO2 (0xc400b480, |
| 2695 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 2696 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 2697 | CSKY_ISA_DSP_1E2), |
| 2698 | OP32 ("ldr.b", |
| 2699 | SOPCODE_INFO2 (0xd0000000, |
| 2700 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 2701 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), |
| 2702 | (5_9or21_25, AREG_WITH_LSHIFT, OPRND_SHIFT_0_BIT))), |
| 2703 | CSKYV2_ISA_2E3), |
| 2704 | OP32 ("ldr.bs", |
| 2705 | SOPCODE_INFO2 (0xd0001000, |
| 2706 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 2707 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), |
| 2708 | (5_9or21_25, AREG_WITH_LSHIFT, OPRND_SHIFT_0_BIT))), |
| 2709 | CSKYV2_ISA_2E3), |
| 2710 | OP32 ("ldr.h", |
| 2711 | SOPCODE_INFO2 (0xd0000400, |
| 2712 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 2713 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), |
| 2714 | (5_9or21_25, AREG_WITH_LSHIFT, OPRND_SHIFT_0_BIT))), |
| 2715 | CSKYV2_ISA_2E3), |
| 2716 | OP32 ("ldr.hs", |
| 2717 | SOPCODE_INFO2 (0xd0001400, |
| 2718 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 2719 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), |
| 2720 | (5_9or21_25, AREG_WITH_LSHIFT, OPRND_SHIFT_0_BIT))), |
| 2721 | CSKYV2_ISA_2E3), |
| 2722 | OP32 ("ldr.w", |
| 2723 | SOPCODE_INFO2 (0xd0000800, |
| 2724 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 2725 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), |
| 2726 | (5_9or21_25, AREG_WITH_LSHIFT, OPRND_SHIFT_0_BIT))), |
| 2727 | CSKYV2_ISA_2E3), |
| 2728 | OP32 ("ldm", |
| 2729 | OPCODE_INFO2 (0xd0001c20, |
| 2730 | (0_4or21_25, REGLIST_DASH, OPRND_SHIFT_0_BIT), |
| 2731 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), |
| 2732 | CSKYV2_ISA_1E2), |
| 2733 | OP32 ("ldq", |
| 2734 | OPCODE_INFO2 (0xd0801c23, |
| 2735 | (NONE, REGr4_r7, OPRND_SHIFT_0_BIT), |
| 2736 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), |
| 2737 | CSKYV2_ISA_2E3), |
| 2738 | OP32 ("str.b", |
| 2739 | SOPCODE_INFO2 (0xd4000000, |
| 2740 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 2741 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), |
| 2742 | (5_9or21_25, AREG_WITH_LSHIFT, OPRND_SHIFT_0_BIT))), |
| 2743 | CSKYV2_ISA_2E3), |
| 2744 | OP32 ("str.h", |
| 2745 | SOPCODE_INFO2 (0xd4000400, |
| 2746 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 2747 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), |
| 2748 | (5_9or21_25, AREG_WITH_LSHIFT, OPRND_SHIFT_0_BIT))), |
| 2749 | CSKYV2_ISA_2E3), |
| 2750 | OP32 ("str.w", |
| 2751 | SOPCODE_INFO2 (0xd4000800, |
| 2752 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 2753 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), |
| 2754 | (5_9or21_25, AREG_WITH_LSHIFT, OPRND_SHIFT_0_BIT))), |
| 2755 | CSKYV2_ISA_2E3), |
| 2756 | OP32 ("stm", |
| 2757 | OPCODE_INFO2 (0xd4001c20, |
| 2758 | (0_4or21_25, REGLIST_DASH, OPRND_SHIFT_0_BIT), |
| 2759 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), |
| 2760 | CSKYV2_ISA_1E2), |
| 2761 | OP32 ("stq", |
| 2762 | OPCODE_INFO2 (0xd4801c23, |
| 2763 | (NONE, REGr4_r7, OPRND_SHIFT_0_BIT), |
| 2764 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), |
| 2765 | CSKYV2_ISA_2E3), |
| 2766 | OP32 ("ld.bs", |
| 2767 | SOPCODE_INFO2 (0xd8004000, |
| 2768 | (21_25, AREG, OPRND_SHIFT_0_BIT), |
| 2769 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), |
| 2770 | (0_11, IMM_LDST, OPRND_SHIFT_0_BIT))), |
| 2771 | CSKYV2_ISA_1E2), |
| 2772 | OP32 ("ldbs", |
| 2773 | SOPCODE_INFO2 (0xd8004000, |
| 2774 | (21_25, AREG, OPRND_SHIFT_0_BIT), |
| 2775 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), |
| 2776 | (0_11, IMM_LDST, OPRND_SHIFT_0_BIT))), |
| 2777 | CSKYV2_ISA_1E2), |
| 2778 | OP32 ("ld.hs", |
| 2779 | SOPCODE_INFO2 (0xd8005000, |
| 2780 | (21_25, AREG, OPRND_SHIFT_0_BIT), |
| 2781 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), |
| 2782 | (0_11, IMM_LDST, OPRND_SHIFT_1_BIT))), |
| 2783 | CSKYV2_ISA_1E2), |
| 2784 | OP32 ("ldhs", |
| 2785 | SOPCODE_INFO2 (0xd8005000, |
| 2786 | (21_25, AREG, OPRND_SHIFT_0_BIT), |
| 2787 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), |
| 2788 | (0_11, IMM_LDST, OPRND_SHIFT_1_BIT))), |
| 2789 | CSKYV2_ISA_1E2), |
| 2790 | OP32 ("ld.d", |
| 2791 | SOPCODE_INFO2 (0xd8003000, |
| 2792 | (21_25, AREG, OPRND_SHIFT_0_BIT), |
| 2793 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), |
| 2794 | (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), |
| 2795 | CSKYV2_ISA_3E7), |
| 2796 | OP32 ("ldex.w", |
| 2797 | SOPCODE_INFO2 (0xd8007000, |
| 2798 | (21_25, AREG, OPRND_SHIFT_0_BIT), |
| 2799 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), |
| 2800 | (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), |
| 2801 | CSKY_ISA_MP_1E2), |
| 2802 | OP32 ("ldexw", |
| 2803 | SOPCODE_INFO2 (0xd8007000, |
| 2804 | (21_25, AREG, OPRND_SHIFT_0_BIT), |
| 2805 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), |
| 2806 | (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), |
| 2807 | CSKY_ISA_MP_1E2), |
| 2808 | OP32 ("ldex", |
| 2809 | SOPCODE_INFO2 (0xd8007000, |
| 2810 | (21_25, AREG, OPRND_SHIFT_0_BIT), |
| 2811 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), |
| 2812 | (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), |
| 2813 | CSKY_ISA_MP_1E2), |
| 2814 | OP32 ("st.d", |
| 2815 | SOPCODE_INFO2 (0xdc003000, |
| 2816 | (21_25, AREG, OPRND_SHIFT_0_BIT), |
| 2817 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), |
| 2818 | (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), |
| 2819 | CSKYV2_ISA_3E7), |
| 2820 | OP32 ("stex.w", |
| 2821 | SOPCODE_INFO2 (0xdc007000, |
| 2822 | (21_25, AREG, OPRND_SHIFT_0_BIT), |
| 2823 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), |
| 2824 | (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), |
| 2825 | CSKY_ISA_MP_1E2), |
| 2826 | OP32 ("stexw", |
| 2827 | SOPCODE_INFO2 (0xdc007000, |
| 2828 | (21_25, AREG, OPRND_SHIFT_0_BIT), |
| 2829 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), |
| 2830 | (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), |
| 2831 | CSKY_ISA_MP_1E2), |
| 2832 | OP32 ("stex", |
| 2833 | SOPCODE_INFO2 (0xdc007000, |
| 2834 | (21_25, AREG, OPRND_SHIFT_0_BIT), |
| 2835 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), |
| 2836 | (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), |
| 2837 | CSKY_ISA_MP_1E2), |
| 2838 | DOP32 ("andi", |
| 2839 | OPCODE_INFO3 (0xe4002000, |
| 2840 | (21_25, AREG, OPRND_SHIFT_0_BIT), |
| 2841 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 2842 | (0_11, IMM12b, OPRND_SHIFT_0_BIT)), |
| 2843 | OPCODE_INFO2 (0xe4002000, |
| 2844 | (16_20or21_25, DUP_AREG, OPRND_SHIFT_0_BIT), |
| 2845 | (0_11, IMM12b, OPRND_SHIFT_0_BIT)), |
| 2846 | CSKYV2_ISA_1E2), |
| 2847 | OP32 ("andni", |
| 2848 | OPCODE_INFO3 (0xe4003000, |
| 2849 | (21_25, AREG, OPRND_SHIFT_0_BIT), |
| 2850 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 2851 | (0_11, IMM12b, OPRND_SHIFT_0_BIT)), |
| 2852 | CSKYV2_ISA_1E2), |
| 2853 | OP32 ("xori", |
| 2854 | OPCODE_INFO3 (0xe4004000, |
| 2855 | (21_25, AREG, OPRND_SHIFT_0_BIT), |
| 2856 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 2857 | (0_11, IMM12b, OPRND_SHIFT_0_BIT)), |
| 2858 | CSKYV2_ISA_1E2), |
| 2859 | OP32 ("ins", |
| 2860 | OPCODE_INFO4 (0xc4005c00, |
| 2861 | (21_25, AREG, OPRND_SHIFT_0_BIT), |
| 2862 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 2863 | (5_9, MSB2SIZE, OPRND_SHIFT_0_BIT), |
| 2864 | (0_4, LSB2SIZE, OPRND_SHIFT_0_BIT)), |
| 2865 | CSKYV2_ISA_2E3), |
| 2866 | #undef _TRANSFER |
| 2867 | #undef _RELOC32 |
| 2868 | #define _TRANSFER 1 |
| 2869 | #define _RELOC32 BFD_RELOC_CKCORE_PCREL_IMM16BY4 |
| 2870 | OP32 ("jmpi", |
| 2871 | OPCODE_INFO1 (0xeac00000, |
| 2872 | (0_15, OFF16b, OPRND_SHIFT_2_BIT)), |
| 2873 | CSKYV2_ISA_2E3), |
| 2874 | #undef _TRANSFER |
| 2875 | #undef _RELOC32 |
| 2876 | #define _TRANSFER 0 |
| 2877 | #define _RELOC32 0 |
| 2878 | |
| 2879 | OP32 ("fadds", |
| 2880 | OPCODE_INFO3 (0xf4000000, |
| 2881 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 2882 | (16_19, FREG, OPRND_SHIFT_0_BIT), |
| 2883 | (21_24, FREG, OPRND_SHIFT_0_BIT)), |
| 2884 | CSKY_ISA_FLOAT_E1), |
| 2885 | OP32 ("fsubs", |
| 2886 | OPCODE_INFO3 (0xf4000020, |
| 2887 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 2888 | (16_19, FREG, OPRND_SHIFT_0_BIT), |
| 2889 | (21_24, FREG, OPRND_SHIFT_0_BIT)), |
| 2890 | CSKY_ISA_FLOAT_E1), |
| 2891 | OP32 ("fmovs", |
| 2892 | OPCODE_INFO2 (0xf4000080, |
| 2893 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 2894 | (16_19, FREG, OPRND_SHIFT_0_BIT)), |
| 2895 | CSKY_ISA_FLOAT_E1), |
| 2896 | OP32 ("fabss", |
| 2897 | OPCODE_INFO2 (0xf40000c0, |
| 2898 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 2899 | (16_19, FREG, OPRND_SHIFT_0_BIT)), |
| 2900 | CSKY_ISA_FLOAT_E1), |
| 2901 | OP32 ("fnegs", |
| 2902 | OPCODE_INFO2 (0xf40000e0, |
| 2903 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 2904 | (16_19, FREG, OPRND_SHIFT_0_BIT)), |
| 2905 | CSKY_ISA_FLOAT_E1), |
| 2906 | OP32 ("fcmpzhss", |
| 2907 | OPCODE_INFO1 (0xf4000100, |
| 2908 | (16_19, FREG, OPRND_SHIFT_0_BIT)), |
| 2909 | CSKY_ISA_FLOAT_E1), |
| 2910 | OP32 ("fcmpzlss", |
| 2911 | OPCODE_INFO1 (0xf4000120, |
| 2912 | (16_19, FREG, OPRND_SHIFT_0_BIT)), |
| 2913 | CSKY_ISA_FLOAT_E1), |
| 2914 | OP32 ("fcmpznes", |
| 2915 | OPCODE_INFO1 (0xf4000140, |
| 2916 | (16_19, FREG, OPRND_SHIFT_0_BIT)), |
| 2917 | CSKY_ISA_FLOAT_E1), |
| 2918 | OP32 ("fcmpzuos", |
| 2919 | OPCODE_INFO1 (0xf4000160, |
| 2920 | (16_19, FREG, OPRND_SHIFT_0_BIT)), |
| 2921 | CSKY_ISA_FLOAT_E1), |
| 2922 | OP32 ("fcmphss", |
| 2923 | OPCODE_INFO2 (0xf4000180, |
| 2924 | (16_19, FREG, OPRND_SHIFT_0_BIT), |
| 2925 | (21_24, FREG, OPRND_SHIFT_0_BIT)), |
| 2926 | CSKY_ISA_FLOAT_E1), |
| 2927 | OP32 ("fcmplts", |
| 2928 | OPCODE_INFO2 (0xf40001a0, |
| 2929 | (16_19, FREG, OPRND_SHIFT_0_BIT), |
| 2930 | (21_24, FREG, OPRND_SHIFT_0_BIT)), |
| 2931 | CSKY_ISA_FLOAT_E1), |
| 2932 | OP32 ("fcmpnes", |
| 2933 | OPCODE_INFO2 (0xf40001c0, |
| 2934 | (16_19, FREG, OPRND_SHIFT_0_BIT), |
| 2935 | (21_24, FREG, OPRND_SHIFT_0_BIT)), |
| 2936 | CSKY_ISA_FLOAT_E1), |
| 2937 | OP32 ("fcmpuos", |
| 2938 | OPCODE_INFO2 (0xf40001e0, |
| 2939 | (16_19, FREG, OPRND_SHIFT_0_BIT), |
| 2940 | (21_24, FREG, OPRND_SHIFT_0_BIT)), |
| 2941 | CSKY_ISA_FLOAT_E1), |
| 2942 | OP32 ("fmuls", |
| 2943 | OPCODE_INFO3 (0xf4000200, |
| 2944 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 2945 | (16_19, FREG, OPRND_SHIFT_0_BIT), |
| 2946 | (21_24, FREG, OPRND_SHIFT_0_BIT)), |
| 2947 | CSKY_ISA_FLOAT_E1), |
| 2948 | OP32 ("fmacs", |
| 2949 | OPCODE_INFO3 (0xf4000280, |
| 2950 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 2951 | (16_19, FREG, OPRND_SHIFT_0_BIT), |
| 2952 | (21_24, FREG, OPRND_SHIFT_0_BIT)), |
| 2953 | CSKY_ISA_FLOAT_E1), |
| 2954 | OP32 ("fmscs", |
| 2955 | OPCODE_INFO3 (0xf40002a0, |
| 2956 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 2957 | (16_19, FREG, OPRND_SHIFT_0_BIT), |
| 2958 | (21_24, FREG, OPRND_SHIFT_0_BIT)), |
| 2959 | CSKY_ISA_FLOAT_E1), |
| 2960 | OP32 ("fnmacs", |
| 2961 | OPCODE_INFO3 (0xf40002c0, |
| 2962 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 2963 | (16_19, FREG, OPRND_SHIFT_0_BIT), |
| 2964 | (21_24, FREG, OPRND_SHIFT_0_BIT)), |
| 2965 | CSKY_ISA_FLOAT_E1), |
| 2966 | OP32 ("fnmscs", |
| 2967 | OPCODE_INFO3 (0xf40002e0, |
| 2968 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 2969 | (16_19, FREG, OPRND_SHIFT_0_BIT), |
| 2970 | (21_24, FREG, OPRND_SHIFT_0_BIT)), |
| 2971 | CSKY_ISA_FLOAT_E1), |
| 2972 | OP32 ("fnmuls", |
| 2973 | OPCODE_INFO3 (0xf4000220, |
| 2974 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 2975 | (16_19, FREG, OPRND_SHIFT_0_BIT), |
| 2976 | (21_24, FREG, OPRND_SHIFT_0_BIT)), |
| 2977 | CSKY_ISA_FLOAT_E1), |
| 2978 | OP32 ("fdivs", |
| 2979 | OPCODE_INFO3 (0xf4000300, |
| 2980 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 2981 | (16_19, FREG, OPRND_SHIFT_0_BIT), |
| 2982 | (21_24, FREG, OPRND_SHIFT_0_BIT)), |
| 2983 | CSKY_ISA_FLOAT_E1), |
| 2984 | OP32 ("frecips", |
| 2985 | OPCODE_INFO2 (0xf4000320, |
| 2986 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 2987 | (16_19, FREG, OPRND_SHIFT_0_BIT)), |
| 2988 | CSKY_ISA_FLOAT_E1), |
| 2989 | OP32 ("fsqrts", |
| 2990 | OPCODE_INFO2 (0xf4000340, |
| 2991 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 2992 | (16_19, FREG, OPRND_SHIFT_0_BIT)), |
| 2993 | CSKY_ISA_FLOAT_E1), |
| 2994 | OP32 ("faddd", |
| 2995 | OPCODE_INFO3 (0xf4000800, |
| 2996 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 2997 | (16_19, FREG, OPRND_SHIFT_0_BIT), |
| 2998 | (21_24, FREG, OPRND_SHIFT_0_BIT)), |
| 2999 | CSKY_ISA_FLOAT_1E2), |
| 3000 | OP32 ("fsubd", |
| 3001 | OPCODE_INFO3 (0xf4000820, |
| 3002 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 3003 | (16_19, FREG, OPRND_SHIFT_0_BIT), |
| 3004 | (21_24, FREG, OPRND_SHIFT_0_BIT)), |
| 3005 | CSKY_ISA_FLOAT_1E2), |
| 3006 | OP32 ("fmovd", |
| 3007 | OPCODE_INFO2 (0xf4000880, |
| 3008 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 3009 | (16_19, FREG, OPRND_SHIFT_0_BIT)), |
| 3010 | CSKY_ISA_FLOAT_1E2), |
| 3011 | OP32 ("fabsd", |
| 3012 | OPCODE_INFO2 (0xf40008c0, |
| 3013 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 3014 | (16_19, FREG, OPRND_SHIFT_0_BIT)), |
| 3015 | CSKY_ISA_FLOAT_1E2), |
| 3016 | OP32 ("fnegd", |
| 3017 | OPCODE_INFO2 (0xf40008e0, |
| 3018 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 3019 | (16_19, FREG, OPRND_SHIFT_0_BIT)), |
| 3020 | CSKY_ISA_FLOAT_1E2), |
| 3021 | OP32 ("fcmpzhsd", |
| 3022 | OPCODE_INFO1 (0xf4000900, |
| 3023 | (16_19, FREG, OPRND_SHIFT_0_BIT)), |
| 3024 | CSKY_ISA_FLOAT_1E2), |
| 3025 | OP32 ("fcmpzlsd", |
| 3026 | OPCODE_INFO1 (0xf4000920, |
| 3027 | (16_19, FREG, OPRND_SHIFT_0_BIT)), |
| 3028 | CSKY_ISA_FLOAT_1E2), |
| 3029 | OP32 ("fcmpzned", |
| 3030 | OPCODE_INFO1 (0xf4000940, |
| 3031 | (16_19, FREG, OPRND_SHIFT_0_BIT)), |
| 3032 | CSKY_ISA_FLOAT_1E2), |
| 3033 | OP32 ("fcmpzuod", |
| 3034 | OPCODE_INFO1 (0xf4000960, |
| 3035 | (16_19, FREG, OPRND_SHIFT_0_BIT)), |
| 3036 | CSKY_ISA_FLOAT_1E2), |
| 3037 | OP32 ("fcmphsd", |
| 3038 | OPCODE_INFO2 (0xf4000980, |
| 3039 | (16_19, FREG, OPRND_SHIFT_0_BIT), |
| 3040 | (21_24, FREG, OPRND_SHIFT_0_BIT)), |
| 3041 | CSKY_ISA_FLOAT_1E2), |
| 3042 | OP32 ("fcmpltd", |
| 3043 | OPCODE_INFO2 (0xf40009a0, |
| 3044 | (16_19, FREG, OPRND_SHIFT_0_BIT), |
| 3045 | (21_24, FREG, OPRND_SHIFT_0_BIT)), |
| 3046 | CSKY_ISA_FLOAT_1E2), |
| 3047 | OP32 ("fcmpned", |
| 3048 | OPCODE_INFO2 (0xf40009c0, |
| 3049 | (16_19, FREG, OPRND_SHIFT_0_BIT), |
| 3050 | (21_24, FREG, OPRND_SHIFT_0_BIT)), |
| 3051 | CSKY_ISA_FLOAT_1E2), |
| 3052 | OP32 ("fcmpuod", |
| 3053 | OPCODE_INFO2 (0xf40009e0, |
| 3054 | (16_19, FREG, OPRND_SHIFT_0_BIT), |
| 3055 | (21_24, FREG, OPRND_SHIFT_0_BIT)), |
| 3056 | CSKY_ISA_FLOAT_1E2), |
| 3057 | OP32 ("fmuld", |
| 3058 | OPCODE_INFO3 (0xf4000a00, |
| 3059 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 3060 | (16_19, FREG, OPRND_SHIFT_0_BIT), |
| 3061 | (21_24, FREG, OPRND_SHIFT_0_BIT)), |
| 3062 | CSKY_ISA_FLOAT_1E2), |
| 3063 | OP32 ("fnmuld", |
| 3064 | OPCODE_INFO3 (0xf4000a20, |
| 3065 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 3066 | (16_19, FREG, OPRND_SHIFT_0_BIT), |
| 3067 | (21_24, FREG, OPRND_SHIFT_0_BIT)), |
| 3068 | CSKY_ISA_FLOAT_1E2), |
| 3069 | OP32 ("fmacd", |
| 3070 | OPCODE_INFO3 (0xf4000a80, |
| 3071 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 3072 | (16_19, FREG, OPRND_SHIFT_0_BIT), |
| 3073 | (21_24, FREG, OPRND_SHIFT_0_BIT)), |
| 3074 | CSKY_ISA_FLOAT_1E2), |
| 3075 | OP32 ("fmscd", |
| 3076 | OPCODE_INFO3 (0xf4000aa0, |
| 3077 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 3078 | (16_19, FREG, OPRND_SHIFT_0_BIT), |
| 3079 | (21_24, FREG, OPRND_SHIFT_0_BIT)), |
| 3080 | CSKY_ISA_FLOAT_1E2), |
| 3081 | OP32 ("fnmacd", |
| 3082 | OPCODE_INFO3 (0xf4000ac0, |
| 3083 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 3084 | (16_19, FREG, OPRND_SHIFT_0_BIT), |
| 3085 | (21_24, FREG, OPRND_SHIFT_0_BIT)), |
| 3086 | CSKY_ISA_FLOAT_1E2), |
| 3087 | OP32 ("fnmscd", |
| 3088 | OPCODE_INFO3 (0xf4000ae0, |
| 3089 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 3090 | (16_19, FREG, OPRND_SHIFT_0_BIT), |
| 3091 | (21_24, FREG, OPRND_SHIFT_0_BIT)), |
| 3092 | CSKY_ISA_FLOAT_1E2), |
| 3093 | OP32 ("fdivd", |
| 3094 | OPCODE_INFO3 (0xf4000b00, |
| 3095 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 3096 | (16_19, FREG, OPRND_SHIFT_0_BIT), |
| 3097 | (21_24, FREG, OPRND_SHIFT_0_BIT)), |
| 3098 | CSKY_ISA_FLOAT_1E2), |
| 3099 | OP32 ("frecipd", |
| 3100 | OPCODE_INFO2 (0xf4000b20, |
| 3101 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 3102 | (16_19, FREG, OPRND_SHIFT_0_BIT)), |
| 3103 | CSKY_ISA_FLOAT_1E2), |
| 3104 | OP32 ("fsqrtd", |
| 3105 | OPCODE_INFO2 (0xf4000b40, |
| 3106 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 3107 | (16_19, FREG, OPRND_SHIFT_0_BIT)), |
| 3108 | CSKY_ISA_FLOAT_1E2), |
| 3109 | OP32 ("faddm", |
| 3110 | OPCODE_INFO3 (0xf4001000, |
| 3111 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 3112 | (16_19, FREG, OPRND_SHIFT_0_BIT), |
| 3113 | (21_24, FREG, OPRND_SHIFT_0_BIT)), |
| 3114 | CSKY_ISA_FLOAT_1E2), |
| 3115 | OP32 ("fsubm", |
| 3116 | OPCODE_INFO3 (0xf4001020, |
| 3117 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 3118 | (16_19, FREG, OPRND_SHIFT_0_BIT), |
| 3119 | (21_24, FREG, OPRND_SHIFT_0_BIT)), |
| 3120 | CSKY_ISA_FLOAT_1E2), |
| 3121 | OP32 ("fmovm", |
| 3122 | OPCODE_INFO2 (0xf4001080, |
| 3123 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 3124 | (16_19, FREG, OPRND_SHIFT_0_BIT)), |
| 3125 | CSKY_ISA_FLOAT_1E2), |
| 3126 | OP32 ("fabsm", |
| 3127 | OPCODE_INFO2 (0xf40010c0, |
| 3128 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 3129 | (16_19, FREG, OPRND_SHIFT_0_BIT)), |
| 3130 | CSKY_ISA_FLOAT_1E2), |
| 3131 | OP32 ("fnegm", |
| 3132 | OPCODE_INFO2 (0xf40010e0, |
| 3133 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 3134 | (16_19, FREG, OPRND_SHIFT_0_BIT)), |
| 3135 | CSKY_ISA_FLOAT_1E2), |
| 3136 | OP32 ("fmulm", |
| 3137 | OPCODE_INFO3 (0xf4001200, |
| 3138 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 3139 | (16_19, FREG, OPRND_SHIFT_0_BIT), |
| 3140 | (21_24, FREG, OPRND_SHIFT_0_BIT)), |
| 3141 | CSKY_ISA_FLOAT_1E2), |
| 3142 | OP32 ("fnmulm", |
| 3143 | OPCODE_INFO3 (0xf4001220, |
| 3144 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 3145 | (16_19, FREG, OPRND_SHIFT_0_BIT), |
| 3146 | (21_24, FREG, OPRND_SHIFT_0_BIT)), |
| 3147 | CSKY_ISA_FLOAT_1E2), |
| 3148 | OP32 ("fmacm", |
| 3149 | OPCODE_INFO3 (0xf4001280, |
| 3150 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 3151 | (16_19, FREG, OPRND_SHIFT_0_BIT), |
| 3152 | (21_24, FREG, OPRND_SHIFT_0_BIT)), |
| 3153 | CSKY_ISA_FLOAT_1E2), |
| 3154 | OP32 ("fmscm", |
| 3155 | OPCODE_INFO3 (0xf40012a0, |
| 3156 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 3157 | (16_19, FREG, OPRND_SHIFT_0_BIT), |
| 3158 | (21_24, FREG, OPRND_SHIFT_0_BIT)), |
| 3159 | CSKY_ISA_FLOAT_1E2), |
| 3160 | OP32 ("fnmacm", |
| 3161 | OPCODE_INFO3 (0xf40012c0, |
| 3162 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 3163 | (16_19, FREG, OPRND_SHIFT_0_BIT), |
| 3164 | (21_24, FREG, OPRND_SHIFT_0_BIT)), |
| 3165 | CSKY_ISA_FLOAT_1E2), |
| 3166 | OP32 ("fnmscm", |
| 3167 | OPCODE_INFO3 (0xf40012e0, |
| 3168 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 3169 | (16_19, FREG, OPRND_SHIFT_0_BIT), |
| 3170 | (21_24, FREG, OPRND_SHIFT_0_BIT)), |
| 3171 | CSKY_ISA_FLOAT_1E2), |
| 3172 | OP32 ("fstosi.rn", |
| 3173 | OPCODE_INFO2 (0xf4001800, |
| 3174 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 3175 | (16_19, FREG, OPRND_SHIFT_0_BIT)), |
| 3176 | CSKY_ISA_FLOAT_E1), |
| 3177 | OP32 ("fstosi.rz", |
| 3178 | OPCODE_INFO2 (0xf4001820, |
| 3179 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 3180 | (16_19, FREG, OPRND_SHIFT_0_BIT)), |
| 3181 | CSKY_ISA_FLOAT_E1), |
| 3182 | OP32 ("fstosi.rpi", |
| 3183 | OPCODE_INFO2 (0xf4001840, |
| 3184 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 3185 | (16_19, FREG, OPRND_SHIFT_0_BIT)), |
| 3186 | CSKY_ISA_FLOAT_E1), |
| 3187 | OP32 ("fstosi.rni", |
| 3188 | OPCODE_INFO2 (0xf4001860, |
| 3189 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 3190 | (16_19, FREG, OPRND_SHIFT_0_BIT)), |
| 3191 | CSKY_ISA_FLOAT_E1), |
| 3192 | OP32 ("fstoui.rn", |
| 3193 | OPCODE_INFO2 (0xf4001880, |
| 3194 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 3195 | (16_19, FREG, OPRND_SHIFT_0_BIT)), |
| 3196 | CSKY_ISA_FLOAT_E1), |
| 3197 | OP32 ("fstoui.rz", |
| 3198 | OPCODE_INFO2 (0xf40018a0, |
| 3199 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 3200 | (16_19, FREG, OPRND_SHIFT_0_BIT)), |
| 3201 | CSKY_ISA_FLOAT_E1), |
| 3202 | OP32 ("fstoui.rpi", |
| 3203 | OPCODE_INFO2 (0xf40018c0, |
| 3204 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 3205 | (16_19, FREG, OPRND_SHIFT_0_BIT)), |
| 3206 | CSKY_ISA_FLOAT_E1), |
| 3207 | OP32 ("fstoui.rni", |
| 3208 | OPCODE_INFO2 (0xf40018e0, |
| 3209 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 3210 | (16_19, FREG, OPRND_SHIFT_0_BIT)), |
| 3211 | CSKY_ISA_FLOAT_E1), |
| 3212 | OP32 ("fdtosi.rn", |
| 3213 | OPCODE_INFO2 (0xf4001900, |
| 3214 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 3215 | (16_19, FREG, OPRND_SHIFT_0_BIT)), |
| 3216 | CSKY_ISA_FLOAT_1E2), |
| 3217 | OP32 ("fdtosi.rz", |
| 3218 | OPCODE_INFO2 (0xf4001920, |
| 3219 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 3220 | (16_19, FREG, OPRND_SHIFT_0_BIT)), |
| 3221 | CSKY_ISA_FLOAT_1E2), |
| 3222 | OP32 ("fdtosi.rpi", |
| 3223 | OPCODE_INFO2 (0xf4001940, |
| 3224 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 3225 | (16_19, FREG, OPRND_SHIFT_0_BIT)), |
| 3226 | CSKY_ISA_FLOAT_1E2), |
| 3227 | OP32 ("fdtosi.rni", |
| 3228 | OPCODE_INFO2 (0xf4001960, |
| 3229 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 3230 | (16_19, FREG, OPRND_SHIFT_0_BIT)), |
| 3231 | CSKY_ISA_FLOAT_1E2), |
| 3232 | OP32 ("fdtoui.rn", |
| 3233 | OPCODE_INFO2 (0xf4001980, |
| 3234 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 3235 | (16_19, FREG, OPRND_SHIFT_0_BIT)), |
| 3236 | CSKY_ISA_FLOAT_1E2), |
| 3237 | OP32 ("fdtoui.rz", |
| 3238 | OPCODE_INFO2 (0xf40019a0, |
| 3239 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 3240 | (16_19, FREG, OPRND_SHIFT_0_BIT)), |
| 3241 | CSKY_ISA_FLOAT_1E2), |
| 3242 | OP32 ("fdtoui.rpi", |
| 3243 | OPCODE_INFO2 (0xf40019c0, |
| 3244 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 3245 | (16_19, FREG, OPRND_SHIFT_0_BIT)), |
| 3246 | CSKY_ISA_FLOAT_1E2), |
| 3247 | OP32 ("fdtoui.rni", |
| 3248 | OPCODE_INFO2 (0xf40019e0, |
| 3249 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 3250 | (16_19, FREG, OPRND_SHIFT_0_BIT)), |
| 3251 | CSKY_ISA_FLOAT_1E2), |
| 3252 | OP32 ("fsitos", |
| 3253 | OPCODE_INFO2 (0xf4001a00, |
| 3254 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 3255 | (16_19, FREG, OPRND_SHIFT_0_BIT)), |
| 3256 | CSKY_ISA_FLOAT_E1), |
| 3257 | OP32 ("fuitos", |
| 3258 | OPCODE_INFO2 (0xf4001a20, |
| 3259 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 3260 | (16_19, FREG, OPRND_SHIFT_0_BIT)), |
| 3261 | CSKY_ISA_FLOAT_E1), |
| 3262 | OP32 ("fsitod", |
| 3263 | OPCODE_INFO2 (0xf4001a80, |
| 3264 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 3265 | (16_19, FREG, OPRND_SHIFT_0_BIT)), |
| 3266 | CSKY_ISA_FLOAT_1E2), |
| 3267 | OP32 ("fuitod", |
| 3268 | OPCODE_INFO2 (0xf4001aa0, |
| 3269 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 3270 | (16_19, FREG, OPRND_SHIFT_0_BIT)), |
| 3271 | CSKY_ISA_FLOAT_1E2), |
| 3272 | OP32 ("fdtos", |
| 3273 | OPCODE_INFO2 (0xf4001ac0, |
| 3274 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 3275 | (16_19, FREG, OPRND_SHIFT_0_BIT)), |
| 3276 | CSKY_ISA_FLOAT_1E2), |
| 3277 | OP32 ("fstod", |
| 3278 | OPCODE_INFO2 (0xf4001ae0, |
| 3279 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 3280 | (16_19, FREG, OPRND_SHIFT_0_BIT)), |
| 3281 | CSKY_ISA_FLOAT_1E2), |
| 3282 | OP32 ("fmfvrh", |
| 3283 | OPCODE_INFO2 (0xf4001b00, |
| 3284 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 3285 | (16_19, FREG, OPRND_SHIFT_0_BIT)), |
| 3286 | CSKY_ISA_FLOAT_1E2), |
| 3287 | OP32 ("fmfvrl", |
| 3288 | OPCODE_INFO2 (0xf4001b20, |
| 3289 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 3290 | (16_19, FREG, OPRND_SHIFT_0_BIT)), |
| 3291 | CSKY_ISA_FLOAT_E1), |
| 3292 | OP32 ("fmtvrh", |
| 3293 | OPCODE_INFO2 (0xf4001b40, |
| 3294 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 3295 | (16_20, AREG, OPRND_SHIFT_0_BIT)), |
| 3296 | CSKY_ISA_FLOAT_1E2), |
| 3297 | OP32 ("fmtvrl", |
| 3298 | OPCODE_INFO2 (0xf4001b60, |
| 3299 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 3300 | (16_20, AREG, OPRND_SHIFT_0_BIT)), |
| 3301 | CSKY_ISA_FLOAT_E1), |
| 3302 | OP32 ("flds", |
| 3303 | SOPCODE_INFO2 (0xf4002000, |
| 3304 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 3305 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), |
| 3306 | (4_7or21_24, IMM_FLDST, OPRND_SHIFT_2_BIT))), |
| 3307 | CSKY_ISA_FLOAT_E1), |
| 3308 | OP32 ("fldd", |
| 3309 | SOPCODE_INFO2 (0xf4002100, |
| 3310 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 3311 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), |
| 3312 | (4_7or21_24, IMM_FLDST, OPRND_SHIFT_2_BIT))), |
| 3313 | CSKY_ISA_FLOAT_1E2), |
| 3314 | OP32 ("fldm", |
| 3315 | SOPCODE_INFO2 (0xf4002200, |
| 3316 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 3317 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), |
| 3318 | (4_7or21_24, IMM_FLDST, OPRND_SHIFT_3_BIT))), |
| 3319 | CSKY_ISA_FLOAT_1E2), |
| 3320 | OP32 ("fsts", |
| 3321 | SOPCODE_INFO2 (0xf4002400, |
| 3322 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 3323 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), |
| 3324 | (4_7or21_24, IMM_FLDST, OPRND_SHIFT_2_BIT))), |
| 3325 | CSKY_ISA_FLOAT_E1), |
| 3326 | OP32 ("fstd", |
| 3327 | SOPCODE_INFO2 (0xf4002500, |
| 3328 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 3329 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), |
| 3330 | (4_7or21_24, IMM_FLDST, OPRND_SHIFT_2_BIT))), |
| 3331 | CSKY_ISA_FLOAT_1E2), |
| 3332 | OP32 ("fstm", |
| 3333 | SOPCODE_INFO2 (0xf4002600, |
| 3334 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 3335 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), |
| 3336 | (4_7or21_24, IMM_FLDST, OPRND_SHIFT_3_BIT))), |
| 3337 | CSKY_ISA_FLOAT_1E2), |
| 3338 | OP32 ("fldrs", |
| 3339 | SOPCODE_INFO2 (0xf4002800, |
| 3340 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 3341 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), |
| 3342 | (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), |
| 3343 | CSKY_ISA_FLOAT_E1), |
| 3344 | OP32 ("fstrs", |
| 3345 | SOPCODE_INFO2 (0xf4002c00, |
| 3346 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 3347 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), |
| 3348 | (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), |
| 3349 | CSKY_ISA_FLOAT_E1), |
| 3350 | OP32 ("fldrd", |
| 3351 | SOPCODE_INFO2 (0xf4002900, |
| 3352 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 3353 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), |
| 3354 | (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), |
| 3355 | CSKY_ISA_FLOAT_1E2), |
| 3356 | OP32 ("fldrm", |
| 3357 | SOPCODE_INFO2 (0xf4002a00, |
| 3358 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 3359 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), |
| 3360 | (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), |
| 3361 | CSKY_ISA_FLOAT_1E2), |
| 3362 | OP32 ("fstrd", |
| 3363 | SOPCODE_INFO2 (0xf4002d00, |
| 3364 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 3365 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), |
| 3366 | (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), |
| 3367 | CSKY_ISA_FLOAT_1E2), |
| 3368 | OP32 ("fstrm", |
| 3369 | SOPCODE_INFO2 (0xf4002e00, |
| 3370 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 3371 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), |
| 3372 | (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), |
| 3373 | CSKY_ISA_FLOAT_1E2), |
| 3374 | OP32 ("fldms", |
| 3375 | OPCODE_INFO2 (0xf4003000, |
| 3376 | (0_3or21_24, FREGLIST_DASH, OPRND_SHIFT_0_BIT), |
| 3377 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), |
| 3378 | CSKY_ISA_FLOAT_E1), |
| 3379 | OP32 ("fldmd", |
| 3380 | OPCODE_INFO2 (0xf4003100, |
| 3381 | (0_3or21_24, FREGLIST_DASH, OPRND_SHIFT_0_BIT), |
| 3382 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), |
| 3383 | CSKY_ISA_FLOAT_1E2), |
| 3384 | OP32 ("fldmm", |
| 3385 | OPCODE_INFO2 (0xf4003200, |
| 3386 | (0_3or21_24, FREGLIST_DASH, OPRND_SHIFT_0_BIT), |
| 3387 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), |
| 3388 | CSKY_ISA_FLOAT_1E2), |
| 3389 | OP32 ("fstms", |
| 3390 | OPCODE_INFO2 (0xf4003400, |
| 3391 | (0_3or21_24, FREGLIST_DASH, OPRND_SHIFT_0_BIT), |
| 3392 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), |
| 3393 | CSKY_ISA_FLOAT_E1), |
| 3394 | OP32 ("fstmd", |
| 3395 | OPCODE_INFO2 (0xf4003500, |
| 3396 | (0_3or21_24, FREGLIST_DASH, OPRND_SHIFT_0_BIT), |
| 3397 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), |
| 3398 | CSKY_ISA_FLOAT_1E2), |
| 3399 | OP32 ("fstmm", |
| 3400 | OPCODE_INFO2 (0xf4003600, |
| 3401 | (0_3or21_24, FREGLIST_DASH, OPRND_SHIFT_0_BIT), |
| 3402 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), |
| 3403 | CSKY_ISA_FLOAT_1E2), |
| 3404 | DOP32 ("sync", |
| 3405 | OPCODE_INFO1 (0xc0000420, |
| 3406 | (21_25, IMM5b, OPRND_SHIFT_0_BIT)), |
| 3407 | OPCODE_INFO0 (0xc0000420), |
| 3408 | CSKYV2_ISA_E1), |
| 3409 | DOP32 ("idly", |
| 3410 | OPCODE_INFO1 (0xc0001c20, |
| 3411 | (21_25, OIMM5b_IDLY, OPRND_SHIFT_0_BIT)), |
| 3412 | OPCODE_INFO0 (0xc0601c20), |
| 3413 | CSKYV2_ISA_E1), |
| 3414 | |
| 3415 | #undef _RELOC32 |
| 3416 | #define _RELOC32 BFD_RELOC_CKCORE_PCREL_IMM18BY2 |
| 3417 | OP32 ("grs", |
| 3418 | OPCODE_INFO2 (0xcc0c0000, |
| 3419 | (21_25, AREG, OPRND_SHIFT_0_BIT), |
| 3420 | (0_17, IMM_OFF18b, OPRND_SHIFT_1_BIT)), |
| 3421 | CSKYV2_ISA_2E3), |
| 3422 | #undef _RELOC32 |
| 3423 | #define _RELOC32 0 |
| 3424 | DOP32 ("ixh", |
| 3425 | OPCODE_INFO3 (0xc4000820, |
| 3426 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 3427 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 3428 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 3429 | OPCODE_INFO2 (0xc4000820, |
| 3430 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), |
| 3431 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 3432 | CSKYV2_ISA_1E2), |
| 3433 | DOP32 ("ixw", |
| 3434 | OPCODE_INFO3 (0xc4000840, |
| 3435 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 3436 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 3437 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 3438 | OPCODE_INFO2 (0xc4000840, |
| 3439 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), |
| 3440 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 3441 | CSKYV2_ISA_1E2), |
| 3442 | OP32 ("ixd", |
| 3443 | OPCODE_INFO3 (0xc4000880, |
| 3444 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 3445 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 3446 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 3447 | CSKYV2_ISA_2E3), |
| 3448 | DOP32 ("divu", |
| 3449 | OPCODE_INFO3 (0xc4008020, |
| 3450 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 3451 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 3452 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 3453 | OPCODE_INFO2 (0xc4008020, |
| 3454 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), |
| 3455 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 3456 | CSKYV2_ISA_2E3), |
| 3457 | DOP32 ("divs", |
| 3458 | OPCODE_INFO3 (0xc4008040, |
| 3459 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 3460 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 3461 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 3462 | OPCODE_INFO2 (0xc4008040, |
| 3463 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), |
| 3464 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 3465 | CSKYV2_ISA_2E3), |
| 3466 | OP32 ("pldr", |
| 3467 | SOPCODE_INFO1 (0xd8006000, |
| 3468 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), |
| 3469 | (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), |
| 3470 | CSKY_ISA_CACHE), |
| 3471 | OP32 ("pldw", |
| 3472 | SOPCODE_INFO1 (0xdc006000, |
| 3473 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), |
| 3474 | (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), |
| 3475 | CSKY_ISA_CACHE), |
| 3476 | OP32 ("cprgr", |
| 3477 | SOPCODE_INFO2 (0xfc000000, |
| 3478 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 3479 | ABRACKET_OPRND ((21_25, IMM5b, OPRND_SHIFT_0_BIT), |
| 3480 | (0_11 , IMM12b, OPRND_SHIFT_0_BIT))), |
| 3481 | CSKYV2_ISA_E1), |
| 3482 | OP32 ("cpwgr", |
| 3483 | SOPCODE_INFO2 (0xfc001000, |
| 3484 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 3485 | ABRACKET_OPRND ((21_25, IMM5b, OPRND_SHIFT_0_BIT), |
| 3486 | (0_11 , IMM12b, OPRND_SHIFT_0_BIT))), |
| 3487 | CSKYV2_ISA_E1), |
| 3488 | OP32 ("cprcr", |
| 3489 | SOPCODE_INFO2 (0xfc002000, |
| 3490 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 3491 | ABRACKET_OPRND ((21_25, IMM5b, OPRND_SHIFT_0_BIT), |
| 3492 | (0_11 , IMM12b, OPRND_SHIFT_0_BIT))), |
| 3493 | CSKYV2_ISA_E1), |
| 3494 | OP32 ("cpwcr", |
| 3495 | SOPCODE_INFO2 (0xfc003000, |
| 3496 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 3497 | ABRACKET_OPRND ((21_25, IMM5b, OPRND_SHIFT_0_BIT), |
| 3498 | (0_11 , IMM12b, OPRND_SHIFT_0_BIT))), |
| 3499 | CSKYV2_ISA_E1), |
| 3500 | OP32 ("cprc", |
| 3501 | SOPCODE_INFO1 (0xfc004000, |
| 3502 | ABRACKET_OPRND ((21_25, IMM5b, OPRND_SHIFT_0_BIT), |
| 3503 | (0_11, IMM12b, OPRND_SHIFT_0_BIT))), |
| 3504 | CSKYV2_ISA_E1), |
| 3505 | OP32 ("cpop", |
| 3506 | SOPCODE_INFO1 (0xfc008000, |
| 3507 | ABRACKET_OPRND ((21_25, IMM5b, OPRND_SHIFT_0_BIT), |
| 3508 | (0_14or16_20 , IMM15b, OPRND_SHIFT_0_BIT))), |
| 3509 | CSKYV2_ISA_E1), |
| 3510 | |
| 3511 | OP16_OP32 ("push", |
| 3512 | OPCODE_INFO_LIST (0x14c0, |
| 3513 | (0_4, REGLIST_DASH_COMMA, OPRND_SHIFT_0_BIT)), |
| 3514 | CSKYV2_ISA_E1, |
| 3515 | OPCODE_INFO_LIST (0xebe00000, |
| 3516 | (0_8, REGLIST_DASH_COMMA, OPRND_SHIFT_0_BIT)), |
| 3517 | CSKYV2_ISA_2E3), |
| 3518 | #undef _TRANSFER |
| 3519 | #define _TRANSFER 2 |
| 3520 | OP16_OP32 ("pop", |
| 3521 | OPCODE_INFO_LIST (0x1480, |
| 3522 | (0_4, REGLIST_DASH_COMMA, OPRND_SHIFT_0_BIT)), |
| 3523 | CSKYV2_ISA_E1, |
| 3524 | OPCODE_INFO_LIST (0xebc00000, |
| 3525 | (0_8, REGLIST_DASH_COMMA, OPRND_SHIFT_0_BIT)), |
| 3526 | CSKYV2_ISA_2E3), |
| 3527 | #undef _TRANSFER |
| 3528 | #define _TRANSFER 0 |
| 3529 | OP16_OP32 ("movi", |
| 3530 | OPCODE_INFO2 (0x3000, |
| 3531 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT), |
| 3532 | (0_7, IMM8b, OPRND_SHIFT_0_BIT)), |
| 3533 | CSKYV2_ISA_E1, |
| 3534 | OPCODE_INFO2 (0xea000000, |
| 3535 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 3536 | (0_15, IMM16b, OPRND_SHIFT_0_BIT)), |
| 3537 | CSKYV2_ISA_1E2), |
| 3538 | /* bmaski will transfer to movi when imm < 17. */ |
| 3539 | OP16_OP32 ("bmaski", |
| 3540 | OPCODE_INFO2 (0x3000, |
| 3541 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT), |
| 3542 | (0_7, IMM8b_BMASKI, OPRND_SHIFT_0_BIT)), |
| 3543 | CSKYV2_ISA_1E2, |
| 3544 | OPCODE_INFO2 (0xc4005020, |
| 3545 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 3546 | (21_25, OIMM5b_BMASKI, OPRND_SHIFT_0_BIT)), |
| 3547 | CSKYV2_ISA_1E2), |
| 3548 | OP16_OP32 ("cmphsi", |
| 3549 | OPCODE_INFO2 (0x3800, |
| 3550 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT), |
| 3551 | (0_4, OIMM5b, OPRND_SHIFT_0_BIT)), |
| 3552 | CSKYV2_ISA_E1, |
| 3553 | OPCODE_INFO2 (0xeb000000, |
| 3554 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 3555 | (0_15, OIMM16b, OPRND_SHIFT_0_BIT)), |
| 3556 | CSKYV2_ISA_1E2), |
| 3557 | OP16_OP32 ("cmplti", |
| 3558 | OPCODE_INFO2 (0x3820, |
| 3559 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT), |
| 3560 | (0_4, OIMM5b, OPRND_SHIFT_0_BIT)), |
| 3561 | CSKYV2_ISA_E1, |
| 3562 | OPCODE_INFO2 (0xeb200000, |
| 3563 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 3564 | (0_15, OIMM16b, OPRND_SHIFT_0_BIT)), |
| 3565 | CSKYV2_ISA_1E2), |
| 3566 | OP16_OP32 ("cmpnei", |
| 3567 | OPCODE_INFO2 (0x3840, |
| 3568 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT), |
| 3569 | (0_4, IMM5b, OPRND_SHIFT_0_BIT)), |
| 3570 | CSKYV2_ISA_E1, |
| 3571 | OPCODE_INFO2 (0xeb400000, |
| 3572 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 3573 | (0_15, IMM16b, OPRND_SHIFT_0_BIT)), |
| 3574 | CSKYV2_ISA_1E2), |
| 3575 | #undef _TRANSFER |
| 3576 | #define _TRANSFER 1 |
| 3577 | OP16_OP32 ("jmpix", |
| 3578 | OPCODE_INFO2 (0x38e0, |
| 3579 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT), |
| 3580 | (0_1, IMM2b_JMPIX, OPRND_SHIFT_0_BIT)), |
| 3581 | CSKY_ISA_JAVA, |
| 3582 | OPCODE_INFO2 (0xe9e00000, |
| 3583 | (16_20, GREG0_7, OPRND_SHIFT_0_BIT), |
| 3584 | (0_1, IMM2b_JMPIX, OPRND_SHIFT_0_BIT)), |
| 3585 | CSKY_ISA_JAVA), |
| 3586 | #undef _TRANSFER |
| 3587 | #define _TRANSFER 0 |
| 3588 | DOP16_DOP32 ("bclri", |
| 3589 | OPCODE_INFO3 (0x3880, |
| 3590 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT), |
| 3591 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), |
| 3592 | (0_4, IMM5b, OPRND_SHIFT_0_BIT)), |
| 3593 | OPCODE_INFO2 (0x3880, |
| 3594 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT), |
| 3595 | (0_4, IMM5b, OPRND_SHIFT_0_BIT)), |
| 3596 | CSKYV2_ISA_E1, |
| 3597 | OPCODE_INFO3 (0xc4002820, |
| 3598 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 3599 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 3600 | (21_25, IMM5b, OPRND_SHIFT_0_BIT)), |
| 3601 | OPCODE_INFO2 (0xc4002820, |
| 3602 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), |
| 3603 | (21_25, IMM5b, OPRND_SHIFT_0_BIT)), |
| 3604 | CSKYV2_ISA_1E2), |
| 3605 | DOP16_DOP32 ("bseti", |
| 3606 | OPCODE_INFO3 (0x38a0, |
| 3607 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT), |
| 3608 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), |
| 3609 | (0_4, IMM5b, OPRND_SHIFT_0_BIT)), |
| 3610 | OPCODE_INFO2 (0x38a0, |
| 3611 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT), |
| 3612 | (0_4, IMM5b, OPRND_SHIFT_0_BIT)), |
| 3613 | CSKYV2_ISA_E1, |
| 3614 | OPCODE_INFO3 (0xc4002840, |
| 3615 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 3616 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 3617 | (21_25, IMM5b, OPRND_SHIFT_0_BIT)), |
| 3618 | OPCODE_INFO2 (0xc4002840, |
| 3619 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), |
| 3620 | (21_25, IMM5b, OPRND_SHIFT_0_BIT)), |
| 3621 | CSKYV2_ISA_1E2), |
| 3622 | OP16_OP32_WITH_WORK ("btsti", |
| 3623 | OPCODE_INFO2 (0x38c0, |
| 3624 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT), |
| 3625 | (0_4, IMM5b, OPRND_SHIFT_0_BIT)), |
| 3626 | CSKYV2_ISA_E1, |
| 3627 | OPCODE_INFO2 (0xc4002880, |
| 3628 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 3629 | (21_25, IMM5b, OPRND_SHIFT_0_BIT)), |
| 3630 | CSKYV2_ISA_1E2, v2_work_btsti), |
| 3631 | DOP16_DOP32 ("lsli", |
| 3632 | OPCODE_INFO3 (0x4000, |
| 3633 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), |
| 3634 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT), |
| 3635 | (0_4, IMM5b, OPRND_SHIFT_0_BIT)), |
| 3636 | OPCODE_INFO2 (0x4000, |
| 3637 | (5_7or8_10, DUP_GREG0_7, OPRND_SHIFT_0_BIT), |
| 3638 | (0_4, IMM5b, OPRND_SHIFT_0_BIT)), |
| 3639 | CSKYV2_ISA_E1, |
| 3640 | OPCODE_INFO3 (0xc4004820, |
| 3641 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 3642 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 3643 | (21_25, IMM5b, OPRND_SHIFT_0_BIT)), |
| 3644 | OPCODE_INFO2 (0xc4004820, |
| 3645 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), |
| 3646 | (21_25, IMM5b, OPRND_SHIFT_0_BIT)), |
| 3647 | CSKYV2_ISA_1E2), |
| 3648 | DOP16_DOP32 ("lsri", |
| 3649 | OPCODE_INFO3 (0x4800, |
| 3650 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), |
| 3651 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT), |
| 3652 | (0_4, IMM5b, OPRND_SHIFT_0_BIT)), |
| 3653 | OPCODE_INFO2 (0x4800, |
| 3654 | (5_7or8_10, DUP_GREG0_7, OPRND_SHIFT_0_BIT), |
| 3655 | (0_4, IMM5b, OPRND_SHIFT_0_BIT)), |
| 3656 | CSKYV2_ISA_E1, |
| 3657 | OPCODE_INFO3 (0xc4004840, |
| 3658 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 3659 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 3660 | (21_25, IMM5b, OPRND_SHIFT_0_BIT)), |
| 3661 | OPCODE_INFO2 (0xc4004840, |
| 3662 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), |
| 3663 | (21_25, IMM5b, OPRND_SHIFT_0_BIT)), |
| 3664 | CSKYV2_ISA_1E2), |
| 3665 | OP16_OP32 ("asri", |
| 3666 | OPCODE_INFO3 (0x5000, |
| 3667 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), |
| 3668 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT), |
| 3669 | (0_4, IMM5b, OPRND_SHIFT_0_BIT)), |
| 3670 | CSKYV2_ISA_E1, |
| 3671 | OPCODE_INFO3 (0xc4004880, |
| 3672 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 3673 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 3674 | (21_25, IMM5b, OPRND_SHIFT_0_BIT)), |
| 3675 | CSKYV2_ISA_1E2), |
| 3676 | DOP16_DOP32 ("addc", |
| 3677 | OPCODE_INFO2 (0x6001, |
| 3678 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), |
| 3679 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 3680 | OPCODE_INFO3 (0x6001, |
| 3681 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), |
| 3682 | (2_5, 2IN1_DUMMY, OPRND_SHIFT_0_BIT), |
| 3683 | (2_5, 2IN1_DUMMY, OPRND_SHIFT_0_BIT)), |
| 3684 | CSKYV2_ISA_E1, |
| 3685 | OPCODE_INFO3 (0xc4000040, |
| 3686 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 3687 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 3688 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 3689 | OPCODE_INFO2 (0xc4000040, |
| 3690 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), |
| 3691 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 3692 | CSKYV2_ISA_1E2), |
| 3693 | DOP16_DOP32 ("subc", |
| 3694 | OPCODE_INFO2 (0x6003, |
| 3695 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), |
| 3696 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 3697 | OPCODE_INFO3 (0x6003, |
| 3698 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), |
| 3699 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), |
| 3700 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 3701 | CSKYV2_ISA_E1, |
| 3702 | OPCODE_INFO3 (0xc4000100, |
| 3703 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 3704 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 3705 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 3706 | OPCODE_INFO2 (0xc4000100, |
| 3707 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), |
| 3708 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 3709 | CSKYV2_ISA_1E2), |
| 3710 | OP16_OP32 ("cmphs", |
| 3711 | OPCODE_INFO2 (0x6400, |
| 3712 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT), |
| 3713 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 3714 | CSKYV2_ISA_E1, |
| 3715 | OPCODE_INFO2 (0xc4000420, |
| 3716 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 3717 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 3718 | CSKYV2_ISA_2E3), |
| 3719 | OP16_OP32 ("cmplt", |
| 3720 | OPCODE_INFO2 (0x6401, |
| 3721 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT), |
| 3722 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 3723 | CSKYV2_ISA_E1, |
| 3724 | OPCODE_INFO2 (0xc4000440, |
| 3725 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 3726 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 3727 | CSKYV2_ISA_2E3), |
| 3728 | OP16_OP32 ("cmpne", |
| 3729 | OPCODE_INFO2 (0x6402, |
| 3730 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT), |
| 3731 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 3732 | CSKYV2_ISA_E1, |
| 3733 | OPCODE_INFO2 (0xc4000480, |
| 3734 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 3735 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 3736 | CSKYV2_ISA_2E3), |
| 3737 | OP16_OP32 ("mvcv", |
| 3738 | OPCODE_INFO1 (0x6403, |
| 3739 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 3740 | CSKYV2_ISA_E1, |
| 3741 | OPCODE_INFO1 (0xc4000600, |
| 3742 | (0_4, AREG, OPRND_SHIFT_0_BIT)), |
| 3743 | CSKYV2_ISA_2E3), |
| 3744 | DOP16_DOP32 ("and", |
| 3745 | OPCODE_INFO2 (0x6800, |
| 3746 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), |
| 3747 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 3748 | OPCODE_INFO3 (0x6800, |
| 3749 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), |
| 3750 | (2_5, 2IN1_DUMMY, OPRND_SHIFT_0_BIT), |
| 3751 | (2_5, 2IN1_DUMMY, OPRND_SHIFT_0_BIT)), |
| 3752 | CSKYV2_ISA_E1, |
| 3753 | OPCODE_INFO3 (0xc4002020, |
| 3754 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 3755 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 3756 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 3757 | OPCODE_INFO2 (0xc4002020, |
| 3758 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), |
| 3759 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 3760 | CSKYV2_ISA_1E2), |
| 3761 | DOP16_DOP32 ("andn", |
| 3762 | OPCODE_INFO2 (0x6801, |
| 3763 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), |
| 3764 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 3765 | OPCODE_INFO3 (0x6801, |
| 3766 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), |
| 3767 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), |
| 3768 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 3769 | CSKYV2_ISA_E1, |
| 3770 | OPCODE_INFO3 (0xc4002040, |
| 3771 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 3772 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 3773 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 3774 | OPCODE_INFO2 (0xc4002040, |
| 3775 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), |
| 3776 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 3777 | CSKYV2_ISA_1E2), |
| 3778 | OP16_OP32 ("tst", |
| 3779 | OPCODE_INFO2 (0x6802, |
| 3780 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT), |
| 3781 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 3782 | CSKYV2_ISA_E1, |
| 3783 | OPCODE_INFO2 (0xc4002080, |
| 3784 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 3785 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 3786 | CSKYV2_ISA_2E3), |
| 3787 | OP16_OP32 ("tstnbz", |
| 3788 | OPCODE_INFO1 (0x6803, |
| 3789 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 3790 | CSKYV2_ISA_E1, |
| 3791 | OPCODE_INFO1 (0xc4002100, |
| 3792 | (16_20, AREG, OPRND_SHIFT_0_BIT)), |
| 3793 | CSKYV2_ISA_2E3), |
| 3794 | DOP16_DOP32 ("or", |
| 3795 | OPCODE_INFO2 (0x6c00, |
| 3796 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), |
| 3797 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 3798 | OPCODE_INFO3 (0x6c00, |
| 3799 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), |
| 3800 | (2_5, 2IN1_DUMMY, OPRND_SHIFT_0_BIT), |
| 3801 | (2_5, 2IN1_DUMMY, OPRND_SHIFT_0_BIT)), |
| 3802 | CSKYV2_ISA_E1, |
| 3803 | OPCODE_INFO3 (0xc4002420, |
| 3804 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 3805 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 3806 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 3807 | OPCODE_INFO2 (0xc4002420, |
| 3808 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), |
| 3809 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 3810 | CSKYV2_ISA_1E2), |
| 3811 | DOP16_DOP32 ("xor", |
| 3812 | OPCODE_INFO2 (0x6c01, |
| 3813 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), |
| 3814 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 3815 | OPCODE_INFO3 (0x6c01, |
| 3816 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), |
| 3817 | (2_5, 2IN1_DUMMY, OPRND_SHIFT_0_BIT), |
| 3818 | (2_5, 2IN1_DUMMY, OPRND_SHIFT_0_BIT)), |
| 3819 | CSKYV2_ISA_E1, |
| 3820 | OPCODE_INFO3 (0xc4002440, |
| 3821 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 3822 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 3823 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 3824 | OPCODE_INFO2 (0xc4002440, |
| 3825 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), |
| 3826 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 3827 | CSKYV2_ISA_1E2), |
| 3828 | DOP16_DOP32 ("nor", |
| 3829 | OPCODE_INFO2 (0x6c02, |
| 3830 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), |
| 3831 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 3832 | OPCODE_INFO3 (0x6c02, |
| 3833 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), |
| 3834 | (2_5, 2IN1_DUMMY, OPRND_SHIFT_0_BIT), |
| 3835 | (2_5, 2IN1_DUMMY, OPRND_SHIFT_0_BIT)), |
| 3836 | CSKYV2_ISA_E1, |
| 3837 | OPCODE_INFO3 (0xc4002480, |
| 3838 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 3839 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 3840 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 3841 | OPCODE_INFO2 (0xc4002480, |
| 3842 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), |
| 3843 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 3844 | CSKYV2_ISA_1E2), |
| 3845 | OP16_OP32 ("mov", |
| 3846 | OPCODE_INFO2 (0x6c03, |
| 3847 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), |
| 3848 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 3849 | CSKYV2_ISA_E1, |
| 3850 | OPCODE_INFO2 (0xc4004820, |
| 3851 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 3852 | (16_20, AREG, OPRND_SHIFT_0_BIT)), |
| 3853 | CSKYV2_ISA_1E2), |
| 3854 | OP16_OP32 ("nop", |
| 3855 | OPCODE_INFO0 (0x6c03), |
| 3856 | CSKYV2_ISA_E1, |
| 3857 | OPCODE_INFO0 (0xc4004820), |
| 3858 | CSKYV2_ISA_E1), |
| 3859 | DOP16_DOP32 ("lsl", |
| 3860 | OPCODE_INFO2 (0x7000, |
| 3861 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), |
| 3862 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 3863 | OPCODE_INFO3 (0x7000, |
| 3864 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), |
| 3865 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), |
| 3866 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 3867 | CSKYV2_ISA_E1, |
| 3868 | OPCODE_INFO3 (0xc4004020, |
| 3869 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 3870 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 3871 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 3872 | OPCODE_INFO2 (0xc4004020, |
| 3873 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), |
| 3874 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 3875 | CSKYV2_ISA_1E2), |
| 3876 | DOP16_DOP32 ("lsr", |
| 3877 | OPCODE_INFO2 (0x7001, |
| 3878 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), |
| 3879 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 3880 | OPCODE_INFO3 (0x7001, |
| 3881 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), |
| 3882 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), |
| 3883 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 3884 | CSKYV2_ISA_E1, |
| 3885 | OPCODE_INFO3 (0xc4004040, |
| 3886 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 3887 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 3888 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 3889 | OPCODE_INFO2 (0xc4004040, |
| 3890 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), |
| 3891 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 3892 | CSKYV2_ISA_1E2), |
| 3893 | DOP16_DOP32 ("asr", |
| 3894 | OPCODE_INFO2 (0x7002, |
| 3895 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), |
| 3896 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 3897 | OPCODE_INFO3 (0x7002, |
| 3898 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), |
| 3899 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), |
| 3900 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 3901 | CSKYV2_ISA_E1, |
| 3902 | OPCODE_INFO3 (0xc4004080, |
| 3903 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 3904 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 3905 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 3906 | OPCODE_INFO2 (0xc4004080, |
| 3907 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), |
| 3908 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 3909 | CSKYV2_ISA_1E2), |
| 3910 | DOP16_DOP32 ("rotl", |
| 3911 | OPCODE_INFO2 (0x7003, |
| 3912 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), |
| 3913 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 3914 | OPCODE_INFO3 (0x7003, |
| 3915 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), |
| 3916 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), |
| 3917 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 3918 | CSKYV2_ISA_E1, |
| 3919 | OPCODE_INFO3 (0xc4004100, |
| 3920 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 3921 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 3922 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 3923 | OPCODE_INFO2 (0xc4004100, |
| 3924 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), |
| 3925 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 3926 | CSKYV2_ISA_1E2), |
| 3927 | DOP16_DOP32 ("zextb", |
| 3928 | OPCODE_INFO2 (0x7400, |
| 3929 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), |
| 3930 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 3931 | OPCODE_INFO1 (0x7400, |
| 3932 | (2_5or6_9, DUP_GREG0_15, OPRND_SHIFT_0_BIT)), |
| 3933 | CSKYV2_ISA_E1, |
| 3934 | OPCODE_INFO2 (0xc40054e0, |
| 3935 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 3936 | (16_20, AREG, OPRND_SHIFT_0_BIT)), |
| 3937 | OPCODE_INFO1 (0xc40054e0, |
| 3938 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT)), |
| 3939 | CSKYV2_ISA_2E3), |
| 3940 | DOP16_DOP32 ("zexth", |
| 3941 | OPCODE_INFO2 (0x7401, |
| 3942 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), |
| 3943 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 3944 | OPCODE_INFO1 (0x7401, |
| 3945 | (2_5or6_9, DUP_GREG0_15, OPRND_SHIFT_0_BIT)), |
| 3946 | CSKYV2_ISA_E1, |
| 3947 | OPCODE_INFO2 (0xc40055e0, |
| 3948 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 3949 | (16_20, AREG, OPRND_SHIFT_0_BIT)), |
| 3950 | OPCODE_INFO1 (0xc40055e0, |
| 3951 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT)), |
| 3952 | CSKYV2_ISA_2E3), |
| 3953 | DOP16_DOP32 ("sextb", |
| 3954 | OPCODE_INFO2 (0x7402, |
| 3955 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), |
| 3956 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 3957 | OPCODE_INFO1 (0x7402, |
| 3958 | (2_5or6_9, DUP_GREG0_15, OPRND_SHIFT_0_BIT)), |
| 3959 | CSKYV2_ISA_E1, |
| 3960 | OPCODE_INFO2 (0xc40058e0, |
| 3961 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 3962 | (16_20, AREG, OPRND_SHIFT_0_BIT)), |
| 3963 | OPCODE_INFO1 (0xc40058e0, |
| 3964 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT)), |
| 3965 | CSKYV2_ISA_2E3), |
| 3966 | DOP16_DOP32 ("sexth", |
| 3967 | OPCODE_INFO2 (0x7403, |
| 3968 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), |
| 3969 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 3970 | OPCODE_INFO1 (0x7403, |
| 3971 | (2_5or6_9, DUP_GREG0_15, OPRND_SHIFT_0_BIT)), |
| 3972 | CSKYV2_ISA_E1, |
| 3973 | OPCODE_INFO2 (0xc40059e0, |
| 3974 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 3975 | (16_20, AREG, OPRND_SHIFT_0_BIT)), |
| 3976 | OPCODE_INFO1 (0xc40059e0, |
| 3977 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT)), |
| 3978 | CSKYV2_ISA_2E3), |
| 3979 | OP32 ("zext", |
| 3980 | OPCODE_INFO4 (0xc4005400, |
| 3981 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 3982 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 3983 | (5_9, IMM5b, OPRND_SHIFT_0_BIT), |
| 3984 | (21_25, IMM5b, OPRND_SHIFT_0_BIT)), |
| 3985 | CSKYV2_ISA_2E3), |
| 3986 | OP32 ("sext", |
| 3987 | OPCODE_INFO4 (0xc4005800, |
| 3988 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 3989 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 3990 | (5_9, IMM5b, OPRND_SHIFT_0_BIT), |
| 3991 | (21_25, IMM5b, OPRND_SHIFT_0_BIT)), |
| 3992 | CSKYV2_ISA_2E3), |
| 3993 | #undef _TRANSFER |
| 3994 | #define _TRANSFER 2 |
| 3995 | OP16_OP32 ("rts", |
| 3996 | OPCODE_INFO0 (0x783c), |
| 3997 | CSKYV2_ISA_E1, |
| 3998 | OPCODE_INFO0 (0xe8cf0000), |
| 3999 | CSKYV2_ISA_E1), |
| 4000 | #undef _TRANSFER |
| 4001 | #define _TRANSFER 1 |
| 4002 | OP16_OP32 ("jmp", |
| 4003 | OPCODE_INFO1 (0x7800, |
| 4004 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 4005 | CSKYV2_ISA_E1, |
| 4006 | OPCODE_INFO1 (0xe8c00000, |
| 4007 | (16_20, AREG, OPRND_SHIFT_0_BIT)), |
| 4008 | CSKYV2_ISA_2E3), |
| 4009 | #undef _TRANSFER |
| 4010 | #define _TRANSFER 0 |
| 4011 | OP16_OP32 ("revb", |
| 4012 | OPCODE_INFO2 (0x7802, |
| 4013 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), |
| 4014 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 4015 | CSKYV2_ISA_1E2, |
| 4016 | OPCODE_INFO2 (0xc4006080, |
| 4017 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 4018 | (16_20, AREG, OPRND_SHIFT_0_BIT)), |
| 4019 | CSKYV2_ISA_2E3), |
| 4020 | OP16_OP32 ("revh", |
| 4021 | OPCODE_INFO2 (0x7803, |
| 4022 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), |
| 4023 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 4024 | CSKYV2_ISA_1E2, |
| 4025 | OPCODE_INFO2 (0xc4006100, |
| 4026 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 4027 | (16_20, AREG, OPRND_SHIFT_0_BIT)), |
| 4028 | CSKYV2_ISA_2E3), |
| 4029 | OP16_OP32 ("jsr", |
| 4030 | OPCODE_INFO1 (0x7bc1, |
| 4031 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 4032 | CSKYV2_ISA_E1, |
| 4033 | OPCODE_INFO1 (0xe8e00000, |
| 4034 | (16_20, AREG, OPRND_SHIFT_0_BIT)), |
| 4035 | CSKYV2_ISA_2E3), |
| 4036 | DOP16_DOP32 ("mult", |
| 4037 | OPCODE_INFO2 (0x7c00, |
| 4038 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), |
| 4039 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 4040 | OPCODE_INFO3 (0x7c00, |
| 4041 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), |
| 4042 | (2_5, 2IN1_DUMMY, OPRND_SHIFT_0_BIT), |
| 4043 | (2_5, 2IN1_DUMMY, OPRND_SHIFT_0_BIT)), |
| 4044 | CSKYV2_ISA_E1, |
| 4045 | OPCODE_INFO3 (0xc4008420, |
| 4046 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 4047 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4048 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 4049 | OPCODE_INFO2 (0xc4008420, |
| 4050 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), |
| 4051 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 4052 | CSKYV2_ISA_1E2), |
| 4053 | OP16 ("mul", |
| 4054 | OPCODE_INFO2 (0x7c00, |
| 4055 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), |
| 4056 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 4057 | CSKYV2_ISA_E1), |
| 4058 | DOP16_DOP32 ("mulsh", |
| 4059 | OPCODE_INFO2 (0x7c01, |
| 4060 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), |
| 4061 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 4062 | OPCODE_INFO3 (0x7c01, |
| 4063 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), |
| 4064 | (2_5, 2IN1_DUMMY, OPRND_SHIFT_0_BIT), |
| 4065 | (2_5, 2IN1_DUMMY, OPRND_SHIFT_0_BIT)), |
| 4066 | CSKYV2_ISA_2E3, |
| 4067 | OPCODE_INFO3 (0xc4009020, |
| 4068 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 4069 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4070 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 4071 | OPCODE_INFO2 (0xc4009020, |
| 4072 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), |
| 4073 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 4074 | CSKYV2_ISA_2E3), |
| 4075 | OP16 ("muls.h", |
| 4076 | OPCODE_INFO2 (0x7c01, |
| 4077 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), |
| 4078 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 4079 | CSKYV2_ISA_2E3), |
| 4080 | DOP32 ("mulsw", |
| 4081 | OPCODE_INFO3 (0xc4009420, |
| 4082 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 4083 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4084 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 4085 | OPCODE_INFO2 (0xc4009420, |
| 4086 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), |
| 4087 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 4088 | CSKY_ISA_DSP), |
| 4089 | OP16_OP32 ("ld.b", |
| 4090 | SOPCODE_INFO2 (0x8000, |
| 4091 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), |
| 4092 | BRACKET_OPRND ((8_10, GREG0_7, OPRND_SHIFT_0_BIT), |
| 4093 | (0_4, IMM_LDST, OPRND_SHIFT_0_BIT))), |
| 4094 | CSKYV2_ISA_E1, |
| 4095 | SOPCODE_INFO2 (0xd8000000, |
| 4096 | (21_25, AREG, OPRND_SHIFT_0_BIT), |
| 4097 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4098 | (0_11, IMM_LDST, OPRND_SHIFT_0_BIT))), |
| 4099 | CSKYV2_ISA_E1), |
| 4100 | OP16_OP32 ("ldb", |
| 4101 | SOPCODE_INFO2 (0x8000, |
| 4102 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), |
| 4103 | BRACKET_OPRND ((8_10, GREG0_7, OPRND_SHIFT_0_BIT), |
| 4104 | (0_4, IMM_LDST, OPRND_SHIFT_0_BIT))), |
| 4105 | CSKYV2_ISA_E1, |
| 4106 | SOPCODE_INFO2 (0xd8000000, |
| 4107 | (21_25, AREG, OPRND_SHIFT_0_BIT), |
| 4108 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4109 | (0_11, IMM_LDST, OPRND_SHIFT_0_BIT))), |
| 4110 | CSKYV2_ISA_E1), |
| 4111 | OP16_OP32 ("st.b", |
| 4112 | SOPCODE_INFO2 (0xa000, |
| 4113 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), |
| 4114 | BRACKET_OPRND ((8_10, GREG0_7, OPRND_SHIFT_0_BIT), |
| 4115 | (0_4, IMM_LDST, OPRND_SHIFT_0_BIT))), |
| 4116 | CSKYV2_ISA_E1, |
| 4117 | SOPCODE_INFO2 (0xdc000000, |
| 4118 | (21_25, AREG, OPRND_SHIFT_0_BIT), |
| 4119 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4120 | (0_11, IMM_LDST, OPRND_SHIFT_0_BIT))), |
| 4121 | CSKYV2_ISA_E1), |
| 4122 | OP16_OP32 ("stb", |
| 4123 | SOPCODE_INFO2 (0xa000, |
| 4124 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), |
| 4125 | BRACKET_OPRND ((8_10, GREG0_7, OPRND_SHIFT_0_BIT), |
| 4126 | (0_4, IMM_LDST, OPRND_SHIFT_0_BIT))), |
| 4127 | CSKYV2_ISA_E1, |
| 4128 | SOPCODE_INFO2 (0xdc000000, |
| 4129 | (21_25, AREG, OPRND_SHIFT_0_BIT), |
| 4130 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4131 | (0_11, IMM_LDST, OPRND_SHIFT_0_BIT))), |
| 4132 | CSKYV2_ISA_E1), |
| 4133 | |
| 4134 | OP16_OP32 ("ld.h", |
| 4135 | SOPCODE_INFO2 (0x8800, |
| 4136 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), |
| 4137 | BRACKET_OPRND ((8_10, GREG0_7, OPRND_SHIFT_0_BIT), |
| 4138 | (0_4, IMM_LDST, OPRND_SHIFT_1_BIT))), |
| 4139 | CSKYV2_ISA_E1, |
| 4140 | SOPCODE_INFO2 (0xd8001000, |
| 4141 | (21_25, AREG, OPRND_SHIFT_0_BIT), |
| 4142 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4143 | (0_11, IMM_LDST, OPRND_SHIFT_1_BIT))), |
| 4144 | CSKYV2_ISA_E1), |
| 4145 | OP16_OP32 ("ldh", |
| 4146 | SOPCODE_INFO2 (0x8800, |
| 4147 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), |
| 4148 | BRACKET_OPRND ((8_10, GREG0_7, OPRND_SHIFT_0_BIT), |
| 4149 | (0_4, IMM_LDST, OPRND_SHIFT_1_BIT))), |
| 4150 | CSKYV2_ISA_E1, |
| 4151 | SOPCODE_INFO2 (0xd8001000, |
| 4152 | (21_25, AREG, OPRND_SHIFT_0_BIT), |
| 4153 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4154 | (0_11, IMM_LDST, OPRND_SHIFT_1_BIT))), |
| 4155 | CSKYV2_ISA_E1), |
| 4156 | OP16_OP32 ("st.h", |
| 4157 | SOPCODE_INFO2 (0xa800, |
| 4158 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), |
| 4159 | BRACKET_OPRND ((8_10, GREG0_7, OPRND_SHIFT_0_BIT), |
| 4160 | (0_4, IMM_LDST, OPRND_SHIFT_1_BIT))), |
| 4161 | CSKYV2_ISA_E1, |
| 4162 | SOPCODE_INFO2 (0xdc001000, |
| 4163 | (21_25, AREG, OPRND_SHIFT_0_BIT), |
| 4164 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4165 | (0_11, IMM_LDST, OPRND_SHIFT_1_BIT))), |
| 4166 | CSKYV2_ISA_E1), |
| 4167 | OP16_OP32 ("sth", |
| 4168 | SOPCODE_INFO2 (0xa800, |
| 4169 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), |
| 4170 | BRACKET_OPRND ((8_10, GREG0_7, OPRND_SHIFT_0_BIT), |
| 4171 | (0_4, IMM_LDST, OPRND_SHIFT_1_BIT))), |
| 4172 | CSKYV2_ISA_E1, |
| 4173 | SOPCODE_INFO2 (0xdc001000, |
| 4174 | (21_25, AREG, OPRND_SHIFT_0_BIT), |
| 4175 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4176 | (0_11, IMM_LDST, OPRND_SHIFT_1_BIT))), |
| 4177 | CSKYV2_ISA_E1), |
| 4178 | DOP16_OP32 ("ld.w", |
| 4179 | SOPCODE_INFO2 (0x9000, |
| 4180 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), |
| 4181 | BRACKET_OPRND ((8_10, GREG0_7, OPRND_SHIFT_0_BIT), |
| 4182 | (0_4, IMM_LDST, OPRND_SHIFT_2_BIT))), |
| 4183 | SOPCODE_INFO2 (0x9800, |
| 4184 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), |
| 4185 | BRACKET_OPRND ((NONE, REGsp, OPRND_SHIFT_0_BIT), |
| 4186 | (0_4or8_10, IMM_LDST, OPRND_SHIFT_2_BIT))), |
| 4187 | CSKYV2_ISA_E1, |
| 4188 | SOPCODE_INFO2 (0xd8002000, |
| 4189 | (21_25, AREG, OPRND_SHIFT_0_BIT), |
| 4190 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4191 | (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), |
| 4192 | CSKYV2_ISA_E1), |
| 4193 | DOP16_OP32 ("ldw", |
| 4194 | SOPCODE_INFO2 (0x9000, |
| 4195 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), |
| 4196 | BRACKET_OPRND ((8_10, GREG0_7, OPRND_SHIFT_0_BIT), |
| 4197 | (0_4, IMM_LDST, OPRND_SHIFT_2_BIT))), |
| 4198 | SOPCODE_INFO2 (0x9800, |
| 4199 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), |
| 4200 | BRACKET_OPRND ((NONE, REGsp, OPRND_SHIFT_0_BIT), |
| 4201 | (0_4or8_10, IMM_LDST, OPRND_SHIFT_2_BIT))), |
| 4202 | CSKYV2_ISA_E1, |
| 4203 | SOPCODE_INFO2 (0xd8002000, |
| 4204 | (21_25, AREG, OPRND_SHIFT_0_BIT), |
| 4205 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4206 | (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), |
| 4207 | CSKYV2_ISA_E1), |
| 4208 | DOP16_OP32 ("ld", |
| 4209 | SOPCODE_INFO2 (0x9000, |
| 4210 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), |
| 4211 | BRACKET_OPRND ((8_10, GREG0_7, OPRND_SHIFT_0_BIT), |
| 4212 | (0_4, IMM_LDST, OPRND_SHIFT_0_BIT))), |
| 4213 | SOPCODE_INFO2 (0x9800, |
| 4214 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), |
| 4215 | BRACKET_OPRND ((NONE, REGsp, OPRND_SHIFT_0_BIT), |
| 4216 | (0_4or8_10, IMM_LDST, OPRND_SHIFT_2_BIT))), |
| 4217 | CSKYV2_ISA_E1, |
| 4218 | SOPCODE_INFO2 (0xd8002000, |
| 4219 | (21_25, AREG, OPRND_SHIFT_0_BIT), |
| 4220 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4221 | (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), |
| 4222 | CSKYV2_ISA_E1), |
| 4223 | DOP16_OP32 ("st.w", |
| 4224 | SOPCODE_INFO2 (0xb000, |
| 4225 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), |
| 4226 | BRACKET_OPRND ((8_10, GREG0_7, OPRND_SHIFT_0_BIT), |
| 4227 | (0_4, IMM_LDST, OPRND_SHIFT_2_BIT))), |
| 4228 | SOPCODE_INFO2 (0xb800, |
| 4229 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), |
| 4230 | BRACKET_OPRND ((NONE, REGsp, OPRND_SHIFT_0_BIT), |
| 4231 | (0_4or8_10, IMM_LDST, OPRND_SHIFT_2_BIT))), |
| 4232 | CSKYV2_ISA_E1, |
| 4233 | SOPCODE_INFO2 (0xdc002000, |
| 4234 | (21_25, AREG, OPRND_SHIFT_0_BIT), |
| 4235 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4236 | (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), |
| 4237 | CSKYV2_ISA_E1), |
| 4238 | DOP16_OP32 ("stw", |
| 4239 | SOPCODE_INFO2 (0xb000, |
| 4240 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), |
| 4241 | BRACKET_OPRND ((8_10, GREG0_7, OPRND_SHIFT_0_BIT), |
| 4242 | (0_4, IMM_LDST, OPRND_SHIFT_2_BIT))), |
| 4243 | SOPCODE_INFO2 (0xb800, |
| 4244 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), |
| 4245 | BRACKET_OPRND ((NONE, REGsp, OPRND_SHIFT_0_BIT), |
| 4246 | (0_4or8_10, IMM_LDST, OPRND_SHIFT_2_BIT))), |
| 4247 | CSKYV2_ISA_E1, |
| 4248 | SOPCODE_INFO2 (0xdc002000, |
| 4249 | (21_25, AREG, OPRND_SHIFT_0_BIT), |
| 4250 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4251 | (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), |
| 4252 | CSKYV2_ISA_E1), |
| 4253 | DOP16_OP32 ("st", |
| 4254 | SOPCODE_INFO2 (0xb000, |
| 4255 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), |
| 4256 | BRACKET_OPRND ((8_10, GREG0_7, OPRND_SHIFT_0_BIT), |
| 4257 | (0_4, IMM_LDST, OPRND_SHIFT_2_BIT))), |
| 4258 | SOPCODE_INFO2 (0xb800, |
| 4259 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), |
| 4260 | BRACKET_OPRND ((NONE, REGsp, OPRND_SHIFT_0_BIT), |
| 4261 | (0_4or8_10, IMM_LDST, OPRND_SHIFT_2_BIT))), |
| 4262 | CSKYV2_ISA_E1, |
| 4263 | SOPCODE_INFO2 (0xdc002000, |
| 4264 | (21_25, AREG, OPRND_SHIFT_0_BIT), |
| 4265 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4266 | (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), |
| 4267 | CSKYV2_ISA_E1), |
| 4268 | #ifdef BUILD_AS |
| 4269 | DOP16_DOP32_WITH_WORK ("addi", |
| 4270 | OPCODE_INFO2 (0x2000, |
| 4271 | (NONE, AREG, OPRND_SHIFT_0_BIT), |
| 4272 | (NONE, IMM32b, OPRND_SHIFT_0_BIT)), |
| 4273 | OPCODE_INFO3 (0x2000, |
| 4274 | (NONE, AREG, OPRND_SHIFT_0_BIT), |
| 4275 | (NONE, AREG, OPRND_SHIFT_0_BIT), |
| 4276 | (NONE, IMM32b, OPRND_SHIFT_0_BIT)), |
| 4277 | CSKYV2_ISA_E1, |
| 4278 | OPCODE_INFO2 (0xe4000000, |
| 4279 | (NONE, AREG, OPRND_SHIFT_0_BIT), |
| 4280 | (NONE, IMM32b, OPRND_SHIFT_0_BIT)), |
| 4281 | OPCODE_INFO3 (0xe4000000, |
| 4282 | (NONE, AREG, OPRND_SHIFT_0_BIT), |
| 4283 | (NONE, AREG, OPRND_SHIFT_0_BIT), |
| 4284 | (NONE, IMM32b, OPRND_SHIFT_0_BIT)), |
| 4285 | CSKYV2_ISA_1E2, |
| 4286 | v2_work_addi), |
| 4287 | #else |
| 4288 | DOP16 ("addi", |
| 4289 | OPCODE_INFO2 (0x2000, |
| 4290 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT), |
| 4291 | (0_7, OIMM8b, OPRND_SHIFT_0_BIT)), |
| 4292 | OPCODE_INFO3 (0x5802, |
| 4293 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), |
| 4294 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT), |
| 4295 | (2_4, OIMM3b, OPRND_SHIFT_0_BIT)), |
| 4296 | CSKYV2_ISA_E1), |
| 4297 | DOP16 ("addi", |
| 4298 | OPCODE_INFO3 (0x1800, |
| 4299 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT), |
| 4300 | (NONE, REGsp, OPRND_SHIFT_0_BIT), |
| 4301 | (0_7, IMM8b_LS2, OPRND_SHIFT_0_BIT)), |
| 4302 | OPCODE_INFO3 (0x1400, |
| 4303 | (NONE, REGsp, OPRND_SHIFT_0_BIT), |
| 4304 | (NONE, REGsp, OPRND_SHIFT_0_BIT), |
| 4305 | (0_4or8_9, IMM7b_LS2, OPRND_SHIFT_0_BIT)), |
| 4306 | CSKYV2_ISA_E1), |
| 4307 | DOP32 ("addi", |
| 4308 | OPCODE_INFO3 (0xe4000000, |
| 4309 | (21_25, AREG, OPRND_SHIFT_0_BIT), |
| 4310 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4311 | (0_11, OIMM12b, OPRND_SHIFT_0_BIT)), |
| 4312 | OPCODE_INFO3 (0xcc1c0000, |
| 4313 | (21_25, AREG, OPRND_SHIFT_0_BIT), |
| 4314 | (NONE, REG_r28, OPRND_SHIFT_0_BIT), |
| 4315 | (0_17, OIMM18b, OPRND_SHIFT_0_BIT)), |
| 4316 | CSKYV2_ISA_1E2), |
| 4317 | #endif |
| 4318 | #ifdef BUILD_AS |
| 4319 | DOP16_DOP32_WITH_WORK ("subi", |
| 4320 | OPCODE_INFO2 (0x2800, |
| 4321 | (NONE, AREG, OPRND_SHIFT_0_BIT), |
| 4322 | (NONE, IMM32b, OPRND_SHIFT_0_BIT)), |
| 4323 | OPCODE_INFO3 (0x2800, |
| 4324 | (NONE, AREG, OPRND_SHIFT_0_BIT), |
| 4325 | (NONE, AREG, OPRND_SHIFT_0_BIT), |
| 4326 | (NONE, IMM32b, OPRND_SHIFT_0_BIT)), |
| 4327 | CSKYV2_ISA_E1, |
| 4328 | OPCODE_INFO2 (0xe4001000, |
| 4329 | (NONE, AREG, OPRND_SHIFT_0_BIT), |
| 4330 | (NONE, IMM32b, OPRND_SHIFT_0_BIT)), |
| 4331 | OPCODE_INFO3 (0xe4001000, |
| 4332 | (NONE, AREG, OPRND_SHIFT_0_BIT), |
| 4333 | (NONE, AREG, OPRND_SHIFT_0_BIT), |
| 4334 | (NONE, IMM32b, OPRND_SHIFT_0_BIT)), |
| 4335 | CSKYV2_ISA_1E2, v2_work_subi), |
| 4336 | #else |
| 4337 | DOP16 ("subi", |
| 4338 | OPCODE_INFO2 (0x2800, |
| 4339 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT), |
| 4340 | (0_7, OIMM8b, OPRND_SHIFT_0_BIT)), |
| 4341 | OPCODE_INFO3 (0x5803, |
| 4342 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), |
| 4343 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT), |
| 4344 | (2_4, OIMM3b, OPRND_SHIFT_0_BIT)), |
| 4345 | CSKYV2_ISA_E1), |
| 4346 | OP32 ("subi", |
| 4347 | OPCODE_INFO3 (0xe4001000, |
| 4348 | (21_25, AREG, OPRND_SHIFT_0_BIT), |
| 4349 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4350 | (0_11, OIMM12b, OPRND_SHIFT_0_BIT)), |
| 4351 | CSKYV2_ISA_1E2), |
| 4352 | OP16 ("subi", |
| 4353 | OPCODE_INFO3 (0x1420, |
| 4354 | (NONE, REGsp, OPRND_SHIFT_0_BIT), |
| 4355 | (NONE, REGsp, OPRND_SHIFT_0_BIT), |
| 4356 | (0_4or8_9, IMM7b_LS2, OPRND_SHIFT_0_BIT)), |
| 4357 | CSKYV2_ISA_E1), |
| 4358 | #endif |
| 4359 | DOP16_DOP32_WITH_WORK ("addu", |
| 4360 | OPCODE_INFO2 (0x6000, |
| 4361 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), |
| 4362 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 4363 | OPCODE_INFO3 (0x5800, |
| 4364 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), |
| 4365 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT), |
| 4366 | (2_4, GREG0_7, OPRND_SHIFT_0_BIT)), |
| 4367 | CSKYV2_ISA_E1, |
| 4368 | OPCODE_INFO3 (0xc4000020, |
| 4369 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 4370 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4371 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 4372 | OPCODE_INFO2 (0xc4000020, |
| 4373 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), |
| 4374 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 4375 | CSKYV2_ISA_E1, |
| 4376 | v2_work_add_sub), |
| 4377 | DOP16_DOP32_WITH_WORK ("add", |
| 4378 | OPCODE_INFO2 (0x6000, |
| 4379 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), |
| 4380 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 4381 | OPCODE_INFO3 (0x5800, |
| 4382 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), |
| 4383 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT), |
| 4384 | (2_4, GREG0_7, OPRND_SHIFT_0_BIT)), |
| 4385 | CSKYV2_ISA_E1, |
| 4386 | OPCODE_INFO3 (0xc4000020, |
| 4387 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 4388 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4389 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 4390 | OPCODE_INFO2 (0xc4000020, |
| 4391 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), |
| 4392 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 4393 | CSKYV2_ISA_E1, |
| 4394 | v2_work_add_sub), |
| 4395 | DOP16_DOP32_WITH_WORK ("subu", |
| 4396 | OPCODE_INFO2 (0x6002, |
| 4397 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), |
| 4398 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 4399 | OPCODE_INFO3 (0x5801, |
| 4400 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), |
| 4401 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT), |
| 4402 | (2_4, GREG0_7, OPRND_SHIFT_0_BIT)), |
| 4403 | CSKYV2_ISA_E1, |
| 4404 | OPCODE_INFO3 (0xc4000080, |
| 4405 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 4406 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4407 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 4408 | OPCODE_INFO2 (0xc4000080, |
| 4409 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), |
| 4410 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 4411 | CSKYV2_ISA_E1, |
| 4412 | v2_work_add_sub), |
| 4413 | DOP16_DOP32_WITH_WORK ("sub", |
| 4414 | OPCODE_INFO2 (0x6002, |
| 4415 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), |
| 4416 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 4417 | OPCODE_INFO3 (0x5801, |
| 4418 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), |
| 4419 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT), |
| 4420 | (2_4, GREG0_7, OPRND_SHIFT_0_BIT)), |
| 4421 | CSKYV2_ISA_E1, |
| 4422 | OPCODE_INFO3 (0xc4000080, |
| 4423 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 4424 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4425 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 4426 | OPCODE_INFO2 (0xc4000080, |
| 4427 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), |
| 4428 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 4429 | CSKYV2_ISA_E1, |
| 4430 | v2_work_add_sub), |
| 4431 | OP32_WITH_WORK ("fmovis", |
| 4432 | OPCODE_INFO2 (0xf4001c00, |
| 4433 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 4434 | (4_7or16_24, SFLOAT, OPRND_SHIFT_2_BIT)), |
| 4435 | CSKY_ISA_FLOAT_1E3, |
| 4436 | float_work_fmovi), |
| 4437 | OP32_WITH_WORK ("fmovid", |
| 4438 | OPCODE_INFO2 (0xf4001e00, |
| 4439 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 4440 | (4_7or16_24, DFLOAT, OPRND_SHIFT_2_BIT)), |
| 4441 | CSKY_ISA_FLOAT_3E4, |
| 4442 | float_work_fmovi), |
| 4443 | #undef _RELOC32 |
| 4444 | #define _RELOC32 BFD_RELOC_CKCORE_PCREL_IMM26BY2 |
| 4445 | OP32 ("bsr", |
| 4446 | OPCODE_INFO1 (0xe0000000, |
| 4447 | (0_25, OFF26b, OPRND_SHIFT_1_BIT)), |
| 4448 | CSKYV2_ISA_E1), |
| 4449 | #undef _RELOC32 |
| 4450 | #define _RELOC32 BFD_RELOC_CKCORE_DOFFSET_IMM18 |
| 4451 | OP32 ("lrs.b", |
| 4452 | OPCODE_INFO2 (0xcc000000, |
| 4453 | (21_25, AREG, OPRND_SHIFT_0_BIT), |
| 4454 | (0_17, LABEL_WITH_BRACKET, OPRND_SHIFT_0_BIT)), |
| 4455 | CSKYV2_ISA_2E3), |
| 4456 | OP32 ("srs.b", |
| 4457 | OPCODE_INFO2 (0xcc100000, |
| 4458 | (21_25, AREG, OPRND_SHIFT_0_BIT), |
| 4459 | (0_17, LABEL_WITH_BRACKET, OPRND_SHIFT_0_BIT)), |
| 4460 | CSKYV2_ISA_2E3), |
| 4461 | #undef _RELOC32 |
| 4462 | #define _RELOC32 BFD_RELOC_CKCORE_DOFFSET_IMM18BY2 |
| 4463 | OP32 ("lrs.h", |
| 4464 | OPCODE_INFO2 (0xcc040000, |
| 4465 | (21_25, AREG, OPRND_SHIFT_0_BIT), |
| 4466 | (0_17, LABEL_WITH_BRACKET, OPRND_SHIFT_0_BIT)), |
| 4467 | CSKYV2_ISA_2E3), |
| 4468 | OP32 ("srs.h", |
| 4469 | OPCODE_INFO2 (0xcc140000, |
| 4470 | (21_25, AREG, OPRND_SHIFT_0_BIT), |
| 4471 | (0_17, LABEL_WITH_BRACKET, OPRND_SHIFT_0_BIT)), |
| 4472 | CSKYV2_ISA_2E3), |
| 4473 | #undef _RELOC32 |
| 4474 | #define _RELOC32 BFD_RELOC_CKCORE_PCREL_FLRW_IMM8BY4 |
| 4475 | OP32 ("flrws", |
| 4476 | OPCODE_INFO2 (0xf4003800, |
| 4477 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 4478 | (4_7or21_24, FCONSTANT, OPRND_SHIFT_2_BIT)), |
| 4479 | CSKY_ISA_FLOAT_1E3), |
| 4480 | OP32 ("flrwd", |
| 4481 | OPCODE_INFO2 (0xf4003900, |
| 4482 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 4483 | (4_7or21_24, FCONSTANT, OPRND_SHIFT_2_BIT)), |
| 4484 | CSKY_ISA_FLOAT_3E4), |
| 4485 | #undef _RELOC32 |
| 4486 | #define _RELOC32 BFD_RELOC_CKCORE_DOFFSET_IMM18BY4 |
| 4487 | OP32_WITH_WORK ("lrs.w", |
| 4488 | OPCODE_INFO2 (0xcc080000, |
| 4489 | (21_25, AREG, OPRND_SHIFT_0_BIT), |
| 4490 | (0_17, LABEL_WITH_BRACKET, OPRND_SHIFT_0_BIT)), |
| 4491 | CSKYV2_ISA_2E3, |
| 4492 | v2_work_lrsrsw), |
| 4493 | OP32_WITH_WORK ("srs.w", |
| 4494 | OPCODE_INFO2 (0xcc180000, |
| 4495 | (21_25, AREG, OPRND_SHIFT_0_BIT), |
| 4496 | (0_17, LABEL_WITH_BRACKET, OPRND_SHIFT_0_BIT)), |
| 4497 | CSKYV2_ISA_2E3, |
| 4498 | v2_work_lrsrsw), |
| 4499 | |
| 4500 | #undef _RELOC32 |
| 4501 | #define _RELOC32 BFD_RELOC_CKCORE_PCREL_IMM16BY4 |
| 4502 | OP32_WITH_WORK ("jsri", |
| 4503 | OPCODE_INFO1 (0xeae00000, |
| 4504 | (0_15, OFF16b, OPRND_SHIFT_2_BIT)), |
| 4505 | CSKYV2_ISA_2E3, |
| 4506 | v2_work_jsri), |
| 4507 | #undef _RELOC32 |
| 4508 | #define _RELOC32 BFD_RELOC_CKCORE_PCREL_IMM16BY2 |
| 4509 | OP32 ("bez", |
| 4510 | OPCODE_INFO2 (0xe9000000, |
| 4511 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4512 | (0_15, OFF16b_LSL1, OPRND_SHIFT_1_BIT)), |
| 4513 | CSKYV2_ISA_2E3), |
| 4514 | OP32 ("bnez", |
| 4515 | OPCODE_INFO2 (0xe9200000, |
| 4516 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4517 | (0_15, OFF16b_LSL1, OPRND_SHIFT_1_BIT)), |
| 4518 | CSKYV2_ISA_2E3), |
| 4519 | OP32 ("bhz", |
| 4520 | OPCODE_INFO2 (0xe9400000, |
| 4521 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4522 | (0_15, OFF16b_LSL1, OPRND_SHIFT_1_BIT)), |
| 4523 | CSKYV2_ISA_2E3), |
| 4524 | OP32 ("blsz", |
| 4525 | OPCODE_INFO2 (0xe9600000, |
| 4526 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4527 | (0_15, OFF16b_LSL1, OPRND_SHIFT_1_BIT)), |
| 4528 | CSKYV2_ISA_2E3), |
| 4529 | OP32 ("blz", |
| 4530 | OPCODE_INFO2 (0xe9800000, |
| 4531 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4532 | (0_15, OFF16b_LSL1, OPRND_SHIFT_1_BIT)), |
| 4533 | CSKYV2_ISA_2E3), |
| 4534 | OP32 ("bhsz", |
| 4535 | OPCODE_INFO2 (0xe9a00000, |
| 4536 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4537 | (0_15, OFF16b_LSL1, OPRND_SHIFT_1_BIT)), |
| 4538 | CSKYV2_ISA_2E3), |
| 4539 | #undef _RELAX |
| 4540 | #undef _RELOC16 |
| 4541 | #undef _TRANSFER |
| 4542 | #define _TRANSFER 1 |
| 4543 | #define _RELAX 1 |
| 4544 | #define _RELOC16 BFD_RELOC_CKCORE_PCREL_IMM10BY2 |
| 4545 | OP16_OP32 ("br", |
| 4546 | OPCODE_INFO1 (0x0400, |
| 4547 | (0_9, UNCOND10b, OPRND_SHIFT_1_BIT)), |
| 4548 | CSKYV2_ISA_E1, |
| 4549 | OPCODE_INFO1 (0xe8000000, |
| 4550 | (0_15, UNCOND16b, OPRND_SHIFT_1_BIT)), |
| 4551 | CSKYV2_ISA_E1), |
| 4552 | #undef _TRANSFER |
| 4553 | #define _TRANSFER 0 |
| 4554 | OP16_OP32 ("bt", |
| 4555 | OPCODE_INFO1 (0x0800, |
| 4556 | (0_9, COND10b, OPRND_SHIFT_1_BIT)), |
| 4557 | CSKYV2_ISA_E1, |
| 4558 | OPCODE_INFO1 (0xe8600000, |
| 4559 | (0_15, COND16b, OPRND_SHIFT_1_BIT)), |
| 4560 | CSKYV2_ISA_1E2), |
| 4561 | OP16_OP32 ("bf", |
| 4562 | OPCODE_INFO1 (0x0c00, |
| 4563 | (0_9, COND10b, OPRND_SHIFT_1_BIT)), |
| 4564 | CSKYV2_ISA_E1, |
| 4565 | OPCODE_INFO1 (0xe8400000, |
| 4566 | (0_15, COND16b, OPRND_SHIFT_1_BIT)), |
| 4567 | CSKYV2_ISA_1E2), |
| 4568 | #undef _RELOC16 |
| 4569 | #undef _RELOC32 |
| 4570 | #undef _RELAX |
| 4571 | #define _RELOC16 0 |
| 4572 | #define _RELOC32 0 |
| 4573 | #define _RELAX 0 |
| 4574 | #undef _TRANSFER |
| 4575 | #define _TRANSFER 1 |
| 4576 | OP16_WITH_WORK ("jbr", |
| 4577 | OPCODE_INFO1 (0x0400, |
| 4578 | (0_10, UNCOND10b, OPRND_SHIFT_1_BIT)), |
| 4579 | CSKYV2_ISA_E1, |
| 4580 | v2_work_jbr), |
| 4581 | #undef _TRANSFER |
| 4582 | #define _TRANSFER 0 |
| 4583 | OP16_WITH_WORK ("jbt", |
| 4584 | OPCODE_INFO1 (0x0800, |
| 4585 | (0_10, COND10b, OPRND_SHIFT_1_BIT)), |
| 4586 | CSKYV2_ISA_E1, |
| 4587 | v2_work_jbtf), |
| 4588 | OP16_WITH_WORK ("jbf", |
| 4589 | OPCODE_INFO1 (0x0c00, |
| 4590 | (0_10, COND10b, OPRND_SHIFT_1_BIT)), |
| 4591 | CSKYV2_ISA_E1, |
| 4592 | v2_work_jbtf), |
| 4593 | OP32_WITH_WORK ("jbsr", |
| 4594 | OPCODE_INFO1 (0xe0000000, |
| 4595 | (0_25, OFF26b, OPRND_SHIFT_1_BIT)), |
| 4596 | CSKYV2_ISA_E1, |
| 4597 | v2_work_jbsr), |
| 4598 | OP32_WITH_WORK ("movih", |
| 4599 | OPCODE_INFO2 (0xea200000, |
| 4600 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4601 | (0_15, IMM16b_MOVIH, OPRND_SHIFT_0_BIT)), |
| 4602 | CSKYV2_ISA_1E2, |
| 4603 | v2_work_movih), |
| 4604 | OP32_WITH_WORK ("ori", |
| 4605 | OPCODE_INFO3 (0xec000000, |
| 4606 | (21_25, AREG, OPRND_SHIFT_0_BIT), |
| 4607 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4608 | (0_15, IMM16b_ORI, OPRND_SHIFT_0_BIT)), |
| 4609 | CSKYV2_ISA_1E2, |
| 4610 | v2_work_ori), |
| 4611 | DOP32_WITH_WORK ("bgeni", |
| 4612 | OPCODE_INFO2 (0xea000000, |
| 4613 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4614 | (0_4, IMM4b, OPRND_SHIFT_0_BIT)), |
| 4615 | OPCODE_INFO2 (0xea200000, |
| 4616 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4617 | (0_4, IMM5b, OPRND_SHIFT_0_BIT)), |
| 4618 | CSKYV2_ISA_E1, |
| 4619 | v2_work_bgeni), |
| 4620 | #undef _RELOC16 |
| 4621 | #undef _RELOC32 |
| 4622 | #define _RELOC16 BFD_RELOC_CKCORE_PCREL_IMM7BY4 |
| 4623 | #define _RELOC32 BFD_RELOC_CKCORE_PCREL_IMM16BY4 |
| 4624 | DOP16_OP32_WITH_WORK ("lrw", |
| 4625 | OPCODE_INFO2 (0x1000, |
| 4626 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), |
| 4627 | (0_4or8_9, CONSTANT, OPRND_SHIFT_2_BIT)), |
| 4628 | OPCODE_INFO2 (0x0000, |
| 4629 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), |
| 4630 | (0_4or8_9, ELRW_CONSTANT, OPRND_SHIFT_2_BIT)), |
| 4631 | CSKYV2_ISA_E1, |
| 4632 | OPCODE_INFO2 (0xea800000, |
| 4633 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4634 | (0_15, CONSTANT, OPRND_SHIFT_2_BIT)), |
| 4635 | CSKYV2_ISA_E1, |
| 4636 | v2_work_lrw), |
| 4637 | #undef _RELOC16 |
| 4638 | #undef _RELOC32 |
| 4639 | #define _RELOC16 0 |
| 4640 | #define _RELOC32 0 |
| 4641 | |
| 4642 | #undef _RELAX |
| 4643 | #define _RELAX 1 |
| 4644 | OP32 ("jbez", |
| 4645 | OPCODE_INFO2 (0xe9000000, |
| 4646 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4647 | (0_15, JCOMPZ, OPRND_SHIFT_0_BIT)), |
| 4648 | CSKYV2_ISA_2E3), |
| 4649 | OP32 ("jbnez", |
| 4650 | OPCODE_INFO2 (0xe9200000, |
| 4651 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4652 | (0_15, JCOMPZ, OPRND_SHIFT_0_BIT)), |
| 4653 | CSKYV2_ISA_2E3), |
| 4654 | OP32 ("jbhz", |
| 4655 | OPCODE_INFO2 (0xe9400000, |
| 4656 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4657 | (0_15, JCOMPZ, OPRND_SHIFT_0_BIT)), |
| 4658 | CSKYV2_ISA_2E3), |
| 4659 | OP32 ("jblsz", |
| 4660 | OPCODE_INFO2 (0xe9600000, |
| 4661 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4662 | (0_15, JCOMPZ, OPRND_SHIFT_0_BIT)), |
| 4663 | CSKYV2_ISA_2E3), |
| 4664 | OP32 ("jblz", |
| 4665 | OPCODE_INFO2 (0xe9800000, |
| 4666 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4667 | (0_15, JCOMPZ, OPRND_SHIFT_0_BIT)), |
| 4668 | CSKYV2_ISA_2E3), |
| 4669 | OP32 ("jbhsz", |
| 4670 | OPCODE_INFO2 (0xe9a00000, |
| 4671 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4672 | (0_15, JCOMPZ, OPRND_SHIFT_0_BIT)), |
| 4673 | CSKYV2_ISA_2E3), |
| 4674 | #undef _RELAX |
| 4675 | #define _RELAX 0 |
| 4676 | |
| 4677 | /* The followings are enhance DSP instructions. */ |
| 4678 | OP32_WITH_WORK ("bloop", |
| 4679 | OPCODE_INFO3 (0xe9c00000, |
| 4680 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4681 | (0_11, BLOOP_OFF12b, OPRND_SHIFT_1_BIT), |
| 4682 | (12_15, BLOOP_OFF4b, OPRND_SHIFT_1_BIT)), |
| 4683 | CSKY_ISA_DSP_ENHANCE, |
| 4684 | dsp_work_bloop), |
| 4685 | /* The followings are ld/st instructions. */ |
| 4686 | OP32 ("ldbi.b", |
| 4687 | OPCODE_INFO2 (0xd0008000, |
| 4688 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 4689 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), |
| 4690 | CSKY_ISA_DSP_ENHANCE), |
| 4691 | OP32 ("ldbi.h", |
| 4692 | OPCODE_INFO2 (0xd0008400, |
| 4693 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 4694 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), |
| 4695 | CSKY_ISA_DSP_ENHANCE), |
| 4696 | OP32 ("ldbi.w", |
| 4697 | OPCODE_INFO2 (0xd0008800, |
| 4698 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 4699 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), |
| 4700 | CSKY_ISA_DSP_ENHANCE), |
| 4701 | OP32 ("pldbi.d", |
| 4702 | OPCODE_INFO2 (0xd0008c00, |
| 4703 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 4704 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), |
| 4705 | CSKY_ISA_DSP_ENHANCE), |
| 4706 | OP32 ("ldbi.hs", |
| 4707 | OPCODE_INFO2 (0xd0009000, |
| 4708 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 4709 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), |
| 4710 | CSKY_ISA_DSP_ENHANCE), |
| 4711 | OP32 ("ldbi.bs", |
| 4712 | OPCODE_INFO2 (0xd0009400, |
| 4713 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 4714 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), |
| 4715 | CSKY_ISA_DSP_ENHANCE), |
| 4716 | OP32 ("stbi.b", |
| 4717 | OPCODE_INFO2 (0xd4008000, |
| 4718 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 4719 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), |
| 4720 | CSKY_ISA_DSP_ENHANCE), |
| 4721 | OP32 ("stbi.h", |
| 4722 | OPCODE_INFO2 (0xd4008400, |
| 4723 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 4724 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), |
| 4725 | CSKY_ISA_DSP_ENHANCE), |
| 4726 | OP32 ("stbi.w", |
| 4727 | OPCODE_INFO2 (0xd4008800, |
| 4728 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 4729 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), |
| 4730 | CSKY_ISA_DSP_ENHANCE), |
| 4731 | OP32 ("ldbir.b", |
| 4732 | OPCODE_INFO3 (0xd000a000, |
| 4733 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 4734 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT), |
| 4735 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 4736 | CSKY_ISA_DSP_ENHANCE), |
| 4737 | OP32 ("ldbir.h", |
| 4738 | OPCODE_INFO3 (0xd000a400, |
| 4739 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 4740 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT), |
| 4741 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 4742 | CSKY_ISA_DSP_ENHANCE), |
| 4743 | OP32 ("ldbir.w", |
| 4744 | OPCODE_INFO3 (0xd000a800, |
| 4745 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 4746 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT), |
| 4747 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 4748 | CSKY_ISA_DSP_ENHANCE), |
| 4749 | OP32 ("pldbir.d", |
| 4750 | OPCODE_INFO3 (0xd000ac00, |
| 4751 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 4752 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT), |
| 4753 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 4754 | CSKY_ISA_DSP_ENHANCE), |
| 4755 | OP32 ("ldbir.bs", |
| 4756 | OPCODE_INFO3 (0xd000b000, |
| 4757 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 4758 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT), |
| 4759 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 4760 | CSKY_ISA_DSP_ENHANCE), |
| 4761 | OP32 ("ldbir.hs", |
| 4762 | OPCODE_INFO3 (0xd000b400, |
| 4763 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 4764 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT), |
| 4765 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 4766 | CSKY_ISA_DSP_ENHANCE), |
| 4767 | OP32 ("stbir.b", |
| 4768 | OPCODE_INFO3 (0xd400a000, |
| 4769 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 4770 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT), |
| 4771 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 4772 | CSKY_ISA_DSP_ENHANCE), |
| 4773 | OP32 ("stbir.h", |
| 4774 | OPCODE_INFO3 (0xd400a400, |
| 4775 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 4776 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT), |
| 4777 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 4778 | CSKY_ISA_DSP_ENHANCE), |
| 4779 | OP32 ("stbir.w", |
| 4780 | OPCODE_INFO3 (0xd400a800, |
| 4781 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 4782 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT), |
| 4783 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 4784 | CSKY_ISA_DSP_ENHANCE), |
| 4785 | /* The followings are add/sub instructions. */ |
| 4786 | OP32 ("padd.8", |
| 4787 | OPCODE_INFO3 (0xf800c040, |
| 4788 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 4789 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4790 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 4791 | CSKY_ISA_DSP_ENHANCE), |
| 4792 | OP32 ("padd.16", |
| 4793 | OPCODE_INFO3 (0xf800c000, |
| 4794 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 4795 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4796 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 4797 | CSKY_ISA_DSP_ENHANCE), |
| 4798 | OP32 ("padd.u8.s", |
| 4799 | OPCODE_INFO3 (0xf800c140, |
| 4800 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 4801 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4802 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 4803 | CSKY_ISA_DSP_ENHANCE), |
| 4804 | OP32 ("padd.s8.s", |
| 4805 | OPCODE_INFO3 (0xf800c1c0, |
| 4806 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 4807 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4808 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 4809 | CSKY_ISA_DSP_ENHANCE), |
| 4810 | OP32 ("padd.u16.s", |
| 4811 | OPCODE_INFO3 (0xf800c100, |
| 4812 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 4813 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4814 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 4815 | CSKY_ISA_DSP_ENHANCE), |
| 4816 | OP32 ("padd.s16.s", |
| 4817 | OPCODE_INFO3 (0xf800c180, |
| 4818 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 4819 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4820 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 4821 | CSKY_ISA_DSP_ENHANCE), |
| 4822 | OP32 ("add.u32.s", |
| 4823 | OPCODE_INFO3 (0xf800c120, |
| 4824 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 4825 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4826 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 4827 | CSKY_ISA_DSP_ENHANCE), |
| 4828 | OP32 ("add.s32.s", |
| 4829 | OPCODE_INFO3 (0xf800c1a0, |
| 4830 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 4831 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4832 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 4833 | CSKY_ISA_DSP_ENHANCE), |
| 4834 | OP32 ("psub.8", |
| 4835 | OPCODE_INFO3 (0xf800c440, |
| 4836 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 4837 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4838 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 4839 | CSKY_ISA_DSP_ENHANCE), |
| 4840 | OP32 ("psub.16", |
| 4841 | OPCODE_INFO3 (0xf800c400, |
| 4842 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 4843 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4844 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 4845 | CSKY_ISA_DSP_ENHANCE), |
| 4846 | OP32 ("psub.u8.s", |
| 4847 | OPCODE_INFO3 (0xf800c540, |
| 4848 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 4849 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4850 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 4851 | CSKY_ISA_DSP_ENHANCE), |
| 4852 | OP32 ("psub.s8.s", |
| 4853 | OPCODE_INFO3 (0xf800c5c0, |
| 4854 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 4855 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4856 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 4857 | CSKY_ISA_DSP_ENHANCE), |
| 4858 | OP32 ("psub.u16.s", |
| 4859 | OPCODE_INFO3 (0xf800c500, |
| 4860 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 4861 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4862 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 4863 | CSKY_ISA_DSP_ENHANCE), |
| 4864 | OP32 ("psub.s16.s", |
| 4865 | OPCODE_INFO3 (0xf800c580, |
| 4866 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 4867 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4868 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 4869 | CSKY_ISA_DSP_ENHANCE), |
| 4870 | OP32 ("sub.u32.s", |
| 4871 | OPCODE_INFO3 (0xf800c520, |
| 4872 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 4873 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4874 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 4875 | CSKY_ISA_DSP_ENHANCE), |
| 4876 | OP32 ("sub.s32.s", |
| 4877 | OPCODE_INFO3 (0xf800c5a0, |
| 4878 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 4879 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4880 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 4881 | CSKY_ISA_DSP_ENHANCE), |
| 4882 | OP32 ("paddh.u8", |
| 4883 | OPCODE_INFO3 (0xf800c240, |
| 4884 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 4885 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4886 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 4887 | CSKY_ISA_DSP_ENHANCE), |
| 4888 | OP32 ("paddh.s8", |
| 4889 | OPCODE_INFO3 (0xf800c2c0, |
| 4890 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 4891 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4892 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 4893 | CSKY_ISA_DSP_ENHANCE), |
| 4894 | OP32 ("paddh.u16", |
| 4895 | OPCODE_INFO3 (0xf800c200, |
| 4896 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 4897 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4898 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 4899 | CSKY_ISA_DSP_ENHANCE), |
| 4900 | OP32 ("paddh.s16", |
| 4901 | OPCODE_INFO3 (0xf800c280, |
| 4902 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 4903 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4904 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 4905 | CSKY_ISA_DSP_ENHANCE), |
| 4906 | OP32 ("addh.u32", |
| 4907 | OPCODE_INFO3 (0xf800c220, |
| 4908 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 4909 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4910 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 4911 | CSKY_ISA_DSP_ENHANCE), |
| 4912 | OP32 ("addh.s32", |
| 4913 | OPCODE_INFO3 (0xf800c2a0, |
| 4914 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 4915 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4916 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 4917 | CSKY_ISA_DSP_ENHANCE), |
| 4918 | OP32 ("psubh.u8", |
| 4919 | OPCODE_INFO3 (0xf800c640, |
| 4920 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 4921 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4922 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 4923 | CSKY_ISA_DSP_ENHANCE), |
| 4924 | OP32 ("psubh.s8", |
| 4925 | OPCODE_INFO3 (0xf800c6c0, |
| 4926 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 4927 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4928 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 4929 | CSKY_ISA_DSP_ENHANCE), |
| 4930 | OP32 ("psubh.u16", |
| 4931 | OPCODE_INFO3 (0xf800c600, |
| 4932 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 4933 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4934 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 4935 | CSKY_ISA_DSP_ENHANCE), |
| 4936 | OP32 ("psubh.s16", |
| 4937 | OPCODE_INFO3 (0xf800c680, |
| 4938 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 4939 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4940 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 4941 | CSKY_ISA_DSP_ENHANCE), |
| 4942 | OP32 ("subh.u32", |
| 4943 | OPCODE_INFO3 (0xf800c620, |
| 4944 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 4945 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4946 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 4947 | CSKY_ISA_DSP_ENHANCE), |
| 4948 | OP32 ("subh.s32", |
| 4949 | OPCODE_INFO3 (0xf800c6a0, |
| 4950 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 4951 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4952 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 4953 | CSKY_ISA_DSP_ENHANCE), |
| 4954 | OP32 ("add.64", |
| 4955 | OPCODE_INFO3 (0xf800c060, |
| 4956 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 4957 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4958 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 4959 | CSKY_ISA_DSP_ENHANCE), |
| 4960 | OP32 ("sub.64", |
| 4961 | OPCODE_INFO3 (0xf800c460, |
| 4962 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 4963 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4964 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 4965 | CSKY_ISA_DSP_ENHANCE), |
| 4966 | OP32 ("add.u64.s", |
| 4967 | OPCODE_INFO3 (0xf800c160, |
| 4968 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 4969 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4970 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 4971 | CSKY_ISA_DSP_ENHANCE), |
| 4972 | OP32 ("add.s64.s", |
| 4973 | OPCODE_INFO3 (0xf800c1e0, |
| 4974 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 4975 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4976 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 4977 | CSKY_ISA_DSP_ENHANCE), |
| 4978 | OP32 ("sub.u64.s", |
| 4979 | OPCODE_INFO3 (0xf800c560, |
| 4980 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 4981 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4982 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 4983 | CSKY_ISA_DSP_ENHANCE), |
| 4984 | OP32 ("sub.s64.s", |
| 4985 | OPCODE_INFO3 (0xf800c5e0, |
| 4986 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 4987 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4988 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 4989 | CSKY_ISA_DSP_ENHANCE), |
| 4990 | /* The following are comparison instructions. */ |
| 4991 | OP32 ("pasx.16", |
| 4992 | OPCODE_INFO3 (0xf800c860, |
| 4993 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 4994 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 4995 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 4996 | CSKY_ISA_DSP_ENHANCE), |
| 4997 | OP32 ("psax.16", |
| 4998 | OPCODE_INFO3 (0xf800cc60, |
| 4999 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5000 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5001 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5002 | CSKY_ISA_DSP_ENHANCE), |
| 5003 | OP32 ("pasx.u16.s", |
| 5004 | OPCODE_INFO3 (0xf800c960, |
| 5005 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5006 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5007 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5008 | CSKY_ISA_DSP_ENHANCE), |
| 5009 | OP32 ("pasx.s16.s", |
| 5010 | OPCODE_INFO3 (0xf800c9e0, |
| 5011 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5012 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5013 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5014 | CSKY_ISA_DSP_ENHANCE), |
| 5015 | OP32 ("psax.u16.s", |
| 5016 | OPCODE_INFO3 (0xf800cd60, |
| 5017 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5018 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5019 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5020 | CSKY_ISA_DSP_ENHANCE), |
| 5021 | OP32 ("psax.s16.s", |
| 5022 | OPCODE_INFO3 (0xf800cde0, |
| 5023 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5024 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5025 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5026 | CSKY_ISA_DSP_ENHANCE), |
| 5027 | OP32 ("pasxh.u16", |
| 5028 | OPCODE_INFO3 (0xf800ca60, |
| 5029 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5030 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5031 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5032 | CSKY_ISA_DSP_ENHANCE), |
| 5033 | OP32 ("pasxh.s16", |
| 5034 | OPCODE_INFO3 (0xf800cae0, |
| 5035 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5036 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5037 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5038 | CSKY_ISA_DSP_ENHANCE), |
| 5039 | OP32 ("psaxh.u16", |
| 5040 | OPCODE_INFO3 (0xf800ce60, |
| 5041 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5042 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5043 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5044 | CSKY_ISA_DSP_ENHANCE), |
| 5045 | OP32 ("psaxh.s16", |
| 5046 | OPCODE_INFO3 (0xf800cee0, |
| 5047 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5048 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5049 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5050 | CSKY_ISA_DSP_ENHANCE), |
| 5051 | OP32 ("pcmpne.8", |
| 5052 | OPCODE_INFO3 (0xf800c840, |
| 5053 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5054 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5055 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5056 | CSKY_ISA_DSP_ENHANCE), |
| 5057 | OP32 ("pcmpne.16", |
| 5058 | OPCODE_INFO3 (0xf800c800, |
| 5059 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5060 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5061 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5062 | CSKY_ISA_DSP_ENHANCE), |
| 5063 | OP32 ("pcmphs.u8", |
| 5064 | OPCODE_INFO3 (0xf800c940, |
| 5065 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5066 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5067 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5068 | CSKY_ISA_DSP_ENHANCE), |
| 5069 | OP32 ("pcmphs.s8", |
| 5070 | OPCODE_INFO3 (0xf800c9c0, |
| 5071 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5072 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5073 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5074 | CSKY_ISA_DSP_ENHANCE), |
| 5075 | OP32 ("pcmphs.u16", |
| 5076 | OPCODE_INFO3 (0xf800c900, |
| 5077 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5078 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5079 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5080 | CSKY_ISA_DSP_ENHANCE), |
| 5081 | OP32 ("pcmphs.s16", |
| 5082 | OPCODE_INFO3 (0xf800c980, |
| 5083 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5084 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5085 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5086 | CSKY_ISA_DSP_ENHANCE), |
| 5087 | OP32 ("pcmplt.u8", |
| 5088 | OPCODE_INFO3 (0xf800ca40, |
| 5089 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5090 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5091 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5092 | CSKY_ISA_DSP_ENHANCE), |
| 5093 | OP32 ("pcmplt.s8", |
| 5094 | OPCODE_INFO3 (0xf800cac0, |
| 5095 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5096 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5097 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5098 | CSKY_ISA_DSP_ENHANCE), |
| 5099 | OP32 ("pcmplt.u16", |
| 5100 | OPCODE_INFO3 (0xf800ca00, |
| 5101 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5102 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5103 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5104 | CSKY_ISA_DSP_ENHANCE), |
| 5105 | OP32 ("pcmplt.s16", |
| 5106 | OPCODE_INFO3 (0xf800ca80, |
| 5107 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5108 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5109 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5110 | CSKY_ISA_DSP_ENHANCE), |
| 5111 | OP32 ("pmax.u8", |
| 5112 | OPCODE_INFO3 (0xf800cc40, |
| 5113 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5114 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5115 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5116 | CSKY_ISA_DSP_ENHANCE), |
| 5117 | OP32 ("pmax.s8", |
| 5118 | OPCODE_INFO3 (0xf800ccc0, |
| 5119 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5120 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5121 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5122 | CSKY_ISA_DSP_ENHANCE), |
| 5123 | OP32 ("pmax.u16", |
| 5124 | OPCODE_INFO3 (0xf800cc00, |
| 5125 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5126 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5127 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5128 | CSKY_ISA_DSP_ENHANCE), |
| 5129 | OP32 ("pmax.s16", |
| 5130 | OPCODE_INFO3 (0xf800cc80, |
| 5131 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5132 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5133 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5134 | CSKY_ISA_DSP_ENHANCE), |
| 5135 | OP32 ("max.u32", |
| 5136 | OPCODE_INFO3 (0xf800cc20, |
| 5137 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5138 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5139 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5140 | CSKY_ISA_DSP_ENHANCE), |
| 5141 | OP32 ("max.s32", |
| 5142 | OPCODE_INFO3 (0xf800cca0, |
| 5143 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5144 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5145 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5146 | CSKY_ISA_DSP_ENHANCE), |
| 5147 | OP32 ("pmin.u8", |
| 5148 | OPCODE_INFO3 (0xf800cd40, |
| 5149 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5150 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5151 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5152 | CSKY_ISA_DSP_ENHANCE), |
| 5153 | OP32 ("pmin.s8", |
| 5154 | OPCODE_INFO3 (0xf800cdc0, |
| 5155 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5156 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5157 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5158 | CSKY_ISA_DSP_ENHANCE), |
| 5159 | OP32 ("pmin.u16", |
| 5160 | OPCODE_INFO3 (0xf800cd00, |
| 5161 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5162 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5163 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5164 | CSKY_ISA_DSP_ENHANCE), |
| 5165 | OP32 ("pmin.s16", |
| 5166 | OPCODE_INFO3 (0xf800cd80, |
| 5167 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5168 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5169 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5170 | CSKY_ISA_DSP_ENHANCE), |
| 5171 | OP32 ("min.u32", |
| 5172 | OPCODE_INFO3 (0xf800cd20, |
| 5173 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5174 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5175 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5176 | CSKY_ISA_DSP_ENHANCE), |
| 5177 | OP32 ("min.s32", |
| 5178 | OPCODE_INFO3 (0xf800cda0, |
| 5179 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5180 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5181 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5182 | CSKY_ISA_DSP_ENHANCE), |
| 5183 | OP32 ("sel", |
| 5184 | OPCODE_INFO4 (0xf8009000, |
| 5185 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5186 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5187 | (21_25, AREG, OPRND_SHIFT_0_BIT), |
| 5188 | (5_9, AREG, OPRND_SHIFT_0_BIT)), |
| 5189 | CSKY_ISA_DSP_ENHANCE), |
| 5190 | /* The followings are miscs. */ |
| 5191 | OP32 ("psabsa.u8", |
| 5192 | OPCODE_INFO3 (0xf800e040, |
| 5193 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5194 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5195 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5196 | CSKY_ISA_DSP_ENHANCE), |
| 5197 | OP32 ("psabsaa.u8", |
| 5198 | OPCODE_INFO3 (0xf800e140, |
| 5199 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5200 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5201 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5202 | CSKY_ISA_DSP_ENHANCE), |
| 5203 | OP32 ("divul", |
| 5204 | OPCODE_INFO3 (0xf800e260, |
| 5205 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5206 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5207 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5208 | CSKY_ISA_DSP_ENHANCE), |
| 5209 | OP32 ("divsl", |
| 5210 | OPCODE_INFO3 (0xf800e2e0, |
| 5211 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5212 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5213 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5214 | CSKY_ISA_DSP_ENHANCE), |
| 5215 | OP32 ("mulaca.s8", |
| 5216 | OPCODE_INFO3 (0xf800e4c0, |
| 5217 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5218 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5219 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5220 | CSKY_ISA_DSP_ENHANCE), |
| 5221 | /* The followings are shift instructions. */ |
| 5222 | OP32 ("asri.s32.r", |
| 5223 | OPCODE_INFO3 (0xf800d1a0, |
| 5224 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5225 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5226 | (21_25, OIMM5b, OPRND_SHIFT_0_BIT)), |
| 5227 | CSKY_ISA_DSP_ENHANCE), |
| 5228 | OP32 ("asr.s32.r", |
| 5229 | OPCODE_INFO3 (0xf800d1e0, |
| 5230 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5231 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5232 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5233 | CSKY_ISA_DSP_ENHANCE), |
| 5234 | OP32 ("lsri.u32.r", |
| 5235 | OPCODE_INFO3 (0xf800d320, |
| 5236 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5237 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5238 | (21_25, OIMM5b, OPRND_SHIFT_0_BIT)), |
| 5239 | CSKY_ISA_DSP_ENHANCE), |
| 5240 | OP32 ("lsr.u32.r", |
| 5241 | OPCODE_INFO3 (0xf800d360, |
| 5242 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5243 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5244 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5245 | CSKY_ISA_DSP_ENHANCE), |
| 5246 | OP32 ("lsli.u32.s", |
| 5247 | OPCODE_INFO3 (0xf800d520, |
| 5248 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5249 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5250 | (21_25, OIMM5b, OPRND_SHIFT_0_BIT)), |
| 5251 | CSKY_ISA_DSP_ENHANCE), |
| 5252 | OP32 ("lsli.s32.s", |
| 5253 | OPCODE_INFO3 (0xf800d5a0, |
| 5254 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5255 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5256 | (21_25, OIMM5b, OPRND_SHIFT_0_BIT)), |
| 5257 | CSKY_ISA_DSP_ENHANCE), |
| 5258 | OP32 ("lsl.u32.s", |
| 5259 | OPCODE_INFO3 (0xf800d560, |
| 5260 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5261 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5262 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5263 | CSKY_ISA_DSP_ENHANCE), |
| 5264 | OP32 ("lsl.s32.s", |
| 5265 | OPCODE_INFO3 (0xf800d5e0, |
| 5266 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5267 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5268 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5269 | CSKY_ISA_DSP_ENHANCE), |
| 5270 | OP32 ("pasri.s16", |
| 5271 | OPCODE_INFO3 (0xf800d080, |
| 5272 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5273 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5274 | (21_25, OIMM4b, OPRND_SHIFT_0_BIT)), |
| 5275 | CSKY_ISA_DSP_ENHANCE), |
| 5276 | OP32 ("pasr.s16", |
| 5277 | OPCODE_INFO3 (0xf800d0c0, |
| 5278 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5279 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5280 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5281 | CSKY_ISA_DSP_ENHANCE), |
| 5282 | OP32 ("pasri.s16.r", |
| 5283 | OPCODE_INFO3 (0xf800d180, |
| 5284 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5285 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5286 | (21_25, OIMM4b, OPRND_SHIFT_0_BIT)), |
| 5287 | CSKY_ISA_DSP_ENHANCE), |
| 5288 | OP32 ("pasr.s16.r", |
| 5289 | OPCODE_INFO3 (0xf800d1c0, |
| 5290 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5291 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5292 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5293 | CSKY_ISA_DSP_ENHANCE), |
| 5294 | OP32 ("plsri.u16", |
| 5295 | OPCODE_INFO3 (0xf800d200, |
| 5296 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5297 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5298 | (21_25, OIMM4b, OPRND_SHIFT_0_BIT)), |
| 5299 | CSKY_ISA_DSP_ENHANCE), |
| 5300 | OP32 ("plsr.u16", |
| 5301 | OPCODE_INFO3 (0xf800d240, |
| 5302 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5303 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5304 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5305 | CSKY_ISA_DSP_ENHANCE), |
| 5306 | OP32 ("plsri.u16.r", |
| 5307 | OPCODE_INFO3 (0xf800d300, |
| 5308 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5309 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5310 | (21_25, OIMM4b, OPRND_SHIFT_0_BIT)), |
| 5311 | CSKY_ISA_DSP_ENHANCE), |
| 5312 | OP32 ("plsr.u16.r", |
| 5313 | OPCODE_INFO3 (0xf800d340, |
| 5314 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5315 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5316 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5317 | CSKY_ISA_DSP_ENHANCE), |
| 5318 | OP32 ("plsli.u16", |
| 5319 | OPCODE_INFO3 (0xf800d400, |
| 5320 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5321 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5322 | (21_25, OIMM4b, OPRND_SHIFT_0_BIT)), |
| 5323 | CSKY_ISA_DSP_ENHANCE), |
| 5324 | OP32 ("plsl.u16", |
| 5325 | OPCODE_INFO3 (0xf800d440, |
| 5326 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5327 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5328 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5329 | CSKY_ISA_DSP_ENHANCE), |
| 5330 | OP32 ("plsli.u16.s", |
| 5331 | OPCODE_INFO3 (0xf800d500, |
| 5332 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5333 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5334 | (21_25, OIMM4b, OPRND_SHIFT_0_BIT)), |
| 5335 | CSKY_ISA_DSP_ENHANCE), |
| 5336 | OP32 ("plsli.s16.s", |
| 5337 | OPCODE_INFO3 (0xf800d580, |
| 5338 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5339 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5340 | (21_25, OIMM4b, OPRND_SHIFT_0_BIT)), |
| 5341 | CSKY_ISA_DSP_ENHANCE), |
| 5342 | OP32 ("plsl.u16.s", |
| 5343 | OPCODE_INFO3 (0xf800d540, |
| 5344 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5345 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5346 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5347 | CSKY_ISA_DSP_ENHANCE), |
| 5348 | OP32 ("plsl.s16.s", |
| 5349 | OPCODE_INFO3 (0xf800d5c0, |
| 5350 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5351 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5352 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5353 | CSKY_ISA_DSP_ENHANCE), |
| 5354 | /* The following are package & unpackage instructions. */ |
| 5355 | OP32 ("pkg", |
| 5356 | OPCODE_INFO5 (0xf800a000, |
| 5357 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5358 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5359 | (5_8, IMM4b, OPRND_SHIFT_0_BIT), |
| 5360 | (21_25, AREG, OPRND_SHIFT_0_BIT), |
| 5361 | (9_12, OIMM4b, OPRND_SHIFT_0_BIT)), |
| 5362 | CSKY_ISA_DSP_ENHANCE), |
| 5363 | OP32 ("dexti", |
| 5364 | OPCODE_INFO4 (0xf8009800, |
| 5365 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5366 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5367 | (21_25, AREG, OPRND_SHIFT_0_BIT), |
| 5368 | (5_9, IMM5b, OPRND_SHIFT_0_BIT)), |
| 5369 | CSKY_ISA_DSP_ENHANCE), |
| 5370 | OP32 ("dext", |
| 5371 | OPCODE_INFO4 (0xf8009c00, |
| 5372 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5373 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5374 | (21_25, AREG, OPRND_SHIFT_0_BIT), |
| 5375 | (5_9, AREG, OPRND_SHIFT_0_BIT)), |
| 5376 | CSKY_ISA_DSP_ENHANCE), |
| 5377 | OP32 ("pkgll", |
| 5378 | OPCODE_INFO3 (0xf800d840, |
| 5379 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5380 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5381 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5382 | CSKY_ISA_DSP_ENHANCE), |
| 5383 | OP32 ("pkghh", |
| 5384 | OPCODE_INFO3 (0xf800d860, |
| 5385 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5386 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5387 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5388 | CSKY_ISA_DSP_ENHANCE), |
| 5389 | OP32 ("pext.u8.e", |
| 5390 | OPCODE_INFO2 (0xf800d900, |
| 5391 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5392 | (16_20, AREG, OPRND_SHIFT_0_BIT)), |
| 5393 | CSKY_ISA_DSP_ENHANCE), |
| 5394 | OP32 ("pext.s8.e", |
| 5395 | OPCODE_INFO2 (0xf800d980, |
| 5396 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5397 | (16_20, AREG, OPRND_SHIFT_0_BIT)), |
| 5398 | CSKY_ISA_DSP_ENHANCE), |
| 5399 | OP32 ("pextx.u8.e", |
| 5400 | OPCODE_INFO2 (0xf800d920, |
| 5401 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5402 | (16_20, AREG, OPRND_SHIFT_0_BIT)), |
| 5403 | CSKY_ISA_DSP_ENHANCE), |
| 5404 | OP32 ("pextx.s8.e", |
| 5405 | OPCODE_INFO2 (0xf800d9a0, |
| 5406 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5407 | (16_20, AREG, OPRND_SHIFT_0_BIT)), |
| 5408 | CSKY_ISA_DSP_ENHANCE), |
| 5409 | OP32 ("narl", |
| 5410 | OPCODE_INFO3 (0xf800da00, |
| 5411 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5412 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5413 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5414 | CSKY_ISA_DSP_ENHANCE), |
| 5415 | OP32 ("narh", |
| 5416 | OPCODE_INFO3 (0xf800da20, |
| 5417 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5418 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5419 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5420 | CSKY_ISA_DSP_ENHANCE), |
| 5421 | OP32 ("narlx", |
| 5422 | OPCODE_INFO3 (0xf800da40, |
| 5423 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5424 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5425 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5426 | CSKY_ISA_DSP_ENHANCE), |
| 5427 | OP32 ("narhx", |
| 5428 | OPCODE_INFO3 (0xf800da60, |
| 5429 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5430 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5431 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5432 | CSKY_ISA_DSP_ENHANCE), |
| 5433 | OP32 ("clipi.u32", |
| 5434 | OPCODE_INFO3 (0xf800db00, |
| 5435 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5436 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5437 | (21_25, IMM5b, OPRND_SHIFT_0_BIT)), |
| 5438 | CSKY_ISA_DSP_ENHANCE), |
| 5439 | OP32 ("clipi.s32", |
| 5440 | OPCODE_INFO3 (0xf800db80, |
| 5441 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5442 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5443 | (21_25, OIMM5b, OPRND_SHIFT_0_BIT)), |
| 5444 | CSKY_ISA_DSP_ENHANCE), |
| 5445 | OP32 ("clip.u32", |
| 5446 | OPCODE_INFO3 (0xf800db20, |
| 5447 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5448 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5449 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5450 | CSKY_ISA_DSP_ENHANCE), |
| 5451 | OP32 ("clip.s32", |
| 5452 | OPCODE_INFO3 (0xf800dba0, |
| 5453 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5454 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5455 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5456 | CSKY_ISA_DSP_ENHANCE), |
| 5457 | OP32 ("pclipi.u16", |
| 5458 | OPCODE_INFO3 (0xf800db40, |
| 5459 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5460 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5461 | (21_25, IMM4b, OPRND_SHIFT_0_BIT)), |
| 5462 | CSKY_ISA_DSP_ENHANCE), |
| 5463 | OP32 ("pclipi.s16", |
| 5464 | OPCODE_INFO3 (0xf800dbc0, |
| 5465 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5466 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5467 | (21_25, OIMM4b, OPRND_SHIFT_0_BIT)), |
| 5468 | CSKY_ISA_DSP_ENHANCE), |
| 5469 | OP32 ("pclip.u16", |
| 5470 | OPCODE_INFO3 (0xf800db60, |
| 5471 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5472 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5473 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5474 | CSKY_ISA_DSP_ENHANCE), |
| 5475 | OP32 ("pclip.s16", |
| 5476 | OPCODE_INFO3 (0xf800dbe0, |
| 5477 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5478 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5479 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5480 | CSKY_ISA_DSP_ENHANCE), |
| 5481 | OP32 ("pabs.s8.s", |
| 5482 | OPCODE_INFO2 (0xf800dc80, |
| 5483 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5484 | (16_20, AREG, OPRND_SHIFT_0_BIT)), |
| 5485 | CSKY_ISA_DSP_ENHANCE), |
| 5486 | OP32 ("pabs.s16.s", |
| 5487 | OPCODE_INFO2 (0xf800dca0, |
| 5488 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5489 | (16_20, AREG, OPRND_SHIFT_0_BIT)), |
| 5490 | CSKY_ISA_DSP_ENHANCE), |
| 5491 | OP32 ("abs.s32.s", |
| 5492 | OPCODE_INFO2 (0xf800dcc0, |
| 5493 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5494 | (16_20, AREG, OPRND_SHIFT_0_BIT)), |
| 5495 | CSKY_ISA_DSP_ENHANCE), |
| 5496 | OP32 ("pneg.s8.s", |
| 5497 | OPCODE_INFO2 (0xf800dd80, |
| 5498 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5499 | (16_20, AREG, OPRND_SHIFT_0_BIT)), |
| 5500 | CSKY_ISA_DSP_ENHANCE), |
| 5501 | OP32 ("pneg.s16.s", |
| 5502 | OPCODE_INFO2 (0xf800dda0, |
| 5503 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5504 | (16_20, AREG, OPRND_SHIFT_0_BIT)), |
| 5505 | CSKY_ISA_DSP_ENHANCE), |
| 5506 | OP32 ("neg.s32.s", |
| 5507 | OPCODE_INFO2 (0xf800ddc0, |
| 5508 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5509 | (16_20, AREG, OPRND_SHIFT_0_BIT)), |
| 5510 | CSKY_ISA_DSP_ENHANCE), |
| 5511 | OP32 ("dup.8", |
| 5512 | OPCODE_INFO3 (0xf800de00, |
| 5513 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5514 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5515 | (5_6, IMM2b, OPRND_SHIFT_0_BIT)), |
| 5516 | CSKY_ISA_DSP_ENHANCE), |
| 5517 | OP32 ("dup.16", |
| 5518 | OPCODE_INFO3 (0xf800df00, |
| 5519 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5520 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5521 | (5_6, IMM1b, OPRND_SHIFT_0_BIT)), |
| 5522 | CSKY_ISA_DSP_ENHANCE), |
| 5523 | /* The followings are multiplication instructions. */ |
| 5524 | OP32 ("mul.u32", |
| 5525 | OPCODE_INFO3 (0xf8008000, |
| 5526 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5527 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5528 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5529 | CSKYV2_ISA_3E3R1), |
| 5530 | OP32 ("mul.s32", |
| 5531 | OPCODE_INFO3 (0xf8008200, |
| 5532 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5533 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5534 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5535 | CSKYV2_ISA_3E3R1), |
| 5536 | OP32 ("mula.u32", |
| 5537 | OPCODE_INFO3 (0xf8008080, |
| 5538 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5539 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5540 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5541 | CSKYV2_ISA_3E3R1), |
| 5542 | OP32 ("mula.s32", |
| 5543 | OPCODE_INFO3 (0xf8008280, |
| 5544 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5545 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5546 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5547 | CSKYV2_ISA_3E3R1), |
| 5548 | OP32 ("mula.32.l", |
| 5549 | OPCODE_INFO3 (0xf8008440, |
| 5550 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5551 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5552 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5553 | CSKYV2_ISA_3E3R1), |
| 5554 | OP32 ("mulall.s16.s", |
| 5555 | OPCODE_INFO3 (0xf80081a0, |
| 5556 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5557 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5558 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5559 | CSKYV2_ISA_3E3R1), |
| 5560 | OP32 ("muls.u32", |
| 5561 | OPCODE_INFO3 (0xf80080c0, |
| 5562 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5563 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5564 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5565 | CSKY_ISA_DSP_ENHANCE), |
| 5566 | OP32 ("muls.s32", |
| 5567 | OPCODE_INFO3 (0xf80082c0, |
| 5568 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5569 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5570 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5571 | CSKY_ISA_DSP_ENHANCE), |
| 5572 | OP32 ("mula.u32.s", |
| 5573 | OPCODE_INFO3 (0xf8008180, |
| 5574 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5575 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5576 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5577 | CSKY_ISA_DSP_ENHANCE), |
| 5578 | OP32 ("mula.s32.s", |
| 5579 | OPCODE_INFO3 (0xf8008380, |
| 5580 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5581 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5582 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5583 | CSKY_ISA_DSP_ENHANCE), |
| 5584 | OP32 ("muls.u32.s", |
| 5585 | OPCODE_INFO3 (0xf80081c0, |
| 5586 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5587 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5588 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5589 | CSKY_ISA_DSP_ENHANCE), |
| 5590 | OP32 ("muls.s32.s", |
| 5591 | OPCODE_INFO3 (0xf80083c0, |
| 5592 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5593 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5594 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5595 | CSKY_ISA_DSP_ENHANCE), |
| 5596 | OP32 ("mul.s32.h", |
| 5597 | OPCODE_INFO3 (0xf8008400, |
| 5598 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5599 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5600 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5601 | CSKY_ISA_DSP_ENHANCE), |
| 5602 | OP32 ("mul.s32.rh", |
| 5603 | OPCODE_INFO3 (0xf8008600, |
| 5604 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5605 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5606 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5607 | CSKY_ISA_DSP_ENHANCE), |
| 5608 | OP32 ("rmul.s32.h", |
| 5609 | OPCODE_INFO3 (0xf8008500, |
| 5610 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5611 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5612 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5613 | CSKY_ISA_DSP_ENHANCE), |
| 5614 | OP32 ("rmul.s32.rh", |
| 5615 | OPCODE_INFO3 (0xf8008700, |
| 5616 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5617 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5618 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5619 | CSKY_ISA_DSP_ENHANCE), |
| 5620 | OP32 ("mula.s32.hs", |
| 5621 | OPCODE_INFO3 (0xf8008580, |
| 5622 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5623 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5624 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5625 | CSKY_ISA_DSP_ENHANCE), |
| 5626 | OP32 ("muls.s32.hs", |
| 5627 | OPCODE_INFO3 (0xf80085c0, |
| 5628 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5629 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5630 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5631 | CSKY_ISA_DSP_ENHANCE), |
| 5632 | OP32 ("mula.s32.rhs", |
| 5633 | OPCODE_INFO3 (0xf8008780, |
| 5634 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5635 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5636 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5637 | CSKY_ISA_DSP_ENHANCE), |
| 5638 | OP32 ("muls.s32.rhs", |
| 5639 | OPCODE_INFO3 (0xf80087c0, |
| 5640 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5641 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5642 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5643 | CSKY_ISA_DSP_ENHANCE), |
| 5644 | OP32 ("mulxl.s32", |
| 5645 | OPCODE_INFO3 (0xf8008800, |
| 5646 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5647 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5648 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5649 | CSKY_ISA_DSP_ENHANCE), |
| 5650 | OP32 ("mulxl.s32.r", |
| 5651 | OPCODE_INFO3 (0xf8008a00, |
| 5652 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5653 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5654 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5655 | CSKY_ISA_DSP_ENHANCE), |
| 5656 | OP32 ("mulxh.s32", |
| 5657 | OPCODE_INFO3 (0xf8008c00, |
| 5658 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5659 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5660 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5661 | CSKY_ISA_DSP_ENHANCE), |
| 5662 | OP32 ("mulxh.s32.r", |
| 5663 | OPCODE_INFO3 (0xf8008e00, |
| 5664 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5665 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5666 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5667 | CSKY_ISA_DSP_ENHANCE), |
| 5668 | OP32 ("rmulxl.s32", |
| 5669 | OPCODE_INFO3 (0xf8008900, |
| 5670 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5671 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5672 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5673 | CSKY_ISA_DSP_ENHANCE), |
| 5674 | OP32 ("rmulxl.s32.r", |
| 5675 | OPCODE_INFO3 (0xf8008b00, |
| 5676 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5677 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5678 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5679 | CSKY_ISA_DSP_ENHANCE), |
| 5680 | OP32 ("rmulxh.s32", |
| 5681 | OPCODE_INFO3 (0xf8008d00, |
| 5682 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5683 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5684 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5685 | CSKY_ISA_DSP_ENHANCE), |
| 5686 | OP32 ("rmulxh.s32.r", |
| 5687 | OPCODE_INFO3 (0xf8008f00, |
| 5688 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5689 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5690 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5691 | CSKY_ISA_DSP_ENHANCE), |
| 5692 | OP32 ("mulaxl.s32.s", |
| 5693 | OPCODE_INFO3 (0xf8008980, |
| 5694 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5695 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5696 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5697 | CSKY_ISA_DSP_ENHANCE), |
| 5698 | OP32 ("mulaxl.s32.rs", |
| 5699 | OPCODE_INFO3 (0xf8008b80, |
| 5700 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5701 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5702 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5703 | CSKY_ISA_DSP_ENHANCE), |
| 5704 | OP32 ("mulaxh.s32.s", |
| 5705 | OPCODE_INFO3 (0xf8008d80, |
| 5706 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5707 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5708 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5709 | CSKY_ISA_DSP_ENHANCE), |
| 5710 | OP32 ("mulaxh.s32.rs", |
| 5711 | OPCODE_INFO3 (0xf8008f80, |
| 5712 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5713 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5714 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5715 | CSKY_ISA_DSP_ENHANCE), |
| 5716 | OP32 ("mulll.s16", |
| 5717 | OPCODE_INFO3 (0xf8008020, |
| 5718 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5719 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5720 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5721 | CSKY_ISA_DSP_ENHANCE), |
| 5722 | OP32 ("mulhh.s16", |
| 5723 | OPCODE_INFO3 (0xf8008260, |
| 5724 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5725 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5726 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5727 | CSKY_ISA_DSP_ENHANCE), |
| 5728 | OP32 ("mulhl.s16", |
| 5729 | OPCODE_INFO3 (0xf8008220, |
| 5730 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5731 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5732 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5733 | CSKY_ISA_DSP_ENHANCE), |
| 5734 | OP32 ("rmulll.s16", |
| 5735 | OPCODE_INFO3 (0xf8008120, |
| 5736 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5737 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5738 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5739 | CSKY_ISA_DSP_ENHANCE), |
| 5740 | OP32 ("rmulhh.s16", |
| 5741 | OPCODE_INFO3 (0xf8008360, |
| 5742 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5743 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5744 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5745 | CSKY_ISA_DSP_ENHANCE), |
| 5746 | OP32 ("rmulhl.s16", |
| 5747 | OPCODE_INFO3 (0xf8008320, |
| 5748 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5749 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5750 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5751 | CSKY_ISA_DSP_ENHANCE), |
| 5752 | OP32 ("mulahh.s16.s", |
| 5753 | OPCODE_INFO3 (0xf80083e0, |
| 5754 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5755 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5756 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5757 | CSKY_ISA_DSP_ENHANCE), |
| 5758 | OP32 ("mulahl.s16.s", |
| 5759 | OPCODE_INFO3 (0xf80083a0, |
| 5760 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5761 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5762 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5763 | CSKY_ISA_DSP_ENHANCE), |
| 5764 | OP32 ("mulall.s16.e", |
| 5765 | OPCODE_INFO3 (0xf80080a0, |
| 5766 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5767 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5768 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5769 | CSKY_ISA_DSP_ENHANCE), |
| 5770 | OP32 ("mulahh.s16.e", |
| 5771 | OPCODE_INFO3 (0xf80082e0, |
| 5772 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5773 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5774 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5775 | CSKY_ISA_DSP_ENHANCE), |
| 5776 | OP32 ("mulahl.s16.e", |
| 5777 | OPCODE_INFO3 (0xf80080e0, |
| 5778 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5779 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5780 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5781 | CSKY_ISA_DSP_ENHANCE), |
| 5782 | OP32 ("pmul.u16", |
| 5783 | OPCODE_INFO3 (0xf80084a0, |
| 5784 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5785 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5786 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5787 | CSKY_ISA_DSP_ENHANCE), |
| 5788 | OP32 ("pmulx.u16", |
| 5789 | OPCODE_INFO3 (0xf80084e0, |
| 5790 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5791 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5792 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5793 | CSKY_ISA_DSP_ENHANCE), |
| 5794 | OP32 ("pmul.s16", |
| 5795 | OPCODE_INFO3 (0xf8008420, |
| 5796 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5797 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5798 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5799 | CSKY_ISA_DSP_ENHANCE), |
| 5800 | OP32 ("pmulx.s16", |
| 5801 | OPCODE_INFO3 (0xf8008460, |
| 5802 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5803 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5804 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5805 | CSKY_ISA_DSP_ENHANCE), |
| 5806 | OP32 ("prmul.s16", |
| 5807 | OPCODE_INFO3 (0xf8008520, |
| 5808 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5809 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5810 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5811 | CSKY_ISA_DSP_ENHANCE), |
| 5812 | OP32 ("prmulx.s16", |
| 5813 | OPCODE_INFO3 (0xf8008560, |
| 5814 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5815 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5816 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5817 | CSKY_ISA_DSP_ENHANCE), |
| 5818 | OP32 ("prmul.s16.h", |
| 5819 | OPCODE_INFO3 (0xf80085a0, |
| 5820 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5821 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5822 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5823 | CSKY_ISA_DSP_ENHANCE), |
| 5824 | OP32 ("prmul.s16.rh", |
| 5825 | OPCODE_INFO3 (0xf80087a0, |
| 5826 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5827 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5828 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5829 | CSKY_ISA_DSP_ENHANCE), |
| 5830 | OP32 ("prmulx.s16.h", |
| 5831 | OPCODE_INFO3 (0xf80085e0, |
| 5832 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5833 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5834 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5835 | CSKY_ISA_DSP_ENHANCE), |
| 5836 | OP32 ("prmulx.s16.rh", |
| 5837 | OPCODE_INFO3 (0xf80087e0, |
| 5838 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5839 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5840 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5841 | CSKY_ISA_DSP_ENHANCE), |
| 5842 | OP32 ("mulca.s16.s", |
| 5843 | OPCODE_INFO3 (0xf8008920, |
| 5844 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5845 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5846 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5847 | CSKY_ISA_DSP_ENHANCE), |
| 5848 | OP32 ("mulcax.s16.s", |
| 5849 | OPCODE_INFO3 (0xf8008960, |
| 5850 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5851 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5852 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5853 | CSKY_ISA_DSP_ENHANCE), |
| 5854 | OP32 ("mulcs.s16", |
| 5855 | OPCODE_INFO3 (0xf8008a20, |
| 5856 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5857 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5858 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5859 | CSKY_ISA_DSP_ENHANCE), |
| 5860 | OP32 ("mulcsr.s16", |
| 5861 | OPCODE_INFO3 (0xf8008a60, |
| 5862 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5863 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5864 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5865 | CSKY_ISA_DSP_ENHANCE), |
| 5866 | OP32 ("mulcsx.s16", |
| 5867 | OPCODE_INFO3 (0xf8008c20, |
| 5868 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5869 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5870 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5871 | CSKY_ISA_DSP_ENHANCE), |
| 5872 | OP32 ("mulaca.s16.s", |
| 5873 | OPCODE_INFO3 (0xf80089a0, |
| 5874 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5875 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5876 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5877 | CSKY_ISA_DSP_ENHANCE), |
| 5878 | OP32 ("mulacax.s16.s", |
| 5879 | OPCODE_INFO3 (0xf80089e0, |
| 5880 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5881 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5882 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5883 | CSKY_ISA_DSP_ENHANCE), |
| 5884 | OP32 ("mulacs.s16.s", |
| 5885 | OPCODE_INFO3 (0xf8008ba0, |
| 5886 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5887 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5888 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5889 | CSKY_ISA_DSP_ENHANCE), |
| 5890 | OP32 ("mulacsr.s16.s", |
| 5891 | OPCODE_INFO3 (0xf8008be0, |
| 5892 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5893 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5894 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5895 | CSKY_ISA_DSP_ENHANCE), |
| 5896 | OP32 ("mulacsx.s16.s", |
| 5897 | OPCODE_INFO3 (0xf8008da0, |
| 5898 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5899 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5900 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5901 | CSKY_ISA_DSP_ENHANCE), |
| 5902 | OP32 ("mulsca.s16.s", |
| 5903 | OPCODE_INFO3 (0xf8008de0, |
| 5904 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5905 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5906 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5907 | CSKY_ISA_DSP_ENHANCE), |
| 5908 | OP32 ("mulscax.s16.s", |
| 5909 | OPCODE_INFO3 (0xf8008fa0, |
| 5910 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5911 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5912 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5913 | CSKY_ISA_DSP_ENHANCE), |
| 5914 | OP32 ("mulaca.s16.e", |
| 5915 | OPCODE_INFO3 (0xf80088a0, |
| 5916 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5917 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5918 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5919 | CSKY_ISA_DSP_ENHANCE), |
| 5920 | OP32 ("mulacax.s16.e", |
| 5921 | OPCODE_INFO3 (0xf80088e0, |
| 5922 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5923 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5924 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5925 | CSKY_ISA_DSP_ENHANCE), |
| 5926 | OP32 ("mulacs.s16.e", |
| 5927 | OPCODE_INFO3 (0xf8008aa0, |
| 5928 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5929 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5930 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5931 | CSKY_ISA_DSP_ENHANCE), |
| 5932 | OP32 ("mulacsr.s16.e", |
| 5933 | OPCODE_INFO3 (0xf8008ae0, |
| 5934 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5935 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5936 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5937 | CSKY_ISA_DSP_ENHANCE), |
| 5938 | OP32 ("mulacsx.s16.e", |
| 5939 | OPCODE_INFO3 (0xf8008ca0, |
| 5940 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5941 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5942 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5943 | CSKY_ISA_DSP_ENHANCE), |
| 5944 | OP32 ("mulsca.s16.e", |
| 5945 | OPCODE_INFO3 (0xf8008ce0, |
| 5946 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5947 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5948 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5949 | CSKY_ISA_DSP_ENHANCE), |
| 5950 | OP32 ("mulscax.s16.e", |
| 5951 | OPCODE_INFO3 (0xf8008ea0, |
| 5952 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5953 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 5954 | (21_25, AREG, OPRND_SHIFT_0_BIT)), |
| 5955 | CSKY_ISA_DSP_ENHANCE), |
| 5956 | |
| 5957 | /* The followings are vdsp instructions for ck810. */ |
| 5958 | OP32 ("vdup.8", |
| 5959 | OPCODE_INFO2 (0xf8000e80, |
| 5960 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 5961 | (16_19or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT)), |
| 5962 | CSKY_ISA_VDSP), |
| 5963 | OP32 ("vdup.16", |
| 5964 | OPCODE_INFO2 (0xf8100e80, |
| 5965 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 5966 | (16_19or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT)), |
| 5967 | CSKY_ISA_VDSP), |
| 5968 | OP32 ("vdup.32", |
| 5969 | OPCODE_INFO2 (0xfa000e80, |
| 5970 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 5971 | (16_19or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT)), |
| 5972 | CSKY_ISA_VDSP), |
| 5973 | OP32 ("vmfvr.u8", |
| 5974 | OPCODE_INFO2 (0xf8001200, |
| 5975 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5976 | (16_19or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT)), |
| 5977 | CSKY_ISA_VDSP), |
| 5978 | OP32 ("vmfvr.u16", |
| 5979 | OPCODE_INFO2 (0xf8001220, |
| 5980 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5981 | (16_19or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT)), |
| 5982 | CSKY_ISA_VDSP), |
| 5983 | OP32 ("vmfvr.u32", |
| 5984 | OPCODE_INFO2 (0xf8001240, |
| 5985 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5986 | (16_19or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT)), |
| 5987 | CSKY_ISA_VDSP), |
| 5988 | OP32 ("vmfvr.s8", |
| 5989 | OPCODE_INFO2 (0xf8001280, |
| 5990 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5991 | (16_19or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT)), |
| 5992 | CSKY_ISA_VDSP), |
| 5993 | OP32 ("vmfvr.s16", |
| 5994 | OPCODE_INFO2 (0xf80012a0, |
| 5995 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 5996 | (16_19or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT)), |
| 5997 | CSKY_ISA_VDSP), |
| 5998 | OP32 ("vmtvr.u8", |
| 5999 | OPCODE_INFO2 (0xf8001300, |
| 6000 | (0_3or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT), |
| 6001 | (16_20, AREG, OPRND_SHIFT_0_BIT)), |
| 6002 | CSKY_ISA_VDSP), |
| 6003 | OP32 ("vmtvr.u16", |
| 6004 | OPCODE_INFO2 (0xf8001320, |
| 6005 | (0_3or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT), |
| 6006 | (16_20, AREG, OPRND_SHIFT_0_BIT)), |
| 6007 | CSKY_ISA_VDSP), |
| 6008 | OP32 ("vmtvr.u32", |
| 6009 | OPCODE_INFO2 (0xf8001340, |
| 6010 | (0_3or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT), |
| 6011 | (16_20, AREG, OPRND_SHIFT_0_BIT)), |
| 6012 | CSKY_ISA_VDSP), |
| 6013 | OP32 ("vldd.8", |
| 6014 | SOPCODE_INFO2 (0xf8002000, |
| 6015 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 6016 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), |
| 6017 | (4_7or21_24, IMM_FLDST, OPRND_SHIFT_3_BIT))), |
| 6018 | CSKY_ISA_VDSP), |
| 6019 | OP32 ("vldd.16", |
| 6020 | SOPCODE_INFO2 (0xf8002100, |
| 6021 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 6022 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), |
| 6023 | (4_7or21_24, IMM_FLDST, OPRND_SHIFT_3_BIT))), |
| 6024 | CSKY_ISA_VDSP), |
| 6025 | OP32 ("vldd.32", |
| 6026 | SOPCODE_INFO2 (0xf8002200, |
| 6027 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 6028 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), |
| 6029 | (4_7or21_24, IMM_FLDST, OPRND_SHIFT_3_BIT))), |
| 6030 | CSKY_ISA_VDSP), |
| 6031 | OP32 ("vldq.8", |
| 6032 | SOPCODE_INFO2 (0xf8002400, |
| 6033 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 6034 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), |
| 6035 | (4_7or21_24, IMM_FLDST, OPRND_SHIFT_4_BIT))), |
| 6036 | CSKY_ISA_VDSP), |
| 6037 | OP32 ("vldq.16", |
| 6038 | SOPCODE_INFO2 (0xf8002500, |
| 6039 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 6040 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), |
| 6041 | (4_7or21_24, IMM_FLDST, OPRND_SHIFT_4_BIT))), |
| 6042 | CSKY_ISA_VDSP), |
| 6043 | OP32 ("vldq.32", |
| 6044 | SOPCODE_INFO2 (0xf8002600, |
| 6045 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 6046 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), |
| 6047 | (4_7or21_24, IMM_FLDST, OPRND_SHIFT_4_BIT))), |
| 6048 | CSKY_ISA_VDSP), |
| 6049 | OP32 ("vstd.8", |
| 6050 | SOPCODE_INFO2 (0xf8002800, |
| 6051 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 6052 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), |
| 6053 | (4_7or21_24, IMM_FLDST, OPRND_SHIFT_3_BIT))), |
| 6054 | CSKY_ISA_VDSP), |
| 6055 | OP32 ("vstd.16", |
| 6056 | SOPCODE_INFO2 (0xf8002900, |
| 6057 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 6058 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), |
| 6059 | (4_7or21_24, IMM_FLDST, OPRND_SHIFT_3_BIT))), |
| 6060 | CSKY_ISA_VDSP), |
| 6061 | OP32 ("vstd.32", |
| 6062 | SOPCODE_INFO2 (0xf8002a00, |
| 6063 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 6064 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), |
| 6065 | (4_7or21_24, IMM_FLDST, OPRND_SHIFT_3_BIT))), |
| 6066 | CSKY_ISA_VDSP), |
| 6067 | OP32 ("vstq.8", |
| 6068 | SOPCODE_INFO2 (0xf8002c00, |
| 6069 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 6070 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), |
| 6071 | (4_7or21_24, IMM_FLDST, OPRND_SHIFT_4_BIT))), |
| 6072 | CSKY_ISA_VDSP), |
| 6073 | OP32 ("vstq.16", |
| 6074 | SOPCODE_INFO2 (0xf8002d00, |
| 6075 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 6076 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), |
| 6077 | (4_7or21_24, IMM_FLDST, OPRND_SHIFT_4_BIT))), |
| 6078 | CSKY_ISA_VDSP), |
| 6079 | OP32 ("vstq.32", |
| 6080 | SOPCODE_INFO2 (0xf8002e00, |
| 6081 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 6082 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), |
| 6083 | (4_7or21_24, IMM_FLDST, OPRND_SHIFT_4_BIT))), |
| 6084 | CSKY_ISA_VDSP), |
| 6085 | OP32 ("vldrd.8", |
| 6086 | SOPCODE_INFO2 (0xf8003000, |
| 6087 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 6088 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), |
| 6089 | (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), |
| 6090 | CSKY_ISA_VDSP), |
| 6091 | OP32 ("vldrd.16", |
| 6092 | SOPCODE_INFO2 (0xf8003100, |
| 6093 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 6094 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), |
| 6095 | (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), |
| 6096 | CSKY_ISA_VDSP), |
| 6097 | OP32 ("vldrd.32", |
| 6098 | SOPCODE_INFO2 (0xf8003200, |
| 6099 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 6100 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), |
| 6101 | (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), |
| 6102 | CSKY_ISA_VDSP), |
| 6103 | OP32 ("vldrq.8", |
| 6104 | SOPCODE_INFO2 (0xf8003400, |
| 6105 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 6106 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), |
| 6107 | (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), |
| 6108 | CSKY_ISA_VDSP), |
| 6109 | OP32 ("vldrq.16", |
| 6110 | SOPCODE_INFO2 (0xf8003500, |
| 6111 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 6112 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), |
| 6113 | (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), |
| 6114 | CSKY_ISA_VDSP), |
| 6115 | OP32 ("vldrq.32", |
| 6116 | SOPCODE_INFO2 (0xf8003600, |
| 6117 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 6118 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), |
| 6119 | (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), |
| 6120 | CSKY_ISA_VDSP), |
| 6121 | OP32 ("vstrd.8", |
| 6122 | SOPCODE_INFO2 (0xf8003800, |
| 6123 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 6124 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), |
| 6125 | (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), |
| 6126 | CSKY_ISA_VDSP), |
| 6127 | OP32 ("vstrd.16", |
| 6128 | SOPCODE_INFO2 (0xf8003900, |
| 6129 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 6130 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), |
| 6131 | (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), |
| 6132 | CSKY_ISA_VDSP), |
| 6133 | OP32 ("vstrd.32", |
| 6134 | SOPCODE_INFO2 (0xf8003a00, |
| 6135 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 6136 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), |
| 6137 | (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), |
| 6138 | CSKY_ISA_VDSP), |
| 6139 | OP32 ("vstrq.8", |
| 6140 | SOPCODE_INFO2 (0xf8003c00, |
| 6141 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 6142 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), |
| 6143 | (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), |
| 6144 | CSKY_ISA_VDSP), |
| 6145 | OP32 ("vstrq.16", |
| 6146 | SOPCODE_INFO2 (0xf8003d00, |
| 6147 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 6148 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), |
| 6149 | (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), |
| 6150 | CSKY_ISA_VDSP), |
| 6151 | OP32 ("vstrq.32", |
| 6152 | SOPCODE_INFO2 (0xf8003e00, |
| 6153 | (0_3, FREG, OPRND_SHIFT_0_BIT), |
| 6154 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), |
| 6155 | (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), |
| 6156 | CSKY_ISA_VDSP), |
| 6157 | OP32 ("vmov", |
| 6158 | OPCODE_INFO2 (0xf8000c00, |
| 6159 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6160 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6161 | CSKY_ISA_VDSP), |
| 6162 | OP32 ("vcadd.eu8", |
| 6163 | OPCODE_INFO2 (0xf8000060, |
| 6164 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6165 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6166 | CSKY_ISA_VDSP), |
| 6167 | OP32 ("vcadd.eu16", |
| 6168 | OPCODE_INFO2 (0xf8100060, |
| 6169 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6170 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6171 | CSKY_ISA_VDSP), |
| 6172 | OP32 ("vcadd.es8", |
| 6173 | OPCODE_INFO2 (0xf8000070, |
| 6174 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6175 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6176 | CSKY_ISA_VDSP), |
| 6177 | OP32 ("vcadd.es16", |
| 6178 | OPCODE_INFO2 (0xf8100070, |
| 6179 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6180 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6181 | CSKY_ISA_VDSP), |
| 6182 | OP32 ("vmov.eu8", |
| 6183 | OPCODE_INFO2 (0xf8000c20, |
| 6184 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6185 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6186 | CSKY_ISA_VDSP), |
| 6187 | OP32 ("vmov.eu16", |
| 6188 | OPCODE_INFO2 (0xf8100c20, |
| 6189 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6190 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6191 | CSKY_ISA_VDSP), |
| 6192 | OP32 ("vmov.es8", |
| 6193 | OPCODE_INFO2 (0xf8000c30, |
| 6194 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6195 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6196 | CSKY_ISA_VDSP), |
| 6197 | OP32 ("vmov.es16", |
| 6198 | OPCODE_INFO2 (0xf8100c30, |
| 6199 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6200 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6201 | CSKY_ISA_VDSP), |
| 6202 | OP32 ("vmov.u16.l", |
| 6203 | OPCODE_INFO2 (0xf8100d00, |
| 6204 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6205 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6206 | CSKY_ISA_VDSP), |
| 6207 | OP32 ("vmov.u32.l", |
| 6208 | OPCODE_INFO2 (0xfa000d00, |
| 6209 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6210 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6211 | CSKY_ISA_VDSP), |
| 6212 | OP32 ("vmov.s16.l", |
| 6213 | OPCODE_INFO2 (0xf8100d10, |
| 6214 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6215 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6216 | CSKY_ISA_VDSP), |
| 6217 | OP32 ("vmov.s32.l", |
| 6218 | OPCODE_INFO2 (0xfa000d10, |
| 6219 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6220 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6221 | CSKY_ISA_VDSP), |
| 6222 | OP32 ("vmov.u16.sl", |
| 6223 | OPCODE_INFO2 (0xf8100d40, |
| 6224 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6225 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6226 | CSKY_ISA_VDSP), |
| 6227 | OP32 ("vmov.u32.sl", |
| 6228 | OPCODE_INFO2 (0xfa000d40, |
| 6229 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6230 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6231 | CSKY_ISA_VDSP), |
| 6232 | OP32 ("vmov.s16.sl", |
| 6233 | OPCODE_INFO2 (0xf8100d50, |
| 6234 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6235 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6236 | CSKY_ISA_VDSP), |
| 6237 | OP32 ("vmov.s32.sl", |
| 6238 | OPCODE_INFO2 (0xfa000d50, |
| 6239 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6240 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6241 | CSKY_ISA_VDSP), |
| 6242 | OP32 ("vmov.u16.h", |
| 6243 | OPCODE_INFO2 (0xf8100d60, |
| 6244 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6245 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6246 | CSKY_ISA_VDSP), |
| 6247 | OP32 ("vmov.u32.h", |
| 6248 | OPCODE_INFO2 (0xfa000d60, |
| 6249 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6250 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6251 | CSKY_ISA_VDSP), |
| 6252 | OP32 ("vmov.s16.h", |
| 6253 | OPCODE_INFO2 (0xf8100d70, |
| 6254 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6255 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6256 | CSKY_ISA_VDSP), |
| 6257 | OP32 ("vmov.s32.h", |
| 6258 | OPCODE_INFO2 (0xfa000d70, |
| 6259 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6260 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6261 | CSKY_ISA_VDSP), |
| 6262 | OP32 ("vmov.u16.rh", |
| 6263 | OPCODE_INFO2 (0xf8100d80, |
| 6264 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6265 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6266 | CSKY_ISA_VDSP), |
| 6267 | OP32 ("vmov.u32.rh", |
| 6268 | OPCODE_INFO2 (0xfa000d80, |
| 6269 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6270 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6271 | CSKY_ISA_VDSP), |
| 6272 | OP32 ("vmov.s16.rh", |
| 6273 | OPCODE_INFO2 (0xf8100d90, |
| 6274 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6275 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6276 | CSKY_ISA_VDSP), |
| 6277 | OP32 ("vmov.s32.rh", |
| 6278 | OPCODE_INFO2 (0xfa000d90, |
| 6279 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6280 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6281 | CSKY_ISA_VDSP), |
| 6282 | OP32 ("vstou.u16.sl", |
| 6283 | OPCODE_INFO2 (0xf8100dc0, |
| 6284 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6285 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6286 | CSKY_ISA_VDSP), |
| 6287 | OP32 ("vstou.u32.sl", |
| 6288 | OPCODE_INFO2 (0xfa000dc0, |
| 6289 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6290 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6291 | CSKY_ISA_VDSP), |
| 6292 | OP32 ("vstou.s16.sl", |
| 6293 | OPCODE_INFO2 (0xf8100dd0, |
| 6294 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6295 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6296 | CSKY_ISA_VDSP), |
| 6297 | OP32 ("vstou.s32.sl", |
| 6298 | OPCODE_INFO2 (0xfa000dd0, |
| 6299 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6300 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6301 | CSKY_ISA_VDSP), |
| 6302 | OP32 ("vrev.8", |
| 6303 | OPCODE_INFO2 (0xf8000e60, |
| 6304 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6305 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6306 | CSKY_ISA_VDSP), |
| 6307 | OP32 ("vrev.16", |
| 6308 | OPCODE_INFO2 (0xf8100e60, |
| 6309 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6310 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6311 | CSKY_ISA_VDSP), |
| 6312 | OP32 ("vrev.32", |
| 6313 | OPCODE_INFO2 (0xfa000e60, |
| 6314 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6315 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6316 | CSKY_ISA_VDSP), |
| 6317 | OP32 ("vcnt1.8", |
| 6318 | OPCODE_INFO2 (0xf8000ea0, |
| 6319 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6320 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6321 | CSKY_ISA_VDSP), |
| 6322 | OP32 ("vclz.8", |
| 6323 | OPCODE_INFO2 (0xf8000ec0, |
| 6324 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6325 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6326 | CSKY_ISA_VDSP), |
| 6327 | OP32 ("vclz.16", |
| 6328 | OPCODE_INFO2 (0xf8100ec0, |
| 6329 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6330 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6331 | CSKY_ISA_VDSP), |
| 6332 | OP32 ("vclz.32", |
| 6333 | OPCODE_INFO2 (0xfa000ec0, |
| 6334 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6335 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6336 | CSKY_ISA_VDSP), |
| 6337 | OP32 ("vcls.u8", |
| 6338 | OPCODE_INFO2 (0xf8000ee0, |
| 6339 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6340 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6341 | CSKY_ISA_VDSP), |
| 6342 | OP32 ("vcls.u16", |
| 6343 | OPCODE_INFO2 (0xf8100ee0, |
| 6344 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6345 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6346 | CSKY_ISA_VDSP), |
| 6347 | OP32 ("vcls.u32", |
| 6348 | OPCODE_INFO2 (0xfa000ee0, |
| 6349 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6350 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6351 | CSKY_ISA_VDSP), |
| 6352 | OP32 ("vcls.s8", |
| 6353 | OPCODE_INFO2 (0xf8000ef0, |
| 6354 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6355 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6356 | CSKY_ISA_VDSP), |
| 6357 | OP32 ("vcls.s16", |
| 6358 | OPCODE_INFO2 (0xf8100ef0, |
| 6359 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6360 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6361 | CSKY_ISA_VDSP), |
| 6362 | OP32 ("vcls.s32", |
| 6363 | OPCODE_INFO2 (0xfa000ef0, |
| 6364 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6365 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6366 | CSKY_ISA_VDSP), |
| 6367 | OP32 ("vabs.s8", |
| 6368 | OPCODE_INFO2 (0xf8001010, |
| 6369 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6370 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6371 | CSKY_ISA_VDSP), |
| 6372 | OP32 ("vabs.s16", |
| 6373 | OPCODE_INFO2 (0xf8101010, |
| 6374 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6375 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6376 | CSKY_ISA_VDSP), |
| 6377 | OP32 ("vabs.s32", |
| 6378 | OPCODE_INFO2 (0xfa001010, |
| 6379 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6380 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6381 | CSKY_ISA_VDSP), |
| 6382 | OP32 ("vabs.u8.s", |
| 6383 | OPCODE_INFO2 (0xf8001040, |
| 6384 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6385 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6386 | CSKY_ISA_VDSP), |
| 6387 | OP32 ("vabs.u16.s", |
| 6388 | OPCODE_INFO2 (0xf8101040, |
| 6389 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6390 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6391 | CSKY_ISA_VDSP), |
| 6392 | OP32 ("vabs.u32.s", |
| 6393 | OPCODE_INFO2 (0xfa001040, |
| 6394 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6395 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6396 | CSKY_ISA_VDSP), |
| 6397 | OP32 ("vabs.s8.s", |
| 6398 | OPCODE_INFO2 (0xf8001050, |
| 6399 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6400 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6401 | CSKY_ISA_VDSP), |
| 6402 | OP32 ("vabs.s16.s", |
| 6403 | OPCODE_INFO2 (0xf8101050, |
| 6404 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6405 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6406 | CSKY_ISA_VDSP), |
| 6407 | OP32 ("vabs.s32.s", |
| 6408 | OPCODE_INFO2 (0xfa001050, |
| 6409 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6410 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6411 | CSKY_ISA_VDSP), |
| 6412 | OP32 ("vneg.u8", |
| 6413 | OPCODE_INFO2 (0xf8001080, |
| 6414 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6415 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6416 | CSKY_ISA_VDSP), |
| 6417 | OP32 ("vneg.u16", |
| 6418 | OPCODE_INFO2 (0xf8101080, |
| 6419 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6420 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6421 | CSKY_ISA_VDSP), |
| 6422 | OP32 ("vneg.u32", |
| 6423 | OPCODE_INFO2 (0xfa001080, |
| 6424 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6425 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6426 | CSKY_ISA_VDSP), |
| 6427 | OP32 ("vneg.s8", |
| 6428 | OPCODE_INFO2 (0xf8001090, |
| 6429 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6430 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6431 | CSKY_ISA_VDSP), |
| 6432 | OP32 ("vneg.s16", |
| 6433 | OPCODE_INFO2 (0xf8101090, |
| 6434 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6435 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6436 | CSKY_ISA_VDSP), |
| 6437 | OP32 ("vneg.s32", |
| 6438 | OPCODE_INFO2 (0xfa001090, |
| 6439 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6440 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6441 | CSKY_ISA_VDSP), |
| 6442 | OP32 ("vneg.u8.s", |
| 6443 | OPCODE_INFO2 (0xf80010c0, |
| 6444 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6445 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6446 | CSKY_ISA_VDSP), |
| 6447 | OP32 ("vneg.u16.s", |
| 6448 | OPCODE_INFO2 (0xf81010c0, |
| 6449 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6450 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6451 | CSKY_ISA_VDSP), |
| 6452 | OP32 ("vneg.u32.s", |
| 6453 | OPCODE_INFO2 (0xfa0010c0, |
| 6454 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6455 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6456 | CSKY_ISA_VDSP), |
| 6457 | OP32 ("vneg.s8.s", |
| 6458 | OPCODE_INFO2 (0xf80010d0, |
| 6459 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6460 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6461 | CSKY_ISA_VDSP), |
| 6462 | OP32 ("vneg.s16.s", |
| 6463 | OPCODE_INFO2 (0xf81010d0, |
| 6464 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6465 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6466 | CSKY_ISA_VDSP), |
| 6467 | OP32 ("vneg.s32.s", |
| 6468 | OPCODE_INFO2 (0xfa0010d0, |
| 6469 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6470 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6471 | CSKY_ISA_VDSP), |
| 6472 | OP32 ("vcmphsz.u8", |
| 6473 | OPCODE_INFO2 (0xf8000880, |
| 6474 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6475 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6476 | CSKY_ISA_VDSP), |
| 6477 | OP32 ("vcmphsz.u16", |
| 6478 | OPCODE_INFO2 (0xf8100880, |
| 6479 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6480 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6481 | CSKY_ISA_VDSP), |
| 6482 | OP32 ("vcmphsz.u32", |
| 6483 | OPCODE_INFO2 (0xfa000880, |
| 6484 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6485 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6486 | CSKY_ISA_VDSP), |
| 6487 | OP32 ("vcmphsz.s8", |
| 6488 | OPCODE_INFO2 (0xf8000890, |
| 6489 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6490 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6491 | CSKY_ISA_VDSP), |
| 6492 | OP32 ("vcmphsz.s16", |
| 6493 | OPCODE_INFO2 (0xf8100890, |
| 6494 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6495 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6496 | CSKY_ISA_VDSP), |
| 6497 | OP32 ("vcmphsz.s32", |
| 6498 | OPCODE_INFO2 (0xfa000890, |
| 6499 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6500 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6501 | CSKY_ISA_VDSP), |
| 6502 | OP32 ("vcmpltz.u8", |
| 6503 | OPCODE_INFO2 (0xf80008a0, |
| 6504 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6505 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6506 | CSKY_ISA_VDSP), |
| 6507 | OP32 ("vcmpltz.u16", |
| 6508 | OPCODE_INFO2 (0xf81008a0, |
| 6509 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6510 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6511 | CSKY_ISA_VDSP), |
| 6512 | OP32 ("vcmpltz.u32", |
| 6513 | OPCODE_INFO2 (0xfa0008a0, |
| 6514 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6515 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6516 | CSKY_ISA_VDSP), |
| 6517 | OP32 ("vcmpltz.s8", |
| 6518 | OPCODE_INFO2 (0xf80008b0, |
| 6519 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6520 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6521 | CSKY_ISA_VDSP), |
| 6522 | OP32 ("vcmpltz.s16", |
| 6523 | OPCODE_INFO2 (0xf81008b0, |
| 6524 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6525 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6526 | CSKY_ISA_VDSP), |
| 6527 | OP32 ("vcmpltz.s32", |
| 6528 | OPCODE_INFO2 (0xfa0008b0, |
| 6529 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6530 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6531 | CSKY_ISA_VDSP), |
| 6532 | OP32 ("vcmpnez.u8", |
| 6533 | OPCODE_INFO2 (0xf80008c0, |
| 6534 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6535 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6536 | CSKY_ISA_VDSP), |
| 6537 | OP32 ("vcmpnez.u16", |
| 6538 | OPCODE_INFO2 (0xf81008c0, |
| 6539 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6540 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6541 | CSKY_ISA_VDSP), |
| 6542 | OP32 ("vcmpnez.u32", |
| 6543 | OPCODE_INFO2 (0xfa0008c0, |
| 6544 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6545 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6546 | CSKY_ISA_VDSP), |
| 6547 | OP32 ("vcmpnez.s8", |
| 6548 | OPCODE_INFO2 (0xf80008d0, |
| 6549 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6550 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6551 | CSKY_ISA_VDSP), |
| 6552 | OP32 ("vcmpnez.s16", |
| 6553 | OPCODE_INFO2 (0xf81008d0, |
| 6554 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6555 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6556 | CSKY_ISA_VDSP), |
| 6557 | OP32 ("vcmpnez.s32", |
| 6558 | OPCODE_INFO2 (0xfa0008d0, |
| 6559 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6560 | (16_19, VREG, OPRND_SHIFT_0_BIT)), |
| 6561 | CSKY_ISA_VDSP), |
| 6562 | OP32 ("vtrch.8", |
| 6563 | OPCODE_INFO3 (0xf8000f40, |
| 6564 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6565 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 6566 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 6567 | CSKY_ISA_VDSP), |
| 6568 | OP32 ("vtrch.16", |
| 6569 | OPCODE_INFO3 (0xf8100f40, |
| 6570 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6571 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 6572 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 6573 | CSKY_ISA_VDSP), |
| 6574 | OP32 ("vtrch.32", |
| 6575 | OPCODE_INFO3 (0xfa000f40, |
| 6576 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6577 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 6578 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 6579 | CSKY_ISA_VDSP), |
| 6580 | OP32 ("vtrcl.8", |
| 6581 | OPCODE_INFO3 (0xf8000f60, |
| 6582 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6583 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 6584 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 6585 | CSKY_ISA_VDSP), |
| 6586 | OP32 ("vtrcl.16", |
| 6587 | OPCODE_INFO3 (0xf8100f60, |
| 6588 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6589 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 6590 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 6591 | CSKY_ISA_VDSP), |
| 6592 | OP32 ("vtrcl.32", |
| 6593 | OPCODE_INFO3 (0xfa000f60, |
| 6594 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6595 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 6596 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 6597 | CSKY_ISA_VDSP), |
| 6598 | OP32 ("vadd.u8", |
| 6599 | OPCODE_INFO3 (0xf8000000, |
| 6600 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6601 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 6602 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 6603 | CSKY_ISA_VDSP), |
| 6604 | OP32 ("vadd.u16", |
| 6605 | OPCODE_INFO3 (0xf8100000, |
| 6606 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6607 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 6608 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 6609 | CSKY_ISA_VDSP), |
| 6610 | OP32 ("vadd.u32", |
| 6611 | OPCODE_INFO3 (0xfa000000, |
| 6612 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6613 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 6614 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 6615 | CSKY_ISA_VDSP), |
| 6616 | OP32 ("vadd.s8", |
| 6617 | OPCODE_INFO3 (0xf8000010, |
| 6618 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6619 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 6620 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 6621 | CSKY_ISA_VDSP), |
| 6622 | OP32 ("vadd.s16", |
| 6623 | OPCODE_INFO3 (0xf8100010, |
| 6624 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6625 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 6626 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 6627 | CSKY_ISA_VDSP), |
| 6628 | OP32 ("vadd.s32", |
| 6629 | OPCODE_INFO3 (0xfa000010, |
| 6630 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6631 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 6632 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 6633 | CSKY_ISA_VDSP), |
| 6634 | OP32 ("vadd.eu8", |
| 6635 | OPCODE_INFO3 (0xf8000020, |
| 6636 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6637 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 6638 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 6639 | CSKY_ISA_VDSP), |
| 6640 | OP32 ("vadd.eu16", |
| 6641 | OPCODE_INFO3 (0xf8100020, |
| 6642 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6643 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 6644 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 6645 | CSKY_ISA_VDSP), |
| 6646 | OP32 ("vadd.es8", |
| 6647 | OPCODE_INFO3 (0xf8000030, |
| 6648 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6649 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 6650 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 6651 | CSKY_ISA_VDSP), |
| 6652 | OP32 ("vadd.es16", |
| 6653 | OPCODE_INFO3 (0xf8100030, |
| 6654 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6655 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 6656 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 6657 | CSKY_ISA_VDSP), |
| 6658 | OP32 ("vcadd.u8", |
| 6659 | OPCODE_INFO3 (0xf8000040, |
| 6660 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6661 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 6662 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 6663 | CSKY_ISA_VDSP), |
| 6664 | OP32 ("vcadd.u16", |
| 6665 | OPCODE_INFO3 (0xf8100040, |
| 6666 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6667 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 6668 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 6669 | CSKY_ISA_VDSP), |
| 6670 | OP32 ("vcadd.u32", |
| 6671 | OPCODE_INFO3 (0xfa000040, |
| 6672 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6673 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 6674 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 6675 | CSKY_ISA_VDSP), |
| 6676 | OP32 ("vcadd.s8", |
| 6677 | OPCODE_INFO3 (0xf8000050, |
| 6678 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6679 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 6680 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 6681 | CSKY_ISA_VDSP), |
| 6682 | OP32 ("vcadd.s16", |
| 6683 | OPCODE_INFO3 (0xf8100050, |
| 6684 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6685 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 6686 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 6687 | CSKY_ISA_VDSP), |
| 6688 | OP32 ("vcadd.s32", |
| 6689 | OPCODE_INFO3 (0xfa000050, |
| 6690 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6691 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 6692 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 6693 | CSKY_ISA_VDSP), |
| 6694 | OP32 ("vadd.xu16.sl", |
| 6695 | OPCODE_INFO3 (0xf8100140, |
| 6696 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6697 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 6698 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 6699 | CSKY_ISA_VDSP), |
| 6700 | OP32 ("vadd.xu32.sl", |
| 6701 | OPCODE_INFO3 (0xfa000140, |
| 6702 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6703 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 6704 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 6705 | CSKY_ISA_VDSP), |
| 6706 | OP32 ("vadd.xs16.sl", |
| 6707 | OPCODE_INFO3 (0xf8100150, |
| 6708 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6709 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 6710 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 6711 | CSKY_ISA_VDSP), |
| 6712 | OP32 ("vadd.xs32.sl", |
| 6713 | OPCODE_INFO3 (0xfa000150, |
| 6714 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6715 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 6716 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 6717 | CSKY_ISA_VDSP), |
| 6718 | OP32 ("vadd.xu16", |
| 6719 | OPCODE_INFO3 (0xf8100160, |
| 6720 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6721 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 6722 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 6723 | CSKY_ISA_VDSP), |
| 6724 | OP32 ("vadd.xu32", |
| 6725 | OPCODE_INFO3 (0xfa000160, |
| 6726 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6727 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 6728 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 6729 | CSKY_ISA_VDSP), |
| 6730 | OP32 ("vadd.xs16", |
| 6731 | OPCODE_INFO3 (0xf8100170, |
| 6732 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6733 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 6734 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 6735 | CSKY_ISA_VDSP), |
| 6736 | OP32 ("vadd.xs32", |
| 6737 | OPCODE_INFO3 (0xfa000170, |
| 6738 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6739 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 6740 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 6741 | CSKY_ISA_VDSP), |
| 6742 | OP32 ("vaddh.u8", |
| 6743 | OPCODE_INFO3 (0xf8000180, |
| 6744 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6745 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 6746 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 6747 | CSKY_ISA_VDSP), |
| 6748 | OP32 ("vaddh.u16", |
| 6749 | OPCODE_INFO3 (0xf8100180, |
| 6750 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6751 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 6752 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 6753 | CSKY_ISA_VDSP), |
| 6754 | OP32 ("vaddh.u32", |
| 6755 | OPCODE_INFO3 (0xfa000180, |
| 6756 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6757 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 6758 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 6759 | CSKY_ISA_VDSP), |
| 6760 | OP32 ("vaddh.s8", |
| 6761 | OPCODE_INFO3 (0xf8000190, |
| 6762 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6763 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 6764 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 6765 | CSKY_ISA_VDSP), |
| 6766 | OP32 ("vaddh.s16", |
| 6767 | OPCODE_INFO3 (0xf8100190, |
| 6768 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6769 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 6770 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 6771 | CSKY_ISA_VDSP), |
| 6772 | OP32 ("vaddh.s32", |
| 6773 | OPCODE_INFO3 (0xfa000190, |
| 6774 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6775 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 6776 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 6777 | CSKY_ISA_VDSP), |
| 6778 | OP32 ("vaddh.u8.r", |
| 6779 | OPCODE_INFO3 (0xf80001a0, |
| 6780 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6781 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 6782 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 6783 | CSKY_ISA_VDSP), |
| 6784 | OP32 ("vaddh.u16.r", |
| 6785 | OPCODE_INFO3 (0xf81001a0, |
| 6786 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6787 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 6788 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 6789 | CSKY_ISA_VDSP), |
| 6790 | OP32 ("vaddh.u32.r", |
| 6791 | OPCODE_INFO3 (0xfa0001a0, |
| 6792 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6793 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 6794 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 6795 | CSKY_ISA_VDSP), |
| 6796 | OP32 ("vaddh.s8.r", |
| 6797 | OPCODE_INFO3 (0xf80001b0, |
| 6798 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6799 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 6800 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 6801 | CSKY_ISA_VDSP), |
| 6802 | OP32 ("vaddh.s16.r", |
| 6803 | OPCODE_INFO3 (0xf81001b0, |
| 6804 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6805 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 6806 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 6807 | CSKY_ISA_VDSP), |
| 6808 | OP32 ("vaddh.s32.r", |
| 6809 | OPCODE_INFO3 (0xfa0001b0, |
| 6810 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6811 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 6812 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 6813 | CSKY_ISA_VDSP), |
| 6814 | OP32 ("vadd.u8.s", |
| 6815 | OPCODE_INFO3 (0xf80001c0, |
| 6816 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6817 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 6818 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 6819 | CSKY_ISA_VDSP), |
| 6820 | OP32 ("vadd.u16.s", |
| 6821 | OPCODE_INFO3 (0xf81001c0, |
| 6822 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6823 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 6824 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 6825 | CSKY_ISA_VDSP), |
| 6826 | OP32 ("vadd.u32.s", |
| 6827 | OPCODE_INFO3 (0xfa0001c0, |
| 6828 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6829 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 6830 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 6831 | CSKY_ISA_VDSP), |
| 6832 | OP32 ("vadd.s8.s", |
| 6833 | OPCODE_INFO3 (0xf80001d0, |
| 6834 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6835 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 6836 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 6837 | CSKY_ISA_VDSP), |
| 6838 | OP32 ("vadd.s16.s", |
| 6839 | OPCODE_INFO3 (0xf81001d0, |
| 6840 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6841 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 6842 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 6843 | CSKY_ISA_VDSP), |
| 6844 | OP32 ("vadd.s32.s", |
| 6845 | OPCODE_INFO3 (0xfa0001d0, |
| 6846 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6847 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 6848 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 6849 | CSKY_ISA_VDSP), |
| 6850 | OP32 ("vsub.u8", |
| 6851 | OPCODE_INFO3 (0xf8000200, |
| 6852 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6853 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 6854 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 6855 | CSKY_ISA_VDSP), |
| 6856 | OP32 ("vsub.u16", |
| 6857 | OPCODE_INFO3 (0xf8100200, |
| 6858 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6859 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 6860 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 6861 | CSKY_ISA_VDSP), |
| 6862 | OP32 ("vsub.u32", |
| 6863 | OPCODE_INFO3 (0xfa000200, |
| 6864 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6865 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 6866 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 6867 | CSKY_ISA_VDSP), |
| 6868 | OP32 ("vsub.s8", |
| 6869 | OPCODE_INFO3 (0xf8000210, |
| 6870 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6871 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 6872 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 6873 | CSKY_ISA_VDSP), |
| 6874 | OP32 ("vsub.s16", |
| 6875 | OPCODE_INFO3 (0xf8100210, |
| 6876 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6877 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 6878 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 6879 | CSKY_ISA_VDSP), |
| 6880 | OP32 ("vsub.s32", |
| 6881 | OPCODE_INFO3 (0xfa000210, |
| 6882 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6883 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 6884 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 6885 | CSKY_ISA_VDSP), |
| 6886 | OP32 ("vsub.eu8", |
| 6887 | OPCODE_INFO3 (0xf8000220, |
| 6888 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6889 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 6890 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 6891 | CSKY_ISA_VDSP), |
| 6892 | OP32 ("vsub.eu16", |
| 6893 | OPCODE_INFO3 (0xf8100220, |
| 6894 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6895 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 6896 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 6897 | CSKY_ISA_VDSP), |
| 6898 | OP32 ("vsub.eu32", |
| 6899 | OPCODE_INFO3 (0xfa000220, |
| 6900 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6901 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 6902 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 6903 | CSKY_ISA_VDSP), |
| 6904 | OP32 ("vsub.es8", |
| 6905 | OPCODE_INFO3 (0xf8000230, |
| 6906 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6907 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 6908 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 6909 | CSKY_ISA_VDSP), |
| 6910 | OP32 ("vsub.es16", |
| 6911 | OPCODE_INFO3 (0xf8100230, |
| 6912 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6913 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 6914 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 6915 | CSKY_ISA_VDSP), |
| 6916 | OP32 ("vsub.es32", |
| 6917 | OPCODE_INFO3 (0xfa000230, |
| 6918 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6919 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 6920 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 6921 | CSKY_ISA_VDSP), |
| 6922 | OP32 ("vsabs.u8", |
| 6923 | OPCODE_INFO3 (0xf8000240, |
| 6924 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6925 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 6926 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 6927 | CSKY_ISA_VDSP), |
| 6928 | OP32 ("vsabs.u16", |
| 6929 | OPCODE_INFO3 (0xf8100240, |
| 6930 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6931 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 6932 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 6933 | CSKY_ISA_VDSP), |
| 6934 | OP32 ("vsabs.u32", |
| 6935 | OPCODE_INFO3 (0xfa000240, |
| 6936 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6937 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 6938 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 6939 | CSKY_ISA_VDSP), |
| 6940 | OP32 ("vsabs.s8", |
| 6941 | OPCODE_INFO3 (0xf8000250, |
| 6942 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6943 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 6944 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 6945 | CSKY_ISA_VDSP), |
| 6946 | OP32 ("vsabs.s16", |
| 6947 | OPCODE_INFO3 (0xf8100250, |
| 6948 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6949 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 6950 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 6951 | CSKY_ISA_VDSP), |
| 6952 | OP32 ("vsabs.s32", |
| 6953 | OPCODE_INFO3 (0xfa000250, |
| 6954 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6955 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 6956 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 6957 | CSKY_ISA_VDSP), |
| 6958 | OP32 ("vsabs.eu8", |
| 6959 | OPCODE_INFO3 (0xf8000260, |
| 6960 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6961 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 6962 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 6963 | CSKY_ISA_VDSP), |
| 6964 | OP32 ("vsabs.eu16", |
| 6965 | OPCODE_INFO3 (0xf8100260, |
| 6966 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6967 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 6968 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 6969 | CSKY_ISA_VDSP), |
| 6970 | OP32 ("vsabs.es8", |
| 6971 | OPCODE_INFO3 (0xf8000270, |
| 6972 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6973 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 6974 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 6975 | CSKY_ISA_VDSP), |
| 6976 | OP32 ("vsabs.es16", |
| 6977 | OPCODE_INFO3 (0xf8100270, |
| 6978 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6979 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 6980 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 6981 | CSKY_ISA_VDSP), |
| 6982 | OP32 ("vsabsa.u8", |
| 6983 | OPCODE_INFO3 (0xf8000280, |
| 6984 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6985 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 6986 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 6987 | CSKY_ISA_VDSP), |
| 6988 | OP32 ("vsabsa.u16", |
| 6989 | OPCODE_INFO3 (0xf8100280, |
| 6990 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6991 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 6992 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 6993 | CSKY_ISA_VDSP), |
| 6994 | OP32 ("vsabsa.u32", |
| 6995 | OPCODE_INFO3 (0xfa000280, |
| 6996 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 6997 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 6998 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 6999 | CSKY_ISA_VDSP), |
| 7000 | OP32 ("vsabsa.s8", |
| 7001 | OPCODE_INFO3 (0xf8000290, |
| 7002 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7003 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7004 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7005 | CSKY_ISA_VDSP), |
| 7006 | OP32 ("vsabsa.s16", |
| 7007 | OPCODE_INFO3 (0xf8100290, |
| 7008 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7009 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7010 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7011 | CSKY_ISA_VDSP), |
| 7012 | OP32 ("vsabsa.s32", |
| 7013 | OPCODE_INFO3 (0xfa000290, |
| 7014 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7015 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7016 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7017 | CSKY_ISA_VDSP), |
| 7018 | OP32 ("vsabsa.eu8", |
| 7019 | OPCODE_INFO3 (0xf80002a0, |
| 7020 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7021 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7022 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7023 | CSKY_ISA_VDSP), |
| 7024 | OP32 ("vsabsa.eu16", |
| 7025 | OPCODE_INFO3 (0xf81002a0, |
| 7026 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7027 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7028 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7029 | CSKY_ISA_VDSP), |
| 7030 | OP32 ("vsabsa.es8", |
| 7031 | OPCODE_INFO3 (0xf80002b0, |
| 7032 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7033 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7034 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7035 | CSKY_ISA_VDSP), |
| 7036 | OP32 ("vsabsa.es16", |
| 7037 | OPCODE_INFO3 (0xf81002b0, |
| 7038 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7039 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7040 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7041 | CSKY_ISA_VDSP), |
| 7042 | OP32 ("vsub.xu16", |
| 7043 | OPCODE_INFO3 (0xf8100360, |
| 7044 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7045 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7046 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7047 | CSKY_ISA_VDSP), |
| 7048 | OP32 ("vsub.xu32", |
| 7049 | OPCODE_INFO3 (0xfa000360, |
| 7050 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7051 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7052 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7053 | CSKY_ISA_VDSP), |
| 7054 | OP32 ("vsub.xs16", |
| 7055 | OPCODE_INFO3 (0xf8100370, |
| 7056 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7057 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7058 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7059 | CSKY_ISA_VDSP), |
| 7060 | OP32 ("vsub.xs32", |
| 7061 | OPCODE_INFO3 (0xfa000370, |
| 7062 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7063 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7064 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7065 | CSKY_ISA_VDSP), |
| 7066 | OP32 ("vsubh.u8", |
| 7067 | OPCODE_INFO3 (0xf8000380, |
| 7068 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7069 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7070 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7071 | CSKY_ISA_VDSP), |
| 7072 | OP32 ("vsubh.u16", |
| 7073 | OPCODE_INFO3 (0xf8100380, |
| 7074 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7075 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7076 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7077 | CSKY_ISA_VDSP), |
| 7078 | OP32 ("vsubh.u32", |
| 7079 | OPCODE_INFO3 (0xfa000380, |
| 7080 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7081 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7082 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7083 | CSKY_ISA_VDSP), |
| 7084 | OP32 ("vsubh.s8", |
| 7085 | OPCODE_INFO3 (0xf8000390, |
| 7086 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7087 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7088 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7089 | CSKY_ISA_VDSP), |
| 7090 | OP32 ("vsubh.s16", |
| 7091 | OPCODE_INFO3 (0xf8100390, |
| 7092 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7093 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7094 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7095 | CSKY_ISA_VDSP), |
| 7096 | OP32 ("vsubh.s32", |
| 7097 | OPCODE_INFO3 (0xfa000390, |
| 7098 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7099 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7100 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7101 | CSKY_ISA_VDSP), |
| 7102 | OP32 ("vsubh.u8.r", |
| 7103 | OPCODE_INFO3 (0xf80003a0, |
| 7104 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7105 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7106 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7107 | CSKY_ISA_VDSP), |
| 7108 | OP32 ("vsubh.u16.r", |
| 7109 | OPCODE_INFO3 (0xf81003a0, |
| 7110 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7111 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7112 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7113 | CSKY_ISA_VDSP), |
| 7114 | OP32 ("vsubh.u32.r", |
| 7115 | OPCODE_INFO3 (0xfa0003a0, |
| 7116 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7117 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7118 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7119 | CSKY_ISA_VDSP), |
| 7120 | OP32 ("vsubh.s8.r", |
| 7121 | OPCODE_INFO3 (0xf80003b0, |
| 7122 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7123 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7124 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7125 | CSKY_ISA_VDSP), |
| 7126 | OP32 ("vsubh.s16.r", |
| 7127 | OPCODE_INFO3 (0xf81003b0, |
| 7128 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7129 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7130 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7131 | CSKY_ISA_VDSP), |
| 7132 | OP32 ("vsubh.s32.r", |
| 7133 | OPCODE_INFO3 (0xfa0003b0, |
| 7134 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7135 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7136 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7137 | CSKY_ISA_VDSP), |
| 7138 | OP32 ("vsub.u8.s", |
| 7139 | OPCODE_INFO3 (0xf80003c0, |
| 7140 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7141 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7142 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7143 | CSKY_ISA_VDSP), |
| 7144 | OP32 ("vsub.u16.s", |
| 7145 | OPCODE_INFO3 (0xf81003c0, |
| 7146 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7147 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7148 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7149 | CSKY_ISA_VDSP), |
| 7150 | OP32 ("vsub.u32.s", |
| 7151 | OPCODE_INFO3 (0xfa0003c0, |
| 7152 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7153 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7154 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7155 | CSKY_ISA_VDSP), |
| 7156 | OP32 ("vsub.s8.s", |
| 7157 | OPCODE_INFO3 (0xf80003d0, |
| 7158 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7159 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7160 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7161 | CSKY_ISA_VDSP), |
| 7162 | OP32 ("vsub.s16.s", |
| 7163 | OPCODE_INFO3 (0xf81003d0, |
| 7164 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7165 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7166 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7167 | CSKY_ISA_VDSP), |
| 7168 | OP32 ("vsub.s32.s", |
| 7169 | OPCODE_INFO3 (0xfa0003d0, |
| 7170 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7171 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7172 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7173 | CSKY_ISA_VDSP), |
| 7174 | OP32 ("vmul.u8", |
| 7175 | OPCODE_INFO3 (0xf8000400, |
| 7176 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7177 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7178 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7179 | CSKY_ISA_VDSP), |
| 7180 | OP32 ("vmul.u16", |
| 7181 | OPCODE_INFO3 (0xf8100400, |
| 7182 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7183 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7184 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7185 | CSKY_ISA_VDSP), |
| 7186 | OP32 ("vmul.u32", |
| 7187 | OPCODE_INFO3 (0xfa000400, |
| 7188 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7189 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7190 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7191 | CSKY_ISA_VDSP), |
| 7192 | OP32 ("vmul.s8", |
| 7193 | OPCODE_INFO3 (0xf8000410, |
| 7194 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7195 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7196 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7197 | CSKY_ISA_VDSP), |
| 7198 | OP32 ("vmul.s16", |
| 7199 | OPCODE_INFO3 (0xf8100410, |
| 7200 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7201 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7202 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7203 | CSKY_ISA_VDSP), |
| 7204 | OP32 ("vmul.s32", |
| 7205 | OPCODE_INFO3 (0xfa000410, |
| 7206 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7207 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7208 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7209 | CSKY_ISA_VDSP), |
| 7210 | OP32 ("vmul.eu8", |
| 7211 | OPCODE_INFO3 (0xf8000420, |
| 7212 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7213 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7214 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7215 | CSKY_ISA_VDSP), |
| 7216 | OP32 ("vmul.eu16", |
| 7217 | OPCODE_INFO3 (0xf8100420, |
| 7218 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7219 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7220 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7221 | CSKY_ISA_VDSP), |
| 7222 | OP32 ("vmul.es8", |
| 7223 | OPCODE_INFO3 (0xf8000430, |
| 7224 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7225 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7226 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7227 | CSKY_ISA_VDSP), |
| 7228 | OP32 ("vmul.es16", |
| 7229 | OPCODE_INFO3 (0xf8100430, |
| 7230 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7231 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7232 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7233 | CSKY_ISA_VDSP), |
| 7234 | OP32 ("vmula.u8", |
| 7235 | OPCODE_INFO3 (0xf8000440, |
| 7236 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7237 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7238 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7239 | CSKY_ISA_VDSP), |
| 7240 | OP32 ("vmula.u16", |
| 7241 | OPCODE_INFO3 (0xf8100440, |
| 7242 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7243 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7244 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7245 | CSKY_ISA_VDSP), |
| 7246 | OP32 ("vmula.u32", |
| 7247 | OPCODE_INFO3 (0xfa000440, |
| 7248 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7249 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7250 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7251 | CSKY_ISA_VDSP), |
| 7252 | OP32 ("vmula.s8", |
| 7253 | OPCODE_INFO3 (0xf8000450, |
| 7254 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7255 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7256 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7257 | CSKY_ISA_VDSP), |
| 7258 | OP32 ("vmula.s16", |
| 7259 | OPCODE_INFO3 (0xf8100450, |
| 7260 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7261 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7262 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7263 | CSKY_ISA_VDSP), |
| 7264 | OP32 ("vmula.s32", |
| 7265 | OPCODE_INFO3 (0xfa000450, |
| 7266 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7267 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7268 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7269 | CSKY_ISA_VDSP), |
| 7270 | OP32 ("vmula.eu8", |
| 7271 | OPCODE_INFO3 (0xf8000460, |
| 7272 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7273 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7274 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7275 | CSKY_ISA_VDSP), |
| 7276 | OP32 ("vmula.eu16", |
| 7277 | OPCODE_INFO3 (0xf8100460, |
| 7278 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7279 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7280 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7281 | CSKY_ISA_VDSP), |
| 7282 | OP32 ("vmula.eu32", |
| 7283 | OPCODE_INFO3 (0xfa000460, |
| 7284 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7285 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7286 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7287 | CSKY_ISA_VDSP), |
| 7288 | OP32 ("vmula.es8", |
| 7289 | OPCODE_INFO3 (0xf8000470, |
| 7290 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7291 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7292 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7293 | CSKY_ISA_VDSP), |
| 7294 | OP32 ("vmula.es16", |
| 7295 | OPCODE_INFO3 (0xf8100470, |
| 7296 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7297 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7298 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7299 | CSKY_ISA_VDSP), |
| 7300 | OP32 ("vmula.es32", |
| 7301 | OPCODE_INFO3 (0xfa000470, |
| 7302 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7303 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7304 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7305 | CSKY_ISA_VDSP), |
| 7306 | OP32 ("vmuls.u8", |
| 7307 | OPCODE_INFO3 (0xf8000480, |
| 7308 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7309 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7310 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7311 | CSKY_ISA_VDSP), |
| 7312 | OP32 ("vmuls.u16", |
| 7313 | OPCODE_INFO3 (0xf8100480, |
| 7314 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7315 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7316 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7317 | CSKY_ISA_VDSP), |
| 7318 | OP32 ("vmuls.u32", |
| 7319 | OPCODE_INFO3 (0xfa000480, |
| 7320 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7321 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7322 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7323 | CSKY_ISA_VDSP), |
| 7324 | OP32 ("vmuls.s8", |
| 7325 | OPCODE_INFO3 (0xf8000490, |
| 7326 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7327 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7328 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7329 | CSKY_ISA_VDSP), |
| 7330 | OP32 ("vmuls.s16", |
| 7331 | OPCODE_INFO3 (0xf8100490, |
| 7332 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7333 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7334 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7335 | CSKY_ISA_VDSP), |
| 7336 | OP32 ("vmuls.s32", |
| 7337 | OPCODE_INFO3 (0xfa000490, |
| 7338 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7339 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7340 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7341 | CSKY_ISA_VDSP), |
| 7342 | OP32 ("vmuls.eu8", |
| 7343 | OPCODE_INFO3 (0xf80004a0, |
| 7344 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7345 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7346 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7347 | CSKY_ISA_VDSP), |
| 7348 | OP32 ("vmuls.eu16", |
| 7349 | OPCODE_INFO3 (0xf81004a0, |
| 7350 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7351 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7352 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7353 | CSKY_ISA_VDSP), |
| 7354 | OP32 ("vmuls.es8", |
| 7355 | OPCODE_INFO3 (0xf80004b0, |
| 7356 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7357 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7358 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7359 | CSKY_ISA_VDSP), |
| 7360 | OP32 ("vmuls.es16", |
| 7361 | OPCODE_INFO3 (0xf81004b0, |
| 7362 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7363 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7364 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7365 | CSKY_ISA_VDSP), |
| 7366 | OP32 ("vshr.u8", |
| 7367 | OPCODE_INFO3 (0xf8000680, |
| 7368 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7369 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7370 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7371 | CSKY_ISA_VDSP), |
| 7372 | OP32 ("vshr.u16", |
| 7373 | OPCODE_INFO3 (0xf8100680, |
| 7374 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7375 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7376 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7377 | CSKY_ISA_VDSP), |
| 7378 | OP32 ("vshr.u32", |
| 7379 | OPCODE_INFO3 (0xfa000680, |
| 7380 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7381 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7382 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7383 | CSKY_ISA_VDSP), |
| 7384 | OP32 ("vshr.s8", |
| 7385 | OPCODE_INFO3 (0xf8000690, |
| 7386 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7387 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7388 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7389 | CSKY_ISA_VDSP), |
| 7390 | OP32 ("vshr.s16", |
| 7391 | OPCODE_INFO3 (0xf8100690, |
| 7392 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7393 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7394 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7395 | CSKY_ISA_VDSP), |
| 7396 | OP32 ("vshr.s32", |
| 7397 | OPCODE_INFO3 (0xfa000690, |
| 7398 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7399 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7400 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7401 | CSKY_ISA_VDSP), |
| 7402 | OP32 ("vshr.u8.r", |
| 7403 | OPCODE_INFO3 (0xf80006c0, |
| 7404 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7405 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7406 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7407 | CSKY_ISA_VDSP), |
| 7408 | OP32 ("vshr.u16.r", |
| 7409 | OPCODE_INFO3 (0xf81006c0, |
| 7410 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7411 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7412 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7413 | CSKY_ISA_VDSP), |
| 7414 | OP32 ("vshr.u32.r", |
| 7415 | OPCODE_INFO3 (0xfa0006c0, |
| 7416 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7417 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7418 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7419 | CSKY_ISA_VDSP), |
| 7420 | OP32 ("vshr.s8.r", |
| 7421 | OPCODE_INFO3 (0xf80006d0, |
| 7422 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7423 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7424 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7425 | CSKY_ISA_VDSP), |
| 7426 | OP32 ("vshr.s16.r", |
| 7427 | OPCODE_INFO3 (0xf81006d0, |
| 7428 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7429 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7430 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7431 | CSKY_ISA_VDSP), |
| 7432 | OP32 ("vshr.s32.r", |
| 7433 | OPCODE_INFO3 (0xfa0006d0, |
| 7434 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7435 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7436 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7437 | CSKY_ISA_VDSP), |
| 7438 | OP32 ("vshl.u8", |
| 7439 | OPCODE_INFO3 (0xf8000780, |
| 7440 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7441 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7442 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7443 | CSKY_ISA_VDSP), |
| 7444 | OP32 ("vshl.u16", |
| 7445 | OPCODE_INFO3 (0xf8100780, |
| 7446 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7447 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7448 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7449 | CSKY_ISA_VDSP), |
| 7450 | OP32 ("vshl.u32", |
| 7451 | OPCODE_INFO3 (0xfa000780, |
| 7452 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7453 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7454 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7455 | CSKY_ISA_VDSP), |
| 7456 | OP32 ("vshl.s8", |
| 7457 | OPCODE_INFO3 (0xf8000790, |
| 7458 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7459 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7460 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7461 | CSKY_ISA_VDSP), |
| 7462 | OP32 ("vshl.s16", |
| 7463 | OPCODE_INFO3 (0xf8100790, |
| 7464 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7465 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7466 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7467 | CSKY_ISA_VDSP), |
| 7468 | OP32 ("vshl.s32", |
| 7469 | OPCODE_INFO3 (0xfa000790, |
| 7470 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7471 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7472 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7473 | CSKY_ISA_VDSP), |
| 7474 | OP32 ("vshl.u8.s", |
| 7475 | OPCODE_INFO3 (0xf80007c0, |
| 7476 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7477 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7478 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7479 | CSKY_ISA_VDSP), |
| 7480 | OP32 ("vshl.u16.s", |
| 7481 | OPCODE_INFO3 (0xf81007c0, |
| 7482 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7483 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7484 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7485 | CSKY_ISA_VDSP), |
| 7486 | OP32 ("vshl.u32.s", |
| 7487 | OPCODE_INFO3 (0xfa0007c0, |
| 7488 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7489 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7490 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7491 | CSKY_ISA_VDSP), |
| 7492 | OP32 ("vshl.s8.s", |
| 7493 | OPCODE_INFO3 (0xf80007d0, |
| 7494 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7495 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7496 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7497 | CSKY_ISA_VDSP), |
| 7498 | OP32 ("vshl.s16.s", |
| 7499 | OPCODE_INFO3 (0xf81007d0, |
| 7500 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7501 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7502 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7503 | CSKY_ISA_VDSP), |
| 7504 | OP32 ("vshl.s32.s", |
| 7505 | OPCODE_INFO3 (0xfa0007d0, |
| 7506 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7507 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7508 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7509 | CSKY_ISA_VDSP), |
| 7510 | OP32 ("vcmphs.u8", |
| 7511 | OPCODE_INFO3 (0xf8000800, |
| 7512 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7513 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7514 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7515 | CSKY_ISA_VDSP), |
| 7516 | OP32 ("vcmphs.u16", |
| 7517 | OPCODE_INFO3 (0xf8100800, |
| 7518 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7519 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7520 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7521 | CSKY_ISA_VDSP), |
| 7522 | OP32 ("vcmphs.u32", |
| 7523 | OPCODE_INFO3 (0xfa000800, |
| 7524 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7525 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7526 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7527 | CSKY_ISA_VDSP), |
| 7528 | OP32 ("vcmphs.s8", |
| 7529 | OPCODE_INFO3 (0xf8000810, |
| 7530 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7531 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7532 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7533 | CSKY_ISA_VDSP), |
| 7534 | OP32 ("vcmphs.s16", |
| 7535 | OPCODE_INFO3 (0xf8100810, |
| 7536 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7537 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7538 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7539 | CSKY_ISA_VDSP), |
| 7540 | OP32 ("vcmphs.s32", |
| 7541 | OPCODE_INFO3 (0xfa000810, |
| 7542 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7543 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7544 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7545 | CSKY_ISA_VDSP), |
| 7546 | OP32 ("vcmplt.u8", |
| 7547 | OPCODE_INFO3 (0xf8000820, |
| 7548 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7549 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7550 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7551 | CSKY_ISA_VDSP), |
| 7552 | OP32 ("vcmplt.u16", |
| 7553 | OPCODE_INFO3 (0xf8100820, |
| 7554 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7555 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7556 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7557 | CSKY_ISA_VDSP), |
| 7558 | OP32 ("vcmplt.u32", |
| 7559 | OPCODE_INFO3 (0xfa000820, |
| 7560 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7561 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7562 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7563 | CSKY_ISA_VDSP), |
| 7564 | OP32 ("vcmplt.s8", |
| 7565 | OPCODE_INFO3 (0xf8000830, |
| 7566 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7567 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7568 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7569 | CSKY_ISA_VDSP), |
| 7570 | OP32 ("vcmplt.s16", |
| 7571 | OPCODE_INFO3 (0xf8100830, |
| 7572 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7573 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7574 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7575 | CSKY_ISA_VDSP), |
| 7576 | OP32 ("vcmplt.s32", |
| 7577 | OPCODE_INFO3 (0xfa000830, |
| 7578 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7579 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7580 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7581 | CSKY_ISA_VDSP), |
| 7582 | OP32 ("vcmpne.u8", |
| 7583 | OPCODE_INFO3 (0xf8000840, |
| 7584 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7585 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7586 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7587 | CSKY_ISA_VDSP), |
| 7588 | OP32 ("vcmpne.u16", |
| 7589 | OPCODE_INFO3 (0xf8100840, |
| 7590 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7591 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7592 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7593 | CSKY_ISA_VDSP), |
| 7594 | OP32 ("vcmpne.u32", |
| 7595 | OPCODE_INFO3 (0xfa000840, |
| 7596 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7597 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7598 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7599 | CSKY_ISA_VDSP), |
| 7600 | OP32 ("vcmpne.s8", |
| 7601 | OPCODE_INFO3 (0xf8000850, |
| 7602 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7603 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7604 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7605 | CSKY_ISA_VDSP), |
| 7606 | OP32 ("vcmpne.s16", |
| 7607 | OPCODE_INFO3 (0xf8100850, |
| 7608 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7609 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7610 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7611 | CSKY_ISA_VDSP), |
| 7612 | OP32 ("vcmpne.s32", |
| 7613 | OPCODE_INFO3 (0xfa000850, |
| 7614 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7615 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7616 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7617 | CSKY_ISA_VDSP), |
| 7618 | OP32 ("vmax.u8", |
| 7619 | OPCODE_INFO3 (0xf8000900, |
| 7620 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7621 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7622 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7623 | CSKY_ISA_VDSP), |
| 7624 | OP32 ("vmax.u16", |
| 7625 | OPCODE_INFO3 (0xf8100900, |
| 7626 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7627 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7628 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7629 | CSKY_ISA_VDSP), |
| 7630 | OP32 ("vmax.u32", |
| 7631 | OPCODE_INFO3 (0xfa000900, |
| 7632 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7633 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7634 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7635 | CSKY_ISA_VDSP), |
| 7636 | OP32 ("vmax.s8", |
| 7637 | OPCODE_INFO3 (0xf8000910, |
| 7638 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7639 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7640 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7641 | CSKY_ISA_VDSP), |
| 7642 | OP32 ("vmax.s16", |
| 7643 | OPCODE_INFO3 (0xf8100910, |
| 7644 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7645 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7646 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7647 | CSKY_ISA_VDSP), |
| 7648 | OP32 ("vmax.s32", |
| 7649 | OPCODE_INFO3 (0xfa000910, |
| 7650 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7651 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7652 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7653 | CSKY_ISA_VDSP), |
| 7654 | OP32 ("vmin.u8", |
| 7655 | OPCODE_INFO3 (0xf8000920, |
| 7656 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7657 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7658 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7659 | CSKY_ISA_VDSP), |
| 7660 | OP32 ("vmin.u16", |
| 7661 | OPCODE_INFO3 (0xf8100920, |
| 7662 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7663 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7664 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7665 | CSKY_ISA_VDSP), |
| 7666 | OP32 ("vmin.u32", |
| 7667 | OPCODE_INFO3 (0xfa000920, |
| 7668 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7669 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7670 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7671 | CSKY_ISA_VDSP), |
| 7672 | OP32 ("vmin.s8", |
| 7673 | OPCODE_INFO3 (0xf8000930, |
| 7674 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7675 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7676 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7677 | CSKY_ISA_VDSP), |
| 7678 | OP32 ("vmin.s16", |
| 7679 | OPCODE_INFO3 (0xf8100930, |
| 7680 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7681 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7682 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7683 | CSKY_ISA_VDSP), |
| 7684 | OP32 ("vmin.s32", |
| 7685 | OPCODE_INFO3 (0xfa000930, |
| 7686 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7687 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7688 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7689 | CSKY_ISA_VDSP), |
| 7690 | OP32 ("vcmax.u8", |
| 7691 | OPCODE_INFO3 (0xf8000980, |
| 7692 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7693 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7694 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7695 | CSKY_ISA_VDSP), |
| 7696 | OP32 ("vcmax.u16", |
| 7697 | OPCODE_INFO3 (0xf8100980, |
| 7698 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7699 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7700 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7701 | CSKY_ISA_VDSP), |
| 7702 | OP32 ("vcmax.u32", |
| 7703 | OPCODE_INFO3 (0xfa000980, |
| 7704 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7705 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7706 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7707 | CSKY_ISA_VDSP), |
| 7708 | OP32 ("vcmax.s8", |
| 7709 | OPCODE_INFO3 (0xf8000990, |
| 7710 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7711 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7712 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7713 | CSKY_ISA_VDSP), |
| 7714 | OP32 ("vcmax.s16", |
| 7715 | OPCODE_INFO3 (0xf8100990, |
| 7716 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7717 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7718 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7719 | CSKY_ISA_VDSP), |
| 7720 | OP32 ("vcmax.s32", |
| 7721 | OPCODE_INFO3 (0xfa000990, |
| 7722 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7723 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7724 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7725 | CSKY_ISA_VDSP), |
| 7726 | OP32 ("vcmin.u8", |
| 7727 | OPCODE_INFO3 (0xf80009a0, |
| 7728 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7729 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7730 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7731 | CSKY_ISA_VDSP), |
| 7732 | OP32 ("vcmin.u16", |
| 7733 | OPCODE_INFO3 (0xf81009a0, |
| 7734 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7735 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7736 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7737 | CSKY_ISA_VDSP), |
| 7738 | OP32 ("vcmin.u32", |
| 7739 | OPCODE_INFO3 (0xfa0009a0, |
| 7740 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7741 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7742 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7743 | CSKY_ISA_VDSP), |
| 7744 | OP32 ("vcmin.s8", |
| 7745 | OPCODE_INFO3 (0xf80009b0, |
| 7746 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7747 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7748 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7749 | CSKY_ISA_VDSP), |
| 7750 | OP32 ("vcmin.s16", |
| 7751 | OPCODE_INFO3 (0xf81009b0, |
| 7752 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7753 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7754 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7755 | CSKY_ISA_VDSP), |
| 7756 | OP32 ("vcmin.s32", |
| 7757 | OPCODE_INFO3 (0xfa0009b0, |
| 7758 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7759 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7760 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7761 | CSKY_ISA_VDSP), |
| 7762 | OP32 ("vand.8", |
| 7763 | OPCODE_INFO3 (0xf8000a00, |
| 7764 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7765 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7766 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7767 | CSKY_ISA_VDSP), |
| 7768 | OP32 ("vand.16", |
| 7769 | OPCODE_INFO3 (0xf8100a00, |
| 7770 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7771 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7772 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7773 | CSKY_ISA_VDSP), |
| 7774 | OP32 ("vand.32", |
| 7775 | OPCODE_INFO3 (0xfa000a00, |
| 7776 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7777 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7778 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7779 | CSKY_ISA_VDSP), |
| 7780 | OP32 ("vandn.8", |
| 7781 | OPCODE_INFO3 (0xf8000a20, |
| 7782 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7783 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7784 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7785 | CSKY_ISA_VDSP), |
| 7786 | OP32 ("vandn.16", |
| 7787 | OPCODE_INFO3 (0xf8100a20, |
| 7788 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7789 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7790 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7791 | CSKY_ISA_VDSP), |
| 7792 | OP32 ("vandn.32", |
| 7793 | OPCODE_INFO3 (0xfa000a20, |
| 7794 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7795 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7796 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7797 | CSKY_ISA_VDSP), |
| 7798 | OP32 ("vor.8", |
| 7799 | OPCODE_INFO3 (0xf8000a40, |
| 7800 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7801 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7802 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7803 | CSKY_ISA_VDSP), |
| 7804 | OP32 ("vor.16", |
| 7805 | OPCODE_INFO3 (0xf8100a40, |
| 7806 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7807 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7808 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7809 | CSKY_ISA_VDSP), |
| 7810 | OP32 ("vor.32", |
| 7811 | OPCODE_INFO3 (0xfa000a40, |
| 7812 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7813 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7814 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7815 | CSKY_ISA_VDSP), |
| 7816 | OP32 ("vnor.8", |
| 7817 | OPCODE_INFO3 (0xf8000a60, |
| 7818 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7819 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7820 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7821 | CSKY_ISA_VDSP), |
| 7822 | OP32 ("vnor.16", |
| 7823 | OPCODE_INFO3 (0xf8100a60, |
| 7824 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7825 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7826 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7827 | CSKY_ISA_VDSP), |
| 7828 | OP32 ("vnor.32", |
| 7829 | OPCODE_INFO3 (0xfa000a60, |
| 7830 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7831 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7832 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7833 | CSKY_ISA_VDSP), |
| 7834 | OP32 ("vxor.8", |
| 7835 | OPCODE_INFO3 (0xf8000a80, |
| 7836 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7837 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7838 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7839 | CSKY_ISA_VDSP), |
| 7840 | OP32 ("vxor.16", |
| 7841 | OPCODE_INFO3 (0xf8100a80, |
| 7842 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7843 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7844 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7845 | CSKY_ISA_VDSP), |
| 7846 | OP32 ("vxor.32", |
| 7847 | OPCODE_INFO3 (0xfa000a80, |
| 7848 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7849 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7850 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7851 | CSKY_ISA_VDSP), |
| 7852 | OP32 ("vtst.8", |
| 7853 | OPCODE_INFO3 (0xf8000b20, |
| 7854 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7855 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7856 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7857 | CSKY_ISA_VDSP), |
| 7858 | OP32 ("vtst.16", |
| 7859 | OPCODE_INFO3 (0xf8100b20, |
| 7860 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7861 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7862 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7863 | CSKY_ISA_VDSP), |
| 7864 | OP32 ("vtst.32", |
| 7865 | OPCODE_INFO3 (0xfa000b20, |
| 7866 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7867 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7868 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7869 | CSKY_ISA_VDSP), |
| 7870 | OP32 ("vbpermz.8", |
| 7871 | OPCODE_INFO3 (0xf8000f00, |
| 7872 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7873 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7874 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7875 | CSKY_ISA_VDSP), |
| 7876 | OP32 ("vbpermz.16", |
| 7877 | OPCODE_INFO3 (0xf8100f00, |
| 7878 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7879 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7880 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7881 | CSKY_ISA_VDSP), |
| 7882 | OP32 ("vbpermz.32", |
| 7883 | OPCODE_INFO3 (0xfa000f00, |
| 7884 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7885 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7886 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7887 | CSKY_ISA_VDSP), |
| 7888 | OP32 ("vbperm.8", |
| 7889 | OPCODE_INFO3 (0xf8000f20, |
| 7890 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7891 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7892 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7893 | CSKY_ISA_VDSP), |
| 7894 | OP32 ("vbperm.16", |
| 7895 | OPCODE_INFO3 (0xf8100f20, |
| 7896 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7897 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7898 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7899 | CSKY_ISA_VDSP), |
| 7900 | OP32 ("vbperm.32", |
| 7901 | OPCODE_INFO3 (0xfa000f20, |
| 7902 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7903 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7904 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7905 | CSKY_ISA_VDSP), |
| 7906 | OP32 ("vdch.8", |
| 7907 | OPCODE_INFO3 (0xf8000fc0, |
| 7908 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7909 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7910 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7911 | CSKY_ISA_VDSP), |
| 7912 | OP32 ("vdch.16", |
| 7913 | OPCODE_INFO3 (0xf8100fc0, |
| 7914 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7915 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7916 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7917 | CSKY_ISA_VDSP), |
| 7918 | OP32 ("vdch.32", |
| 7919 | OPCODE_INFO3 (0xfa000fc0, |
| 7920 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7921 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7922 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7923 | CSKY_ISA_VDSP), |
| 7924 | OP32 ("vdcl.8", |
| 7925 | OPCODE_INFO3 (0xf8000fe0, |
| 7926 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7927 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7928 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7929 | CSKY_ISA_VDSP), |
| 7930 | OP32 ("vdcl.16", |
| 7931 | OPCODE_INFO3 (0xf8100fe0, |
| 7932 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7933 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7934 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7935 | CSKY_ISA_VDSP), |
| 7936 | OP32 ("vdcl.32", |
| 7937 | OPCODE_INFO3 (0xfa000fe0, |
| 7938 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7939 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7940 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7941 | CSKY_ISA_VDSP), |
| 7942 | OP32 ("vich.8", |
| 7943 | OPCODE_INFO3 (0xf8000f80, |
| 7944 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7945 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7946 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7947 | CSKY_ISA_VDSP), |
| 7948 | OP32 ("vich.16", |
| 7949 | OPCODE_INFO3 (0xf8100f80, |
| 7950 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7951 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7952 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7953 | CSKY_ISA_VDSP), |
| 7954 | OP32 ("vich.32", |
| 7955 | OPCODE_INFO3 (0xfa000f80, |
| 7956 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7957 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7958 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7959 | CSKY_ISA_VDSP), |
| 7960 | OP32 ("vicl.8", |
| 7961 | OPCODE_INFO3 (0xf8000fa0, |
| 7962 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7963 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7964 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7965 | CSKY_ISA_VDSP), |
| 7966 | OP32 ("vicl.16", |
| 7967 | OPCODE_INFO3 (0xf8100fa0, |
| 7968 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7969 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7970 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7971 | CSKY_ISA_VDSP), |
| 7972 | OP32 ("vicl.32", |
| 7973 | OPCODE_INFO3 (0xfa000fa0, |
| 7974 | (0_3, VREG, OPRND_SHIFT_0_BIT), |
| 7975 | (16_19, VREG, OPRND_SHIFT_0_BIT), |
| 7976 | (21_24, VREG, OPRND_SHIFT_0_BIT)), |
| 7977 | CSKY_ISA_VDSP), |
| 7978 | |
| 7979 | /* The following are aliases for other instructions. */ |
| 7980 | /* setc -> cmphs r0, r0 */ |
| 7981 | OP16 ("setc", |
| 7982 | OPCODE_INFO0 (0x6400), |
| 7983 | CSKYV2_ISA_E1), |
| 7984 | /* clrc -> cmpne r0, r0 */ |
| 7985 | OP16 ("clrc", |
| 7986 | OPCODE_INFO0 (0x6402), |
| 7987 | CSKYV2_ISA_E1), |
| 7988 | /* tstlt rd -> btsti rd,31 */ |
| 7989 | OP32 ("tstlt", |
| 7990 | OPCODE_INFO1 (0xc7e02880, |
| 7991 | (16_20, AREG, OPRND_SHIFT_0_BIT)), |
| 7992 | CSKYV2_ISA_1E2), |
| 7993 | /* idly4 -> idly 4 */ |
| 7994 | OP32 ("idly4", |
| 7995 | OPCODE_INFO0 (0xc0601c20), |
| 7996 | CSKYV2_ISA_E1), |
| 7997 | /* rsub rz, ry, rx -> subu rz, rx, ry */ |
| 7998 | DOP32 ("rsub", |
| 7999 | OPCODE_INFO3 (0xc4000080, |
| 8000 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 8001 | (21_25, AREG, OPRND_SHIFT_0_BIT), |
| 8002 | (16_20, AREG, OPRND_SHIFT_0_BIT)), |
| 8003 | OPCODE_INFO2 (0xc4000080, |
| 8004 | (0_4or21_25, DUP_AREG, OPRND_SHIFT_0_BIT), |
| 8005 | (16_20, AREG, OPRND_SHIFT_0_BIT)), CSKYV2_ISA_1E2), |
| 8006 | /* cmplei rd,X -> cmplti rd,X+1 */ |
| 8007 | OP16_OP32 ("cmplei", |
| 8008 | OPCODE_INFO2 (0x3820, |
| 8009 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT), |
| 8010 | (0_4, IMM5b, OPRND_SHIFT_0_BIT)), |
| 8011 | CSKYV2_ISA_E1, |
| 8012 | OPCODE_INFO2 (0xeb200000, |
| 8013 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 8014 | (0_15, IMM16b, OPRND_SHIFT_0_BIT)), |
| 8015 | CSKYV2_ISA_1E2), |
| 8016 | /* cmpls -> cmphs */ |
| 8017 | OP16_OP32 ("cmpls", |
| 8018 | OPCODE_INFO2 (0x6400, |
| 8019 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), |
| 8020 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 8021 | CSKYV2_ISA_E1, |
| 8022 | OPCODE_INFO2 (0xc4000420, |
| 8023 | (21_25, AREG, OPRND_SHIFT_0_BIT), |
| 8024 | (16_20, AREG, OPRND_SHIFT_0_BIT)), |
| 8025 | CSKYV2_ISA_2E3), |
| 8026 | /* cmpgt -> cmplt */ |
| 8027 | OP16_OP32 ("cmpgt", |
| 8028 | OPCODE_INFO2 (0x6401, |
| 8029 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), |
| 8030 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), |
| 8031 | CSKYV2_ISA_E1, |
| 8032 | OPCODE_INFO2 (0xc4000440, |
| 8033 | (21_25, AREG, OPRND_SHIFT_0_BIT), |
| 8034 | (16_20, AREG, OPRND_SHIFT_0_BIT)), |
| 8035 | CSKYV2_ISA_2E3), |
| 8036 | /* tstle rd -> cmplti rd,1 */ |
| 8037 | OP16_OP32 ("tstle", |
| 8038 | OPCODE_INFO1 (0x3820, |
| 8039 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT)), |
| 8040 | CSKYV2_ISA_E1, |
| 8041 | OPCODE_INFO1 (0xeb200000, |
| 8042 | (16_20, AREG, OPRND_SHIFT_0_BIT)), |
| 8043 | CSKYV2_ISA_1E2), |
| 8044 | /* tstne rd -> cmpnei rd,0 */ |
| 8045 | OP16_OP32 ("tstne", |
| 8046 | OPCODE_INFO1 (0x3840, |
| 8047 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT)), |
| 8048 | CSKYV2_ISA_E1, |
| 8049 | OPCODE_INFO1 (0xeb400000, |
| 8050 | (16_20, AREG, OPRND_SHIFT_0_BIT)), |
| 8051 | CSKYV2_ISA_1E2), |
| 8052 | /* rotri rz, rx, imm5 -> rotli rz, rx, 32-imm5 */ |
| 8053 | DOP32 ("rotri", |
| 8054 | OPCODE_INFO3 (0xc4004900, |
| 8055 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 8056 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 8057 | (21_25, IMM5b_RORI, OPRND_SHIFT_0_BIT)), |
| 8058 | OPCODE_INFO2 (0xc4004900, |
| 8059 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), |
| 8060 | (21_25, IMM5b_RORI, OPRND_SHIFT_0_BIT)), |
| 8061 | CSKYV2_ISA_2E3), |
| 8062 | DOP32 ("rori", |
| 8063 | OPCODE_INFO3 (0xc4004900, |
| 8064 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 8065 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
| 8066 | (21_25, IMM5b_RORI, OPRND_SHIFT_0_BIT)), |
| 8067 | OPCODE_INFO2 (0xc4004900, |
| 8068 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), |
| 8069 | (21_25, IMM5b_RORI, OPRND_SHIFT_0_BIT)), |
| 8070 | CSKYV2_ISA_2E3), |
| 8071 | |
| 8072 | /* rotlc rd -> addc rd, rd/ addc rd, rd, rd */ |
| 8073 | OP16_OP32_WITH_WORK ("rotlc", |
| 8074 | OPCODE_INFO2 (0x6001, |
| 8075 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT), |
| 8076 | (NONE, CONST1, OPRND_SHIFT_0_BIT)), |
| 8077 | CSKYV2_ISA_E1, |
| 8078 | OPCODE_INFO2 (0xc4000040, |
| 8079 | (NONE, AREG, OPRND_SHIFT_0_BIT), |
| 8080 | (NONE, CONST1, OPRND_SHIFT_0_BIT)), |
| 8081 | CSKYV2_ISA_2E3, |
| 8082 | v2_work_rotlc), |
| 8083 | /* not rd -> nor rd, rd, not rz, rx -> nor rz, rx, rx */ |
| 8084 | OP16_OP32_WITH_WORK ("not", |
| 8085 | OPCODE_INFO1 (0x6c02, |
| 8086 | (NONE, AREG, OPRND_SHIFT_0_BIT)), |
| 8087 | CSKYV2_ISA_E1, |
| 8088 | OPCODE_INFO2 (0xc4002480, |
| 8089 | (NONE, AREG, OPRND_SHIFT_0_BIT), |
| 8090 | (NONE, AREG, OPRND_SHIFT_0_BIT)), |
| 8091 | CSKYV2_ISA_E1, v2_work_not), |
| 8092 | |
| 8093 | /* Special force 32 bits instruction. */ |
| 8094 | OP32 ("xtrb0.32", |
| 8095 | OPCODE_INFO2 (0xc4007020, |
| 8096 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 8097 | (16_20, AREG, OPRND_SHIFT_0_BIT)), |
| 8098 | CSKYV2_ISA_1E2), |
| 8099 | OP32 ("xtrb1.32", |
| 8100 | OPCODE_INFO2 (0xc4007040, |
| 8101 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 8102 | (16_20, AREG, OPRND_SHIFT_0_BIT)), |
| 8103 | CSKYV2_ISA_1E2), |
| 8104 | OP32 ("xtrb2.32", |
| 8105 | OPCODE_INFO2 (0xc4007080, |
| 8106 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 8107 | (16_20, AREG, OPRND_SHIFT_0_BIT)), |
| 8108 | CSKYV2_ISA_1E2), |
| 8109 | OP32 ("xtrb3.32", |
| 8110 | OPCODE_INFO2 (0xc4007100, |
| 8111 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 8112 | (16_20, AREG, OPRND_SHIFT_0_BIT)), |
| 8113 | CSKYV2_ISA_1E2), |
| 8114 | OP32 ("ff0.32", |
| 8115 | OPCODE_INFO2 (0xc4007c20, |
| 8116 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 8117 | (16_20, AREG, OPRND_SHIFT_0_BIT)), |
| 8118 | CSKYV2_ISA_1E2), |
| 8119 | DOP32 ("ff1.32", |
| 8120 | OPCODE_INFO2 (0xc4007c40, |
| 8121 | (0_4, AREG, OPRND_SHIFT_0_BIT), |
| 8122 | (16_20, AREG, OPRND_SHIFT_0_BIT)), |
| 8123 | OPCODE_INFO1 (0xc4007c40, |
| 8124 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT)), |
| 8125 | CSKYV2_ISA_1E2), |
| 8126 | {NULL, 0, {}, {}, 0, 0, 0, 0, 0, NULL} |
| 8127 | }; |