| | 1 | // i386 register table. |
| | 2 | // Copyright 2007, 2008 |
| | 3 | // Free Software Foundation, Inc. |
| | 4 | // |
| | 5 | // This file is part of the GNU opcodes library. |
| | 6 | // |
| | 7 | // This library is free software; you can redistribute it and/or modify |
| | 8 | // it under the terms of the GNU General Public License as published by |
| | 9 | // the Free Software Foundation; either version 3, or (at your option) |
| | 10 | // any later version. |
| | 11 | // |
| | 12 | // It is distributed in the hope that it will be useful, but WITHOUT |
| | 13 | // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
| | 14 | // or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public |
| | 15 | // License for more details. |
| | 16 | // |
| | 17 | // You should have received a copy of the GNU General Public License |
| | 18 | // along with GAS; see the file COPYING. If not, write to the Free |
| | 19 | // Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
| | 20 | // 02110-1301, USA. |
| | 21 | |
| | 22 | // Make %st first as we test for it. |
| | 23 | st, FloatReg|FloatAcc, 0, 0, 11, 33 |
| | 24 | // 8 bit regs |
| | 25 | al, Reg8|Acc|Byte, 0, 0, Dw2Inval, Dw2Inval |
| | 26 | cl, Reg8|ShiftCount, 0, 1, Dw2Inval, Dw2Inval |
| | 27 | dl, Reg8, 0, 2, Dw2Inval, Dw2Inval |
| | 28 | bl, Reg8, 0, 3, Dw2Inval, Dw2Inval |
| | 29 | ah, Reg8, 0, 4, Dw2Inval, Dw2Inval |
| | 30 | ch, Reg8, 0, 5, Dw2Inval, Dw2Inval |
| | 31 | dh, Reg8, 0, 6, Dw2Inval, Dw2Inval |
| | 32 | bh, Reg8, 0, 7, Dw2Inval, Dw2Inval |
| | 33 | axl, Reg8|Acc|Byte, RegRex64, 0, Dw2Inval, Dw2Inval |
| | 34 | cxl, Reg8, RegRex64, 1, Dw2Inval, Dw2Inval |
| | 35 | dxl, Reg8, RegRex64, 2, Dw2Inval, Dw2Inval |
| | 36 | bxl, Reg8, RegRex64, 3, Dw2Inval, Dw2Inval |
| | 37 | spl, Reg8, RegRex64, 4, Dw2Inval, Dw2Inval |
| | 38 | bpl, Reg8, RegRex64, 5, Dw2Inval, Dw2Inval |
| | 39 | sil, Reg8, RegRex64, 6, Dw2Inval, Dw2Inval |
| | 40 | dil, Reg8, RegRex64, 7, Dw2Inval, Dw2Inval |
| | 41 | r8b, Reg8, RegRex|RegRex64, 0, Dw2Inval, Dw2Inval |
| | 42 | r9b, Reg8, RegRex|RegRex64, 1, Dw2Inval, Dw2Inval |
| | 43 | r10b, Reg8, RegRex|RegRex64, 2, Dw2Inval, Dw2Inval |
| | 44 | r11b, Reg8, RegRex|RegRex64, 3, Dw2Inval, Dw2Inval |
| | 45 | r12b, Reg8, RegRex|RegRex64, 4, Dw2Inval, Dw2Inval |
| | 46 | r13b, Reg8, RegRex|RegRex64, 5, Dw2Inval, Dw2Inval |
| | 47 | r14b, Reg8, RegRex|RegRex64, 6, Dw2Inval, Dw2Inval |
| | 48 | r15b, Reg8, RegRex|RegRex64, 7, Dw2Inval, Dw2Inval |
| | 49 | // 16 bit regs |
| | 50 | ax, Reg16|Acc|Word, 0, 0, Dw2Inval, Dw2Inval |
| | 51 | cx, Reg16, 0, 1, Dw2Inval, Dw2Inval |
| | 52 | dx, Reg16|InOutPortReg, 0, 2, Dw2Inval, Dw2Inval |
| | 53 | bx, Reg16|BaseIndex, 0, 3, Dw2Inval, Dw2Inval |
| | 54 | sp, Reg16, 0, 4, Dw2Inval, Dw2Inval |
| | 55 | bp, Reg16|BaseIndex, 0, 5, Dw2Inval, Dw2Inval |
| | 56 | si, Reg16|BaseIndex, 0, 6, Dw2Inval, Dw2Inval |
| | 57 | di, Reg16|BaseIndex, 0, 7, Dw2Inval, Dw2Inval |
| | 58 | r8w, Reg16, RegRex, 0, Dw2Inval, Dw2Inval |
| | 59 | r9w, Reg16, RegRex, 1, Dw2Inval, Dw2Inval |
| | 60 | r10w, Reg16, RegRex, 2, Dw2Inval, Dw2Inval |
| | 61 | r11w, Reg16, RegRex, 3, Dw2Inval, Dw2Inval |
| | 62 | r12w, Reg16, RegRex, 4, Dw2Inval, Dw2Inval |
| | 63 | r13w, Reg16, RegRex, 5, Dw2Inval, Dw2Inval |
| | 64 | r14w, Reg16, RegRex, 6, Dw2Inval, Dw2Inval |
| | 65 | r15w, Reg16, RegRex, 7, Dw2Inval, Dw2Inval |
| | 66 | // 32 bit regs |
| | 67 | eax, Reg32|BaseIndex|Acc|Dword, 0, 0, 0, Dw2Inval |
| | 68 | ecx, Reg32|BaseIndex, 0, 1, 1, Dw2Inval |
| | 69 | edx, Reg32|BaseIndex, 0, 2, 2, Dw2Inval |
| | 70 | ebx, Reg32|BaseIndex, 0, 3, 3, Dw2Inval |
| | 71 | esp, Reg32, 0, 4, 4, Dw2Inval |
| | 72 | ebp, Reg32|BaseIndex, 0, 5, 5, Dw2Inval |
| | 73 | esi, Reg32|BaseIndex, 0, 6, 6, Dw2Inval |
| | 74 | edi, Reg32|BaseIndex, 0, 7, 7, Dw2Inval |
| | 75 | r8d, Reg32|BaseIndex, RegRex, 0, Dw2Inval, Dw2Inval |
| | 76 | r9d, Reg32|BaseIndex, RegRex, 1, Dw2Inval, Dw2Inval |
| | 77 | r10d, Reg32|BaseIndex, RegRex, 2, Dw2Inval, Dw2Inval |
| | 78 | r11d, Reg32|BaseIndex, RegRex, 3, Dw2Inval, Dw2Inval |
| | 79 | r12d, Reg32|BaseIndex, RegRex, 4, Dw2Inval, Dw2Inval |
| | 80 | r13d, Reg32|BaseIndex, RegRex, 5, Dw2Inval, Dw2Inval |
| | 81 | r14d, Reg32|BaseIndex, RegRex, 6, Dw2Inval, Dw2Inval |
| | 82 | r15d, Reg32|BaseIndex, RegRex, 7, Dw2Inval, Dw2Inval |
| | 83 | rax, Reg64|BaseIndex|Acc|Qword, 0, 0, Dw2Inval, 0 |
| | 84 | rcx, Reg64|BaseIndex, 0, 1, Dw2Inval, 2 |
| | 85 | rdx, Reg64|BaseIndex, 0, 2, Dw2Inval, 1 |
| | 86 | rbx, Reg64|BaseIndex, 0, 3, Dw2Inval, 3 |
| | 87 | rsp, Reg64, 0, 4, Dw2Inval, 7 |
| | 88 | rbp, Reg64|BaseIndex, 0, 5, Dw2Inval, 6 |
| | 89 | rsi, Reg64|BaseIndex, 0, 6, Dw2Inval, 4 |
| | 90 | rdi, Reg64|BaseIndex, 0, 7, Dw2Inval, 5 |
| | 91 | r8, Reg64|BaseIndex, RegRex, 0, Dw2Inval, 8 |
| | 92 | r9, Reg64|BaseIndex, RegRex, 1, Dw2Inval, 9 |
| | 93 | r10, Reg64|BaseIndex, RegRex, 2, Dw2Inval, 10 |
| | 94 | r11, Reg64|BaseIndex, RegRex, 3, Dw2Inval, 11 |
| | 95 | r12, Reg64|BaseIndex, RegRex, 4, Dw2Inval, 12 |
| | 96 | r13, Reg64|BaseIndex, RegRex, 5, Dw2Inval, 13 |
| | 97 | r14, Reg64|BaseIndex, RegRex, 6, Dw2Inval, 14 |
| | 98 | r15, Reg64|BaseIndex, RegRex, 7, Dw2Inval, 15 |
| | 99 | // Vector mask registers. |
| | 100 | k0, RegMask, 0, 0, 93, 118 |
| | 101 | k1, RegMask, 0, 1, 94, 119 |
| | 102 | k2, RegMask, 0, 2, 95, 120 |
| | 103 | k3, RegMask, 0, 3, 96, 121 |
| | 104 | k4, RegMask, 0, 4, 97, 122 |
| | 105 | k5, RegMask, 0, 5, 98, 123 |
| | 106 | k6, RegMask, 0, 6, 99, 124 |
| | 107 | k7, RegMask, 0, 7, 100, 125 |
| | 108 | // Segment registers. |
| | 109 | es, SReg2, 0, 0, 40, 50 |
| | 110 | cs, SReg2, 0, 1, 41, 51 |
| | 111 | ss, SReg2, 0, 2, 42, 52 |
| | 112 | ds, SReg2, 0, 3, 43, 53 |
| | 113 | fs, SReg3, 0, 4, 44, 54 |
| | 114 | gs, SReg3, 0, 5, 45, 55 |
| | 115 | flat, SReg3, 0, RegFlat, Dw2Inval, Dw2Inval |
| | 116 | // Control registers. |
| | 117 | cr0, Control, 0, 0, Dw2Inval, Dw2Inval |
| | 118 | cr1, Control, 0, 1, Dw2Inval, Dw2Inval |
| | 119 | cr2, Control, 0, 2, Dw2Inval, Dw2Inval |
| | 120 | cr3, Control, 0, 3, Dw2Inval, Dw2Inval |
| | 121 | cr4, Control, 0, 4, Dw2Inval, Dw2Inval |
| | 122 | cr5, Control, 0, 5, Dw2Inval, Dw2Inval |
| | 123 | cr6, Control, 0, 6, Dw2Inval, Dw2Inval |
| | 124 | cr7, Control, 0, 7, Dw2Inval, Dw2Inval |
| | 125 | cr8, Control, RegRex, 0, Dw2Inval, Dw2Inval |
| | 126 | cr9, Control, RegRex, 1, Dw2Inval, Dw2Inval |
| | 127 | cr10, Control, RegRex, 2, Dw2Inval, Dw2Inval |
| | 128 | cr11, Control, RegRex, 3, Dw2Inval, Dw2Inval |
| | 129 | cr12, Control, RegRex, 4, Dw2Inval, Dw2Inval |
| | 130 | cr13, Control, RegRex, 5, Dw2Inval, Dw2Inval |
| | 131 | cr14, Control, RegRex, 6, Dw2Inval, Dw2Inval |
| | 132 | cr15, Control, RegRex, 7, Dw2Inval, Dw2Inval |
| | 133 | // Debug registers. |
| | 134 | db0, Debug, 0, 0, Dw2Inval, Dw2Inval |
| | 135 | db1, Debug, 0, 1, Dw2Inval, Dw2Inval |
| | 136 | db2, Debug, 0, 2, Dw2Inval, Dw2Inval |
| | 137 | db3, Debug, 0, 3, Dw2Inval, Dw2Inval |
| | 138 | db4, Debug, 0, 4, Dw2Inval, Dw2Inval |
| | 139 | db5, Debug, 0, 5, Dw2Inval, Dw2Inval |
| | 140 | db6, Debug, 0, 6, Dw2Inval, Dw2Inval |
| | 141 | db7, Debug, 0, 7, Dw2Inval, Dw2Inval |
| | 142 | db8, Debug, RegRex, 0, Dw2Inval, Dw2Inval |
| | 143 | db9, Debug, RegRex, 1, Dw2Inval, Dw2Inval |
| | 144 | db10, Debug, RegRex, 2, Dw2Inval, Dw2Inval |
| | 145 | db11, Debug, RegRex, 3, Dw2Inval, Dw2Inval |
| | 146 | db12, Debug, RegRex, 4, Dw2Inval, Dw2Inval |
| | 147 | db13, Debug, RegRex, 5, Dw2Inval, Dw2Inval |
| | 148 | db14, Debug, RegRex, 6, Dw2Inval, Dw2Inval |
| | 149 | db15, Debug, RegRex, 7, Dw2Inval, Dw2Inval |
| | 150 | dr0, Debug, 0, 0, Dw2Inval, Dw2Inval |
| | 151 | dr1, Debug, 0, 1, Dw2Inval, Dw2Inval |
| | 152 | dr2, Debug, 0, 2, Dw2Inval, Dw2Inval |
| | 153 | dr3, Debug, 0, 3, Dw2Inval, Dw2Inval |
| | 154 | dr4, Debug, 0, 4, Dw2Inval, Dw2Inval |
| | 155 | dr5, Debug, 0, 5, Dw2Inval, Dw2Inval |
| | 156 | dr6, Debug, 0, 6, Dw2Inval, Dw2Inval |
| | 157 | dr7, Debug, 0, 7, Dw2Inval, Dw2Inval |
| | 158 | dr8, Debug, RegRex, 0, Dw2Inval, Dw2Inval |
| | 159 | dr9, Debug, RegRex, 1, Dw2Inval, Dw2Inval |
| | 160 | dr10, Debug, RegRex, 2, Dw2Inval, Dw2Inval |
| | 161 | dr11, Debug, RegRex, 3, Dw2Inval, Dw2Inval |
| | 162 | dr12, Debug, RegRex, 4, Dw2Inval, Dw2Inval |
| | 163 | dr13, Debug, RegRex, 5, Dw2Inval, Dw2Inval |
| | 164 | dr14, Debug, RegRex, 6, Dw2Inval, Dw2Inval |
| | 165 | dr15, Debug, RegRex, 7, Dw2Inval, Dw2Inval |
| | 166 | // Test registers. |
| | 167 | tr0, Test, 0, 0, Dw2Inval, Dw2Inval |
| | 168 | tr1, Test, 0, 1, Dw2Inval, Dw2Inval |
| | 169 | tr2, Test, 0, 2, Dw2Inval, Dw2Inval |
| | 170 | tr3, Test, 0, 3, Dw2Inval, Dw2Inval |
| | 171 | tr4, Test, 0, 4, Dw2Inval, Dw2Inval |
| | 172 | tr5, Test, 0, 5, Dw2Inval, Dw2Inval |
| | 173 | tr6, Test, 0, 6, Dw2Inval, Dw2Inval |
| | 174 | tr7, Test, 0, 7, Dw2Inval, Dw2Inval |
| | 175 | // MMX and simd registers. |
| | 176 | mm0, RegMMX, 0, 0, 29, 41 |
| | 177 | mm1, RegMMX, 0, 1, 30, 42 |
| | 178 | mm2, RegMMX, 0, 2, 31, 43 |
| | 179 | mm3, RegMMX, 0, 3, 32, 44 |
| | 180 | mm4, RegMMX, 0, 4, 33, 45 |
| | 181 | mm5, RegMMX, 0, 5, 34, 46 |
| | 182 | mm6, RegMMX, 0, 6, 35, 47 |
| | 183 | mm7, RegMMX, 0, 7, 36, 48 |
| | 184 | xmm0, RegXMM, 0, 0, 21, 17 |
| | 185 | xmm1, RegXMM, 0, 1, 22, 18 |
| | 186 | xmm2, RegXMM, 0, 2, 23, 19 |
| | 187 | xmm3, RegXMM, 0, 3, 24, 20 |
| | 188 | xmm4, RegXMM, 0, 4, 25, 21 |
| | 189 | xmm5, RegXMM, 0, 5, 26, 22 |
| | 190 | xmm6, RegXMM, 0, 6, 27, 23 |
| | 191 | xmm7, RegXMM, 0, 7, 28, 24 |
| | 192 | xmm8, RegXMM, RegRex, 0, Dw2Inval, 25 |
| | 193 | xmm9, RegXMM, RegRex, 1, Dw2Inval, 26 |
| | 194 | xmm10, RegXMM, RegRex, 2, Dw2Inval, 27 |
| | 195 | xmm11, RegXMM, RegRex, 3, Dw2Inval, 28 |
| | 196 | xmm12, RegXMM, RegRex, 4, Dw2Inval, 29 |
| | 197 | xmm13, RegXMM, RegRex, 5, Dw2Inval, 30 |
| | 198 | xmm14, RegXMM, RegRex, 6, Dw2Inval, 31 |
| | 199 | xmm15, RegXMM, RegRex, 7, Dw2Inval, 32 |
| | 200 | xmm16, RegXMM, RegVRex, 0, Dw2Inval, 67 |
| | 201 | xmm17, RegXMM, RegVRex, 1, Dw2Inval, 68 |
| | 202 | xmm18, RegXMM, RegVRex, 2, Dw2Inval, 69 |
| | 203 | xmm19, RegXMM, RegVRex, 3, Dw2Inval, 70 |
| | 204 | xmm20, RegXMM, RegVRex, 4, Dw2Inval, 71 |
| | 205 | xmm21, RegXMM, RegVRex, 5, Dw2Inval, 72 |
| | 206 | xmm22, RegXMM, RegVRex, 6, Dw2Inval, 73 |
| | 207 | xmm23, RegXMM, RegVRex, 7, Dw2Inval, 74 |
| | 208 | xmm24, RegXMM, RegVRex|RegRex, 0, Dw2Inval, 75 |
| | 209 | xmm25, RegXMM, RegVRex|RegRex, 1, Dw2Inval, 76 |
| | 210 | xmm26, RegXMM, RegVRex|RegRex, 2, Dw2Inval, 77 |
| | 211 | xmm27, RegXMM, RegVRex|RegRex, 3, Dw2Inval, 78 |
| | 212 | xmm28, RegXMM, RegVRex|RegRex, 4, Dw2Inval, 79 |
| | 213 | xmm29, RegXMM, RegVRex|RegRex, 5, Dw2Inval, 80 |
| | 214 | xmm30, RegXMM, RegVRex|RegRex, 6, Dw2Inval, 81 |
| | 215 | xmm31, RegXMM, RegVRex|RegRex, 7, Dw2Inval, 82 |
| | 216 | // AVX registers. |
| | 217 | ymm0, RegYMM, 0, 0, Dw2Inval, Dw2Inval |
| | 218 | ymm1, RegYMM, 0, 1, Dw2Inval, Dw2Inval |
| | 219 | ymm2, RegYMM, 0, 2, Dw2Inval, Dw2Inval |
| | 220 | ymm3, RegYMM, 0, 3, Dw2Inval, Dw2Inval |
| | 221 | ymm4, RegYMM, 0, 4, Dw2Inval, Dw2Inval |
| | 222 | ymm5, RegYMM, 0, 5, Dw2Inval, Dw2Inval |
| | 223 | ymm6, RegYMM, 0, 6, Dw2Inval, Dw2Inval |
| | 224 | ymm7, RegYMM, 0, 7, Dw2Inval, Dw2Inval |
| | 225 | ymm8, RegYMM, RegRex, 0, Dw2Inval, Dw2Inval |
| | 226 | ymm9, RegYMM, RegRex, 1, Dw2Inval, Dw2Inval |
| | 227 | ymm10, RegYMM, RegRex, 2, Dw2Inval, Dw2Inval |
| | 228 | ymm11, RegYMM, RegRex, 3, Dw2Inval, Dw2Inval |
| | 229 | ymm12, RegYMM, RegRex, 4, Dw2Inval, Dw2Inval |
| | 230 | ymm13, RegYMM, RegRex, 5, Dw2Inval, Dw2Inval |
| | 231 | ymm14, RegYMM, RegRex, 6, Dw2Inval, Dw2Inval |
| | 232 | ymm15, RegYMM, RegRex, 7, Dw2Inval, Dw2Inval |
| | 233 | ymm16, RegYMM, RegVRex, 0, Dw2Inval, Dw2Inval |
| | 234 | ymm17, RegYMM, RegVRex, 1, Dw2Inval, Dw2Inval |
| | 235 | ymm18, RegYMM, RegVRex, 2, Dw2Inval, Dw2Inval |
| | 236 | ymm19, RegYMM, RegVRex, 3, Dw2Inval, Dw2Inval |
| | 237 | ymm20, RegYMM, RegVRex, 4, Dw2Inval, Dw2Inval |
| | 238 | ymm21, RegYMM, RegVRex, 5, Dw2Inval, Dw2Inval |
| | 239 | ymm22, RegYMM, RegVRex, 6, Dw2Inval, Dw2Inval |
| | 240 | ymm23, RegYMM, RegVRex, 7, Dw2Inval, Dw2Inval |
| | 241 | ymm24, RegYMM, RegVRex|RegRex, 0, Dw2Inval, Dw2Inval |
| | 242 | ymm25, RegYMM, RegVRex|RegRex, 1, Dw2Inval, Dw2Inval |
| | 243 | ymm26, RegYMM, RegVRex|RegRex, 2, Dw2Inval, Dw2Inval |
| | 244 | ymm27, RegYMM, RegVRex|RegRex, 3, Dw2Inval, Dw2Inval |
| | 245 | ymm28, RegYMM, RegVRex|RegRex, 4, Dw2Inval, Dw2Inval |
| | 246 | ymm29, RegYMM, RegVRex|RegRex, 5, Dw2Inval, Dw2Inval |
| | 247 | ymm30, RegYMM, RegVRex|RegRex, 6, Dw2Inval, Dw2Inval |
| | 248 | ymm31, RegYMM, RegVRex|RegRex, 7, Dw2Inval, Dw2Inval |
| | 249 | // AVX512 registers. |
| | 250 | zmm0, RegZMM, 0, 0, Dw2Inval, Dw2Inval |
| | 251 | zmm1, RegZMM, 0, 1, Dw2Inval, Dw2Inval |
| | 252 | zmm2, RegZMM, 0, 2, Dw2Inval, Dw2Inval |
| | 253 | zmm3, RegZMM, 0, 3, Dw2Inval, Dw2Inval |
| | 254 | zmm4, RegZMM, 0, 4, Dw2Inval, Dw2Inval |
| | 255 | zmm5, RegZMM, 0, 5, Dw2Inval, Dw2Inval |
| | 256 | zmm6, RegZMM, 0, 6, Dw2Inval, Dw2Inval |
| | 257 | zmm7, RegZMM, 0, 7, Dw2Inval, Dw2Inval |
| | 258 | zmm8, RegZMM, RegRex, 0, Dw2Inval, Dw2Inval |
| | 259 | zmm9, RegZMM, RegRex, 1, Dw2Inval, Dw2Inval |
| | 260 | zmm10, RegZMM, RegRex, 2, Dw2Inval, Dw2Inval |
| | 261 | zmm11, RegZMM, RegRex, 3, Dw2Inval, Dw2Inval |
| | 262 | zmm12, RegZMM, RegRex, 4, Dw2Inval, Dw2Inval |
| | 263 | zmm13, RegZMM, RegRex, 5, Dw2Inval, Dw2Inval |
| | 264 | zmm14, RegZMM, RegRex, 6, Dw2Inval, Dw2Inval |
| | 265 | zmm15, RegZMM, RegRex, 7, Dw2Inval, Dw2Inval |
| | 266 | zmm16, RegZMM, RegVRex, 0, Dw2Inval, Dw2Inval |
| | 267 | zmm17, RegZMM, RegVRex, 1, Dw2Inval, Dw2Inval |
| | 268 | zmm18, RegZMM, RegVRex, 2, Dw2Inval, Dw2Inval |
| | 269 | zmm19, RegZMM, RegVRex, 3, Dw2Inval, Dw2Inval |
| | 270 | zmm20, RegZMM, RegVRex, 4, Dw2Inval, Dw2Inval |
| | 271 | zmm21, RegZMM, RegVRex, 5, Dw2Inval, Dw2Inval |
| | 272 | zmm22, RegZMM, RegVRex, 6, Dw2Inval, Dw2Inval |
| | 273 | zmm23, RegZMM, RegVRex, 7, Dw2Inval, Dw2Inval |
| | 274 | zmm24, RegZMM, RegVRex|RegRex, 0, Dw2Inval, Dw2Inval |
| | 275 | zmm25, RegZMM, RegVRex|RegRex, 1, Dw2Inval, Dw2Inval |
| | 276 | zmm26, RegZMM, RegVRex|RegRex, 2, Dw2Inval, Dw2Inval |
| | 277 | zmm27, RegZMM, RegVRex|RegRex, 3, Dw2Inval, Dw2Inval |
| | 278 | zmm28, RegZMM, RegVRex|RegRex, 4, Dw2Inval, Dw2Inval |
| | 279 | zmm29, RegZMM, RegVRex|RegRex, 5, Dw2Inval, Dw2Inval |
| | 280 | zmm30, RegZMM, RegVRex|RegRex, 6, Dw2Inval, Dw2Inval |
| | 281 | zmm31, RegZMM, RegVRex|RegRex, 7, Dw2Inval, Dw2Inval |
| | 282 | // Bound registers for MPX |
| | 283 | bnd0, RegBND, 0, 0, Dw2Inval, Dw2Inval |
| | 284 | bnd1, RegBND, 0, 1, Dw2Inval, Dw2Inval |
| | 285 | bnd2, RegBND, 0, 2, Dw2Inval, Dw2Inval |
| | 286 | bnd3, RegBND, 0, 3, Dw2Inval, Dw2Inval |
| | 287 | // No type will make these registers rejected for all purposes except |
| | 288 | // for addressing. This saves creating one extra type for RIP/EIP. |
| | 289 | rip, BaseIndex, RegRex64, RegRip, Dw2Inval, 16 |
| | 290 | eip, BaseIndex, RegRex64, RegEip, 8, Dw2Inval |
| | 291 | // No type will make these registers rejected for all purposes except |
| | 292 | // for addressing. |
| | 293 | riz, BaseIndex, RegRex64, RegRiz, Dw2Inval, Dw2Inval |
| | 294 | eiz, BaseIndex, 0, RegEiz, Dw2Inval, Dw2Inval |
| | 295 | // fp regs. |
| | 296 | st(0), FloatReg|FloatAcc, 0, 0, 11, 33 |
| | 297 | st(1), FloatReg, 0, 1, 12, 34 |
| | 298 | st(2), FloatReg, 0, 2, 13, 35 |
| | 299 | st(3), FloatReg, 0, 3, 14, 36 |
| | 300 | st(4), FloatReg, 0, 4, 15, 37 |
| | 301 | st(5), FloatReg, 0, 5, 16, 38 |
| | 302 | st(6), FloatReg, 0, 6, 17, 39 |
| | 303 | st(7), FloatReg, 0, 7, 18, 40 |
| | 304 | // Pseudo-register names only used in .cfi_* directives |
| | 305 | eflags, 0, 0, 0, 9, 49 |
| | 306 | rflags, 0, 0, 0, Dw2Inval, 49 |
| | 307 | fs.base, 0, 0, 0, Dw2Inval, 58 |
| | 308 | gs.base, 0, 0, 0, Dw2Inval, 59 |
| | 309 | tr, 0, 0, 0, 48, 62 |
| | 310 | ldtr, 0, 0, 0, 49, 63 |
| | 311 | // st0...7 for backward compatibility |
| | 312 | st0, 0, 0, 0, 11, 33 |
| | 313 | st1, 0, 0, 1, 12, 34 |
| | 314 | st2, 0, 0, 2, 13, 35 |
| | 315 | st3, 0, 0, 3, 14, 36 |
| | 316 | st4, 0, 0, 4, 15, 37 |
| | 317 | st5, 0, 0, 5, 16, 38 |
| | 318 | st6, 0, 0, 6, 17, 39 |
| | 319 | st7, 0, 0, 7, 18, 40 |
| | 320 | fcw, 0, 0, 0, 37, 65 |
| | 321 | fsw, 0, 0, 0, 38, 66 |
| | 322 | mxcsr, 0, 0, 0, 39, 64 |
projects / deliverable / binutils-gdb.git / blame_incremental