| 1 | // i386 register table. |
| 2 | // Copyright (C) 2007-2020 Free Software Foundation, Inc. |
| 3 | // |
| 4 | // This file is part of the GNU opcodes library. |
| 5 | // |
| 6 | // This library is free software; you can redistribute it and/or modify |
| 7 | // it under the terms of the GNU General Public License as published by |
| 8 | // the Free Software Foundation; either version 3, or (at your option) |
| 9 | // any later version. |
| 10 | // |
| 11 | // It is distributed in the hope that it will be useful, but WITHOUT |
| 12 | // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
| 13 | // or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public |
| 14 | // License for more details. |
| 15 | // |
| 16 | // You should have received a copy of the GNU General Public License |
| 17 | // along with GAS; see the file COPYING. If not, write to the Free |
| 18 | // Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
| 19 | // 02110-1301, USA. |
| 20 | |
| 21 | // Make %st first as we test for it. |
| 22 | st, Class=Reg|Instance=Accum|Tbyte, 0, 0, 11, 33 |
| 23 | // 8 bit regs |
| 24 | al, Class=Reg|Instance=Accum|Byte, 0, 0, Dw2Inval, Dw2Inval |
| 25 | cl, Class=Reg|Instance=RegC|Byte, 0, 1, Dw2Inval, Dw2Inval |
| 26 | dl, Class=Reg|Byte, 0, 2, Dw2Inval, Dw2Inval |
| 27 | bl, Class=Reg|Byte, 0, 3, Dw2Inval, Dw2Inval |
| 28 | ah, Class=Reg|Byte, 0, 4, Dw2Inval, Dw2Inval |
| 29 | ch, Class=Reg|Byte, 0, 5, Dw2Inval, Dw2Inval |
| 30 | dh, Class=Reg|Byte, 0, 6, Dw2Inval, Dw2Inval |
| 31 | bh, Class=Reg|Byte, 0, 7, Dw2Inval, Dw2Inval |
| 32 | axl, Class=Reg|Byte, RegRex64, 0, Dw2Inval, Dw2Inval |
| 33 | cxl, Class=Reg|Byte, RegRex64, 1, Dw2Inval, Dw2Inval |
| 34 | dxl, Class=Reg|Byte, RegRex64, 2, Dw2Inval, Dw2Inval |
| 35 | bxl, Class=Reg|Byte, RegRex64, 3, Dw2Inval, Dw2Inval |
| 36 | spl, Class=Reg|Byte, RegRex64, 4, Dw2Inval, Dw2Inval |
| 37 | bpl, Class=Reg|Byte, RegRex64, 5, Dw2Inval, Dw2Inval |
| 38 | sil, Class=Reg|Byte, RegRex64, 6, Dw2Inval, Dw2Inval |
| 39 | dil, Class=Reg|Byte, RegRex64, 7, Dw2Inval, Dw2Inval |
| 40 | r8b, Class=Reg|Byte, RegRex|RegRex64, 0, Dw2Inval, Dw2Inval |
| 41 | r9b, Class=Reg|Byte, RegRex|RegRex64, 1, Dw2Inval, Dw2Inval |
| 42 | r10b, Class=Reg|Byte, RegRex|RegRex64, 2, Dw2Inval, Dw2Inval |
| 43 | r11b, Class=Reg|Byte, RegRex|RegRex64, 3, Dw2Inval, Dw2Inval |
| 44 | r12b, Class=Reg|Byte, RegRex|RegRex64, 4, Dw2Inval, Dw2Inval |
| 45 | r13b, Class=Reg|Byte, RegRex|RegRex64, 5, Dw2Inval, Dw2Inval |
| 46 | r14b, Class=Reg|Byte, RegRex|RegRex64, 6, Dw2Inval, Dw2Inval |
| 47 | r15b, Class=Reg|Byte, RegRex|RegRex64, 7, Dw2Inval, Dw2Inval |
| 48 | // 16 bit regs |
| 49 | ax, Class=Reg|Instance=Accum|Word, 0, 0, Dw2Inval, Dw2Inval |
| 50 | cx, Class=Reg|Word, 0, 1, Dw2Inval, Dw2Inval |
| 51 | dx, Class=Reg|Instance=RegD|Word, 0, 2, Dw2Inval, Dw2Inval |
| 52 | bx, Class=Reg|Word|BaseIndex, 0, 3, Dw2Inval, Dw2Inval |
| 53 | sp, Class=Reg|Word, 0, 4, Dw2Inval, Dw2Inval |
| 54 | bp, Class=Reg|Word|BaseIndex, 0, 5, Dw2Inval, Dw2Inval |
| 55 | si, Class=Reg|Word|BaseIndex, 0, 6, Dw2Inval, Dw2Inval |
| 56 | di, Class=Reg|Word|BaseIndex, 0, 7, Dw2Inval, Dw2Inval |
| 57 | r8w, Class=Reg|Word, RegRex, 0, Dw2Inval, Dw2Inval |
| 58 | r9w, Class=Reg|Word, RegRex, 1, Dw2Inval, Dw2Inval |
| 59 | r10w, Class=Reg|Word, RegRex, 2, Dw2Inval, Dw2Inval |
| 60 | r11w, Class=Reg|Word, RegRex, 3, Dw2Inval, Dw2Inval |
| 61 | r12w, Class=Reg|Word, RegRex, 4, Dw2Inval, Dw2Inval |
| 62 | r13w, Class=Reg|Word, RegRex, 5, Dw2Inval, Dw2Inval |
| 63 | r14w, Class=Reg|Word, RegRex, 6, Dw2Inval, Dw2Inval |
| 64 | r15w, Class=Reg|Word, RegRex, 7, Dw2Inval, Dw2Inval |
| 65 | // 32 bit regs |
| 66 | eax, Class=Reg|Instance=Accum|Dword|BaseIndex, 0, 0, 0, Dw2Inval |
| 67 | ecx, Class=Reg|Instance=RegC|Dword|BaseIndex, 0, 1, 1, Dw2Inval |
| 68 | edx, Class=Reg|Instance=RegD|Dword|BaseIndex, 0, 2, 2, Dw2Inval |
| 69 | ebx, Class=Reg|Instance=RegB|Dword|BaseIndex, 0, 3, 3, Dw2Inval |
| 70 | esp, Class=Reg|Dword, 0, 4, 4, Dw2Inval |
| 71 | ebp, Class=Reg|Dword|BaseIndex, 0, 5, 5, Dw2Inval |
| 72 | esi, Class=Reg|Dword|BaseIndex, 0, 6, 6, Dw2Inval |
| 73 | edi, Class=Reg|Dword|BaseIndex, 0, 7, 7, Dw2Inval |
| 74 | r8d, Class=Reg|Dword|BaseIndex, RegRex, 0, Dw2Inval, Dw2Inval |
| 75 | r9d, Class=Reg|Dword|BaseIndex, RegRex, 1, Dw2Inval, Dw2Inval |
| 76 | r10d, Class=Reg|Dword|BaseIndex, RegRex, 2, Dw2Inval, Dw2Inval |
| 77 | r11d, Class=Reg|Dword|BaseIndex, RegRex, 3, Dw2Inval, Dw2Inval |
| 78 | r12d, Class=Reg|Dword|BaseIndex, RegRex, 4, Dw2Inval, Dw2Inval |
| 79 | r13d, Class=Reg|Dword|BaseIndex, RegRex, 5, Dw2Inval, Dw2Inval |
| 80 | r14d, Class=Reg|Dword|BaseIndex, RegRex, 6, Dw2Inval, Dw2Inval |
| 81 | r15d, Class=Reg|Dword|BaseIndex, RegRex, 7, Dw2Inval, Dw2Inval |
| 82 | rax, Class=Reg|Instance=Accum|Qword|BaseIndex, 0, 0, Dw2Inval, 0 |
| 83 | rcx, Class=Reg|Instance=RegC|Qword|BaseIndex, 0, 1, Dw2Inval, 2 |
| 84 | rdx, Class=Reg|Instance=RegD|Qword|BaseIndex, 0, 2, Dw2Inval, 1 |
| 85 | rbx, Class=Reg|Instance=RegB|Qword|BaseIndex, 0, 3, Dw2Inval, 3 |
| 86 | rsp, Class=Reg|Qword, 0, 4, Dw2Inval, 7 |
| 87 | rbp, Class=Reg|Qword|BaseIndex, 0, 5, Dw2Inval, 6 |
| 88 | rsi, Class=Reg|Qword|BaseIndex, 0, 6, Dw2Inval, 4 |
| 89 | rdi, Class=Reg|Qword|BaseIndex, 0, 7, Dw2Inval, 5 |
| 90 | r8, Class=Reg|Qword|BaseIndex, RegRex, 0, Dw2Inval, 8 |
| 91 | r9, Class=Reg|Qword|BaseIndex, RegRex, 1, Dw2Inval, 9 |
| 92 | r10, Class=Reg|Qword|BaseIndex, RegRex, 2, Dw2Inval, 10 |
| 93 | r11, Class=Reg|Qword|BaseIndex, RegRex, 3, Dw2Inval, 11 |
| 94 | r12, Class=Reg|Qword|BaseIndex, RegRex, 4, Dw2Inval, 12 |
| 95 | r13, Class=Reg|Qword|BaseIndex, RegRex, 5, Dw2Inval, 13 |
| 96 | r14, Class=Reg|Qword|BaseIndex, RegRex, 6, Dw2Inval, 14 |
| 97 | r15, Class=Reg|Qword|BaseIndex, RegRex, 7, Dw2Inval, 15 |
| 98 | // Vector mask registers. |
| 99 | k0, Class=RegMask, 0, 0, 93, 118 |
| 100 | k1, Class=RegMask, 0, 1, 94, 119 |
| 101 | k2, Class=RegMask, 0, 2, 95, 120 |
| 102 | k3, Class=RegMask, 0, 3, 96, 121 |
| 103 | k4, Class=RegMask, 0, 4, 97, 122 |
| 104 | k5, Class=RegMask, 0, 5, 98, 123 |
| 105 | k6, Class=RegMask, 0, 6, 99, 124 |
| 106 | k7, Class=RegMask, 0, 7, 100, 125 |
| 107 | // Segment registers. |
| 108 | es, Class=SReg, 0, 0, 40, 50 |
| 109 | cs, Class=SReg, 0, 1, 41, 51 |
| 110 | ss, Class=SReg, 0, 2, 42, 52 |
| 111 | ds, Class=SReg, 0, 3, 43, 53 |
| 112 | fs, Class=SReg, 0, 4, 44, 54 |
| 113 | gs, Class=SReg, 0, 5, 45, 55 |
| 114 | flat, Class=SReg, 0, RegFlat, Dw2Inval, Dw2Inval |
| 115 | // Control registers. |
| 116 | cr0, Class=RegCR, 0, 0, Dw2Inval, Dw2Inval |
| 117 | cr1, Class=RegCR, 0, 1, Dw2Inval, Dw2Inval |
| 118 | cr2, Class=RegCR, 0, 2, Dw2Inval, Dw2Inval |
| 119 | cr3, Class=RegCR, 0, 3, Dw2Inval, Dw2Inval |
| 120 | cr4, Class=RegCR, 0, 4, Dw2Inval, Dw2Inval |
| 121 | cr5, Class=RegCR, 0, 5, Dw2Inval, Dw2Inval |
| 122 | cr6, Class=RegCR, 0, 6, Dw2Inval, Dw2Inval |
| 123 | cr7, Class=RegCR, 0, 7, Dw2Inval, Dw2Inval |
| 124 | cr8, Class=RegCR, RegRex, 0, Dw2Inval, Dw2Inval |
| 125 | cr9, Class=RegCR, RegRex, 1, Dw2Inval, Dw2Inval |
| 126 | cr10, Class=RegCR, RegRex, 2, Dw2Inval, Dw2Inval |
| 127 | cr11, Class=RegCR, RegRex, 3, Dw2Inval, Dw2Inval |
| 128 | cr12, Class=RegCR, RegRex, 4, Dw2Inval, Dw2Inval |
| 129 | cr13, Class=RegCR, RegRex, 5, Dw2Inval, Dw2Inval |
| 130 | cr14, Class=RegCR, RegRex, 6, Dw2Inval, Dw2Inval |
| 131 | cr15, Class=RegCR, RegRex, 7, Dw2Inval, Dw2Inval |
| 132 | // Debug registers. |
| 133 | db0, Class=RegDR, 0, 0, Dw2Inval, Dw2Inval |
| 134 | db1, Class=RegDR, 0, 1, Dw2Inval, Dw2Inval |
| 135 | db2, Class=RegDR, 0, 2, Dw2Inval, Dw2Inval |
| 136 | db3, Class=RegDR, 0, 3, Dw2Inval, Dw2Inval |
| 137 | db4, Class=RegDR, 0, 4, Dw2Inval, Dw2Inval |
| 138 | db5, Class=RegDR, 0, 5, Dw2Inval, Dw2Inval |
| 139 | db6, Class=RegDR, 0, 6, Dw2Inval, Dw2Inval |
| 140 | db7, Class=RegDR, 0, 7, Dw2Inval, Dw2Inval |
| 141 | db8, Class=RegDR, RegRex, 0, Dw2Inval, Dw2Inval |
| 142 | db9, Class=RegDR, RegRex, 1, Dw2Inval, Dw2Inval |
| 143 | db10, Class=RegDR, RegRex, 2, Dw2Inval, Dw2Inval |
| 144 | db11, Class=RegDR, RegRex, 3, Dw2Inval, Dw2Inval |
| 145 | db12, Class=RegDR, RegRex, 4, Dw2Inval, Dw2Inval |
| 146 | db13, Class=RegDR, RegRex, 5, Dw2Inval, Dw2Inval |
| 147 | db14, Class=RegDR, RegRex, 6, Dw2Inval, Dw2Inval |
| 148 | db15, Class=RegDR, RegRex, 7, Dw2Inval, Dw2Inval |
| 149 | dr0, Class=RegDR, 0, 0, Dw2Inval, Dw2Inval |
| 150 | dr1, Class=RegDR, 0, 1, Dw2Inval, Dw2Inval |
| 151 | dr2, Class=RegDR, 0, 2, Dw2Inval, Dw2Inval |
| 152 | dr3, Class=RegDR, 0, 3, Dw2Inval, Dw2Inval |
| 153 | dr4, Class=RegDR, 0, 4, Dw2Inval, Dw2Inval |
| 154 | dr5, Class=RegDR, 0, 5, Dw2Inval, Dw2Inval |
| 155 | dr6, Class=RegDR, 0, 6, Dw2Inval, Dw2Inval |
| 156 | dr7, Class=RegDR, 0, 7, Dw2Inval, Dw2Inval |
| 157 | dr8, Class=RegDR, RegRex, 0, Dw2Inval, Dw2Inval |
| 158 | dr9, Class=RegDR, RegRex, 1, Dw2Inval, Dw2Inval |
| 159 | dr10, Class=RegDR, RegRex, 2, Dw2Inval, Dw2Inval |
| 160 | dr11, Class=RegDR, RegRex, 3, Dw2Inval, Dw2Inval |
| 161 | dr12, Class=RegDR, RegRex, 4, Dw2Inval, Dw2Inval |
| 162 | dr13, Class=RegDR, RegRex, 5, Dw2Inval, Dw2Inval |
| 163 | dr14, Class=RegDR, RegRex, 6, Dw2Inval, Dw2Inval |
| 164 | dr15, Class=RegDR, RegRex, 7, Dw2Inval, Dw2Inval |
| 165 | // Test registers. |
| 166 | tr0, Class=RegTR, 0, 0, Dw2Inval, Dw2Inval |
| 167 | tr1, Class=RegTR, 0, 1, Dw2Inval, Dw2Inval |
| 168 | tr2, Class=RegTR, 0, 2, Dw2Inval, Dw2Inval |
| 169 | tr3, Class=RegTR, 0, 3, Dw2Inval, Dw2Inval |
| 170 | tr4, Class=RegTR, 0, 4, Dw2Inval, Dw2Inval |
| 171 | tr5, Class=RegTR, 0, 5, Dw2Inval, Dw2Inval |
| 172 | tr6, Class=RegTR, 0, 6, Dw2Inval, Dw2Inval |
| 173 | tr7, Class=RegTR, 0, 7, Dw2Inval, Dw2Inval |
| 174 | // MMX and simd registers. |
| 175 | mm0, Class=RegMMX, 0, 0, 29, 41 |
| 176 | mm1, Class=RegMMX, 0, 1, 30, 42 |
| 177 | mm2, Class=RegMMX, 0, 2, 31, 43 |
| 178 | mm3, Class=RegMMX, 0, 3, 32, 44 |
| 179 | mm4, Class=RegMMX, 0, 4, 33, 45 |
| 180 | mm5, Class=RegMMX, 0, 5, 34, 46 |
| 181 | mm6, Class=RegMMX, 0, 6, 35, 47 |
| 182 | mm7, Class=RegMMX, 0, 7, 36, 48 |
| 183 | xmm0, Class=RegSIMD|Instance=Accum|Xmmword, 0, 0, 21, 17 |
| 184 | xmm1, Class=RegSIMD|Xmmword, 0, 1, 22, 18 |
| 185 | xmm2, Class=RegSIMD|Xmmword, 0, 2, 23, 19 |
| 186 | xmm3, Class=RegSIMD|Xmmword, 0, 3, 24, 20 |
| 187 | xmm4, Class=RegSIMD|Xmmword, 0, 4, 25, 21 |
| 188 | xmm5, Class=RegSIMD|Xmmword, 0, 5, 26, 22 |
| 189 | xmm6, Class=RegSIMD|Xmmword, 0, 6, 27, 23 |
| 190 | xmm7, Class=RegSIMD|Xmmword, 0, 7, 28, 24 |
| 191 | xmm8, Class=RegSIMD|Xmmword, RegRex, 0, Dw2Inval, 25 |
| 192 | xmm9, Class=RegSIMD|Xmmword, RegRex, 1, Dw2Inval, 26 |
| 193 | xmm10, Class=RegSIMD|Xmmword, RegRex, 2, Dw2Inval, 27 |
| 194 | xmm11, Class=RegSIMD|Xmmword, RegRex, 3, Dw2Inval, 28 |
| 195 | xmm12, Class=RegSIMD|Xmmword, RegRex, 4, Dw2Inval, 29 |
| 196 | xmm13, Class=RegSIMD|Xmmword, RegRex, 5, Dw2Inval, 30 |
| 197 | xmm14, Class=RegSIMD|Xmmword, RegRex, 6, Dw2Inval, 31 |
| 198 | xmm15, Class=RegSIMD|Xmmword, RegRex, 7, Dw2Inval, 32 |
| 199 | xmm16, Class=RegSIMD|Xmmword, RegVRex, 0, Dw2Inval, 67 |
| 200 | xmm17, Class=RegSIMD|Xmmword, RegVRex, 1, Dw2Inval, 68 |
| 201 | xmm18, Class=RegSIMD|Xmmword, RegVRex, 2, Dw2Inval, 69 |
| 202 | xmm19, Class=RegSIMD|Xmmword, RegVRex, 3, Dw2Inval, 70 |
| 203 | xmm20, Class=RegSIMD|Xmmword, RegVRex, 4, Dw2Inval, 71 |
| 204 | xmm21, Class=RegSIMD|Xmmword, RegVRex, 5, Dw2Inval, 72 |
| 205 | xmm22, Class=RegSIMD|Xmmword, RegVRex, 6, Dw2Inval, 73 |
| 206 | xmm23, Class=RegSIMD|Xmmword, RegVRex, 7, Dw2Inval, 74 |
| 207 | xmm24, Class=RegSIMD|Xmmword, RegVRex|RegRex, 0, Dw2Inval, 75 |
| 208 | xmm25, Class=RegSIMD|Xmmword, RegVRex|RegRex, 1, Dw2Inval, 76 |
| 209 | xmm26, Class=RegSIMD|Xmmword, RegVRex|RegRex, 2, Dw2Inval, 77 |
| 210 | xmm27, Class=RegSIMD|Xmmword, RegVRex|RegRex, 3, Dw2Inval, 78 |
| 211 | xmm28, Class=RegSIMD|Xmmword, RegVRex|RegRex, 4, Dw2Inval, 79 |
| 212 | xmm29, Class=RegSIMD|Xmmword, RegVRex|RegRex, 5, Dw2Inval, 80 |
| 213 | xmm30, Class=RegSIMD|Xmmword, RegVRex|RegRex, 6, Dw2Inval, 81 |
| 214 | xmm31, Class=RegSIMD|Xmmword, RegVRex|RegRex, 7, Dw2Inval, 82 |
| 215 | // AVX registers. |
| 216 | ymm0, Class=RegSIMD|Ymmword, 0, 0, Dw2Inval, Dw2Inval |
| 217 | ymm1, Class=RegSIMD|Ymmword, 0, 1, Dw2Inval, Dw2Inval |
| 218 | ymm2, Class=RegSIMD|Ymmword, 0, 2, Dw2Inval, Dw2Inval |
| 219 | ymm3, Class=RegSIMD|Ymmword, 0, 3, Dw2Inval, Dw2Inval |
| 220 | ymm4, Class=RegSIMD|Ymmword, 0, 4, Dw2Inval, Dw2Inval |
| 221 | ymm5, Class=RegSIMD|Ymmword, 0, 5, Dw2Inval, Dw2Inval |
| 222 | ymm6, Class=RegSIMD|Ymmword, 0, 6, Dw2Inval, Dw2Inval |
| 223 | ymm7, Class=RegSIMD|Ymmword, 0, 7, Dw2Inval, Dw2Inval |
| 224 | ymm8, Class=RegSIMD|Ymmword, RegRex, 0, Dw2Inval, Dw2Inval |
| 225 | ymm9, Class=RegSIMD|Ymmword, RegRex, 1, Dw2Inval, Dw2Inval |
| 226 | ymm10, Class=RegSIMD|Ymmword, RegRex, 2, Dw2Inval, Dw2Inval |
| 227 | ymm11, Class=RegSIMD|Ymmword, RegRex, 3, Dw2Inval, Dw2Inval |
| 228 | ymm12, Class=RegSIMD|Ymmword, RegRex, 4, Dw2Inval, Dw2Inval |
| 229 | ymm13, Class=RegSIMD|Ymmword, RegRex, 5, Dw2Inval, Dw2Inval |
| 230 | ymm14, Class=RegSIMD|Ymmword, RegRex, 6, Dw2Inval, Dw2Inval |
| 231 | ymm15, Class=RegSIMD|Ymmword, RegRex, 7, Dw2Inval, Dw2Inval |
| 232 | ymm16, Class=RegSIMD|Ymmword, RegVRex, 0, Dw2Inval, Dw2Inval |
| 233 | ymm17, Class=RegSIMD|Ymmword, RegVRex, 1, Dw2Inval, Dw2Inval |
| 234 | ymm18, Class=RegSIMD|Ymmword, RegVRex, 2, Dw2Inval, Dw2Inval |
| 235 | ymm19, Class=RegSIMD|Ymmword, RegVRex, 3, Dw2Inval, Dw2Inval |
| 236 | ymm20, Class=RegSIMD|Ymmword, RegVRex, 4, Dw2Inval, Dw2Inval |
| 237 | ymm21, Class=RegSIMD|Ymmword, RegVRex, 5, Dw2Inval, Dw2Inval |
| 238 | ymm22, Class=RegSIMD|Ymmword, RegVRex, 6, Dw2Inval, Dw2Inval |
| 239 | ymm23, Class=RegSIMD|Ymmword, RegVRex, 7, Dw2Inval, Dw2Inval |
| 240 | ymm24, Class=RegSIMD|Ymmword, RegVRex|RegRex, 0, Dw2Inval, Dw2Inval |
| 241 | ymm25, Class=RegSIMD|Ymmword, RegVRex|RegRex, 1, Dw2Inval, Dw2Inval |
| 242 | ymm26, Class=RegSIMD|Ymmword, RegVRex|RegRex, 2, Dw2Inval, Dw2Inval |
| 243 | ymm27, Class=RegSIMD|Ymmword, RegVRex|RegRex, 3, Dw2Inval, Dw2Inval |
| 244 | ymm28, Class=RegSIMD|Ymmword, RegVRex|RegRex, 4, Dw2Inval, Dw2Inval |
| 245 | ymm29, Class=RegSIMD|Ymmword, RegVRex|RegRex, 5, Dw2Inval, Dw2Inval |
| 246 | ymm30, Class=RegSIMD|Ymmword, RegVRex|RegRex, 6, Dw2Inval, Dw2Inval |
| 247 | ymm31, Class=RegSIMD|Ymmword, RegVRex|RegRex, 7, Dw2Inval, Dw2Inval |
| 248 | // AVX512 registers. |
| 249 | zmm0, Class=RegSIMD|Zmmword, 0, 0, Dw2Inval, Dw2Inval |
| 250 | zmm1, Class=RegSIMD|Zmmword, 0, 1, Dw2Inval, Dw2Inval |
| 251 | zmm2, Class=RegSIMD|Zmmword, 0, 2, Dw2Inval, Dw2Inval |
| 252 | zmm3, Class=RegSIMD|Zmmword, 0, 3, Dw2Inval, Dw2Inval |
| 253 | zmm4, Class=RegSIMD|Zmmword, 0, 4, Dw2Inval, Dw2Inval |
| 254 | zmm5, Class=RegSIMD|Zmmword, 0, 5, Dw2Inval, Dw2Inval |
| 255 | zmm6, Class=RegSIMD|Zmmword, 0, 6, Dw2Inval, Dw2Inval |
| 256 | zmm7, Class=RegSIMD|Zmmword, 0, 7, Dw2Inval, Dw2Inval |
| 257 | zmm8, Class=RegSIMD|Zmmword, RegRex, 0, Dw2Inval, Dw2Inval |
| 258 | zmm9, Class=RegSIMD|Zmmword, RegRex, 1, Dw2Inval, Dw2Inval |
| 259 | zmm10, Class=RegSIMD|Zmmword, RegRex, 2, Dw2Inval, Dw2Inval |
| 260 | zmm11, Class=RegSIMD|Zmmword, RegRex, 3, Dw2Inval, Dw2Inval |
| 261 | zmm12, Class=RegSIMD|Zmmword, RegRex, 4, Dw2Inval, Dw2Inval |
| 262 | zmm13, Class=RegSIMD|Zmmword, RegRex, 5, Dw2Inval, Dw2Inval |
| 263 | zmm14, Class=RegSIMD|Zmmword, RegRex, 6, Dw2Inval, Dw2Inval |
| 264 | zmm15, Class=RegSIMD|Zmmword, RegRex, 7, Dw2Inval, Dw2Inval |
| 265 | zmm16, Class=RegSIMD|Zmmword, RegVRex, 0, Dw2Inval, Dw2Inval |
| 266 | zmm17, Class=RegSIMD|Zmmword, RegVRex, 1, Dw2Inval, Dw2Inval |
| 267 | zmm18, Class=RegSIMD|Zmmword, RegVRex, 2, Dw2Inval, Dw2Inval |
| 268 | zmm19, Class=RegSIMD|Zmmword, RegVRex, 3, Dw2Inval, Dw2Inval |
| 269 | zmm20, Class=RegSIMD|Zmmword, RegVRex, 4, Dw2Inval, Dw2Inval |
| 270 | zmm21, Class=RegSIMD|Zmmword, RegVRex, 5, Dw2Inval, Dw2Inval |
| 271 | zmm22, Class=RegSIMD|Zmmword, RegVRex, 6, Dw2Inval, Dw2Inval |
| 272 | zmm23, Class=RegSIMD|Zmmword, RegVRex, 7, Dw2Inval, Dw2Inval |
| 273 | zmm24, Class=RegSIMD|Zmmword, RegVRex|RegRex, 0, Dw2Inval, Dw2Inval |
| 274 | zmm25, Class=RegSIMD|Zmmword, RegVRex|RegRex, 1, Dw2Inval, Dw2Inval |
| 275 | zmm26, Class=RegSIMD|Zmmword, RegVRex|RegRex, 2, Dw2Inval, Dw2Inval |
| 276 | zmm27, Class=RegSIMD|Zmmword, RegVRex|RegRex, 3, Dw2Inval, Dw2Inval |
| 277 | zmm28, Class=RegSIMD|Zmmword, RegVRex|RegRex, 4, Dw2Inval, Dw2Inval |
| 278 | zmm29, Class=RegSIMD|Zmmword, RegVRex|RegRex, 5, Dw2Inval, Dw2Inval |
| 279 | zmm30, Class=RegSIMD|Zmmword, RegVRex|RegRex, 6, Dw2Inval, Dw2Inval |
| 280 | zmm31, Class=RegSIMD|Zmmword, RegVRex|RegRex, 7, Dw2Inval, Dw2Inval |
| 281 | // Bound registers for MPX |
| 282 | bnd0, Class=RegBND, 0, 0, Dw2Inval, Dw2Inval |
| 283 | bnd1, Class=RegBND, 0, 1, Dw2Inval, Dw2Inval |
| 284 | bnd2, Class=RegBND, 0, 2, Dw2Inval, Dw2Inval |
| 285 | bnd3, Class=RegBND, 0, 3, Dw2Inval, Dw2Inval |
| 286 | // No Class=Reg will make these registers rejected for all purposes except |
| 287 | // for addressing. This saves creating one extra type for RIP/EIP. |
| 288 | rip, Qword, RegRex64, RegIP, Dw2Inval, 16 |
| 289 | eip, Dword, RegRex64, RegIP, 8, Dw2Inval |
| 290 | // No Class=Reg will make these registers rejected for all purposes except |
| 291 | // for addressing. |
| 292 | riz, Qword|BaseIndex, RegRex64, RegIZ, Dw2Inval, Dw2Inval |
| 293 | eiz, Dword|BaseIndex, 0, RegIZ, Dw2Inval, Dw2Inval |
| 294 | // fp regs. |
| 295 | st(0), Class=Reg|Instance=Accum|Tbyte, 0, 0, 11, 33 |
| 296 | st(1), Class=Reg|Tbyte, 0, 1, 12, 34 |
| 297 | st(2), Class=Reg|Tbyte, 0, 2, 13, 35 |
| 298 | st(3), Class=Reg|Tbyte, 0, 3, 14, 36 |
| 299 | st(4), Class=Reg|Tbyte, 0, 4, 15, 37 |
| 300 | st(5), Class=Reg|Tbyte, 0, 5, 16, 38 |
| 301 | st(6), Class=Reg|Tbyte, 0, 6, 17, 39 |
| 302 | st(7), Class=Reg|Tbyte, 0, 7, 18, 40 |
| 303 | // Pseudo-register names only used in .cfi_* directives |
| 304 | eflags, 0, 0, 0, 9, 49 |
| 305 | rflags, 0, 0, 0, Dw2Inval, 49 |
| 306 | fs.base, 0, 0, 0, Dw2Inval, 58 |
| 307 | gs.base, 0, 0, 0, Dw2Inval, 59 |
| 308 | tr, 0, 0, 0, 48, 62 |
| 309 | ldtr, 0, 0, 0, 49, 63 |
| 310 | // st0...7 for backward compatibility |
| 311 | st0, 0, 0, 0, 11, 33 |
| 312 | st1, 0, 0, 1, 12, 34 |
| 313 | st2, 0, 0, 2, 13, 35 |
| 314 | st3, 0, 0, 3, 14, 36 |
| 315 | st4, 0, 0, 4, 15, 37 |
| 316 | st5, 0, 0, 5, 16, 38 |
| 317 | st6, 0, 0, 6, 17, 39 |
| 318 | st7, 0, 0, 7, 18, 40 |
| 319 | fcw, 0, 0, 0, 37, 65 |
| 320 | fsw, 0, 0, 0, 38, 66 |
| 321 | mxcsr, 0, 0, 0, 39, 64 |