| 1 | /* microblaze-opcm.h -- Header used in microblaze-opc.h |
| 2 | |
| 3 | Copyright (C) 2009-2020 Free Software Foundation, Inc. |
| 4 | |
| 5 | This file is part of the GNU opcodes library. |
| 6 | |
| 7 | This library is free software; you can redistribute it and/or modify |
| 8 | it under the terms of the GNU General Public License as published by |
| 9 | the Free Software Foundation; either version 3, or (at your option) |
| 10 | any later version. |
| 11 | |
| 12 | It is distributed in the hope that it will be useful, but WITHOUT |
| 13 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
| 14 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public |
| 15 | License for more details. |
| 16 | |
| 17 | You should have received a copy of the GNU General Public License |
| 18 | along with this file; see the file COPYING. If not, write to the |
| 19 | Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, |
| 20 | MA 02110-1301, USA. */ |
| 21 | |
| 22 | |
| 23 | #ifndef MICROBLAZE_OPCM |
| 24 | #define MICROBLAZE_OPCM |
| 25 | |
| 26 | enum microblaze_instr |
| 27 | { |
| 28 | add, rsub, addc, rsubc, addk, rsubk, addkc, rsubkc, clz, cmp, cmpu, |
| 29 | addi, rsubi, addic, rsubic, addik, rsubik, addikc, rsubikc, mul, |
| 30 | mulh, mulhu, mulhsu,swapb,swaph, |
| 31 | idiv, idivu, bsll, bsra, bsrl, get, put, nget, nput, cget, cput, |
| 32 | ncget, ncput, muli, bslli, bsrai, bsrli, mului, |
| 33 | /* 'or/and/xor' are C++ keywords. */ |
| 34 | microblaze_or, microblaze_and, microblaze_xor, |
| 35 | andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16, |
| 36 | wic, wdc, wdcclear, wdcflush, mts, mfs, mbar, br, brd, |
| 37 | brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned, blt, |
| 38 | bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni, |
| 39 | imm, rtsd, rtid, rtbd, rted, bri, brid, brlid, brai, braid, bralid, |
| 40 | brki, beqi, beqid, bnei, bneid, blti, bltid, blei, bleid, bgti, |
| 41 | bgtid, bgei, bgeid, lbu, lbur, lhu, lhur, lw, lwr, lwx, sb, sbr, sh, |
| 42 | shr, sw, swr, swx, lbui, lhui, lwi, |
| 43 | sbi, shi, swi, msrset, msrclr, tuqula, mbi_fadd, frsub, mbi_fmul, mbi_fdiv, |
| 44 | fcmp_lt, fcmp_eq, fcmp_le, fcmp_gt, fcmp_ne, fcmp_ge, fcmp_un, flt, |
| 45 | fint, fsqrt, |
| 46 | tget, tcget, tnget, tncget, tput, tcput, tnput, tncput, |
| 47 | eget, ecget, neget, necget, eput, ecput, neput, necput, |
| 48 | teget, tecget, tneget, tnecget, teput, tecput, tneput, tnecput, |
| 49 | aget, caget, naget, ncaget, aput, caput, naput, ncaput, |
| 50 | taget, tcaget, tnaget, tncaget, taput, tcaput, tnaput, tncaput, |
| 51 | eaget, ecaget, neaget, necaget, eaput, ecaput, neaput, necaput, |
| 52 | teaget, tecaget, tneaget, tnecaget, teaput, tecaput, tneaput, tnecaput, |
| 53 | getd, tgetd, cgetd, tcgetd, ngetd, tngetd, ncgetd, tncgetd, |
| 54 | putd, tputd, cputd, tcputd, nputd, tnputd, ncputd, tncputd, |
| 55 | egetd, tegetd, ecgetd, tecgetd, negetd, tnegetd, necgetd, tnecgetd, |
| 56 | eputd, teputd, ecputd, tecputd, neputd, tneputd, necputd, tnecputd, |
| 57 | agetd, tagetd, cagetd, tcagetd, nagetd, tnagetd, ncagetd, tncagetd, |
| 58 | aputd, taputd, caputd, tcaputd, naputd, tnaputd, ncaputd, tncaputd, |
| 59 | eagetd, teagetd, ecagetd, tecagetd, neagetd, tneagetd, necagetd, tnecagetd, |
| 60 | eaputd, teaputd, ecaputd, tecaputd, neaputd, tneaputd, necaputd, tnecaputd, |
| 61 | invalid_inst |
| 62 | }; |
| 63 | |
| 64 | enum microblaze_instr_type |
| 65 | { |
| 66 | arithmetic_inst, logical_inst, mult_inst, div_inst, branch_inst, |
| 67 | return_inst, immediate_inst, special_inst, memory_load_inst, |
| 68 | memory_store_inst, barrel_shift_inst, anyware_inst |
| 69 | }; |
| 70 | |
| 71 | #define INST_WORD_SIZE 4 |
| 72 | |
| 73 | /* Gen purpose regs go from 0 to 31. */ |
| 74 | /* Mask is reg num - max_reg_num, ie reg_num - 32 in this case. */ |
| 75 | |
| 76 | #define REG_PC_MASK 0x8000 |
| 77 | #define REG_MSR_MASK 0x8001 |
| 78 | #define REG_EAR_MASK 0x8003 |
| 79 | #define REG_ESR_MASK 0x8005 |
| 80 | #define REG_FSR_MASK 0x8007 |
| 81 | #define REG_BTR_MASK 0x800b |
| 82 | #define REG_EDR_MASK 0x800d |
| 83 | #define REG_PVR_MASK 0xa000 |
| 84 | #define REG_SLR_MASK 0x8800 |
| 85 | #define REG_SHR_MASK 0x8802 |
| 86 | |
| 87 | #define REG_PID_MASK 0x9000 |
| 88 | #define REG_ZPR_MASK 0x9001 |
| 89 | #define REG_TLBX_MASK 0x9002 |
| 90 | #define REG_TLBLO_MASK 0x9003 |
| 91 | #define REG_TLBHI_MASK 0x9004 |
| 92 | #define REG_TLBSX_MASK 0x9005 |
| 93 | |
| 94 | #define MIN_REGNUM 0 |
| 95 | #define MAX_REGNUM 31 |
| 96 | |
| 97 | #define MIN_PVR_REGNUM 0 |
| 98 | #define MAX_PVR_REGNUM 15 |
| 99 | |
| 100 | #define REG_PC 32 /* PC. */ |
| 101 | #define REG_MSR 33 /* Machine status reg. */ |
| 102 | #define REG_EAR 35 /* Exception reg. */ |
| 103 | #define REG_ESR 37 /* Exception reg. */ |
| 104 | #define REG_FSR 39 /* FPU Status reg. */ |
| 105 | #define REG_BTR 43 /* Branch Target reg. */ |
| 106 | #define REG_EDR 45 /* Exception reg. */ |
| 107 | #define REG_SHR 50 /* Stack High reg. */ |
| 108 | #define REG_SLR 51 /* Stack Low reg. */ |
| 109 | #define REG_PVR 40960 /* Program Verification reg. */ |
| 110 | |
| 111 | #define REG_PID 36864 /* MMU: Process ID reg. */ |
| 112 | #define REG_ZPR 36865 /* MMU: Zone Protect reg. */ |
| 113 | #define REG_TLBX 36866 /* MMU: TLB Index reg. */ |
| 114 | #define REG_TLBLO 36867 /* MMU: TLB Low reg. */ |
| 115 | #define REG_TLBHI 36868 /* MMU: TLB High reg. */ |
| 116 | #define REG_TLBSX 36869 /* MMU: TLB Search Index reg. */ |
| 117 | |
| 118 | /* Alternate names for gen purpose regs. */ |
| 119 | #define REG_SP 1 /* stack pointer. */ |
| 120 | #define REG_ROSDP 2 /* read-only small data pointer. */ |
| 121 | #define REG_RWSDP 13 /* read-write small data pointer. */ |
| 122 | |
| 123 | /* Assembler Register - Used in Delay Slot Optimization. */ |
| 124 | #define REG_AS 18 |
| 125 | #define REG_ZERO 0 |
| 126 | |
| 127 | #define RD_LOW 21 /* Low bit for RD. */ |
| 128 | #define RA_LOW 16 /* Low bit for RA. */ |
| 129 | #define RB_LOW 11 /* Low bit for RB. */ |
| 130 | #define IMM_LOW 0 /* Low bit for immediate. */ |
| 131 | #define IMM_MBAR 21 /* low bit for mbar instruction. */ |
| 132 | |
| 133 | #define RD_MASK 0x03E00000 |
| 134 | #define RA_MASK 0x001F0000 |
| 135 | #define RB_MASK 0x0000F800 |
| 136 | #define IMM_MASK 0x0000FFFF |
| 137 | |
| 138 | /* Imm mask for barrel shifts. */ |
| 139 | #define IMM5_MASK 0x0000001F |
| 140 | |
| 141 | /* Imm mask for mbar. */ |
| 142 | #define IMM5_MBAR_MASK 0x03E00000 |
| 143 | |
| 144 | /* FSL imm mask for get, put instructions. */ |
| 145 | #define RFSL_MASK 0x000000F |
| 146 | |
| 147 | /* Imm mask for msrset, msrclr instructions. */ |
| 148 | #define IMM15_MASK 0x00007FFF |
| 149 | |
| 150 | #endif /* MICROBLAZE-OPCM */ |