| 1 | /* Simulator header for cgen parallel support. |
| 2 | Copyright (C) 1999, 2000 Free Software Foundation, Inc. |
| 3 | Contributed by Cygnus Solutions. |
| 4 | |
| 5 | This file is part of the GNU instruction set simulator. |
| 6 | |
| 7 | This program is free software; you can redistribute it and/or modify |
| 8 | it under the terms of the GNU General Public License as published by |
| 9 | the Free Software Foundation; either version 2, or (at your option) |
| 10 | any later version. |
| 11 | |
| 12 | This program is distributed in the hope that it will be useful, |
| 13 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | GNU General Public License for more details. |
| 16 | |
| 17 | You should have received a copy of the GNU General Public License along |
| 18 | with this program; if not, write to the Free Software Foundation, Inc., |
| 19 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ |
| 20 | |
| 21 | #ifndef CGEN_PAR_H |
| 22 | #define CGEN_PAR_H |
| 23 | |
| 24 | /* Kinds of writes stored on the write queue. */ |
| 25 | enum cgen_write_queue_kind { |
| 26 | CGEN_BI_WRITE, CGEN_QI_WRITE, CGEN_SI_WRITE, CGEN_SF_WRITE, |
| 27 | CGEN_PC_WRITE, |
| 28 | CGEN_FN_HI_WRITE, CGEN_FN_SI_WRITE, CGEN_FN_SF_WRITE, |
| 29 | CGEN_FN_DI_WRITE, CGEN_FN_DF_WRITE, |
| 30 | CGEN_FN_XI_WRITE, CGEN_FN_PC_WRITE, |
| 31 | CGEN_MEM_QI_WRITE, CGEN_MEM_HI_WRITE, CGEN_MEM_SI_WRITE, CGEN_MEM_DI_WRITE, |
| 32 | CGEN_MEM_DF_WRITE, CGEN_MEM_XI_WRITE, |
| 33 | CGEN_FN_MEM_QI_WRITE, CGEN_FN_MEM_HI_WRITE, CGEN_FN_MEM_SI_WRITE, |
| 34 | CGEN_FN_MEM_DI_WRITE, CGEN_FN_MEM_DF_WRITE, CGEN_FN_MEM_XI_WRITE, |
| 35 | CGEN_NUM_WRITE_KINDS |
| 36 | }; |
| 37 | |
| 38 | /* Element of the write queue. */ |
| 39 | typedef struct { |
| 40 | enum cgen_write_queue_kind kind; /* Used to select union member below. */ |
| 41 | IADDR insn_address; /* Address of the insn performing the write. */ |
| 42 | union { |
| 43 | struct { |
| 44 | BI *target; |
| 45 | BI value; |
| 46 | } bi_write; |
| 47 | struct { |
| 48 | UQI *target; |
| 49 | QI value; |
| 50 | } qi_write; |
| 51 | struct { |
| 52 | SI *target; |
| 53 | SI value; |
| 54 | } si_write; |
| 55 | struct { |
| 56 | SI *target; |
| 57 | SF value; |
| 58 | } sf_write; |
| 59 | struct { |
| 60 | USI value; |
| 61 | } pc_write; |
| 62 | struct { |
| 63 | UINT regno; |
| 64 | UHI value; |
| 65 | void (*function)(SIM_CPU *, UINT, UHI); |
| 66 | } fn_hi_write; |
| 67 | struct { |
| 68 | UINT regno; |
| 69 | SI value; |
| 70 | void (*function)(SIM_CPU *, UINT, USI); |
| 71 | } fn_si_write; |
| 72 | struct { |
| 73 | UINT regno; |
| 74 | SF value; |
| 75 | void (*function)(SIM_CPU *, UINT, SF); |
| 76 | } fn_sf_write; |
| 77 | struct { |
| 78 | UINT regno; |
| 79 | DI value; |
| 80 | void (*function)(SIM_CPU *, UINT, DI); |
| 81 | } fn_di_write; |
| 82 | struct { |
| 83 | UINT regno; |
| 84 | DF value; |
| 85 | void (*function)(SIM_CPU *, UINT, DF); |
| 86 | } fn_df_write; |
| 87 | struct { |
| 88 | UINT regno; |
| 89 | SI value[4]; |
| 90 | void (*function)(SIM_CPU *, UINT, SI *); |
| 91 | } fn_xi_write; |
| 92 | struct { |
| 93 | USI value; |
| 94 | void (*function)(SIM_CPU *, USI); |
| 95 | } fn_pc_write; |
| 96 | struct { |
| 97 | SI address; |
| 98 | QI value; |
| 99 | } mem_qi_write; |
| 100 | struct { |
| 101 | SI address; |
| 102 | HI value; |
| 103 | } mem_hi_write; |
| 104 | struct { |
| 105 | SI address; |
| 106 | SI value; |
| 107 | } mem_si_write; |
| 108 | struct { |
| 109 | SI address; |
| 110 | DI value; |
| 111 | } mem_di_write; |
| 112 | struct { |
| 113 | SI address; |
| 114 | DF value; |
| 115 | } mem_df_write; |
| 116 | struct { |
| 117 | SI address; |
| 118 | SI value[4]; |
| 119 | } mem_xi_write; |
| 120 | struct { |
| 121 | SI address; |
| 122 | QI value; |
| 123 | void (*function)(SIM_CPU *, IADDR, SI, QI); |
| 124 | } fn_mem_qi_write; |
| 125 | struct { |
| 126 | SI address; |
| 127 | HI value; |
| 128 | void (*function)(SIM_CPU *, IADDR, SI, HI); |
| 129 | } fn_mem_hi_write; |
| 130 | struct { |
| 131 | SI address; |
| 132 | SI value; |
| 133 | void (*function)(SIM_CPU *, IADDR, SI, SI); |
| 134 | } fn_mem_si_write; |
| 135 | struct { |
| 136 | SI address; |
| 137 | DI value; |
| 138 | void (*function)(SIM_CPU *, IADDR, SI, DI); |
| 139 | } fn_mem_di_write; |
| 140 | struct { |
| 141 | SI address; |
| 142 | DF value; |
| 143 | void (*function)(SIM_CPU *, IADDR, SI, DF); |
| 144 | } fn_mem_df_write; |
| 145 | struct { |
| 146 | SI address; |
| 147 | SI value[4]; |
| 148 | void (*function)(SIM_CPU *, IADDR, SI, SI *); |
| 149 | } fn_mem_xi_write; |
| 150 | } kinds; |
| 151 | } CGEN_WRITE_QUEUE_ELEMENT; |
| 152 | |
| 153 | #define CGEN_WRITE_QUEUE_ELEMENT_KIND(element) ((element)->kind) |
| 154 | #define CGEN_WRITE_QUEUE_ELEMENT_IADDR(element) ((element)->insn_address) |
| 155 | |
| 156 | extern void cgen_write_queue_element_execute ( |
| 157 | SIM_CPU *, CGEN_WRITE_QUEUE_ELEMENT * |
| 158 | ); |
| 159 | |
| 160 | /* Instance of the queue for parallel write-after support. */ |
| 161 | /* FIXME: Should be dynamic? */ |
| 162 | #define CGEN_WRITE_QUEUE_SIZE (64 * 4) /* 64 writes x 4 insns -- for now. */ |
| 163 | |
| 164 | typedef struct { |
| 165 | int index; |
| 166 | CGEN_WRITE_QUEUE_ELEMENT q[CGEN_WRITE_QUEUE_SIZE]; |
| 167 | } CGEN_WRITE_QUEUE; |
| 168 | |
| 169 | #define CGEN_WRITE_QUEUE_CLEAR(queue) ((queue)->index = 0) |
| 170 | #define CGEN_WRITE_QUEUE_INDEX(queue) ((queue)->index) |
| 171 | #define CGEN_WRITE_QUEUE_ELEMENT(queue, ix) (&(queue)->q[(ix)]) |
| 172 | |
| 173 | #define CGEN_WRITE_QUEUE_NEXT(queue) ( \ |
| 174 | (queue)->index < CGEN_WRITE_QUEUE_SIZE \ |
| 175 | ? &(queue)->q[(queue)->index++] \ |
| 176 | : cgen_write_queue_overflow (queue) \ |
| 177 | ) |
| 178 | |
| 179 | extern CGEN_WRITE_QUEUE_ELEMENT *cgen_write_queue_overflow (CGEN_WRITE_QUEUE *); |
| 180 | |
| 181 | /* Functions for queuing writes. Used by semantic code. */ |
| 182 | extern void sim_queue_bi_write (SIM_CPU *, BI *, BI); |
| 183 | extern void sim_queue_qi_write (SIM_CPU *, UQI *, UQI); |
| 184 | extern void sim_queue_si_write (SIM_CPU *, SI *, SI); |
| 185 | extern void sim_queue_sf_write (SIM_CPU *, SI *, SF); |
| 186 | |
| 187 | extern void sim_queue_pc_write (SIM_CPU *, USI); |
| 188 | |
| 189 | extern void sim_queue_fn_hi_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, UHI), UINT, UHI); |
| 190 | extern void sim_queue_fn_si_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, USI), UINT, USI); |
| 191 | extern void sim_queue_fn_sf_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, SF), UINT, SF); |
| 192 | extern void sim_queue_fn_di_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, DI), UINT, DI); |
| 193 | extern void sim_queue_fn_df_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, DF), UINT, DF); |
| 194 | extern void sim_queue_fn_xi_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, SI *), UINT, SI *); |
| 195 | extern void sim_queue_fn_pc_write (SIM_CPU *, void (*)(SIM_CPU *, USI), USI); |
| 196 | |
| 197 | extern void sim_queue_mem_qi_write (SIM_CPU *, SI, QI); |
| 198 | extern void sim_queue_mem_hi_write (SIM_CPU *, SI, HI); |
| 199 | extern void sim_queue_mem_si_write (SIM_CPU *, SI, SI); |
| 200 | extern void sim_queue_mem_di_write (SIM_CPU *, SI, DI); |
| 201 | extern void sim_queue_mem_df_write (SIM_CPU *, SI, DF); |
| 202 | extern void sim_queue_mem_xi_write (SIM_CPU *, SI, SI *); |
| 203 | |
| 204 | extern void sim_queue_fn_mem_qi_write (SIM_CPU *, void (*)(SIM_CPU *, IADDR, SI, QI), SI, QI); |
| 205 | extern void sim_queue_fn_mem_hi_write (SIM_CPU *, void (*)(SIM_CPU *, IADDR, SI, HI), SI, HI); |
| 206 | extern void sim_queue_fn_mem_si_write (SIM_CPU *, void (*)(SIM_CPU *, IADDR, SI, SI), SI, SI); |
| 207 | extern void sim_queue_fn_mem_di_write (SIM_CPU *, void (*)(SIM_CPU *, IADDR, SI, DI), SI, DI); |
| 208 | extern void sim_queue_fn_mem_df_write (SIM_CPU *, void (*)(SIM_CPU *, IADDR, SI, DF), SI, DF); |
| 209 | extern void sim_queue_fn_mem_xi_write (SIM_CPU *, void (*)(SIM_CPU *, IADDR, SI, SI *), SI, SI *); |
| 210 | |
| 211 | #endif /* CGEN_PAR_H */ |