| 1 | /* frv trap support |
| 2 | Copyright (C) 1999-2020 Free Software Foundation, Inc. |
| 3 | Contributed by Red Hat. |
| 4 | |
| 5 | This file is part of the GNU simulators. |
| 6 | |
| 7 | This program is free software; you can redistribute it and/or modify |
| 8 | it under the terms of the GNU General Public License as published by |
| 9 | the Free Software Foundation; either version 3 of the License, or |
| 10 | (at your option) any later version. |
| 11 | |
| 12 | This program is distributed in the hope that it will be useful, |
| 13 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | GNU General Public License for more details. |
| 16 | |
| 17 | You should have received a copy of the GNU General Public License |
| 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
| 19 | |
| 20 | #define WANT_CPU frvbf |
| 21 | #define WANT_CPU_FRVBF |
| 22 | |
| 23 | #include "sim-main.h" |
| 24 | #include "targ-vals.h" |
| 25 | #include "cgen-engine.h" |
| 26 | #include "cgen-par.h" |
| 27 | #include "sim-fpu.h" |
| 28 | |
| 29 | #include "bfd.h" |
| 30 | #include "libiberty.h" |
| 31 | |
| 32 | CGEN_ATTR_VALUE_ENUM_TYPE frv_current_fm_slot; |
| 33 | |
| 34 | /* The semantic code invokes this for invalid (unrecognized) instructions. */ |
| 35 | |
| 36 | SEM_PC |
| 37 | sim_engine_invalid_insn (SIM_CPU *current_cpu, IADDR cia, SEM_PC vpc) |
| 38 | { |
| 39 | frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION); |
| 40 | return vpc; |
| 41 | } |
| 42 | |
| 43 | /* Process an address exception. */ |
| 44 | |
| 45 | void |
| 46 | frv_core_signal (SIM_DESC sd, SIM_CPU *current_cpu, sim_cia cia, |
| 47 | unsigned int map, int nr_bytes, address_word addr, |
| 48 | transfer_type transfer, sim_core_signals sig) |
| 49 | { |
| 50 | if (sig == sim_core_unaligned_signal) |
| 51 | { |
| 52 | if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400 |
| 53 | || STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr450) |
| 54 | frv_queue_data_access_error_interrupt (current_cpu, addr); |
| 55 | else |
| 56 | frv_queue_mem_address_not_aligned_interrupt (current_cpu, addr); |
| 57 | } |
| 58 | |
| 59 | frv_term (sd); |
| 60 | sim_core_signal (sd, current_cpu, cia, map, nr_bytes, addr, transfer, sig); |
| 61 | } |
| 62 | |
| 63 | void |
| 64 | frv_sim_engine_halt_hook (SIM_DESC sd, SIM_CPU *current_cpu, sim_cia cia) |
| 65 | { |
| 66 | int i; |
| 67 | if (current_cpu != NULL) |
| 68 | CPU_PC_SET (current_cpu, cia); |
| 69 | |
| 70 | /* Invalidate the insn and data caches of all cpus. */ |
| 71 | for (i = 0; i < MAX_NR_PROCESSORS; ++i) |
| 72 | { |
| 73 | current_cpu = STATE_CPU (sd, i); |
| 74 | frv_cache_invalidate_all (CPU_INSN_CACHE (current_cpu), 0); |
| 75 | frv_cache_invalidate_all (CPU_DATA_CACHE (current_cpu), 1); |
| 76 | } |
| 77 | frv_term (sd); |
| 78 | } |
| 79 | \f |
| 80 | /* Read/write functions for system call interface. */ |
| 81 | |
| 82 | static int |
| 83 | syscall_read_mem (host_callback *cb, struct cb_syscall *sc, |
| 84 | unsigned long taddr, char *buf, int bytes) |
| 85 | { |
| 86 | SIM_DESC sd = (SIM_DESC) sc->p1; |
| 87 | SIM_CPU *cpu = (SIM_CPU *) sc->p2; |
| 88 | |
| 89 | frv_cache_invalidate_all (CPU_DATA_CACHE (cpu), 1); |
| 90 | return sim_core_read_buffer (sd, cpu, read_map, buf, taddr, bytes); |
| 91 | } |
| 92 | |
| 93 | static int |
| 94 | syscall_write_mem (host_callback *cb, struct cb_syscall *sc, |
| 95 | unsigned long taddr, const char *buf, int bytes) |
| 96 | { |
| 97 | SIM_DESC sd = (SIM_DESC) sc->p1; |
| 98 | SIM_CPU *cpu = (SIM_CPU *) sc->p2; |
| 99 | |
| 100 | frv_cache_invalidate_all (CPU_INSN_CACHE (cpu), 0); |
| 101 | frv_cache_invalidate_all (CPU_DATA_CACHE (cpu), 1); |
| 102 | return sim_core_write_buffer (sd, cpu, write_map, buf, taddr, bytes); |
| 103 | } |
| 104 | |
| 105 | /* Handle TRA and TIRA insns. */ |
| 106 | void |
| 107 | frv_itrap (SIM_CPU *current_cpu, PCADDR pc, USI base, SI offset) |
| 108 | { |
| 109 | SIM_DESC sd = CPU_STATE (current_cpu); |
| 110 | host_callback *cb = STATE_CALLBACK (sd); |
| 111 | USI num = ((base + offset) & 0x7f) + 0x80; |
| 112 | |
| 113 | if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT) |
| 114 | { |
| 115 | frv_queue_software_interrupt (current_cpu, num); |
| 116 | return; |
| 117 | } |
| 118 | |
| 119 | switch (num) |
| 120 | { |
| 121 | case TRAP_SYSCALL : |
| 122 | { |
| 123 | CB_SYSCALL s; |
| 124 | CB_SYSCALL_INIT (&s); |
| 125 | s.func = GET_H_GR (7); |
| 126 | s.arg1 = GET_H_GR (8); |
| 127 | s.arg2 = GET_H_GR (9); |
| 128 | s.arg3 = GET_H_GR (10); |
| 129 | |
| 130 | if (s.func == TARGET_SYS_exit) |
| 131 | { |
| 132 | sim_engine_halt (sd, current_cpu, NULL, pc, sim_exited, s.arg1); |
| 133 | } |
| 134 | |
| 135 | s.p1 = (PTR) sd; |
| 136 | s.p2 = (PTR) current_cpu; |
| 137 | s.read_mem = syscall_read_mem; |
| 138 | s.write_mem = syscall_write_mem; |
| 139 | cb_syscall (cb, &s); |
| 140 | SET_H_GR (8, s.result); |
| 141 | SET_H_GR (9, s.result2); |
| 142 | SET_H_GR (10, s.errcode); |
| 143 | break; |
| 144 | } |
| 145 | |
| 146 | case TRAP_BREAKPOINT: |
| 147 | sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGTRAP); |
| 148 | break; |
| 149 | |
| 150 | /* Add support for dumping registers, either at fixed traps, or all |
| 151 | unknown traps if configured with --enable-sim-trapdump. */ |
| 152 | default: |
| 153 | #if !TRAPDUMP |
| 154 | frv_queue_software_interrupt (current_cpu, num); |
| 155 | return; |
| 156 | #endif |
| 157 | |
| 158 | #ifdef TRAP_REGDUMP1 |
| 159 | case TRAP_REGDUMP1: |
| 160 | #endif |
| 161 | |
| 162 | #ifdef TRAP_REGDUMP2 |
| 163 | case TRAP_REGDUMP2: |
| 164 | #endif |
| 165 | |
| 166 | #if TRAPDUMP || (defined (TRAP_REGDUMP1)) || (defined (TRAP_REGDUMP2)) |
| 167 | { |
| 168 | char buf[256]; |
| 169 | int i, j; |
| 170 | |
| 171 | buf[0] = 0; |
| 172 | if (STATE_TEXT_SECTION (sd) |
| 173 | && pc >= STATE_TEXT_START (sd) |
| 174 | && pc < STATE_TEXT_END (sd)) |
| 175 | { |
| 176 | const char *pc_filename = (const char *)0; |
| 177 | const char *pc_function = (const char *)0; |
| 178 | unsigned int pc_linenum = 0; |
| 179 | |
| 180 | if (bfd_find_nearest_line (STATE_PROG_BFD (sd), |
| 181 | STATE_TEXT_SECTION (sd), |
| 182 | (struct bfd_symbol **) 0, |
| 183 | pc - STATE_TEXT_START (sd), |
| 184 | &pc_filename, &pc_function, &pc_linenum) |
| 185 | && (pc_function || pc_filename)) |
| 186 | { |
| 187 | char *p = buf+2; |
| 188 | buf[0] = ' '; |
| 189 | buf[1] = '('; |
| 190 | if (pc_function) |
| 191 | { |
| 192 | strcpy (p, pc_function); |
| 193 | p += strlen (p); |
| 194 | } |
| 195 | else |
| 196 | { |
| 197 | char *q = (char *) strrchr (pc_filename, '/'); |
| 198 | strcpy (p, (q) ? q+1 : pc_filename); |
| 199 | p += strlen (p); |
| 200 | } |
| 201 | |
| 202 | if (pc_linenum) |
| 203 | { |
| 204 | sprintf (p, " line %d", pc_linenum); |
| 205 | p += strlen (p); |
| 206 | } |
| 207 | |
| 208 | p[0] = ')'; |
| 209 | p[1] = '\0'; |
| 210 | if ((p+1) - buf > sizeof (buf)) |
| 211 | abort (); |
| 212 | } |
| 213 | } |
| 214 | |
| 215 | sim_io_printf (sd, |
| 216 | "\nRegister dump, pc = 0x%.8x%s, base = %u, offset = %d\n", |
| 217 | (unsigned)pc, buf, (unsigned)base, (int)offset); |
| 218 | |
| 219 | for (i = 0; i < 64; i += 8) |
| 220 | { |
| 221 | long g0 = (long)GET_H_GR (i); |
| 222 | long g1 = (long)GET_H_GR (i+1); |
| 223 | long g2 = (long)GET_H_GR (i+2); |
| 224 | long g3 = (long)GET_H_GR (i+3); |
| 225 | long g4 = (long)GET_H_GR (i+4); |
| 226 | long g5 = (long)GET_H_GR (i+5); |
| 227 | long g6 = (long)GET_H_GR (i+6); |
| 228 | long g7 = (long)GET_H_GR (i+7); |
| 229 | |
| 230 | if ((g0 | g1 | g2 | g3 | g4 | g5 | g6 | g7) != 0) |
| 231 | sim_io_printf (sd, |
| 232 | "\tgr%02d - gr%02d: 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx\n", |
| 233 | i, i+7, g0, g1, g2, g3, g4, g5, g6, g7); |
| 234 | } |
| 235 | |
| 236 | for (i = 0; i < 64; i += 8) |
| 237 | { |
| 238 | long f0 = (long)GET_H_FR (i); |
| 239 | long f1 = (long)GET_H_FR (i+1); |
| 240 | long f2 = (long)GET_H_FR (i+2); |
| 241 | long f3 = (long)GET_H_FR (i+3); |
| 242 | long f4 = (long)GET_H_FR (i+4); |
| 243 | long f5 = (long)GET_H_FR (i+5); |
| 244 | long f6 = (long)GET_H_FR (i+6); |
| 245 | long f7 = (long)GET_H_FR (i+7); |
| 246 | |
| 247 | if ((f0 | f1 | f2 | f3 | f4 | f5 | f6 | f7) != 0) |
| 248 | sim_io_printf (sd, |
| 249 | "\tfr%02d - fr%02d: 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx\n", |
| 250 | i, i+7, f0, f1, f2, f3, f4, f5, f6, f7); |
| 251 | } |
| 252 | |
| 253 | sim_io_printf (sd, |
| 254 | "\tlr/lcr/cc/ccc: 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx\n", |
| 255 | (long)GET_H_SPR (272), |
| 256 | (long)GET_H_SPR (273), |
| 257 | (long)GET_H_SPR (256), |
| 258 | (long)GET_H_SPR (263)); |
| 259 | } |
| 260 | break; |
| 261 | #endif |
| 262 | } |
| 263 | } |
| 264 | |
| 265 | /* Handle the MTRAP insn. */ |
| 266 | void |
| 267 | frv_mtrap (SIM_CPU *current_cpu) |
| 268 | { |
| 269 | SIM_DESC sd = CPU_STATE (current_cpu); |
| 270 | |
| 271 | /* Check the status of media exceptions in MSR0. */ |
| 272 | SI msr = GET_MSR (0); |
| 273 | if (GET_MSR_AOVF (msr) || GET_MSR_MTT (msr) && STATE_ARCHITECTURE (sd)->mach != bfd_mach_fr550) |
| 274 | frv_queue_program_interrupt (current_cpu, FRV_MP_EXCEPTION); |
| 275 | } |
| 276 | |
| 277 | /* Handle the BREAK insn. */ |
| 278 | void |
| 279 | frv_break (SIM_CPU *current_cpu) |
| 280 | { |
| 281 | IADDR pc; |
| 282 | SIM_DESC sd = CPU_STATE (current_cpu); |
| 283 | |
| 284 | if (STATE_ENVIRONMENT (sd) != OPERATING_ENVIRONMENT) |
| 285 | { |
| 286 | /* Invalidate the insn cache because the debugger will presumably |
| 287 | replace the breakpoint insn with the real one. */ |
| 288 | sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGTRAP); |
| 289 | } |
| 290 | |
| 291 | frv_queue_break_interrupt (current_cpu); |
| 292 | } |
| 293 | |
| 294 | /* Return from trap. */ |
| 295 | USI |
| 296 | frv_rett (SIM_CPU *current_cpu, PCADDR pc, BI debug_field) |
| 297 | { |
| 298 | USI new_pc; |
| 299 | /* if (normal running mode and debug_field==0 |
| 300 | PC=PCSR |
| 301 | PSR.ET=1 |
| 302 | PSR.S=PSR.PS |
| 303 | else if (debug running mode and debug_field==1) |
| 304 | PC=(BPCSR) |
| 305 | PSR.ET=BPSR.BET |
| 306 | PSR.S=BPSR.BS |
| 307 | change to normal running mode |
| 308 | */ |
| 309 | int psr_s = GET_H_PSR_S (); |
| 310 | int psr_et = GET_H_PSR_ET (); |
| 311 | |
| 312 | /* Check for exceptions in the priority order listed in the FRV Architecture |
| 313 | Volume 2. */ |
| 314 | if (! psr_s) |
| 315 | { |
| 316 | /* Halt if PSR.ET is not set. See chapter 6 of the LSI. */ |
| 317 | if (! psr_et) |
| 318 | { |
| 319 | SIM_DESC sd = CPU_STATE (current_cpu); |
| 320 | sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGTRAP); |
| 321 | } |
| 322 | |
| 323 | /* privileged_instruction interrupt will have already been queued by |
| 324 | frv_detect_insn_access_interrupts. */ |
| 325 | new_pc = pc + 4; |
| 326 | } |
| 327 | else if (psr_et) |
| 328 | { |
| 329 | /* Halt if PSR.S is set. See chapter 6 of the LSI. */ |
| 330 | if (psr_s) |
| 331 | { |
| 332 | SIM_DESC sd = CPU_STATE (current_cpu); |
| 333 | sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGTRAP); |
| 334 | } |
| 335 | |
| 336 | frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION); |
| 337 | new_pc = pc + 4; |
| 338 | } |
| 339 | else if (! CPU_DEBUG_STATE (current_cpu) && debug_field == 0) |
| 340 | { |
| 341 | USI psr = GET_PSR (); |
| 342 | /* Return from normal running state. */ |
| 343 | new_pc = GET_H_SPR (H_SPR_PCSR); |
| 344 | SET_PSR_ET (psr, 1); |
| 345 | SET_PSR_S (psr, GET_PSR_PS (psr)); |
| 346 | sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, H_SPR_PSR, psr); |
| 347 | } |
| 348 | else if (CPU_DEBUG_STATE (current_cpu) && debug_field == 1) |
| 349 | { |
| 350 | USI psr = GET_PSR (); |
| 351 | /* Return from debug state. */ |
| 352 | new_pc = GET_H_SPR (H_SPR_BPCSR); |
| 353 | SET_PSR_ET (psr, GET_H_BPSR_BET ()); |
| 354 | SET_PSR_S (psr, GET_H_BPSR_BS ()); |
| 355 | sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, H_SPR_PSR, psr); |
| 356 | CPU_DEBUG_STATE (current_cpu) = 0; |
| 357 | } |
| 358 | else |
| 359 | new_pc = pc + 4; |
| 360 | |
| 361 | return new_pc; |
| 362 | } |
| 363 | \f |
| 364 | /* Functions for handling non-excepting instruction side effects. */ |
| 365 | static SI next_available_nesr (SIM_CPU *current_cpu, SI current_index) |
| 366 | { |
| 367 | FRV_REGISTER_CONTROL *control = CPU_REGISTER_CONTROL (current_cpu); |
| 368 | if (control->spr[H_SPR_NECR].implemented) |
| 369 | { |
| 370 | int limit; |
| 371 | USI necr = GET_NECR (); |
| 372 | |
| 373 | /* See if any NESRs are implemented. First need to check the validity of |
| 374 | the NECR. */ |
| 375 | if (! GET_NECR_VALID (necr)) |
| 376 | return NO_NESR; |
| 377 | |
| 378 | limit = GET_NECR_NEN (necr); |
| 379 | for (++current_index; current_index < limit; ++current_index) |
| 380 | { |
| 381 | SI nesr = GET_NESR (current_index); |
| 382 | if (! GET_NESR_VALID (nesr)) |
| 383 | return current_index; |
| 384 | } |
| 385 | } |
| 386 | return NO_NESR; |
| 387 | } |
| 388 | |
| 389 | static SI next_valid_nesr (SIM_CPU *current_cpu, SI current_index) |
| 390 | { |
| 391 | FRV_REGISTER_CONTROL *control = CPU_REGISTER_CONTROL (current_cpu); |
| 392 | if (control->spr[H_SPR_NECR].implemented) |
| 393 | { |
| 394 | int limit; |
| 395 | USI necr = GET_NECR (); |
| 396 | |
| 397 | /* See if any NESRs are implemented. First need to check the validity of |
| 398 | the NECR. */ |
| 399 | if (! GET_NECR_VALID (necr)) |
| 400 | return NO_NESR; |
| 401 | |
| 402 | limit = GET_NECR_NEN (necr); |
| 403 | for (++current_index; current_index < limit; ++current_index) |
| 404 | { |
| 405 | SI nesr = GET_NESR (current_index); |
| 406 | if (GET_NESR_VALID (nesr)) |
| 407 | return current_index; |
| 408 | } |
| 409 | } |
| 410 | return NO_NESR; |
| 411 | } |
| 412 | |
| 413 | BI |
| 414 | frvbf_check_non_excepting_load ( |
| 415 | SIM_CPU *current_cpu, SI base_index, SI disp_index, SI target_index, |
| 416 | SI immediate_disp, QI data_size, BI is_float |
| 417 | ) |
| 418 | { |
| 419 | BI rc = 1; /* perform the load. */ |
| 420 | SIM_DESC sd = CPU_STATE (current_cpu); |
| 421 | int daec = 0; |
| 422 | int rec = 0; |
| 423 | int ec = 0; |
| 424 | USI necr; |
| 425 | int do_elos; |
| 426 | SI NE_flags[2]; |
| 427 | SI NE_base; |
| 428 | SI nesr; |
| 429 | SI ne_index; |
| 430 | FRV_REGISTER_CONTROL *control; |
| 431 | |
| 432 | SI address = GET_H_GR (base_index); |
| 433 | if (disp_index >= 0) |
| 434 | address += GET_H_GR (disp_index); |
| 435 | else |
| 436 | address += immediate_disp; |
| 437 | |
| 438 | /* Check for interrupt factors. */ |
| 439 | switch (data_size) |
| 440 | { |
| 441 | case NESR_UQI_SIZE: |
| 442 | case NESR_QI_SIZE: |
| 443 | break; |
| 444 | case NESR_UHI_SIZE: |
| 445 | case NESR_HI_SIZE: |
| 446 | if (address & 1) |
| 447 | ec = 1; |
| 448 | break; |
| 449 | case NESR_SI_SIZE: |
| 450 | if (address & 3) |
| 451 | ec = 1; |
| 452 | break; |
| 453 | case NESR_DI_SIZE: |
| 454 | if (address & 7) |
| 455 | ec = 1; |
| 456 | if (target_index & 1) |
| 457 | rec = 1; |
| 458 | break; |
| 459 | case NESR_XI_SIZE: |
| 460 | if (address & 0xf) |
| 461 | ec = 1; |
| 462 | if (target_index & 3) |
| 463 | rec = 1; |
| 464 | break; |
| 465 | default: |
| 466 | { |
| 467 | IADDR pc = GET_H_PC (); |
| 468 | sim_engine_abort (sd, current_cpu, pc, |
| 469 | "check_non_excepting_load: Incorrect data_size\n"); |
| 470 | break; |
| 471 | } |
| 472 | } |
| 473 | |
| 474 | control = CPU_REGISTER_CONTROL (current_cpu); |
| 475 | if (control->spr[H_SPR_NECR].implemented) |
| 476 | { |
| 477 | necr = GET_NECR (); |
| 478 | do_elos = GET_NECR_VALID (necr) && GET_NECR_ELOS (necr); |
| 479 | } |
| 480 | else |
| 481 | do_elos = 0; |
| 482 | |
| 483 | /* NECR, NESR, NEEAR are only implemented for the full frv machine. */ |
| 484 | if (do_elos) |
| 485 | { |
| 486 | ne_index = next_available_nesr (current_cpu, NO_NESR); |
| 487 | if (ne_index == NO_NESR) |
| 488 | { |
| 489 | IADDR pc = GET_H_PC (); |
| 490 | sim_engine_abort (sd, current_cpu, pc, |
| 491 | "No available NESR register\n"); |
| 492 | } |
| 493 | |
| 494 | /* Fill in the basic fields of the NESR. */ |
| 495 | nesr = GET_NESR (ne_index); |
| 496 | SET_NESR_VALID (nesr); |
| 497 | SET_NESR_EAV (nesr); |
| 498 | SET_NESR_DRN (nesr, target_index); |
| 499 | SET_NESR_SIZE (nesr, data_size); |
| 500 | SET_NESR_NEAN (nesr, ne_index); |
| 501 | if (is_float) |
| 502 | SET_NESR_FR (nesr); |
| 503 | else |
| 504 | CLEAR_NESR_FR (nesr); |
| 505 | |
| 506 | /* Set the corresponding NEEAR. */ |
| 507 | SET_NEEAR (ne_index, address); |
| 508 | |
| 509 | SET_NESR_DAEC (nesr, 0); |
| 510 | SET_NESR_REC (nesr, 0); |
| 511 | SET_NESR_EC (nesr, 0); |
| 512 | } |
| 513 | |
| 514 | /* Set the NE flag corresponding to the target register if an interrupt |
| 515 | factor was detected. |
| 516 | daec is not checked here yet, but is declared for future reference. */ |
| 517 | if (is_float) |
| 518 | NE_base = H_SPR_FNER0; |
| 519 | else |
| 520 | NE_base = H_SPR_GNER0; |
| 521 | |
| 522 | GET_NE_FLAGS (NE_flags, NE_base); |
| 523 | if (rec) |
| 524 | { |
| 525 | SET_NE_FLAG (NE_flags, target_index); |
| 526 | if (do_elos) |
| 527 | SET_NESR_REC (nesr, NESR_REGISTER_NOT_ALIGNED); |
| 528 | } |
| 529 | |
| 530 | if (ec) |
| 531 | { |
| 532 | SET_NE_FLAG (NE_flags, target_index); |
| 533 | if (do_elos) |
| 534 | SET_NESR_EC (nesr, NESR_MEM_ADDRESS_NOT_ALIGNED); |
| 535 | } |
| 536 | |
| 537 | if (do_elos) |
| 538 | SET_NESR (ne_index, nesr); |
| 539 | |
| 540 | /* If no interrupt factor was detected then set the NE flag on the |
| 541 | target register if the NE flag on one of the input registers |
| 542 | is already set. */ |
| 543 | if (! rec && ! ec && ! daec) |
| 544 | { |
| 545 | BI ne_flag = GET_NE_FLAG (NE_flags, base_index); |
| 546 | if (disp_index >= 0) |
| 547 | ne_flag |= GET_NE_FLAG (NE_flags, disp_index); |
| 548 | if (ne_flag) |
| 549 | { |
| 550 | SET_NE_FLAG (NE_flags, target_index); |
| 551 | rc = 0; /* Do not perform the load. */ |
| 552 | } |
| 553 | else |
| 554 | CLEAR_NE_FLAG (NE_flags, target_index); |
| 555 | } |
| 556 | |
| 557 | SET_NE_FLAGS (NE_base, NE_flags); |
| 558 | |
| 559 | return rc; /* perform the load? */ |
| 560 | } |
| 561 | |
| 562 | /* Record state for media exception: media_cr_not_aligned. */ |
| 563 | void |
| 564 | frvbf_media_cr_not_aligned (SIM_CPU *current_cpu) |
| 565 | { |
| 566 | SIM_DESC sd = CPU_STATE (current_cpu); |
| 567 | |
| 568 | /* On some machines this generates an illegal_instruction interrupt. */ |
| 569 | switch (STATE_ARCHITECTURE (sd)->mach) |
| 570 | { |
| 571 | /* Note: there is a discrepancy between V2.2 of the FR400 |
| 572 | instruction manual and the various FR4xx LSI specs. The former |
| 573 | claims that unaligned registers cause an mp_exception while the |
| 574 | latter say it's an illegal_instruction. The LSI specs appear |
| 575 | to be correct since MTT is fixed at 1. */ |
| 576 | case bfd_mach_fr400: |
| 577 | case bfd_mach_fr450: |
| 578 | case bfd_mach_fr550: |
| 579 | frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION); |
| 580 | break; |
| 581 | default: |
| 582 | frv_set_mp_exception_registers (current_cpu, MTT_CR_NOT_ALIGNED, 0); |
| 583 | break; |
| 584 | } |
| 585 | } |
| 586 | |
| 587 | /* Record state for media exception: media_acc_not_aligned. */ |
| 588 | void |
| 589 | frvbf_media_acc_not_aligned (SIM_CPU *current_cpu) |
| 590 | { |
| 591 | SIM_DESC sd = CPU_STATE (current_cpu); |
| 592 | |
| 593 | /* On some machines this generates an illegal_instruction interrupt. */ |
| 594 | switch (STATE_ARCHITECTURE (sd)->mach) |
| 595 | { |
| 596 | /* See comment in frvbf_cr_not_aligned(). */ |
| 597 | case bfd_mach_fr400: |
| 598 | case bfd_mach_fr450: |
| 599 | case bfd_mach_fr550: |
| 600 | frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION); |
| 601 | break; |
| 602 | default: |
| 603 | frv_set_mp_exception_registers (current_cpu, MTT_ACC_NOT_ALIGNED, 0); |
| 604 | break; |
| 605 | } |
| 606 | } |
| 607 | |
| 608 | /* Record state for media exception: media_register_not_aligned. */ |
| 609 | void |
| 610 | frvbf_media_register_not_aligned (SIM_CPU *current_cpu) |
| 611 | { |
| 612 | SIM_DESC sd = CPU_STATE (current_cpu); |
| 613 | |
| 614 | /* On some machines this generates an illegal_instruction interrupt. */ |
| 615 | switch (STATE_ARCHITECTURE (sd)->mach) |
| 616 | { |
| 617 | /* See comment in frvbf_cr_not_aligned(). */ |
| 618 | case bfd_mach_fr400: |
| 619 | case bfd_mach_fr450: |
| 620 | case bfd_mach_fr550: |
| 621 | frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION); |
| 622 | break; |
| 623 | default: |
| 624 | frv_set_mp_exception_registers (current_cpu, MTT_INVALID_FR, 0); |
| 625 | break; |
| 626 | } |
| 627 | } |
| 628 | |
| 629 | /* Record state for media exception: media_overflow. */ |
| 630 | void |
| 631 | frvbf_media_overflow (SIM_CPU *current_cpu, int sie) |
| 632 | { |
| 633 | frv_set_mp_exception_registers (current_cpu, MTT_OVERFLOW, sie); |
| 634 | } |
| 635 | |
| 636 | /* Queue a division exception. */ |
| 637 | enum frv_dtt |
| 638 | frvbf_division_exception (SIM_CPU *current_cpu, enum frv_dtt dtt, |
| 639 | int target_index, int non_excepting) |
| 640 | { |
| 641 | /* If there was an overflow and it is masked, then record it in |
| 642 | ISR.AEXC. */ |
| 643 | USI isr = GET_ISR (); |
| 644 | if ((dtt & FRV_DTT_OVERFLOW) && GET_ISR_EDE (isr)) |
| 645 | { |
| 646 | dtt &= ~FRV_DTT_OVERFLOW; |
| 647 | SET_ISR_AEXC (isr); |
| 648 | SET_ISR (isr); |
| 649 | } |
| 650 | if (dtt != FRV_DTT_NO_EXCEPTION) |
| 651 | { |
| 652 | if (non_excepting) |
| 653 | { |
| 654 | /* Non excepting instruction, simply set the NE flag for the target |
| 655 | register. */ |
| 656 | SI NE_flags[2]; |
| 657 | GET_NE_FLAGS (NE_flags, H_SPR_GNER0); |
| 658 | SET_NE_FLAG (NE_flags, target_index); |
| 659 | SET_NE_FLAGS (H_SPR_GNER0, NE_flags); |
| 660 | } |
| 661 | else |
| 662 | frv_queue_division_exception_interrupt (current_cpu, dtt); |
| 663 | } |
| 664 | return dtt; |
| 665 | } |
| 666 | |
| 667 | void |
| 668 | frvbf_check_recovering_store ( |
| 669 | SIM_CPU *current_cpu, PCADDR address, SI regno, int size, int is_float |
| 670 | ) |
| 671 | { |
| 672 | FRV_CACHE *cache = CPU_DATA_CACHE (current_cpu); |
| 673 | int reg_ix; |
| 674 | |
| 675 | CPU_RSTR_INVALIDATE(current_cpu) = 0; |
| 676 | |
| 677 | for (reg_ix = next_valid_nesr (current_cpu, NO_NESR); |
| 678 | reg_ix != NO_NESR; |
| 679 | reg_ix = next_valid_nesr (current_cpu, reg_ix)) |
| 680 | { |
| 681 | if (address == GET_H_SPR (H_SPR_NEEAR0 + reg_ix)) |
| 682 | { |
| 683 | SI nesr = GET_NESR (reg_ix); |
| 684 | int nesr_drn = GET_NESR_DRN (nesr); |
| 685 | BI nesr_fr = GET_NESR_FR (nesr); |
| 686 | SI remain; |
| 687 | |
| 688 | /* Invalidate cache block containing this address. |
| 689 | If we need to count cycles, then the cache operation will be |
| 690 | initiated from the model profiling functions. |
| 691 | See frvbf_model_.... */ |
| 692 | if (model_insn) |
| 693 | { |
| 694 | CPU_RSTR_INVALIDATE(current_cpu) = 1; |
| 695 | CPU_LOAD_ADDRESS (current_cpu) = address; |
| 696 | } |
| 697 | else |
| 698 | frv_cache_invalidate (cache, address, 1/* flush */); |
| 699 | |
| 700 | /* Copy the stored value to the register indicated by NESR.DRN. */ |
| 701 | for (remain = size; remain > 0; remain -= 4) |
| 702 | { |
| 703 | SI value; |
| 704 | |
| 705 | if (is_float) |
| 706 | value = GET_H_FR (regno); |
| 707 | else |
| 708 | value = GET_H_GR (regno); |
| 709 | |
| 710 | switch (size) |
| 711 | { |
| 712 | case 1: |
| 713 | value &= 0xff; |
| 714 | break; |
| 715 | case 2: |
| 716 | value &= 0xffff; |
| 717 | break; |
| 718 | default: |
| 719 | break; |
| 720 | } |
| 721 | |
| 722 | if (nesr_fr) |
| 723 | sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, nesr_drn, |
| 724 | value); |
| 725 | else |
| 726 | sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, nesr_drn, |
| 727 | value); |
| 728 | |
| 729 | nesr_drn++; |
| 730 | regno++; |
| 731 | } |
| 732 | break; /* Only consider the first matching register. */ |
| 733 | } |
| 734 | } /* loop over active neear registers. */ |
| 735 | } |
| 736 | |
| 737 | SI |
| 738 | frvbf_check_acc_range (SIM_CPU *current_cpu, SI regno) |
| 739 | { |
| 740 | /* Only applicable to fr550 */ |
| 741 | SIM_DESC sd = CPU_STATE (current_cpu); |
| 742 | if (STATE_ARCHITECTURE (sd)->mach != bfd_mach_fr550) |
| 743 | return; |
| 744 | |
| 745 | /* On the fr550, media insns in slots 0 and 2 can only access |
| 746 | accumulators acc0-acc3. Insns in slots 1 and 3 can only access |
| 747 | accumulators acc4-acc7 */ |
| 748 | switch (frv_current_fm_slot) |
| 749 | { |
| 750 | case UNIT_FM0: |
| 751 | case UNIT_FM2: |
| 752 | if (regno <= 3) |
| 753 | return 1; /* all is ok */ |
| 754 | break; |
| 755 | case UNIT_FM1: |
| 756 | case UNIT_FM3: |
| 757 | if (regno >= 4) |
| 758 | return 1; /* all is ok */ |
| 759 | break; |
| 760 | } |
| 761 | |
| 762 | /* The specified accumulator is out of range. Queue an illegal_instruction |
| 763 | interrupt. */ |
| 764 | frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION); |
| 765 | return 0; |
| 766 | } |
| 767 | |
| 768 | void |
| 769 | frvbf_check_swap_address (SIM_CPU *current_cpu, SI address) |
| 770 | { |
| 771 | /* Only applicable to fr550 */ |
| 772 | SIM_DESC sd = CPU_STATE (current_cpu); |
| 773 | if (STATE_ARCHITECTURE (sd)->mach != bfd_mach_fr550) |
| 774 | return; |
| 775 | |
| 776 | /* Adress must be aligned on a word boundary. */ |
| 777 | if (address & 0x3) |
| 778 | frv_queue_data_access_exception_interrupt (current_cpu); |
| 779 | } |
| 780 | |
| 781 | static void |
| 782 | clear_nesr_neear (SIM_CPU *current_cpu, SI target_index, BI is_float) |
| 783 | { |
| 784 | int reg_ix; |
| 785 | |
| 786 | /* Only implemented for full frv. */ |
| 787 | SIM_DESC sd = CPU_STATE (current_cpu); |
| 788 | if (STATE_ARCHITECTURE (sd)->mach != bfd_mach_frv) |
| 789 | return; |
| 790 | |
| 791 | /* Clear the appropriate NESR and NEEAR registers. */ |
| 792 | for (reg_ix = next_valid_nesr (current_cpu, NO_NESR); |
| 793 | reg_ix != NO_NESR; |
| 794 | reg_ix = next_valid_nesr (current_cpu, reg_ix)) |
| 795 | { |
| 796 | SI nesr; |
| 797 | /* The register is available, now check if it is active. */ |
| 798 | nesr = GET_NESR (reg_ix); |
| 799 | if (GET_NESR_FR (nesr) == is_float) |
| 800 | { |
| 801 | if (target_index < 0 || GET_NESR_DRN (nesr) == target_index) |
| 802 | { |
| 803 | SET_NESR (reg_ix, 0); |
| 804 | SET_NEEAR (reg_ix, 0); |
| 805 | } |
| 806 | } |
| 807 | } |
| 808 | } |
| 809 | |
| 810 | static void |
| 811 | clear_ne_flags ( |
| 812 | SIM_CPU *current_cpu, |
| 813 | SI target_index, |
| 814 | int hi_available, |
| 815 | int lo_available, |
| 816 | SI NE_base |
| 817 | ) |
| 818 | { |
| 819 | SI NE_flags[2]; |
| 820 | int exception; |
| 821 | |
| 822 | GET_NE_FLAGS (NE_flags, NE_base); |
| 823 | if (target_index >= 0) |
| 824 | CLEAR_NE_FLAG (NE_flags, target_index); |
| 825 | else |
| 826 | { |
| 827 | if (lo_available) |
| 828 | NE_flags[1] = 0; |
| 829 | if (hi_available) |
| 830 | NE_flags[0] = 0; |
| 831 | } |
| 832 | SET_NE_FLAGS (NE_base, NE_flags); |
| 833 | } |
| 834 | |
| 835 | /* Return 1 if the given register is available, 0 otherwise. TARGET_INDEX==-1 |
| 836 | means to check for any register available. */ |
| 837 | static void |
| 838 | which_registers_available ( |
| 839 | SIM_CPU *current_cpu, int *hi_available, int *lo_available, int is_float |
| 840 | ) |
| 841 | { |
| 842 | if (is_float) |
| 843 | frv_fr_registers_available (current_cpu, hi_available, lo_available); |
| 844 | else |
| 845 | frv_gr_registers_available (current_cpu, hi_available, lo_available); |
| 846 | } |
| 847 | |
| 848 | void |
| 849 | frvbf_clear_ne_flags (SIM_CPU *current_cpu, SI target_index, BI is_float) |
| 850 | { |
| 851 | int hi_available; |
| 852 | int lo_available; |
| 853 | int exception; |
| 854 | SI NE_base; |
| 855 | USI necr; |
| 856 | FRV_REGISTER_CONTROL *control; |
| 857 | |
| 858 | /* Check for availability of the target register(s). */ |
| 859 | which_registers_available (current_cpu, & hi_available, & lo_available, |
| 860 | is_float); |
| 861 | |
| 862 | /* Check to make sure that the target register is available. */ |
| 863 | if (! frv_check_register_access (current_cpu, target_index, |
| 864 | hi_available, lo_available)) |
| 865 | return; |
| 866 | |
| 867 | /* Determine whether we're working with GR or FR registers. */ |
| 868 | if (is_float) |
| 869 | NE_base = H_SPR_FNER0; |
| 870 | else |
| 871 | NE_base = H_SPR_GNER0; |
| 872 | |
| 873 | /* Always clear the appropriate NE flags. */ |
| 874 | clear_ne_flags (current_cpu, target_index, hi_available, lo_available, |
| 875 | NE_base); |
| 876 | |
| 877 | /* Clear the appropriate NESR and NEEAR registers. */ |
| 878 | control = CPU_REGISTER_CONTROL (current_cpu); |
| 879 | if (control->spr[H_SPR_NECR].implemented) |
| 880 | { |
| 881 | necr = GET_NECR (); |
| 882 | if (GET_NECR_VALID (necr) && GET_NECR_ELOS (necr)) |
| 883 | clear_nesr_neear (current_cpu, target_index, is_float); |
| 884 | } |
| 885 | } |
| 886 | |
| 887 | void |
| 888 | frvbf_commit (SIM_CPU *current_cpu, SI target_index, BI is_float) |
| 889 | { |
| 890 | SI NE_base; |
| 891 | SI NE_flags[2]; |
| 892 | BI NE_flag; |
| 893 | int exception; |
| 894 | int hi_available; |
| 895 | int lo_available; |
| 896 | USI necr; |
| 897 | FRV_REGISTER_CONTROL *control; |
| 898 | |
| 899 | /* Check for availability of the target register(s). */ |
| 900 | which_registers_available (current_cpu, & hi_available, & lo_available, |
| 901 | is_float); |
| 902 | |
| 903 | /* Check to make sure that the target register is available. */ |
| 904 | if (! frv_check_register_access (current_cpu, target_index, |
| 905 | hi_available, lo_available)) |
| 906 | return; |
| 907 | |
| 908 | /* Determine whether we're working with GR or FR registers. */ |
| 909 | if (is_float) |
| 910 | NE_base = H_SPR_FNER0; |
| 911 | else |
| 912 | NE_base = H_SPR_GNER0; |
| 913 | |
| 914 | /* Determine whether a ne exception is pending. */ |
| 915 | GET_NE_FLAGS (NE_flags, NE_base); |
| 916 | if (target_index >= 0) |
| 917 | NE_flag = GET_NE_FLAG (NE_flags, target_index); |
| 918 | else |
| 919 | { |
| 920 | NE_flag = |
| 921 | hi_available && NE_flags[0] != 0 || lo_available && NE_flags[1] != 0; |
| 922 | } |
| 923 | |
| 924 | /* Always clear the appropriate NE flags. */ |
| 925 | clear_ne_flags (current_cpu, target_index, hi_available, lo_available, |
| 926 | NE_base); |
| 927 | |
| 928 | control = CPU_REGISTER_CONTROL (current_cpu); |
| 929 | if (control->spr[H_SPR_NECR].implemented) |
| 930 | { |
| 931 | necr = GET_NECR (); |
| 932 | if (GET_NECR_VALID (necr) && GET_NECR_ELOS (necr) && NE_flag) |
| 933 | { |
| 934 | /* Clear the appropriate NESR and NEEAR registers. */ |
| 935 | clear_nesr_neear (current_cpu, target_index, is_float); |
| 936 | frv_queue_program_interrupt (current_cpu, FRV_COMMIT_EXCEPTION); |
| 937 | } |
| 938 | } |
| 939 | } |
| 940 | |
| 941 | /* Generate the appropriate fp_exception(s) based on the given status code. */ |
| 942 | void |
| 943 | frvbf_fpu_error (CGEN_FPU* fpu, int status) |
| 944 | { |
| 945 | struct frv_fp_exception_info fp_info = { |
| 946 | FSR_NO_EXCEPTION, FTT_IEEE_754_EXCEPTION |
| 947 | }; |
| 948 | |
| 949 | if (status & |
| 950 | (sim_fpu_status_invalid_snan | |
| 951 | sim_fpu_status_invalid_qnan | |
| 952 | sim_fpu_status_invalid_isi | |
| 953 | sim_fpu_status_invalid_idi | |
| 954 | sim_fpu_status_invalid_zdz | |
| 955 | sim_fpu_status_invalid_imz | |
| 956 | sim_fpu_status_invalid_cvi | |
| 957 | sim_fpu_status_invalid_cmp | |
| 958 | sim_fpu_status_invalid_sqrt)) |
| 959 | fp_info.fsr_mask |= FSR_INVALID_OPERATION; |
| 960 | |
| 961 | if (status & sim_fpu_status_invalid_div0) |
| 962 | fp_info.fsr_mask |= FSR_DIVISION_BY_ZERO; |
| 963 | |
| 964 | if (status & sim_fpu_status_inexact) |
| 965 | fp_info.fsr_mask |= FSR_INEXACT; |
| 966 | |
| 967 | if (status & sim_fpu_status_overflow) |
| 968 | fp_info.fsr_mask |= FSR_OVERFLOW; |
| 969 | |
| 970 | if (status & sim_fpu_status_underflow) |
| 971 | fp_info.fsr_mask |= FSR_UNDERFLOW; |
| 972 | |
| 973 | if (status & sim_fpu_status_denorm) |
| 974 | { |
| 975 | fp_info.fsr_mask |= FSR_DENORMAL_INPUT; |
| 976 | fp_info.ftt = FTT_DENORMAL_INPUT; |
| 977 | } |
| 978 | |
| 979 | if (fp_info.fsr_mask != FSR_NO_EXCEPTION) |
| 980 | { |
| 981 | SIM_CPU *current_cpu = (SIM_CPU *)fpu->owner; |
| 982 | frv_queue_fp_exception_interrupt (current_cpu, & fp_info); |
| 983 | } |
| 984 | } |