| 1 | /* CPU family header for iq2000bf. |
| 2 | |
| 3 | THIS FILE IS MACHINE GENERATED WITH CGEN. |
| 4 | |
| 5 | Copyright 1996-2015 Free Software Foundation, Inc. |
| 6 | |
| 7 | This file is part of the GNU simulators. |
| 8 | |
| 9 | This file is free software; you can redistribute it and/or modify |
| 10 | it under the terms of the GNU General Public License as published by |
| 11 | the Free Software Foundation; either version 3, or (at your option) |
| 12 | any later version. |
| 13 | |
| 14 | It is distributed in the hope that it will be useful, but WITHOUT |
| 15 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
| 16 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public |
| 17 | License for more details. |
| 18 | |
| 19 | You should have received a copy of the GNU General Public License along |
| 20 | with this program; if not, see <http://www.gnu.org/licenses/>. |
| 21 | |
| 22 | */ |
| 23 | |
| 24 | #ifndef CPU_IQ2000BF_H |
| 25 | #define CPU_IQ2000BF_H |
| 26 | |
| 27 | /* Maximum number of instructions that are fetched at a time. |
| 28 | This is for LIW type instructions sets (e.g. m32r). */ |
| 29 | #define MAX_LIW_INSNS 1 |
| 30 | |
| 31 | /* Maximum number of instructions that can be executed in parallel. */ |
| 32 | #define MAX_PARALLEL_INSNS 1 |
| 33 | |
| 34 | /* The size of an "int" needed to hold an instruction word. |
| 35 | This is usually 32 bits, but some architectures needs 64 bits. */ |
| 36 | typedef CGEN_INSN_INT CGEN_INSN_WORD; |
| 37 | |
| 38 | #include "cgen-engine.h" |
| 39 | |
| 40 | /* CPU state information. */ |
| 41 | typedef struct { |
| 42 | /* Hardware elements. */ |
| 43 | struct { |
| 44 | /* program counter */ |
| 45 | USI h_pc; |
| 46 | #define GET_H_PC() get_h_pc (current_cpu) |
| 47 | #define SET_H_PC(x) \ |
| 48 | do { \ |
| 49 | set_h_pc (current_cpu, (x));\ |
| 50 | ;} while (0) |
| 51 | /* General purpose registers */ |
| 52 | SI h_gr[32]; |
| 53 | #define GET_H_GR(index) (((index) == (0))) ? (0) : (CPU (h_gr[index])) |
| 54 | #define SET_H_GR(index, x) \ |
| 55 | do { \ |
| 56 | if ((((index)) == (0))) {\ |
| 57 | ((void) 0); /*nop*/\ |
| 58 | }\ |
| 59 | else {\ |
| 60 | CPU (h_gr[(index)]) = (x);\ |
| 61 | }\ |
| 62 | ;} while (0) |
| 63 | } hardware; |
| 64 | #define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware) |
| 65 | } IQ2000BF_CPU_DATA; |
| 66 | |
| 67 | /* Cover fns for register access. */ |
| 68 | USI iq2000bf_h_pc_get (SIM_CPU *); |
| 69 | void iq2000bf_h_pc_set (SIM_CPU *, USI); |
| 70 | SI iq2000bf_h_gr_get (SIM_CPU *, UINT); |
| 71 | void iq2000bf_h_gr_set (SIM_CPU *, UINT, SI); |
| 72 | |
| 73 | /* These must be hand-written. */ |
| 74 | extern CPUREG_FETCH_FN iq2000bf_fetch_register; |
| 75 | extern CPUREG_STORE_FN iq2000bf_store_register; |
| 76 | |
| 77 | typedef struct { |
| 78 | int empty; |
| 79 | } MODEL_IQ2000_DATA; |
| 80 | |
| 81 | /* Instruction argument buffer. */ |
| 82 | |
| 83 | union sem_fields { |
| 84 | struct { /* no operands */ |
| 85 | int empty; |
| 86 | } sfmt_empty; |
| 87 | struct { /* */ |
| 88 | IADDR i_jmptarg; |
| 89 | } sfmt_j; |
| 90 | struct { /* */ |
| 91 | IADDR i_offset; |
| 92 | UINT f_rs; |
| 93 | UINT f_rt; |
| 94 | } sfmt_bbi; |
| 95 | struct { /* */ |
| 96 | UINT f_imm; |
| 97 | UINT f_rs; |
| 98 | UINT f_rt; |
| 99 | } sfmt_addi; |
| 100 | struct { /* */ |
| 101 | UINT f_mask; |
| 102 | UINT f_rd; |
| 103 | UINT f_rs; |
| 104 | UINT f_rt; |
| 105 | } sfmt_mrgb; |
| 106 | struct { /* */ |
| 107 | UINT f_maskl; |
| 108 | UINT f_rd; |
| 109 | UINT f_rs; |
| 110 | UINT f_rt; |
| 111 | UINT f_shamt; |
| 112 | } sfmt_ram; |
| 113 | #if WITH_SCACHE_PBB |
| 114 | /* Writeback handler. */ |
| 115 | struct { |
| 116 | /* Pointer to argbuf entry for insn whose results need writing back. */ |
| 117 | const struct argbuf *abuf; |
| 118 | } write; |
| 119 | /* x-before handler */ |
| 120 | struct { |
| 121 | /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/ |
| 122 | int first_p; |
| 123 | } before; |
| 124 | /* x-after handler */ |
| 125 | struct { |
| 126 | int empty; |
| 127 | } after; |
| 128 | /* This entry is used to terminate each pbb. */ |
| 129 | struct { |
| 130 | /* Number of insns in pbb. */ |
| 131 | int insn_count; |
| 132 | /* Next pbb to execute. */ |
| 133 | SCACHE *next; |
| 134 | SCACHE *branch_target; |
| 135 | } chain; |
| 136 | #endif |
| 137 | }; |
| 138 | |
| 139 | /* The ARGBUF struct. */ |
| 140 | struct argbuf { |
| 141 | /* These are the baseclass definitions. */ |
| 142 | IADDR addr; |
| 143 | const IDESC *idesc; |
| 144 | char trace_p; |
| 145 | char profile_p; |
| 146 | /* ??? Temporary hack for skip insns. */ |
| 147 | char skip_count; |
| 148 | char unused; |
| 149 | /* cpu specific data follows */ |
| 150 | union sem semantic; |
| 151 | int written; |
| 152 | union sem_fields fields; |
| 153 | }; |
| 154 | |
| 155 | /* A cached insn. |
| 156 | |
| 157 | ??? SCACHE used to contain more than just argbuf. We could delete the |
| 158 | type entirely and always just use ARGBUF, but for future concerns and as |
| 159 | a level of abstraction it is left in. */ |
| 160 | |
| 161 | struct scache { |
| 162 | struct argbuf argbuf; |
| 163 | }; |
| 164 | |
| 165 | /* Macros to simplify extraction, reading and semantic code. |
| 166 | These define and assign the local vars that contain the insn's fields. */ |
| 167 | |
| 168 | #define EXTRACT_IFMT_EMPTY_VARS \ |
| 169 | unsigned int length; |
| 170 | #define EXTRACT_IFMT_EMPTY_CODE \ |
| 171 | length = 0; \ |
| 172 | |
| 173 | #define EXTRACT_IFMT_ADD_VARS \ |
| 174 | UINT f_opcode; \ |
| 175 | UINT f_rs; \ |
| 176 | UINT f_rt; \ |
| 177 | UINT f_rd; \ |
| 178 | UINT f_shamt; \ |
| 179 | UINT f_func; \ |
| 180 | unsigned int length; |
| 181 | #define EXTRACT_IFMT_ADD_CODE \ |
| 182 | length = 4; \ |
| 183 | f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ |
| 184 | f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ |
| 185 | f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ |
| 186 | f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \ |
| 187 | f_shamt = EXTRACT_LSB0_UINT (insn, 32, 10, 5); \ |
| 188 | f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ |
| 189 | |
| 190 | #define EXTRACT_IFMT_ADDI_VARS \ |
| 191 | UINT f_opcode; \ |
| 192 | UINT f_rs; \ |
| 193 | UINT f_rt; \ |
| 194 | UINT f_imm; \ |
| 195 | unsigned int length; |
| 196 | #define EXTRACT_IFMT_ADDI_CODE \ |
| 197 | length = 4; \ |
| 198 | f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ |
| 199 | f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ |
| 200 | f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ |
| 201 | f_imm = EXTRACT_LSB0_UINT (insn, 32, 15, 16); \ |
| 202 | |
| 203 | #define EXTRACT_IFMT_RAM_VARS \ |
| 204 | UINT f_opcode; \ |
| 205 | UINT f_rs; \ |
| 206 | UINT f_rt; \ |
| 207 | UINT f_rd; \ |
| 208 | UINT f_shamt; \ |
| 209 | UINT f_5; \ |
| 210 | UINT f_maskl; \ |
| 211 | unsigned int length; |
| 212 | #define EXTRACT_IFMT_RAM_CODE \ |
| 213 | length = 4; \ |
| 214 | f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ |
| 215 | f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ |
| 216 | f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ |
| 217 | f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \ |
| 218 | f_shamt = EXTRACT_LSB0_UINT (insn, 32, 10, 5); \ |
| 219 | f_5 = EXTRACT_LSB0_UINT (insn, 32, 5, 1); \ |
| 220 | f_maskl = EXTRACT_LSB0_UINT (insn, 32, 4, 5); \ |
| 221 | |
| 222 | #define EXTRACT_IFMT_SLL_VARS \ |
| 223 | UINT f_opcode; \ |
| 224 | UINT f_rs; \ |
| 225 | UINT f_rt; \ |
| 226 | UINT f_rd; \ |
| 227 | UINT f_shamt; \ |
| 228 | UINT f_func; \ |
| 229 | unsigned int length; |
| 230 | #define EXTRACT_IFMT_SLL_CODE \ |
| 231 | length = 4; \ |
| 232 | f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ |
| 233 | f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ |
| 234 | f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ |
| 235 | f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \ |
| 236 | f_shamt = EXTRACT_LSB0_UINT (insn, 32, 10, 5); \ |
| 237 | f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ |
| 238 | |
| 239 | #define EXTRACT_IFMT_SLMV_VARS \ |
| 240 | UINT f_opcode; \ |
| 241 | UINT f_rs; \ |
| 242 | UINT f_rt; \ |
| 243 | UINT f_rd; \ |
| 244 | UINT f_shamt; \ |
| 245 | UINT f_func; \ |
| 246 | unsigned int length; |
| 247 | #define EXTRACT_IFMT_SLMV_CODE \ |
| 248 | length = 4; \ |
| 249 | f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ |
| 250 | f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ |
| 251 | f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ |
| 252 | f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \ |
| 253 | f_shamt = EXTRACT_LSB0_UINT (insn, 32, 10, 5); \ |
| 254 | f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ |
| 255 | |
| 256 | #define EXTRACT_IFMT_SLTI_VARS \ |
| 257 | UINT f_opcode; \ |
| 258 | UINT f_rs; \ |
| 259 | UINT f_rt; \ |
| 260 | UINT f_imm; \ |
| 261 | unsigned int length; |
| 262 | #define EXTRACT_IFMT_SLTI_CODE \ |
| 263 | length = 4; \ |
| 264 | f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ |
| 265 | f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ |
| 266 | f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ |
| 267 | f_imm = EXTRACT_LSB0_UINT (insn, 32, 15, 16); \ |
| 268 | |
| 269 | #define EXTRACT_IFMT_BBI_VARS \ |
| 270 | UINT f_opcode; \ |
| 271 | UINT f_rs; \ |
| 272 | UINT f_rt; \ |
| 273 | SI f_offset; \ |
| 274 | unsigned int length; |
| 275 | #define EXTRACT_IFMT_BBI_CODE \ |
| 276 | length = 4; \ |
| 277 | f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ |
| 278 | f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ |
| 279 | f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ |
| 280 | f_offset = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) << (2))) + (((pc) + (4)))); \ |
| 281 | |
| 282 | #define EXTRACT_IFMT_BBV_VARS \ |
| 283 | UINT f_opcode; \ |
| 284 | UINT f_rs; \ |
| 285 | UINT f_rt; \ |
| 286 | SI f_offset; \ |
| 287 | unsigned int length; |
| 288 | #define EXTRACT_IFMT_BBV_CODE \ |
| 289 | length = 4; \ |
| 290 | f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ |
| 291 | f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ |
| 292 | f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ |
| 293 | f_offset = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) << (2))) + (((pc) + (4)))); \ |
| 294 | |
| 295 | #define EXTRACT_IFMT_BGEZ_VARS \ |
| 296 | UINT f_opcode; \ |
| 297 | UINT f_rs; \ |
| 298 | UINT f_rt; \ |
| 299 | SI f_offset; \ |
| 300 | unsigned int length; |
| 301 | #define EXTRACT_IFMT_BGEZ_CODE \ |
| 302 | length = 4; \ |
| 303 | f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ |
| 304 | f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ |
| 305 | f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ |
| 306 | f_offset = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) << (2))) + (((pc) + (4)))); \ |
| 307 | |
| 308 | #define EXTRACT_IFMT_JALR_VARS \ |
| 309 | UINT f_opcode; \ |
| 310 | UINT f_rs; \ |
| 311 | UINT f_rt; \ |
| 312 | UINT f_rd; \ |
| 313 | UINT f_shamt; \ |
| 314 | UINT f_func; \ |
| 315 | unsigned int length; |
| 316 | #define EXTRACT_IFMT_JALR_CODE \ |
| 317 | length = 4; \ |
| 318 | f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ |
| 319 | f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ |
| 320 | f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ |
| 321 | f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \ |
| 322 | f_shamt = EXTRACT_LSB0_UINT (insn, 32, 10, 5); \ |
| 323 | f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ |
| 324 | |
| 325 | #define EXTRACT_IFMT_JR_VARS \ |
| 326 | UINT f_opcode; \ |
| 327 | UINT f_rs; \ |
| 328 | UINT f_rt; \ |
| 329 | UINT f_rd; \ |
| 330 | UINT f_shamt; \ |
| 331 | UINT f_func; \ |
| 332 | unsigned int length; |
| 333 | #define EXTRACT_IFMT_JR_CODE \ |
| 334 | length = 4; \ |
| 335 | f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ |
| 336 | f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ |
| 337 | f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ |
| 338 | f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \ |
| 339 | f_shamt = EXTRACT_LSB0_UINT (insn, 32, 10, 5); \ |
| 340 | f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ |
| 341 | |
| 342 | #define EXTRACT_IFMT_LB_VARS \ |
| 343 | UINT f_opcode; \ |
| 344 | UINT f_rs; \ |
| 345 | UINT f_rt; \ |
| 346 | UINT f_imm; \ |
| 347 | unsigned int length; |
| 348 | #define EXTRACT_IFMT_LB_CODE \ |
| 349 | length = 4; \ |
| 350 | f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ |
| 351 | f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ |
| 352 | f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ |
| 353 | f_imm = EXTRACT_LSB0_UINT (insn, 32, 15, 16); \ |
| 354 | |
| 355 | #define EXTRACT_IFMT_LUI_VARS \ |
| 356 | UINT f_opcode; \ |
| 357 | UINT f_rs; \ |
| 358 | UINT f_rt; \ |
| 359 | UINT f_imm; \ |
| 360 | unsigned int length; |
| 361 | #define EXTRACT_IFMT_LUI_CODE \ |
| 362 | length = 4; \ |
| 363 | f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ |
| 364 | f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ |
| 365 | f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ |
| 366 | f_imm = EXTRACT_LSB0_UINT (insn, 32, 15, 16); \ |
| 367 | |
| 368 | #define EXTRACT_IFMT_BREAK_VARS \ |
| 369 | UINT f_opcode; \ |
| 370 | UINT f_rs; \ |
| 371 | UINT f_rt; \ |
| 372 | UINT f_rd; \ |
| 373 | UINT f_shamt; \ |
| 374 | UINT f_func; \ |
| 375 | unsigned int length; |
| 376 | #define EXTRACT_IFMT_BREAK_CODE \ |
| 377 | length = 4; \ |
| 378 | f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ |
| 379 | f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ |
| 380 | f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ |
| 381 | f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \ |
| 382 | f_shamt = EXTRACT_LSB0_UINT (insn, 32, 10, 5); \ |
| 383 | f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ |
| 384 | |
| 385 | #define EXTRACT_IFMT_SYSCALL_VARS \ |
| 386 | UINT f_opcode; \ |
| 387 | UINT f_excode; \ |
| 388 | UINT f_func; \ |
| 389 | unsigned int length; |
| 390 | #define EXTRACT_IFMT_SYSCALL_CODE \ |
| 391 | length = 4; \ |
| 392 | f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ |
| 393 | f_excode = EXTRACT_LSB0_UINT (insn, 32, 25, 20); \ |
| 394 | f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ |
| 395 | |
| 396 | #define EXTRACT_IFMT_ANDOUI_VARS \ |
| 397 | UINT f_opcode; \ |
| 398 | UINT f_rs; \ |
| 399 | UINT f_rt; \ |
| 400 | UINT f_imm; \ |
| 401 | unsigned int length; |
| 402 | #define EXTRACT_IFMT_ANDOUI_CODE \ |
| 403 | length = 4; \ |
| 404 | f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ |
| 405 | f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ |
| 406 | f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ |
| 407 | f_imm = EXTRACT_LSB0_UINT (insn, 32, 15, 16); \ |
| 408 | |
| 409 | #define EXTRACT_IFMT_MRGB_VARS \ |
| 410 | UINT f_opcode; \ |
| 411 | UINT f_rs; \ |
| 412 | UINT f_rt; \ |
| 413 | UINT f_rd; \ |
| 414 | UINT f_10; \ |
| 415 | UINT f_mask; \ |
| 416 | UINT f_func; \ |
| 417 | unsigned int length; |
| 418 | #define EXTRACT_IFMT_MRGB_CODE \ |
| 419 | length = 4; \ |
| 420 | f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ |
| 421 | f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ |
| 422 | f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ |
| 423 | f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \ |
| 424 | f_10 = EXTRACT_LSB0_UINT (insn, 32, 10, 1); \ |
| 425 | f_mask = EXTRACT_LSB0_UINT (insn, 32, 9, 4); \ |
| 426 | f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ |
| 427 | |
| 428 | #define EXTRACT_IFMT_BC0F_VARS \ |
| 429 | UINT f_opcode; \ |
| 430 | UINT f_rs; \ |
| 431 | UINT f_rt; \ |
| 432 | SI f_offset; \ |
| 433 | unsigned int length; |
| 434 | #define EXTRACT_IFMT_BC0F_CODE \ |
| 435 | length = 4; \ |
| 436 | f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ |
| 437 | f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ |
| 438 | f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ |
| 439 | f_offset = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) << (2))) + (((pc) + (4)))); \ |
| 440 | |
| 441 | #define EXTRACT_IFMT_CFC0_VARS \ |
| 442 | UINT f_opcode; \ |
| 443 | UINT f_rs; \ |
| 444 | UINT f_rt; \ |
| 445 | UINT f_rd; \ |
| 446 | UINT f_10_11; \ |
| 447 | unsigned int length; |
| 448 | #define EXTRACT_IFMT_CFC0_CODE \ |
| 449 | length = 4; \ |
| 450 | f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ |
| 451 | f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ |
| 452 | f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ |
| 453 | f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \ |
| 454 | f_10_11 = EXTRACT_LSB0_UINT (insn, 32, 10, 11); \ |
| 455 | |
| 456 | #define EXTRACT_IFMT_CHKHDR_VARS \ |
| 457 | UINT f_opcode; \ |
| 458 | UINT f_rs; \ |
| 459 | UINT f_rt; \ |
| 460 | UINT f_rd; \ |
| 461 | UINT f_shamt; \ |
| 462 | UINT f_func; \ |
| 463 | unsigned int length; |
| 464 | #define EXTRACT_IFMT_CHKHDR_CODE \ |
| 465 | length = 4; \ |
| 466 | f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ |
| 467 | f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ |
| 468 | f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ |
| 469 | f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \ |
| 470 | f_shamt = EXTRACT_LSB0_UINT (insn, 32, 10, 5); \ |
| 471 | f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ |
| 472 | |
| 473 | #define EXTRACT_IFMT_LULCK_VARS \ |
| 474 | UINT f_opcode; \ |
| 475 | UINT f_rs; \ |
| 476 | UINT f_rt; \ |
| 477 | UINT f_rd; \ |
| 478 | UINT f_shamt; \ |
| 479 | UINT f_func; \ |
| 480 | unsigned int length; |
| 481 | #define EXTRACT_IFMT_LULCK_CODE \ |
| 482 | length = 4; \ |
| 483 | f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ |
| 484 | f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ |
| 485 | f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ |
| 486 | f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \ |
| 487 | f_shamt = EXTRACT_LSB0_UINT (insn, 32, 10, 5); \ |
| 488 | f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ |
| 489 | |
| 490 | #define EXTRACT_IFMT_PKRLR1_VARS \ |
| 491 | UINT f_opcode; \ |
| 492 | UINT f_rs; \ |
| 493 | UINT f_rt; \ |
| 494 | UINT f_count; \ |
| 495 | UINT f_index; \ |
| 496 | unsigned int length; |
| 497 | #define EXTRACT_IFMT_PKRLR1_CODE \ |
| 498 | length = 4; \ |
| 499 | f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ |
| 500 | f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ |
| 501 | f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ |
| 502 | f_count = EXTRACT_LSB0_UINT (insn, 32, 15, 7); \ |
| 503 | f_index = EXTRACT_LSB0_UINT (insn, 32, 8, 9); \ |
| 504 | |
| 505 | #define EXTRACT_IFMT_RFE_VARS \ |
| 506 | UINT f_opcode; \ |
| 507 | UINT f_25; \ |
| 508 | UINT f_24_19; \ |
| 509 | UINT f_func; \ |
| 510 | unsigned int length; |
| 511 | #define EXTRACT_IFMT_RFE_CODE \ |
| 512 | length = 4; \ |
| 513 | f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ |
| 514 | f_25 = EXTRACT_LSB0_UINT (insn, 32, 25, 1); \ |
| 515 | f_24_19 = EXTRACT_LSB0_UINT (insn, 32, 24, 19); \ |
| 516 | f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ |
| 517 | |
| 518 | #define EXTRACT_IFMT_J_VARS \ |
| 519 | UINT f_opcode; \ |
| 520 | UINT f_rsrvd; \ |
| 521 | USI f_jtarg; \ |
| 522 | unsigned int length; |
| 523 | #define EXTRACT_IFMT_J_CODE \ |
| 524 | length = 4; \ |
| 525 | f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ |
| 526 | f_rsrvd = EXTRACT_LSB0_UINT (insn, 32, 25, 10); \ |
| 527 | f_jtarg = ((((pc) & (0xf0000000))) | (((EXTRACT_LSB0_UINT (insn, 32, 15, 16)) << (2)))); \ |
| 528 | |
| 529 | /* Collection of various things for the trace handler to use. */ |
| 530 | |
| 531 | typedef struct trace_record { |
| 532 | IADDR pc; |
| 533 | /* FIXME:wip */ |
| 534 | } TRACE_RECORD; |
| 535 | |
| 536 | #endif /* CPU_IQ2000BF_H */ |