| 1 | /* gdb.c --- sim interface to GDB. |
| 2 | |
| 3 | Copyright (C) 2005, 2007 Free Software Foundation, Inc. |
| 4 | Contributed by Red Hat, Inc. |
| 5 | |
| 6 | This file is part of the GNU simulators. |
| 7 | |
| 8 | The GNU simulators are free software; you can redistribute them and/or |
| 9 | modify them under the terms of the GNU General Public License as |
| 10 | published by the Free Software Foundation; either version 2 of the |
| 11 | License, or (at your option) any later version. |
| 12 | |
| 13 | The GNU simulators are distributed in the hope that they will be |
| 14 | useful, but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 16 | General Public License for more details. |
| 17 | |
| 18 | You should have received a copy of the GNU General Public License |
| 19 | along with the GNU simulators; if not, write to the Free Software |
| 20 | Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
| 21 | 02110-1301, USA */ |
| 22 | |
| 23 | |
| 24 | #include <stdio.h> |
| 25 | #include <assert.h> |
| 26 | #include <signal.h> |
| 27 | #include <string.h> |
| 28 | #include <ctype.h> |
| 29 | |
| 30 | #include "ansidecl.h" |
| 31 | #include "gdb/callback.h" |
| 32 | #include "gdb/remote-sim.h" |
| 33 | #include "gdb/signals.h" |
| 34 | #include "gdb/sim-m32c.h" |
| 35 | |
| 36 | #include "cpu.h" |
| 37 | #include "mem.h" |
| 38 | #include "load.h" |
| 39 | #include "syscalls.h" |
| 40 | |
| 41 | /* I don't want to wrap up all the minisim's data structures in an |
| 42 | object and pass that around. That'd be a big change, and neither |
| 43 | GDB nor run needs that ability. |
| 44 | |
| 45 | So we just have one instance, that lives in global variables, and |
| 46 | each time we open it, we re-initialize it. */ |
| 47 | struct sim_state |
| 48 | { |
| 49 | const char *message; |
| 50 | }; |
| 51 | |
| 52 | static struct sim_state the_minisim = { |
| 53 | "This is the sole m32c minisim instance. See libsim.a's global variables." |
| 54 | }; |
| 55 | |
| 56 | static int open; |
| 57 | |
| 58 | SIM_DESC |
| 59 | sim_open (SIM_OPEN_KIND kind, |
| 60 | struct host_callback_struct *callback, |
| 61 | struct bfd *abfd, char **argv) |
| 62 | { |
| 63 | if (open) |
| 64 | fprintf (stderr, "m32c minisim: re-opened sim\n"); |
| 65 | |
| 66 | /* The 'run' interface doesn't use this function, so we don't care |
| 67 | about KIND; it's always SIM_OPEN_DEBUG. */ |
| 68 | if (kind != SIM_OPEN_DEBUG) |
| 69 | fprintf (stderr, "m32c minisim: sim_open KIND != SIM_OPEN_DEBUG: %d\n", |
| 70 | kind); |
| 71 | |
| 72 | if (abfd) |
| 73 | m32c_set_mach (bfd_get_mach (abfd)); |
| 74 | |
| 75 | /* We can use ABFD, if non-NULL to select the appropriate |
| 76 | architecture. But we only support the r8c right now. */ |
| 77 | |
| 78 | set_callbacks (callback); |
| 79 | |
| 80 | /* We don't expect any command-line arguments. */ |
| 81 | |
| 82 | init_mem (); |
| 83 | init_regs (); |
| 84 | |
| 85 | open = 1; |
| 86 | return &the_minisim; |
| 87 | } |
| 88 | |
| 89 | static void |
| 90 | check_desc (SIM_DESC sd) |
| 91 | { |
| 92 | if (sd != &the_minisim) |
| 93 | fprintf (stderr, "m32c minisim: desc != &the_minisim\n"); |
| 94 | } |
| 95 | |
| 96 | void |
| 97 | sim_close (SIM_DESC sd, int quitting) |
| 98 | { |
| 99 | check_desc (sd); |
| 100 | |
| 101 | /* Not much to do. At least free up our memory. */ |
| 102 | init_mem (); |
| 103 | |
| 104 | open = 0; |
| 105 | } |
| 106 | |
| 107 | static bfd * |
| 108 | open_objfile (const char *filename) |
| 109 | { |
| 110 | bfd *prog = bfd_openr (filename, 0); |
| 111 | |
| 112 | if (!prog) |
| 113 | { |
| 114 | fprintf (stderr, "Can't read %s\n", filename); |
| 115 | return 0; |
| 116 | } |
| 117 | |
| 118 | if (!bfd_check_format (prog, bfd_object)) |
| 119 | { |
| 120 | fprintf (stderr, "%s not a m32c program\n", filename); |
| 121 | return 0; |
| 122 | } |
| 123 | |
| 124 | return prog; |
| 125 | } |
| 126 | |
| 127 | |
| 128 | SIM_RC |
| 129 | sim_load (SIM_DESC sd, char *prog, struct bfd *abfd, int from_tty) |
| 130 | { |
| 131 | check_desc (sd); |
| 132 | |
| 133 | if (!abfd) |
| 134 | abfd = open_objfile (prog); |
| 135 | if (!abfd) |
| 136 | return SIM_RC_FAIL; |
| 137 | |
| 138 | m32c_load (abfd); |
| 139 | |
| 140 | return SIM_RC_OK; |
| 141 | } |
| 142 | |
| 143 | SIM_RC |
| 144 | sim_create_inferior (SIM_DESC sd, struct bfd *abfd, char **argv, char **env) |
| 145 | { |
| 146 | check_desc (sd); |
| 147 | |
| 148 | if (abfd) |
| 149 | m32c_load (abfd); |
| 150 | |
| 151 | return SIM_RC_OK; |
| 152 | } |
| 153 | |
| 154 | int |
| 155 | sim_read (SIM_DESC sd, SIM_ADDR mem, unsigned char *buf, int length) |
| 156 | { |
| 157 | check_desc (sd); |
| 158 | |
| 159 | if (mem == 0) |
| 160 | return 0; |
| 161 | |
| 162 | mem_get_blk ((int) mem, buf, length); |
| 163 | |
| 164 | return length; |
| 165 | } |
| 166 | |
| 167 | int |
| 168 | sim_write (SIM_DESC sd, SIM_ADDR mem, unsigned char *buf, int length) |
| 169 | { |
| 170 | check_desc (sd); |
| 171 | |
| 172 | mem_put_blk ((int) mem, buf, length); |
| 173 | |
| 174 | return length; |
| 175 | } |
| 176 | |
| 177 | |
| 178 | /* Read the LENGTH bytes at BUF as an little-endian value. */ |
| 179 | static DI |
| 180 | get_le (unsigned char *buf, int length) |
| 181 | { |
| 182 | DI acc = 0; |
| 183 | while (--length >= 0) |
| 184 | acc = (acc << 8) + buf[length]; |
| 185 | |
| 186 | return acc; |
| 187 | } |
| 188 | |
| 189 | /* Store VAL as a little-endian value in the LENGTH bytes at BUF. */ |
| 190 | static void |
| 191 | put_le (unsigned char *buf, int length, DI val) |
| 192 | { |
| 193 | int i; |
| 194 | |
| 195 | for (i = 0; i < length; i++) |
| 196 | { |
| 197 | buf[i] = val & 0xff; |
| 198 | val >>= 8; |
| 199 | } |
| 200 | } |
| 201 | |
| 202 | static int |
| 203 | check_regno (enum m32c_sim_reg regno) |
| 204 | { |
| 205 | return 0 <= regno && regno < m32c_sim_reg_num_regs; |
| 206 | } |
| 207 | |
| 208 | static size_t |
| 209 | mask_size (int addr_mask) |
| 210 | { |
| 211 | switch (addr_mask) |
| 212 | { |
| 213 | case 0xffff: |
| 214 | return 2; |
| 215 | case 0xfffff: |
| 216 | case 0xffffff: |
| 217 | return 3; |
| 218 | default: |
| 219 | fprintf (stderr, |
| 220 | "m32c minisim: addr_mask_size: unexpected mask 0x%x\n", |
| 221 | addr_mask); |
| 222 | return sizeof (addr_mask); |
| 223 | } |
| 224 | } |
| 225 | |
| 226 | static size_t |
| 227 | reg_size (enum m32c_sim_reg regno) |
| 228 | { |
| 229 | switch (regno) |
| 230 | { |
| 231 | case m32c_sim_reg_r0_bank0: |
| 232 | case m32c_sim_reg_r1_bank0: |
| 233 | case m32c_sim_reg_r2_bank0: |
| 234 | case m32c_sim_reg_r3_bank0: |
| 235 | case m32c_sim_reg_r0_bank1: |
| 236 | case m32c_sim_reg_r1_bank1: |
| 237 | case m32c_sim_reg_r2_bank1: |
| 238 | case m32c_sim_reg_r3_bank1: |
| 239 | case m32c_sim_reg_flg: |
| 240 | case m32c_sim_reg_svf: |
| 241 | return 2; |
| 242 | |
| 243 | case m32c_sim_reg_a0_bank0: |
| 244 | case m32c_sim_reg_a1_bank0: |
| 245 | case m32c_sim_reg_fb_bank0: |
| 246 | case m32c_sim_reg_sb_bank0: |
| 247 | case m32c_sim_reg_a0_bank1: |
| 248 | case m32c_sim_reg_a1_bank1: |
| 249 | case m32c_sim_reg_fb_bank1: |
| 250 | case m32c_sim_reg_sb_bank1: |
| 251 | case m32c_sim_reg_usp: |
| 252 | case m32c_sim_reg_isp: |
| 253 | return mask_size (addr_mask); |
| 254 | |
| 255 | case m32c_sim_reg_pc: |
| 256 | case m32c_sim_reg_intb: |
| 257 | case m32c_sim_reg_svp: |
| 258 | case m32c_sim_reg_vct: |
| 259 | return mask_size (membus_mask); |
| 260 | |
| 261 | case m32c_sim_reg_dmd0: |
| 262 | case m32c_sim_reg_dmd1: |
| 263 | return 1; |
| 264 | |
| 265 | case m32c_sim_reg_dct0: |
| 266 | case m32c_sim_reg_dct1: |
| 267 | case m32c_sim_reg_drc0: |
| 268 | case m32c_sim_reg_drc1: |
| 269 | return 2; |
| 270 | |
| 271 | case m32c_sim_reg_dma0: |
| 272 | case m32c_sim_reg_dma1: |
| 273 | case m32c_sim_reg_dsa0: |
| 274 | case m32c_sim_reg_dsa1: |
| 275 | case m32c_sim_reg_dra0: |
| 276 | case m32c_sim_reg_dra1: |
| 277 | return 3; |
| 278 | |
| 279 | default: |
| 280 | fprintf (stderr, "m32c minisim: unrecognized register number: %d\n", |
| 281 | regno); |
| 282 | return -1; |
| 283 | } |
| 284 | } |
| 285 | |
| 286 | int |
| 287 | sim_fetch_register (SIM_DESC sd, int regno, unsigned char *buf, int length) |
| 288 | { |
| 289 | size_t size; |
| 290 | |
| 291 | check_desc (sd); |
| 292 | |
| 293 | if (!check_regno (regno)) |
| 294 | return 0; |
| 295 | |
| 296 | size = reg_size (regno); |
| 297 | if (length == size) |
| 298 | { |
| 299 | DI val; |
| 300 | |
| 301 | switch (regno) |
| 302 | { |
| 303 | case m32c_sim_reg_r0_bank0: |
| 304 | val = regs.r[0].r_r0; |
| 305 | break; |
| 306 | case m32c_sim_reg_r1_bank0: |
| 307 | val = regs.r[0].r_r1; |
| 308 | break; |
| 309 | case m32c_sim_reg_r2_bank0: |
| 310 | val = regs.r[0].r_r2; |
| 311 | break; |
| 312 | case m32c_sim_reg_r3_bank0: |
| 313 | val = regs.r[0].r_r3; |
| 314 | break; |
| 315 | case m32c_sim_reg_a0_bank0: |
| 316 | val = regs.r[0].r_a0; |
| 317 | break; |
| 318 | case m32c_sim_reg_a1_bank0: |
| 319 | val = regs.r[0].r_a1; |
| 320 | break; |
| 321 | case m32c_sim_reg_fb_bank0: |
| 322 | val = regs.r[0].r_fb; |
| 323 | break; |
| 324 | case m32c_sim_reg_sb_bank0: |
| 325 | val = regs.r[0].r_sb; |
| 326 | break; |
| 327 | case m32c_sim_reg_r0_bank1: |
| 328 | val = regs.r[1].r_r0; |
| 329 | break; |
| 330 | case m32c_sim_reg_r1_bank1: |
| 331 | val = regs.r[1].r_r1; |
| 332 | break; |
| 333 | case m32c_sim_reg_r2_bank1: |
| 334 | val = regs.r[1].r_r2; |
| 335 | break; |
| 336 | case m32c_sim_reg_r3_bank1: |
| 337 | val = regs.r[1].r_r3; |
| 338 | break; |
| 339 | case m32c_sim_reg_a0_bank1: |
| 340 | val = regs.r[1].r_a0; |
| 341 | break; |
| 342 | case m32c_sim_reg_a1_bank1: |
| 343 | val = regs.r[1].r_a1; |
| 344 | break; |
| 345 | case m32c_sim_reg_fb_bank1: |
| 346 | val = regs.r[1].r_fb; |
| 347 | break; |
| 348 | case m32c_sim_reg_sb_bank1: |
| 349 | val = regs.r[1].r_sb; |
| 350 | break; |
| 351 | |
| 352 | case m32c_sim_reg_usp: |
| 353 | val = regs.r_usp; |
| 354 | break; |
| 355 | case m32c_sim_reg_isp: |
| 356 | val = regs.r_isp; |
| 357 | break; |
| 358 | case m32c_sim_reg_pc: |
| 359 | val = regs.r_pc; |
| 360 | break; |
| 361 | case m32c_sim_reg_intb: |
| 362 | val = regs.r_intbl * 65536 + regs.r_intbl; |
| 363 | break; |
| 364 | case m32c_sim_reg_flg: |
| 365 | val = regs.r_flags; |
| 366 | break; |
| 367 | |
| 368 | /* These registers aren't implemented by the minisim. */ |
| 369 | case m32c_sim_reg_svf: |
| 370 | case m32c_sim_reg_svp: |
| 371 | case m32c_sim_reg_vct: |
| 372 | case m32c_sim_reg_dmd0: |
| 373 | case m32c_sim_reg_dmd1: |
| 374 | case m32c_sim_reg_dct0: |
| 375 | case m32c_sim_reg_dct1: |
| 376 | case m32c_sim_reg_drc0: |
| 377 | case m32c_sim_reg_drc1: |
| 378 | case m32c_sim_reg_dma0: |
| 379 | case m32c_sim_reg_dma1: |
| 380 | case m32c_sim_reg_dsa0: |
| 381 | case m32c_sim_reg_dsa1: |
| 382 | case m32c_sim_reg_dra0: |
| 383 | case m32c_sim_reg_dra1: |
| 384 | return 0; |
| 385 | |
| 386 | default: |
| 387 | fprintf (stderr, "m32c minisim: unrecognized register number: %d\n", |
| 388 | regno); |
| 389 | return -1; |
| 390 | } |
| 391 | |
| 392 | put_le (buf, length, val); |
| 393 | } |
| 394 | |
| 395 | return size; |
| 396 | } |
| 397 | |
| 398 | int |
| 399 | sim_store_register (SIM_DESC sd, int regno, unsigned char *buf, int length) |
| 400 | { |
| 401 | size_t size; |
| 402 | |
| 403 | check_desc (sd); |
| 404 | |
| 405 | if (!check_regno (regno)) |
| 406 | return 0; |
| 407 | |
| 408 | size = reg_size (regno); |
| 409 | |
| 410 | if (length == size) |
| 411 | { |
| 412 | DI val = get_le (buf, length); |
| 413 | |
| 414 | switch (regno) |
| 415 | { |
| 416 | case m32c_sim_reg_r0_bank0: |
| 417 | regs.r[0].r_r0 = val & 0xffff; |
| 418 | break; |
| 419 | case m32c_sim_reg_r1_bank0: |
| 420 | regs.r[0].r_r1 = val & 0xffff; |
| 421 | break; |
| 422 | case m32c_sim_reg_r2_bank0: |
| 423 | regs.r[0].r_r2 = val & 0xffff; |
| 424 | break; |
| 425 | case m32c_sim_reg_r3_bank0: |
| 426 | regs.r[0].r_r3 = val & 0xffff; |
| 427 | break; |
| 428 | case m32c_sim_reg_a0_bank0: |
| 429 | regs.r[0].r_a0 = val & addr_mask; |
| 430 | break; |
| 431 | case m32c_sim_reg_a1_bank0: |
| 432 | regs.r[0].r_a1 = val & addr_mask; |
| 433 | break; |
| 434 | case m32c_sim_reg_fb_bank0: |
| 435 | regs.r[0].r_fb = val & addr_mask; |
| 436 | break; |
| 437 | case m32c_sim_reg_sb_bank0: |
| 438 | regs.r[0].r_sb = val & addr_mask; |
| 439 | break; |
| 440 | case m32c_sim_reg_r0_bank1: |
| 441 | regs.r[1].r_r0 = val & 0xffff; |
| 442 | break; |
| 443 | case m32c_sim_reg_r1_bank1: |
| 444 | regs.r[1].r_r1 = val & 0xffff; |
| 445 | break; |
| 446 | case m32c_sim_reg_r2_bank1: |
| 447 | regs.r[1].r_r2 = val & 0xffff; |
| 448 | break; |
| 449 | case m32c_sim_reg_r3_bank1: |
| 450 | regs.r[1].r_r3 = val & 0xffff; |
| 451 | break; |
| 452 | case m32c_sim_reg_a0_bank1: |
| 453 | regs.r[1].r_a0 = val & addr_mask; |
| 454 | break; |
| 455 | case m32c_sim_reg_a1_bank1: |
| 456 | regs.r[1].r_a1 = val & addr_mask; |
| 457 | break; |
| 458 | case m32c_sim_reg_fb_bank1: |
| 459 | regs.r[1].r_fb = val & addr_mask; |
| 460 | break; |
| 461 | case m32c_sim_reg_sb_bank1: |
| 462 | regs.r[1].r_sb = val & addr_mask; |
| 463 | break; |
| 464 | |
| 465 | case m32c_sim_reg_usp: |
| 466 | regs.r_usp = val & addr_mask; |
| 467 | break; |
| 468 | case m32c_sim_reg_isp: |
| 469 | regs.r_isp = val & addr_mask; |
| 470 | break; |
| 471 | case m32c_sim_reg_pc: |
| 472 | regs.r_pc = val & membus_mask; |
| 473 | break; |
| 474 | case m32c_sim_reg_intb: |
| 475 | regs.r_intbl = (val & membus_mask) & 0xffff; |
| 476 | regs.r_intbh = (val & membus_mask) >> 16; |
| 477 | break; |
| 478 | case m32c_sim_reg_flg: |
| 479 | regs.r_flags = val & 0xffff; |
| 480 | break; |
| 481 | |
| 482 | /* These registers aren't implemented by the minisim. */ |
| 483 | case m32c_sim_reg_svf: |
| 484 | case m32c_sim_reg_svp: |
| 485 | case m32c_sim_reg_vct: |
| 486 | case m32c_sim_reg_dmd0: |
| 487 | case m32c_sim_reg_dmd1: |
| 488 | case m32c_sim_reg_dct0: |
| 489 | case m32c_sim_reg_dct1: |
| 490 | case m32c_sim_reg_drc0: |
| 491 | case m32c_sim_reg_drc1: |
| 492 | case m32c_sim_reg_dma0: |
| 493 | case m32c_sim_reg_dma1: |
| 494 | case m32c_sim_reg_dsa0: |
| 495 | case m32c_sim_reg_dsa1: |
| 496 | case m32c_sim_reg_dra0: |
| 497 | case m32c_sim_reg_dra1: |
| 498 | return 0; |
| 499 | |
| 500 | default: |
| 501 | fprintf (stderr, "m32c minisim: unrecognized register number: %d\n", |
| 502 | regno); |
| 503 | return -1; |
| 504 | } |
| 505 | } |
| 506 | |
| 507 | return size; |
| 508 | } |
| 509 | |
| 510 | void |
| 511 | sim_info (SIM_DESC sd, int verbose) |
| 512 | { |
| 513 | check_desc (sd); |
| 514 | |
| 515 | printf ("The m32c minisim doesn't collect any statistics.\n"); |
| 516 | } |
| 517 | |
| 518 | static volatile int stop; |
| 519 | static enum sim_stop reason; |
| 520 | int siggnal; |
| 521 | |
| 522 | |
| 523 | /* Given a signal number used by the M32C bsp (that is, newlib), |
| 524 | return a host signal number. (Oddly, the gdb/sim interface uses |
| 525 | host signal numbers...) */ |
| 526 | int |
| 527 | m32c_signal_to_host (int m32c) |
| 528 | { |
| 529 | switch (m32c) |
| 530 | { |
| 531 | case 4: |
| 532 | #ifdef SIGILL |
| 533 | return SIGILL; |
| 534 | #else |
| 535 | return SIGSEGV; |
| 536 | #endif |
| 537 | |
| 538 | case 5: |
| 539 | return SIGTRAP; |
| 540 | |
| 541 | case 10: |
| 542 | #ifdef SIGBUS |
| 543 | return SIGBUS; |
| 544 | #else |
| 545 | return SIGSEGV; |
| 546 | #endif |
| 547 | |
| 548 | case 11: |
| 549 | return SIGSEGV; |
| 550 | |
| 551 | case 24: |
| 552 | #ifdef SIGXCPU |
| 553 | return SIGXCPU; |
| 554 | #else |
| 555 | break; |
| 556 | #endif |
| 557 | |
| 558 | case 2: |
| 559 | return SIGINT; |
| 560 | |
| 561 | case 8: |
| 562 | #ifdef SIGFPE |
| 563 | return SIGFPE; |
| 564 | #else |
| 565 | break; |
| 566 | #endif |
| 567 | |
| 568 | case 6: |
| 569 | return SIGABRT; |
| 570 | } |
| 571 | |
| 572 | return 0; |
| 573 | } |
| 574 | |
| 575 | |
| 576 | /* Take a step return code RC and set up the variables consulted by |
| 577 | sim_stop_reason appropriately. */ |
| 578 | void |
| 579 | handle_step (int rc) |
| 580 | { |
| 581 | if (M32C_STEPPED (rc) || M32C_HIT_BREAK (rc)) |
| 582 | { |
| 583 | reason = sim_stopped; |
| 584 | siggnal = TARGET_SIGNAL_TRAP; |
| 585 | } |
| 586 | else if (M32C_STOPPED (rc)) |
| 587 | { |
| 588 | reason = sim_stopped; |
| 589 | siggnal = m32c_signal_to_host (M32C_STOP_SIG (rc)); |
| 590 | } |
| 591 | else |
| 592 | { |
| 593 | assert (M32C_EXITED (rc)); |
| 594 | reason = sim_exited; |
| 595 | siggnal = M32C_EXIT_STATUS (rc); |
| 596 | } |
| 597 | } |
| 598 | |
| 599 | |
| 600 | void |
| 601 | sim_resume (SIM_DESC sd, int step, int sig_to_deliver) |
| 602 | { |
| 603 | check_desc (sd); |
| 604 | |
| 605 | if (sig_to_deliver != 0) |
| 606 | { |
| 607 | fprintf (stderr, |
| 608 | "Warning: the m32c minisim does not implement " |
| 609 | "signal delivery yet.\n" "Resuming with no signal.\n"); |
| 610 | } |
| 611 | |
| 612 | if (step) |
| 613 | handle_step (decode_opcode ()); |
| 614 | else |
| 615 | { |
| 616 | /* We don't clear 'stop' here, because then we would miss |
| 617 | interrupts that arrived on the way here. Instead, we clear |
| 618 | the flag in sim_stop_reason, after GDB has disabled the |
| 619 | interrupt signal handler. */ |
| 620 | for (;;) |
| 621 | { |
| 622 | if (stop) |
| 623 | { |
| 624 | stop = 0; |
| 625 | reason = sim_stopped; |
| 626 | siggnal = TARGET_SIGNAL_INT; |
| 627 | break; |
| 628 | } |
| 629 | |
| 630 | int rc = decode_opcode (); |
| 631 | |
| 632 | if (!M32C_STEPPED (rc)) |
| 633 | { |
| 634 | handle_step (rc); |
| 635 | break; |
| 636 | } |
| 637 | } |
| 638 | } |
| 639 | } |
| 640 | |
| 641 | int |
| 642 | sim_stop (SIM_DESC sd) |
| 643 | { |
| 644 | stop = 1; |
| 645 | |
| 646 | return 1; |
| 647 | } |
| 648 | |
| 649 | void |
| 650 | sim_stop_reason (SIM_DESC sd, enum sim_stop *reason_p, int *sigrc_p) |
| 651 | { |
| 652 | check_desc (sd); |
| 653 | |
| 654 | *reason_p = reason; |
| 655 | *sigrc_p = siggnal; |
| 656 | } |
| 657 | |
| 658 | void |
| 659 | sim_do_command (SIM_DESC sd, char *cmd) |
| 660 | { |
| 661 | check_desc (sd); |
| 662 | |
| 663 | char *p = cmd; |
| 664 | |
| 665 | /* Skip leading whitespace. */ |
| 666 | while (isspace (*p)) |
| 667 | p++; |
| 668 | |
| 669 | /* Find the extent of the command word. */ |
| 670 | for (p = cmd; *p; p++) |
| 671 | if (isspace (*p)) |
| 672 | break; |
| 673 | |
| 674 | /* Null-terminate the command word, and record the start of any |
| 675 | further arguments. */ |
| 676 | char *args; |
| 677 | if (*p) |
| 678 | { |
| 679 | *p = '\0'; |
| 680 | args = p + 1; |
| 681 | while (isspace (*args)) |
| 682 | args++; |
| 683 | } |
| 684 | else |
| 685 | args = p; |
| 686 | |
| 687 | if (strcmp (cmd, "trace") == 0) |
| 688 | { |
| 689 | if (strcmp (args, "on") == 0) |
| 690 | trace = 1; |
| 691 | else if (strcmp (args, "off") == 0) |
| 692 | trace = 0; |
| 693 | else |
| 694 | printf ("The 'sim trace' command expects 'on' or 'off' " |
| 695 | "as an argument.\n"); |
| 696 | } |
| 697 | else if (strcmp (cmd, "verbose") == 0) |
| 698 | { |
| 699 | if (strcmp (args, "on") == 0) |
| 700 | verbose = 1; |
| 701 | else if (strcmp (args, "off") == 0) |
| 702 | verbose = 0; |
| 703 | else |
| 704 | printf ("The 'sim verbose' command expects 'on' or 'off'" |
| 705 | " as an argument.\n"); |
| 706 | } |
| 707 | else |
| 708 | printf ("The 'sim' command expects either 'trace' or 'verbose'" |
| 709 | " as a subcommand.\n"); |
| 710 | } |