| 1 | /* CPU data header for sh. |
| 2 | |
| 3 | THIS FILE IS MACHINE GENERATED WITH CGEN. |
| 4 | |
| 5 | Copyright 1996-2020 Free Software Foundation, Inc. |
| 6 | |
| 7 | This file is part of the GNU Binutils and/or GDB, the GNU debugger. |
| 8 | |
| 9 | This file is free software; you can redistribute it and/or modify |
| 10 | it under the terms of the GNU General Public License as published by |
| 11 | the Free Software Foundation; either version 3, or (at your option) |
| 12 | any later version. |
| 13 | |
| 14 | It is distributed in the hope that it will be useful, but WITHOUT |
| 15 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
| 16 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public |
| 17 | License for more details. |
| 18 | |
| 19 | You should have received a copy of the GNU General Public License along |
| 20 | with this program; if not, see <http://www.gnu.org/licenses/>. |
| 21 | |
| 22 | */ |
| 23 | |
| 24 | #ifndef SH_CPU_H |
| 25 | #define SH_CPU_H |
| 26 | |
| 27 | #define CGEN_ARCH sh |
| 28 | |
| 29 | /* Given symbol S, return sh_cgen_<S>. */ |
| 30 | #define CGEN_SYM(s) sh##_cgen_##s |
| 31 | |
| 32 | |
| 33 | /* Selected cpu families. */ |
| 34 | #define HAVE_CPU_SH64 |
| 35 | |
| 36 | #define CGEN_INSN_LSB0_P 0 |
| 37 | |
| 38 | /* Minimum size of any insn (in bytes). */ |
| 39 | #define CGEN_MIN_INSN_SIZE 2 |
| 40 | |
| 41 | /* Maximum size of any insn (in bytes). */ |
| 42 | #define CGEN_MAX_INSN_SIZE 4 |
| 43 | |
| 44 | #define CGEN_INT_INSN_P 1 |
| 45 | |
| 46 | /* Maximum number of syntax elements in an instruction. */ |
| 47 | #define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 22 |
| 48 | |
| 49 | /* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands. |
| 50 | e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands |
| 51 | we can't hash on everything up to the space. */ |
| 52 | #define CGEN_MNEMONIC_OPERANDS |
| 53 | |
| 54 | /* Maximum number of fields in an instruction. */ |
| 55 | #define CGEN_ACTUAL_MAX_IFMT_OPERANDS 8 |
| 56 | |
| 57 | /* Enums. */ |
| 58 | |
| 59 | /* Enum declaration for . */ |
| 60 | typedef enum frc_names { |
| 61 | H_FRC_FR0, H_FRC_FR1, H_FRC_FR2, H_FRC_FR3 |
| 62 | , H_FRC_FR4, H_FRC_FR5, H_FRC_FR6, H_FRC_FR7 |
| 63 | , H_FRC_FR8, H_FRC_FR9, H_FRC_FR10, H_FRC_FR11 |
| 64 | , H_FRC_FR12, H_FRC_FR13, H_FRC_FR14, H_FRC_FR15 |
| 65 | } FRC_NAMES; |
| 66 | |
| 67 | /* Enum declaration for . */ |
| 68 | typedef enum drc_names { |
| 69 | H_DRC_DR0 = 0, H_DRC_DR2 = 2, H_DRC_DR4 = 4, H_DRC_DR6 = 6 |
| 70 | , H_DRC_DR8 = 8, H_DRC_DR10 = 10, H_DRC_DR12 = 12, H_DRC_DR14 = 14 |
| 71 | } DRC_NAMES; |
| 72 | |
| 73 | /* Enum declaration for . */ |
| 74 | typedef enum xf_names { |
| 75 | H_XF_XF0, H_XF_XF1, H_XF_XF2, H_XF_XF3 |
| 76 | , H_XF_XF4, H_XF_XF5, H_XF_XF6, H_XF_XF7 |
| 77 | , H_XF_XF8, H_XF_XF9, H_XF_XF10, H_XF_XF11 |
| 78 | , H_XF_XF12, H_XF_XF13, H_XF_XF14, H_XF_XF15 |
| 79 | } XF_NAMES; |
| 80 | |
| 81 | /* Attributes. */ |
| 82 | |
| 83 | /* Enum declaration for machine type selection. */ |
| 84 | typedef enum mach_attr { |
| 85 | MACH_BASE, MACH_SH2, MACH_SH2E, MACH_SH2A_FPU |
| 86 | , MACH_SH2A_NOFPU, MACH_SH3, MACH_SH3E, MACH_SH4_NOFPU |
| 87 | , MACH_SH4, MACH_SH4A_NOFPU, MACH_SH4A, MACH_SH4AL |
| 88 | , MACH_SH5, MACH_MAX |
| 89 | } MACH_ATTR; |
| 90 | |
| 91 | /* Enum declaration for instruction set selection. */ |
| 92 | typedef enum isa_attr { |
| 93 | ISA_COMPACT, ISA_MEDIA, ISA_MAX |
| 94 | } ISA_ATTR; |
| 95 | |
| 96 | /* Enum declaration for sh4 insn groups. */ |
| 97 | typedef enum sh4_group_attr { |
| 98 | SH4_GROUP_NONE, SH4_GROUP_MT, SH4_GROUP_EX, SH4_GROUP_BR |
| 99 | , SH4_GROUP_LS, SH4_GROUP_FE, SH4_GROUP_CO, SH4_GROUP_MAX |
| 100 | } SH4_GROUP_ATTR; |
| 101 | |
| 102 | /* Enum declaration for sh4a insn groups. */ |
| 103 | typedef enum sh4a_group_attr { |
| 104 | SH4A_GROUP_NONE, SH4A_GROUP_MT, SH4A_GROUP_EX, SH4A_GROUP_BR |
| 105 | , SH4A_GROUP_LS, SH4A_GROUP_FE, SH4A_GROUP_CO, SH4A_GROUP_MAX |
| 106 | } SH4A_GROUP_ATTR; |
| 107 | |
| 108 | /* Number of architecture variants. */ |
| 109 | #define MAX_ISAS ((int) ISA_MAX) |
| 110 | #define MAX_MACHS ((int) MACH_MAX) |
| 111 | |
| 112 | /* Ifield support. */ |
| 113 | |
| 114 | /* Ifield attribute indices. */ |
| 115 | |
| 116 | /* Enum declaration for cgen_ifld attrs. */ |
| 117 | typedef enum cgen_ifld_attr { |
| 118 | CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED |
| 119 | , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31 |
| 120 | , CGEN_IFLD_MACH, CGEN_IFLD_ISA, CGEN_IFLD_END_NBOOLS |
| 121 | } CGEN_IFLD_ATTR; |
| 122 | |
| 123 | /* Number of non-boolean elements in cgen_ifld_attr. */ |
| 124 | #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1) |
| 125 | |
| 126 | /* cgen_ifld attribute accessor macros. */ |
| 127 | #define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset) |
| 128 | #define CGEN_ATTR_CGEN_IFLD_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_ISA-CGEN_IFLD_START_NBOOLS-1].bitset) |
| 129 | #define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_VIRTUAL)) != 0) |
| 130 | #define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_PCREL_ADDR)) != 0) |
| 131 | #define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_ABS_ADDR)) != 0) |
| 132 | #define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_RESERVED)) != 0) |
| 133 | #define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGN_OPT)) != 0) |
| 134 | #define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGNED)) != 0) |
| 135 | |
| 136 | /* Enum declaration for sh ifield types. */ |
| 137 | typedef enum ifield_type { |
| 138 | SH_F_NIL, SH_F_ANYOF, SH_F_OP4, SH_F_OP8 |
| 139 | , SH_F_OP16, SH_F_SUB4, SH_F_SUB8, SH_F_SUB10 |
| 140 | , SH_F_RN, SH_F_RM, SH_F_7_1, SH_F_11_1 |
| 141 | , SH_F_16_4, SH_F_DISP8, SH_F_DISP12, SH_F_IMM8 |
| 142 | , SH_F_IMM4, SH_F_IMM4X2, SH_F_IMM4X4, SH_F_IMM8X2 |
| 143 | , SH_F_IMM8X4, SH_F_IMM12X4, SH_F_IMM12X8, SH_F_DN |
| 144 | , SH_F_DM, SH_F_VN, SH_F_VM, SH_F_XN |
| 145 | , SH_F_XM, SH_F_IMM20_HI, SH_F_IMM20_LO, SH_F_IMM20 |
| 146 | , SH_F_OP, SH_F_EXT, SH_F_RSVD, SH_F_LEFT |
| 147 | , SH_F_RIGHT, SH_F_DEST, SH_F_LEFT_RIGHT, SH_F_TRA |
| 148 | , SH_F_TRB, SH_F_LIKELY, SH_F_6_3, SH_F_23_2 |
| 149 | , SH_F_IMM6, SH_F_IMM10, SH_F_IMM16, SH_F_UIMM6 |
| 150 | , SH_F_UIMM16, SH_F_DISP6, SH_F_DISP6X32, SH_F_DISP10 |
| 151 | , SH_F_DISP10X8, SH_F_DISP10X4, SH_F_DISP10X2, SH_F_DISP16 |
| 152 | , SH_F_MAX |
| 153 | } IFIELD_TYPE; |
| 154 | |
| 155 | #define MAX_IFLD ((int) SH_F_MAX) |
| 156 | |
| 157 | /* Hardware attribute indices. */ |
| 158 | |
| 159 | /* Enum declaration for cgen_hw attrs. */ |
| 160 | typedef enum cgen_hw_attr { |
| 161 | CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE |
| 162 | , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_ISA |
| 163 | , CGEN_HW_END_NBOOLS |
| 164 | } CGEN_HW_ATTR; |
| 165 | |
| 166 | /* Number of non-boolean elements in cgen_hw_attr. */ |
| 167 | #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) |
| 168 | |
| 169 | /* cgen_hw attribute accessor macros. */ |
| 170 | #define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset) |
| 171 | #define CGEN_ATTR_CGEN_HW_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_ISA-CGEN_HW_START_NBOOLS-1].bitset) |
| 172 | #define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_VIRTUAL)) != 0) |
| 173 | #define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_CACHE_ADDR)) != 0) |
| 174 | #define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PC)) != 0) |
| 175 | #define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PROFILE)) != 0) |
| 176 | |
| 177 | /* Enum declaration for sh hardware types. */ |
| 178 | typedef enum cgen_hw_type { |
| 179 | HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR |
| 180 | , HW_H_IADDR, HW_H_PC, HW_H_GR, HW_H_GRC |
| 181 | , HW_H_CR, HW_H_SR, HW_H_FPSCR, HW_H_FRBIT |
| 182 | , HW_H_SZBIT, HW_H_PRBIT, HW_H_SBIT, HW_H_MBIT |
| 183 | , HW_H_QBIT, HW_H_FR, HW_H_FP, HW_H_FV |
| 184 | , HW_H_FMTX, HW_H_DR, HW_H_FSD, HW_H_FMOV |
| 185 | , HW_H_TR, HW_H_ENDIAN, HW_H_ISM, HW_H_FRC |
| 186 | , HW_H_DRC, HW_H_XF, HW_H_XD, HW_H_FVC |
| 187 | , HW_H_GBR, HW_H_VBR, HW_H_PR, HW_H_MACL |
| 188 | , HW_H_MACH, HW_H_TBIT, HW_MAX |
| 189 | } CGEN_HW_TYPE; |
| 190 | |
| 191 | #define MAX_HW ((int) HW_MAX) |
| 192 | |
| 193 | /* Operand attribute indices. */ |
| 194 | |
| 195 | /* Enum declaration for cgen_operand attrs. */ |
| 196 | typedef enum cgen_operand_attr { |
| 197 | CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT |
| 198 | , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY |
| 199 | , CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_ISA |
| 200 | , CGEN_OPERAND_END_NBOOLS |
| 201 | } CGEN_OPERAND_ATTR; |
| 202 | |
| 203 | /* Number of non-boolean elements in cgen_operand_attr. */ |
| 204 | #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1) |
| 205 | |
| 206 | /* cgen_operand attribute accessor macros. */ |
| 207 | #define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset) |
| 208 | #define CGEN_ATTR_CGEN_OPERAND_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_ISA-CGEN_OPERAND_START_NBOOLS-1].bitset) |
| 209 | #define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_VIRTUAL)) != 0) |
| 210 | #define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0) |
| 211 | #define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_ABS_ADDR)) != 0) |
| 212 | #define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGN_OPT)) != 0) |
| 213 | #define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGNED)) != 0) |
| 214 | #define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_NEGATIVE)) != 0) |
| 215 | #define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_RELAX)) != 0) |
| 216 | #define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SEM_ONLY)) != 0) |
| 217 | |
| 218 | /* Enum declaration for sh operand types. */ |
| 219 | typedef enum cgen_operand_type { |
| 220 | SH_OPERAND_PC, SH_OPERAND_ENDIAN, SH_OPERAND_ISM, SH_OPERAND_RM |
| 221 | , SH_OPERAND_RN, SH_OPERAND_R0, SH_OPERAND_FRN, SH_OPERAND_FRM |
| 222 | , SH_OPERAND_FR0, SH_OPERAND_FMOVN, SH_OPERAND_FMOVM, SH_OPERAND_FVN |
| 223 | , SH_OPERAND_FVM, SH_OPERAND_DRN, SH_OPERAND_DRM, SH_OPERAND_IMM4 |
| 224 | , SH_OPERAND_IMM8, SH_OPERAND_UIMM8, SH_OPERAND_IMM20, SH_OPERAND_IMM4X2 |
| 225 | , SH_OPERAND_IMM4X4, SH_OPERAND_IMM8X2, SH_OPERAND_IMM8X4, SH_OPERAND_DISP8 |
| 226 | , SH_OPERAND_DISP12, SH_OPERAND_IMM12X4, SH_OPERAND_IMM12X8, SH_OPERAND_RM64 |
| 227 | , SH_OPERAND_RN64, SH_OPERAND_GBR, SH_OPERAND_VBR, SH_OPERAND_PR |
| 228 | , SH_OPERAND_FPSCR, SH_OPERAND_TBIT, SH_OPERAND_SBIT, SH_OPERAND_MBIT |
| 229 | , SH_OPERAND_QBIT, SH_OPERAND_FPUL, SH_OPERAND_FRBIT, SH_OPERAND_SZBIT |
| 230 | , SH_OPERAND_PRBIT, SH_OPERAND_MACL, SH_OPERAND_MACH, SH_OPERAND_FSDM |
| 231 | , SH_OPERAND_FSDN, SH_OPERAND_RD, SH_OPERAND_FRG, SH_OPERAND_FRH |
| 232 | , SH_OPERAND_FRF, SH_OPERAND_FRGH, SH_OPERAND_FPF, SH_OPERAND_FVG |
| 233 | , SH_OPERAND_FVH, SH_OPERAND_FVF, SH_OPERAND_MTRXG, SH_OPERAND_DRG |
| 234 | , SH_OPERAND_DRH, SH_OPERAND_DRF, SH_OPERAND_DRGH, SH_OPERAND_CRJ |
| 235 | , SH_OPERAND_CRK, SH_OPERAND_TRA, SH_OPERAND_TRB, SH_OPERAND_DISP6 |
| 236 | , SH_OPERAND_DISP6X32, SH_OPERAND_DISP10, SH_OPERAND_DISP10X2, SH_OPERAND_DISP10X4 |
| 237 | , SH_OPERAND_DISP10X8, SH_OPERAND_DISP16, SH_OPERAND_IMM6, SH_OPERAND_IMM10 |
| 238 | , SH_OPERAND_IMM16, SH_OPERAND_UIMM6, SH_OPERAND_UIMM16, SH_OPERAND_LIKELY |
| 239 | , SH_OPERAND_MAX |
| 240 | } CGEN_OPERAND_TYPE; |
| 241 | |
| 242 | /* Number of operands types. */ |
| 243 | #define MAX_OPERANDS 79 |
| 244 | |
| 245 | /* Maximum number of operands referenced by any insn. */ |
| 246 | #define MAX_OPERAND_INSTANCES 8 |
| 247 | |
| 248 | /* Insn attribute indices. */ |
| 249 | |
| 250 | /* Enum declaration for cgen_insn attrs. */ |
| 251 | typedef enum cgen_insn_attr { |
| 252 | CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI |
| 253 | , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED |
| 254 | , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_ILLSLOT, CGEN_INSN_FP_INSN |
| 255 | , CGEN_INSN_32_BIT_INSN, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH |
| 256 | , CGEN_INSN_ISA, CGEN_INSN_SH4_GROUP, CGEN_INSN_SH4A_GROUP, CGEN_INSN_END_NBOOLS |
| 257 | } CGEN_INSN_ATTR; |
| 258 | |
| 259 | /* Number of non-boolean elements in cgen_insn_attr. */ |
| 260 | #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1) |
| 261 | |
| 262 | /* cgen_insn attribute accessor macros. */ |
| 263 | #define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset) |
| 264 | #define CGEN_ATTR_CGEN_INSN_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_ISA-CGEN_INSN_START_NBOOLS-1].bitset) |
| 265 | #define CGEN_ATTR_CGEN_INSN_SH4_GROUP_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_SH4_GROUP-CGEN_INSN_START_NBOOLS-1].nonbitset) |
| 266 | #define CGEN_ATTR_CGEN_INSN_SH4A_GROUP_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_SH4A_GROUP-CGEN_INSN_START_NBOOLS-1].nonbitset) |
| 267 | #define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_ALIAS)) != 0) |
| 268 | #define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_VIRTUAL)) != 0) |
| 269 | #define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_UNCOND_CTI)) != 0) |
| 270 | #define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_COND_CTI)) != 0) |
| 271 | #define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_SKIP_CTI)) != 0) |
| 272 | #define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_DELAY_SLOT)) != 0) |
| 273 | #define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXABLE)) != 0) |
| 274 | #define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXED)) != 0) |
| 275 | #define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_NO_DIS)) != 0) |
| 276 | #define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_PBB)) != 0) |
| 277 | #define CGEN_ATTR_CGEN_INSN_ILLSLOT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_ILLSLOT)) != 0) |
| 278 | #define CGEN_ATTR_CGEN_INSN_FP_INSN_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_FP_INSN)) != 0) |
| 279 | #define CGEN_ATTR_CGEN_INSN_32_BIT_INSN_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_32_BIT_INSN)) != 0) |
| 280 | |
| 281 | /* cgen.h uses things we just defined. */ |
| 282 | #include "opcode/cgen.h" |
| 283 | |
| 284 | extern const struct cgen_ifld sh_cgen_ifld_table[]; |
| 285 | |
| 286 | /* Attributes. */ |
| 287 | extern const CGEN_ATTR_TABLE sh_cgen_hardware_attr_table[]; |
| 288 | extern const CGEN_ATTR_TABLE sh_cgen_ifield_attr_table[]; |
| 289 | extern const CGEN_ATTR_TABLE sh_cgen_operand_attr_table[]; |
| 290 | extern const CGEN_ATTR_TABLE sh_cgen_insn_attr_table[]; |
| 291 | |
| 292 | /* Hardware decls. */ |
| 293 | |
| 294 | extern CGEN_KEYWORD sh_cgen_opval_h_gr; |
| 295 | extern CGEN_KEYWORD sh_cgen_opval_h_grc; |
| 296 | extern CGEN_KEYWORD sh_cgen_opval_h_cr; |
| 297 | extern CGEN_KEYWORD sh_cgen_opval_h_fr; |
| 298 | extern CGEN_KEYWORD sh_cgen_opval_h_fp; |
| 299 | extern CGEN_KEYWORD sh_cgen_opval_h_fv; |
| 300 | extern CGEN_KEYWORD sh_cgen_opval_h_fmtx; |
| 301 | extern CGEN_KEYWORD sh_cgen_opval_h_dr; |
| 302 | extern CGEN_KEYWORD sh_cgen_opval_h_fsd; |
| 303 | extern CGEN_KEYWORD sh_cgen_opval_h_fmov; |
| 304 | extern CGEN_KEYWORD sh_cgen_opval_h_tr; |
| 305 | extern CGEN_KEYWORD sh_cgen_opval_frc_names; |
| 306 | extern CGEN_KEYWORD sh_cgen_opval_drc_names; |
| 307 | extern CGEN_KEYWORD sh_cgen_opval_xf_names; |
| 308 | extern CGEN_KEYWORD sh_cgen_opval_frc_names; |
| 309 | extern CGEN_KEYWORD sh_cgen_opval_h_fvc; |
| 310 | |
| 311 | extern const CGEN_HW_ENTRY sh_cgen_hw_table[]; |
| 312 | |
| 313 | |
| 314 | |
| 315 | #endif /* SH_CPU_H */ |