Documentation/devicetree/bindings/arm/arch_timer.txt

   1 * ARM architected timer
   2
   3 ARM cores may have a per-core architected timer, which provides per-cpu timers,
   4 or a memory mapped architected timer, which provides up to 8 frames with a
   5 physical and optional virtual timer per frame.
   6
   7 The per-core architected timer is attached to a GIC to deliver its
   8 per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
   9 to deliver its interrupts via SPIs.
  10
  11 ** CP15 Timer node properties:
  12
  13 - compatible : Should at least contain one of
  14         "arm,armv7-timer"
  15         "arm,armv8-timer"
  16
  17 - interrupts : Interrupt list for secure, non-secure, virtual and
  18   hypervisor timers, in that order.
  19
  20 - clock-frequency : The frequency of the main counter, in Hz. Optional.
  21
  22 - always-on : a boolean property. If present, the timer is powered through an
  23   always-on power domain, therefore it never loses context.
  24
  25 Example:
  26
  27         timer {
  28                 compatible = "arm,cortex-a15-timer",
  29                              "arm,armv7-timer";
  30                 interrupts = <1 13 0xf08>,
  31                              <1 14 0xf08>,
  32                              <1 11 0xf08>,
  33                              <1 10 0xf08>;
  34                 clock-frequency = <100000000>;
  35         };
  36
  37 ** Memory mapped timer node properties:
  38
  39 - compatible : Should at least contain "arm,armv7-timer-mem".
  40
  41 - clock-frequency : The frequency of the main counter, in Hz. Optional.
  42
  43 - reg : The control frame base address.
  44
  45 Note that #address-cells, #size-cells, and ranges shall be present to ensure
  46 the CPU can address a frame's registers.
  47
  48 A timer node has up to 8 frame sub-nodes, each with the following properties:
  49
  50 - frame-number: 0 to 7.
  51
  52 - interrupts : Interrupt list for physical and virtual timers in that order.
  53   The virtual timer interrupt is optional.
  54
  55 - reg : The first and second view base addresses in that order. The second view
  56   base address is optional.
  57
  58 - status : "disabled" indicates the frame is not available for use. Optional.
  59
  60 Example:
  61
  62         timer@f0000000 {
  63                 compatible = "arm,armv7-timer-mem";
  64                 #address-cells = <1>;
  65                 #size-cells = <1>;
  66                 ranges;
  67                 reg = <0xf0000000 0x1000>;
  68                 clock-frequency = <50000000>;
  69
  70                 frame@f0001000 {
  71                         frame-number = <0>
  72                         interrupts = <0 13 0x8>,
  73                                      <0 14 0x8>;
  74                         reg = <0xf0001000 0x1000>,
  75                               <0xf0002000 0x1000>;
  76                 };
  77
  78                 frame@f0003000 {
  79                         frame-number = <1>
  80                         interrupts = <0 15 0x8>;
  81                         reg = <0xf0003000 0x1000>;
  82                         status = "disabled";
  83                 };
  84         };