Documentation/devicetree/bindings/arm/l2cc.txt

   1 * ARM L2 Cache Controller
   2
   3 ARM cores often have a separate level 2 cache controller. There are various
   4 implementations of the L2 cache controller with compatible programming models.
   5 The ARM L2 cache representation in the device tree should be done as follows:
   6
   7 Required properties:
   8
   9 - compatible : should be one of:
  10   "arm,pl310-cache"
  11   "arm,l220-cache"
  12   "arm,l210-cache"
  13   "bcm,bcm11351-a2-pl310-cache": DEPRECATED by "brcm,bcm11351-a2-pl310-cache"
  14   "brcm,bcm11351-a2-pl310-cache": For Broadcom bcm11351 chipset where an
  15      offset needs to be added to the address before passing down to the L2
  16      cache controller
  17   "marvell,aurora-system-cache": Marvell Controller designed to be
  18      compatible with the ARM one, with system cache mode (meaning
  19      maintenance operations on L1 are broadcasted to the L2 and L2
  20      performs the same operation).
  21   "marvell,aurora-outer-cache": Marvell Controller designed to be
  22      compatible with the ARM one with outer cache mode.
  23   "marvell,tauros3-cache": Marvell Tauros3 cache controller, compatible
  24      with arm,pl310-cache controller.
  25 - cache-unified : Specifies the cache is a unified cache.
  26 - cache-level : Should be set to 2 for a level 2 cache.
  27 - reg : Physical base address and size of cache controller's memory mapped
  28   registers.
  29
  30 Optional properties:
  31
  32 - arm,data-latency : Cycles of latency for Data RAM accesses. Specifies 3 cells of
  33   read, write and setup latencies. Minimum valid values are 1. Controllers
  34   without setup latency control should use a value of 0.
  35 - arm,tag-latency : Cycles of latency for Tag RAM accesses. Specifies 3 cells of
  36   read, write and setup latencies. Controllers without setup latency control
  37   should use 0. Controllers without separate read and write Tag RAM latency
  38   values should only use the first cell.
  39 - arm,dirty-latency : Cycles of latency for Dirty RAMs. This is a single cell.
  40 - arm,filter-ranges : <start length> Starting address and length of window to
  41   filter. Addresses in the filter window are directed to the M1 port. Other
  42   addresses will go to the M0 port.
  43 - arm,io-coherent : indicates that the system is operating in an hardware
  44   I/O coherent mode. Valid only when the arm,pl310-cache compatible
  45   string is used.
  46 - interrupts : 1 combined interrupt.
  47 - cache-id-part: cache id part number to be used if it is not present
  48   on hardware
  49 - wt-override: If present then L2 is forced to Write through mode
  50
  51 Example:
  52
  53 L2: cache-controller {
  54         compatible = "arm,pl310-cache";
  55         reg = <0xfff12000 0x1000>;
  56         arm,data-latency = <1 1 1>;
  57         arm,tag-latency = <2 2 2>;
  58         arm,filter-ranges = <0x80000000 0x8000000>;
  59         cache-unified;
  60         cache-level = <2>;
  61         interrupts = <45>;
  62 };