Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt

   1 * Renesas Clock Pulse Generator / Module Standby and Software Reset
   2
   3 On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse Generator)
   4 and MSSR (Module Standby and Software Reset) blocks are intimately connected,
   5 and share the same register block.
   6
   7 They provide the following functionalities:
   8   - The CPG block generates various core clocks,
   9   - The MSSR block provides two functions:
  10       1. Module Standby, providing a Clock Domain to control the clock supply
  11          to individual SoC devices,
  12       2. Reset Control, to perform a software reset of individual SoC devices.
  13
  14 Required Properties:
  15   - compatible: Must be one of:
  16       - "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3)
  17       - "renesas,r8a7796-cpg-mssr" for the r8a7796 SoC (R-Car M3-W)
  18
  19   - reg: Base address and length of the memory resource used by the CPG/MSSR
  20     block
  21
  22   - clocks: References to external parent clocks, one entry for each entry in
  23     clock-names
  24   - clock-names: List of external parent clock names. Valid names are:
  25       - "extal" (r8a7795, r8a7796)
  26       - "extalr" (r8a7795, r8a7796)
  27
  28   - #clock-cells: Must be 2
  29       - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
  30         and a core clock reference, as defined in
  31         <dt-bindings/clock/*-cpg-mssr.h>.
  32       - For module clocks, the two clock specifier cells must be "CPG_MOD" and
  33         a module number, as defined in the datasheet.
  34
  35   - #power-domain-cells: Must be 0
  36       - SoC devices that are part of the CPG/MSSR Clock Domain and can be
  37         power-managed through Module Standby should refer to the CPG device
  38         node in their "power-domains" property, as documented by the generic PM
  39         Domain bindings in
  40         Documentation/devicetree/bindings/power/power_domain.txt.
  41
  42
  43 Examples
  44 --------
  45
  46   - CPG device node:
  47
  48         cpg: clock-controller@e6150000 {
  49                 compatible = "renesas,r8a7795-cpg-mssr";
  50                 reg = <0 0xe6150000 0 0x1000>;
  51                 clocks = <&extal_clk>, <&extalr_clk>;
  52                 clock-names = "extal", "extalr";
  53                 #clock-cells = <2>;
  54                 #power-domain-cells = <0>;
  55         };
  56
  57
  58   - CPG/MSSR Clock Domain member device node:
  59
  60         scif2: serial@e6e88000 {
  61                 compatible = "renesas,scif-r8a7795", "renesas,scif";
  62                 reg = <0 0xe6e88000 0 64>;
  63                 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
  64                 clocks = <&cpg CPG_MOD 310>;
  65                 clock-names = "fck";
  66                 dmas = <&dmac1 0x13>, <&dmac1 0x12>;
  67                 dma-names = "tx", "rx";
  68                 power-domains = <&cpg>;
  69                 status = "disabled";
  70         };