1 Allwinner A10 Display Pipeline
2 ==============================
4 The Allwinner A10 Display pipeline is composed of several components
5 that are going to be documented below:
10 The TV Encoder supports the composite and VGA output. It is one end of
14 - compatible: value should be "allwinner,sun4i-a10-tv-encoder".
15 - reg: base address and size of memory-mapped region
16 - clocks: the clocks driving the TV encoder
17 - resets: phandle to the reset controller driving the encoder
19 - ports: A ports node with endpoint definitions as defined in
20 Documentation/devicetree/bindings/media/video-interfaces.txt. The
21 first port should be the input endpoint.
26 The TCON acts as a timing controller for RGB, LVDS and TV interfaces.
29 - compatible: value must be either:
30 * allwinner,sun5i-a13-tcon
31 * allwinner,sun8i-a33-tcon
32 - reg: base address and size of memory-mapped region
33 - interrupts: interrupt associated to this IP
34 - clocks: phandles to the clocks feeding the TCON. Three are needed:
35 - 'ahb': the interface clocks
36 - 'tcon-ch0': The clock driving the TCON channel 0
37 - resets: phandles to the reset controllers driving the encoder
38 - "lcd": the reset line for the TCON channel 0
40 - clock-names: the clock names mentioned above
41 - reset-names: the reset names mentioned above
42 - clock-output-names: Name of the pixel clock created
44 - ports: A ports node with endpoint definitions as defined in
45 Documentation/devicetree/bindings/media/video-interfaces.txt. The
46 first port should be the input endpoint, the second one the output
48 The output should have two endpoints. The first is the block
49 connected to the TCON channel 0 (usually a panel or a bridge), the
50 second the block connected to the TCON channel 1 (usually the TV
53 On the A13, there is one more clock required:
54 - 'tcon-ch1': The clock driving the TCON channel 1
59 The DRC (Dynamic Range Controller), found in the latest Allwinner SoCs
60 (A31, A23, A33), allows to dynamically adjust pixel
61 brightness/contrast based on histogram measurements for LCD content
62 adaptive backlight control.
66 - compatible: value must be one of:
67 * allwinner,sun8i-a33-drc
68 - reg: base address and size of the memory-mapped region.
69 - interrupts: interrupt associated to this IP
70 - clocks: phandles to the clocks feeding the DRC
71 * ahb: the DRC interface clock
72 * mod: the DRC module clock
73 * ram: the DRC DRAM clock
74 - clock-names: the clock names mentioned above
75 - resets: phandles to the reset line driving the DRC
77 - ports: A ports node with endpoint definitions as defined in
78 Documentation/devicetree/bindings/media/video-interfaces.txt. The
79 first port should be the input endpoints, the second one the outputs
81 Display Engine Backend
82 ----------------------
84 The display engine backend exposes layers and sprites to the
88 - compatible: value must be one of:
89 * allwinner,sun5i-a13-display-backend
90 * allwinner,sun8i-a33-display-backend
91 - reg: base address and size of the memory-mapped region.
92 - clocks: phandles to the clocks feeding the frontend and backend
93 * ahb: the backend interface clock
94 * mod: the backend module clock
95 * ram: the backend DRAM clock
96 - clock-names: the clock names mentioned above
97 - resets: phandles to the reset controllers driving the backend
99 - ports: A ports node with endpoint definitions as defined in
100 Documentation/devicetree/bindings/media/video-interfaces.txt. The
101 first port should be the input endpoints, the second one the output
103 On the A33, some additional properties are required:
104 - reg needs to have an additional region corresponding to the SAT
105 - reg-names need to be set, with "be" and "sat"
106 - clocks and clock-names need to have a phandle to the SAT bus
107 clocks, whose name will be "sat"
108 - resets and reset-names need to have a phandle to the SAT bus
109 resets, whose name will be "sat"
111 Display Engine Frontend
112 -----------------------
114 The display engine frontend does formats conversion, scaling,
115 deinterlacing and color space conversion.
118 - compatible: value must be one of:
119 * allwinner,sun5i-a13-display-frontend
120 * allwinner,sun8i-a33-display-frontend
121 - reg: base address and size of the memory-mapped region.
122 - interrupts: interrupt associated to this IP
123 - clocks: phandles to the clocks feeding the frontend and backend
124 * ahb: the backend interface clock
125 * mod: the backend module clock
126 * ram: the backend DRAM clock
127 - clock-names: the clock names mentioned above
128 - resets: phandles to the reset controllers driving the backend
130 - ports: A ports node with endpoint definitions as defined in
131 Documentation/devicetree/bindings/media/video-interfaces.txt. The
132 first port should be the input endpoints, the second one the outputs
135 Display Engine Pipeline
136 -----------------------
138 The display engine pipeline (and its entry point, since it can be
139 either directly the backend or the frontend) is represented as an
143 - compatible: value must be one of:
144 * allwinner,sun5i-a13-display-engine
145 * allwinner,sun8i-a33-display-engine
147 - allwinner,pipelines: list of phandle to the display engine
153 compatible = "olimex,lcd-olinuxino-43-ts";
154 #address-cells = <1>;
158 #address-cells = <1>;
161 panel_input: endpoint {
162 remote-endpoint = <&tcon0_out_panel>;
167 tve0: tv-encoder@01c0a000 {
168 compatible = "allwinner,sun4i-a10-tv-encoder";
169 reg = <0x01c0a000 0x1000>;
170 clocks = <&ahb_gates 34>;
171 resets = <&tcon_ch0_clk 0>;
174 #address-cells = <1>;
177 tve0_in_tcon0: endpoint@0 {
179 remote-endpoint = <&tcon0_out_tve0>;
184 tcon0: lcd-controller@1c0c000 {
185 compatible = "allwinner,sun5i-a13-tcon";
186 reg = <0x01c0c000 0x1000>;
188 resets = <&tcon_ch0_clk 1>;
190 clocks = <&ahb_gates 36>,
196 clock-output-names = "tcon-pixel-clock";
199 #address-cells = <1>;
203 #address-cells = <1>;
207 tcon0_in_be0: endpoint@0 {
209 remote-endpoint = <&be0_out_tcon0>;
214 #address-cells = <1>;
218 tcon0_out_panel: endpoint@0 {
220 remote-endpoint = <&panel_input>;
223 tcon0_out_tve0: endpoint@1 {
225 remote-endpoint = <&tve0_in_tcon0>;
231 fe0: display-frontend@1e00000 {
232 compatible = "allwinner,sun5i-a13-display-frontend";
233 reg = <0x01e00000 0x20000>;
235 clocks = <&ahb_gates 46>, <&de_fe_clk>,
237 clock-names = "ahb", "mod",
239 resets = <&de_fe_clk>;
242 #address-cells = <1>;
246 #address-cells = <1>;
250 fe0_out_be0: endpoint {
251 remote-endpoint = <&be0_in_fe0>;
257 be0: display-backend@1e60000 {
258 compatible = "allwinner,sun5i-a13-display-backend";
259 reg = <0x01e60000 0x10000>;
260 clocks = <&ahb_gates 44>, <&de_be_clk>,
262 clock-names = "ahb", "mod",
264 resets = <&de_be_clk>;
267 #address-cells = <1>;
271 #address-cells = <1>;
275 be0_in_fe0: endpoint@0 {
277 remote-endpoint = <&fe0_out_be0>;
282 #address-cells = <1>;
286 be0_out_tcon0: endpoint@0 {
288 remote-endpoint = <&tcon0_in_be0>;
295 compatible = "allwinner,sun5i-a13-display-engine";
296 allwinner,pipelines = <&fe0>;