Documentation/devicetree/bindings/drm/msm/edp.txt

   1 Qualcomm Technologies Inc. adreno/snapdragon eDP output
   2
   3 Required properties:
   4 - compatible:
   5   * "qcom,mdss-edp"
   6 - reg: Physical base address and length of the registers of controller and PLL
   7 - reg-names: The names of register regions. The following regions are required:
   8   * "edp"
   9   * "pll_base"
  10 - interrupts: The interrupt signal from the eDP block.
  11 - power-domains: Should be <&mmcc MDSS_GDSC>.
  12 - clocks: device clocks
  13   See Documentation/devicetree/bindings/clocks/clock-bindings.txt for details.
  14 - clock-names: the following clocks are required:
  15   * "core_clk"
  16   * "iface_clk"
  17   * "mdp_core_clk"
  18   * "pixel_clk"
  19   * "link_clk"
  20 - #clock-cells: The value should be 1.
  21 - vdda-supply: phandle to vdda regulator device node
  22 - lvl-vdd-supply: phandle to regulator device node which is used to supply power
  23   to HPD receiving chip
  24 - panel-en-gpios: GPIO pin to supply power to panel.
  25 - panel-hpd-gpios: GPIO pin used for eDP hpd.
  26
  27
  28 Optional properties:
  29 - interrupt-parent: phandle to the MDP block if the interrupt signal is routed
  30   through MDP block
  31
  32 Example:
  33         mdss_edp: qcom,mdss_edp@fd923400 {
  34                         compatible = "qcom,mdss-edp";
  35                         reg-names =
  36                                 "edp",
  37                                 "pll_base";
  38                         reg =   <0xfd923400 0x700>,
  39                                 <0xfd923a00 0xd4>;
  40                         interrupt-parent = <&mdss_mdp>;
  41                         interrupts = <12 0>;
  42                         power-domains = <&mmcc MDSS_GDSC>;
  43                         clock-names =
  44                                 "core_clk",
  45                                 "pixel_clk",
  46                                 "iface_clk",
  47                                 "link_clk",
  48                                 "mdp_core_clk";
  49                         clocks =
  50                                 <&mmcc MDSS_EDPAUX_CLK>,
  51                                 <&mmcc MDSS_EDPPIXEL_CLK>,
  52                                 <&mmcc MDSS_AHB_CLK>,
  53                                 <&mmcc MDSS_EDPLINK_CLK>,
  54                                 <&mmcc MDSS_MDP_CLK>;
  55                         #clock-cells = <1>;
  56                         vdda-supply = <&pma8084_l12>;
  57                         lvl-vdd-supply = <&lvl_vreg>;
  58                         panel-en-gpios = <&tlmm 137 0>;
  59                         panel-hpd-gpios = <&tlmm 103 0>;
  60         };