Documentation/devicetree/bindings/mtd/sunxi-nand.txt

   1 Allwinner NAND Flash Controller (NFC)
   2
   3 Required properties:
   4 - compatible : "allwinner,sun4i-a10-nand".
   5 - reg : shall contain registers location and length for data and reg.
   6 - interrupts : shall define the nand controller interrupt.
   7 - #address-cells: shall be set to 1. Encode the nand CS.
   8 - #size-cells : shall be set to 0.
   9 - clocks : shall reference nand controller clocks.
  10 - clock-names : nand controller internal clock names. Shall contain :
  11     * "ahb" : AHB gating clock
  12     * "mod" : nand controller clock
  13
  14 Optional properties:
  15 - dmas : shall reference DMA channel associated to the NAND controller.
  16 - dma-names : shall be "rxtx".
  17
  18 Optional children nodes:
  19 Children nodes represent the available nand chips.
  20
  21 Optional properties:
  22 - allwinner,rb : shall contain the native Ready/Busy ids.
  23  or
  24 - rb-gpios : shall contain the gpios used as R/B pins.
  25 - nand-ecc-mode : one of the supported ECC modes ("hw", "hw_syndrome", "soft",
  26   "soft_bch" or "none")
  27
  28 see Documentation/devicetree/bindings/mtd/nand.txt for generic bindings.
  29
  30
  31 Examples:
  32 nfc: nand@01c03000 {
  33         compatible = "allwinner,sun4i-a10-nand";
  34         reg = <0x01c03000 0x1000>;
  35         interrupts = <0 37 1>;
  36         clocks = <&ahb_gates 13>, <&nand_clk>;
  37         clock-names = "ahb", "mod";
  38         #address-cells = <1>;
  39         #size-cells = <0>;
  40         pinctrl-names = "default";
  41         pinctrl-0 = <&nand_pins_a &nand_cs0_pins_a &nand_rb0_pins_a>;
  42         status = "okay";
  43
  44         nand@0 {
  45                 reg = <0>;
  46                 allwinner,rb = <0>;
  47                 nand-ecc-mode = "soft_bch";
  48         };
  49 };