Documentation/devicetree/bindings/usb/msm-hsusb.txt

   1 MSM SoC HSUSB controllers
   2
   3 EHCI
   4
   5 Required properties:
   6 - compatible:   Should contain "qcom,ehci-host"
   7 - regs:                 offset and length of the register set in the memory map
   8 - usb-phy:              phandle for the PHY device
   9
  10 Example EHCI controller device node:
  11
  12         ehci: ehci@f9a55000 {
  13                 compatible = "qcom,ehci-host";
  14                 reg = <0xf9a55000 0x400>;
  15                 usb-phy = <&usb_otg>;
  16         };
  17
  18 USB PHY with optional OTG:
  19
  20 Required properties:
  21 - compatible:   Should contain:
  22   "qcom,usb-otg-ci" for chipsets with ChipIdea 45nm PHY
  23   "qcom,usb-otg-snps" for chipsets with Synopsys 28nm PHY
  24
  25 - regs:         Offset and length of the register set in the memory map
  26 - interrupts:   interrupt-specifier for the OTG interrupt.
  27
  28 - clocks:       A list of phandle + clock-specifier pairs for the
  29                 clocks listed in clock-names
  30 - clock-names:  Should contain the following:
  31   "phy"         USB PHY reference clock
  32   "core"        Protocol engine clock
  33   "iface"       Interface bus clock
  34   "alt_core"    Protocol engine clock for targets with asynchronous
  35                 reset methodology. (optional)
  36
  37 - vdccx-supply: phandle to the regulator for the vdd supply for
  38                 digital circuit operation.
  39 - v1p8-supply:  phandle to the regulator for the 1.8V supply
  40 - v3p3-supply:  phandle to the regulator for the 3.3V supply
  41
  42 - resets:       A list of phandle + reset-specifier pairs for the
  43                 resets listed in reset-names
  44 - reset-names:  Should contain the following:
  45   "phy"         USB PHY controller reset
  46   "link"        USB LINK controller reset
  47
  48 - qcom,otg-control: OTG control (VBUS and ID notifications) can be one of
  49                 1 - PHY control
  50                 2 - PMIC control
  51
  52 Optional properties:
  53 - dr_mode:      One of "host", "peripheral" or "otg". Defaults to "otg"
  54
  55 - qcom,phy-init-sequence: PHY configuration sequence values. This is related to Device
  56                 Mode Eye Diagram test. Start address at which these values will be
  57                 written is ULPI_EXT_VENDOR_SPECIFIC. Value of -1 is reserved as
  58                 "do not overwrite default value at this address".
  59                 For example: qcom,phy-init-sequence = < -1 0x63 >;
  60                 Will update only value at address ULPI_EXT_VENDOR_SPECIFIC + 1.
  61
  62 - qcom,phy-num: Select number of pyco-phy to use, can be one of
  63                 0 - PHY one, default
  64                 1 - Second PHY
  65                 Some platforms may have configuration to allow USB
  66                 controller work with any of the two HSPHYs present.
  67
  68 - qcom,vdd-levels: This property must be a list of three integer values
  69                 (no, min, max) where each value represents either a voltage
  70                 in microvolts or a value corresponding to voltage corner.
  71
  72 Example HSUSB OTG controller device node:
  73
  74     usb@f9a55000 {
  75         compatible = "qcom,usb-otg-snps";
  76         reg = <0xf9a55000 0x400>;
  77         interrupts = <0 134 0>;
  78         dr_mode = "peripheral";
  79
  80         clocks = <&gcc GCC_XO_CLK>, <&gcc GCC_USB_HS_SYSTEM_CLK>,
  81                 <&gcc GCC_USB_HS_AHB_CLK>;
  82
  83         clock-names = "phy", "core", "iface";
  84
  85         vddcx-supply = <&pm8841_s2_corner>;
  86         v1p8-supply = <&pm8941_l6>;
  87         v3p3-supply = <&pm8941_l24>;
  88
  89         resets = <&gcc GCC_USB2A_PHY_BCR>, <&gcc GCC_USB_HS_BCR>;
  90         reset-names = "phy", "link";
  91
  92         qcom,otg-control = <1>;
  93         qcom,phy-init-sequence = < -1 0x63 >;
  94         qcom,vdd-levels = <1 5 7>;
  95         };