5 * National Semiconductor LM90
7 Addresses scanned: I2C 0x4c
8 Datasheet: Publicly available at the National Semiconductor website
9 http://www.national.com/pf/LM/LM90.html
10 * National Semiconductor LM89
12 Addresses scanned: I2C 0x4c and 0x4d
13 Datasheet: Publicly available at the National Semiconductor website
14 http://www.national.com/mpf/LM/LM89.html
15 * National Semiconductor LM99
17 Addresses scanned: I2C 0x4c and 0x4d
18 Datasheet: Publicly available at the National Semiconductor website
19 http://www.national.com/pf/LM/LM99.html
20 * National Semiconductor LM86
22 Addresses scanned: I2C 0x4c
23 Datasheet: Publicly available at the National Semiconductor website
24 http://www.national.com/mpf/LM/LM86.html
25 * Analog Devices ADM1032
27 Addresses scanned: I2C 0x4c and 0x4d
28 Datasheet: Publicly available at the ON Semiconductor website
29 http://www.onsemi.com/PowerSolutions/product.do?id=ADM1032
30 * Analog Devices ADT7461
32 Addresses scanned: I2C 0x4c and 0x4d
33 Datasheet: Publicly available at the ON Semiconductor website
34 http://www.onsemi.com/PowerSolutions/product.do?id=ADT7461
35 Note: Only if in ADM1032 compatibility mode
38 Addresses scanned: I2C 0x4c
39 Datasheet: Publicly available at the Maxim website
40 http://www.maxim-ic.com/quick_view2.cfm/qv_pk/2578
43 Addresses scanned: I2C 0x4c
44 Datasheet: Publicly available at the Maxim website
45 http://www.maxim-ic.com/quick_view2.cfm/qv_pk/2578
48 Addresses scanned: I2C 0x4c, 0x4d (unsupported 0x4e)
49 Datasheet: Publicly available at the Maxim website
50 http://www.maxim-ic.com/quick_view2.cfm/qv_pk/2578
53 Addresses scanned: I2C 0x18, 0x19, 0x1a, 0x29, 0x2a, 0x2b,
55 Datasheet: Publicly available at the Maxim website
56 http://www.maxim-ic.com/quick_view2.cfm/qv_pk/3370
59 Addresses scanned: I2C 0x18, 0x19, 0x1a, 0x29, 0x2a, 0x2b,
61 Datasheet: Publicly available at the Maxim website
62 http://www.maxim-ic.com/quick_view2.cfm/qv_pk/3370
65 Author: Jean Delvare <khali@linux-fr.org>
71 The LM90 is a digital temperature sensor. It senses its own temperature as
72 well as the temperature of up to one external diode. It is compatible
73 with many other devices such as the LM86, the LM89, the LM99, the ADM1032,
74 the MAX6657, MAX6658, MAX6659, MAX6680 and the MAX6681 all of which are
75 supported by this driver.
77 Note that there is no easy way to differentiate between the MAX6657,
78 MAX6658 and MAX6659 variants. The extra address and features of the
79 MAX6659 are not supported by this driver. The MAX6680 and MAX6681 only
80 differ in their pinout, therefore they obviously can't (and don't need to)
81 be distinguished. Additionally, the ADT7461 is supported if found in
82 ADM1032 compatibility mode.
84 The specificity of this family of chipsets over the ADM1021/LM84
85 family is that it features critical limits with hysteresis, and an
86 increased resolution of the remote temperature measurement.
88 The different chipsets of the family are not strictly identical, although
89 very similar. For reference, here comes a non-exhaustive list of specific
93 * Filter and alert configuration register at 0xBF.
94 * ALERT is triggered by temperatures over critical limits.
98 * Better external channel accuracy
102 * External temperature shifted by 16 degrees down
105 * Consecutive alert register at 0x22.
106 * Conversion averaging.
107 * Up to 64 conversions/s.
108 * ALERT is triggered by open remote sensor.
109 * SMBus PEC support for Write Byte and Receive Byte transactions.
112 * Extended temperature range (breaks compatibility)
113 * Lower resolution for remote temperature
116 * Better local resolution
117 * Remote sensor type selection
120 * Better local resolution
122 * Second critical temperature limit
123 * Remote sensor type selection
127 * Remote sensor type selection
129 All temperature values are given in degrees Celsius. Resolution
130 is 1.0 degree for the local temperature, 0.125 degree for the remote
131 temperature, except for the MAX6657, MAX6658 and MAX6659 which have a
132 resolution of 0.125 degree for both temperatures.
134 Each sensor has its own high and low limits, plus a critical limit.
135 Additionally, there is a relative hysteresis value common to both critical
136 values. To make life easier to user-space applications, two absolute values
137 are exported, one for each channel, but these values are of course linked.
138 Only the local hysteresis can be set from user-space, and the same delta
139 applies to the remote hysteresis.
141 The lm90 driver will not update its values more frequently than every
142 other second; reading them more often will do no harm, but will return
148 The ADM1032 is the only chip of the family which supports PEC. It does
149 not support PEC on all transactions though, so some care must be taken.
151 When reading a register value, the PEC byte is computed and sent by the
152 ADM1032 chip. However, in the case of a combined transaction (SMBus Read
153 Byte), the ADM1032 computes the CRC value over only the second half of
154 the message rather than its entirety, because it thinks the first half
155 of the message belongs to a different transaction. As a result, the CRC
156 value differs from what the SMBus master expects, and all reads fail.
158 For this reason, the lm90 driver will enable PEC for the ADM1032 only if
159 the bus supports the SMBus Send Byte and Receive Byte transaction types.
160 These transactions will be used to read register values, instead of
161 SMBus Read Byte, and PEC will work properly.
163 Additionally, the ADM1032 doesn't support SMBus Send Byte with PEC.
164 Instead, it will try to write the PEC value to the register (because the
165 SMBus Send Byte transaction with PEC is similar to a Write Byte transaction
166 without PEC), which is not what we want. Thus, PEC is explicitly disabled
167 on SMBus Send Byte transactions in the lm90 driver.
169 PEC on byte data transactions represents a significant increase in bandwidth
170 usage (+33% for writes, +25% for reads) in normal conditions. With the need
171 to use two SMBus transaction for reads, this overhead jumps to +50%. Worse,
172 two transactions will typically mean twice as much delay waiting for
173 transaction completion, effectively doubling the register cache refresh time.
174 I guess reliability comes at a price, but it's quite expensive this time.
176 So, as not everyone might enjoy the slowdown, PEC can be disabled through
177 sysfs. Just write 0 to the "pec" file and PEC will be disabled. Write 1
178 to that file to enable PEC again.