arch/arc/include/asm/mmu_context.h

   1 /*
   2  * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * vineetg: May 2011
   9  *  -Refactored get_new_mmu_context( ) to only handle live-mm.
  10  *   retiring-mm handled in other hooks
  11  *
  12  * Vineetg: March 25th, 2008: Bug #92690
  13  *  -Major rewrite of Core ASID allocation routine get_new_mmu_context
  14  *
  15  * Amit Bhor, Sameer Dhavale: Codito Technologies 2004
  16  */
  17
  18 #ifndef _ASM_ARC_MMU_CONTEXT_H
  19 #define _ASM_ARC_MMU_CONTEXT_H
  20
  21 #include <asm/arcregs.h>
  22 #include <asm/tlb.h>
  23
  24 #include <asm-generic/mm_hooks.h>
  25
  26 /*              ARC700 ASID Management
  27  *
  28  * ARC MMU provides 8-bit ASID (0..255) to TAG TLB entries, allowing entries
  29  * with same vaddr (different tasks) to co-exit. This provides for
  30  * "Fast Context Switch" i.e. no TLB flush on ctxt-switch
  31  *
  32  * Linux assigns each task a unique ASID. A simple round-robin allocation
  33  * of H/w ASID is done using software tracker @asid_cache.
  34  * When it reaches max 255, the allocation cycle starts afresh by flushing
  35  * the entire TLB and wrapping ASID back to zero.
  36  *
  37  * A new allocation cycle, post rollover, could potentially reassign an ASID
  38  * to a different task. Thus the rule is to refresh the ASID in a new cycle.
  39  * The 32 bit @asid_cache (and mm->asid) have 8 bits MMU PID and rest 24 bits
  40  * serve as cycle/generation indicator and natural 32 bit unsigned math
  41  * automagically increments the generation when lower 8 bits rollover.
  42  */
  43
  44 #define MM_CTXT_ASID_MASK       0x000000ff /* MMU PID reg :8 bit PID */
  45 #define MM_CTXT_CYCLE_MASK      (~MM_CTXT_ASID_MASK)
  46
  47 #define MM_CTXT_FIRST_CYCLE     (MM_CTXT_ASID_MASK + 1)
  48 #define MM_CTXT_NO_ASID         0UL
  49
  50 #define hw_pid(mm)              (mm->context.asid & MM_CTXT_ASID_MASK)
  51
  52 extern unsigned int asid_cache;
  53
  54 /*
  55  * Get a new ASID if task doesn't have a valid one (unalloc or from prev cycle)
  56  * Also set the MMU PID register to existing/updated ASID
  57  */
  58 static inline void get_new_mmu_context(struct mm_struct *mm)
  59 {
  60         unsigned long flags;
  61
  62         local_irq_save(flags);
  63
  64         /*
  65          * Move to new ASID if it was not from current alloc-cycle/generation.
  66          * This is done by ensuring that the generation bits in both mm->ASID
  67          * and cpu's ASID counter are exactly same.
  68          *
  69          * Note: Callers needing new ASID unconditionally, independent of
  70          *       generation, e.g. local_flush_tlb_mm() for forking  parent,
  71          *       first need to destroy the context, setting it to invalid
  72          *       value.
  73          */
  74         if (!((mm->context.asid ^ asid_cache) & MM_CTXT_CYCLE_MASK))
  75                 goto set_hw;
  76
  77         /* move to new ASID and handle rollover */
  78         if (unlikely(!(++asid_cache & MM_CTXT_ASID_MASK))) {
  79
  80                 flush_tlb_all();
  81
  82                 /*
  83                  * Above checke for rollover of 8 bit ASID in 32 bit container.
  84                  * If the container itself wrapped around, set it to a non zero
  85                  * "generation" to distinguish from no context
  86                  */
  87                 if (!asid_cache)
  88                         asid_cache = MM_CTXT_FIRST_CYCLE;
  89         }
  90
  91         /* Assign new ASID to tsk */
  92         mm->context.asid = asid_cache;
  93
  94 set_hw:
  95         write_aux_reg(ARC_REG_PID, hw_pid(mm) | MMU_ENABLE);
  96
  97         local_irq_restore(flags);
  98 }
  99
 100 /*
 101  * Initialize the context related info for a new mm_struct
 102  * instance.
 103  */
 104 static inline int
 105 init_new_context(struct task_struct *tsk, struct mm_struct *mm)
 106 {
 107         mm->context.asid = MM_CTXT_NO_ASID;
 108         return 0;
 109 }
 110
 111 /* Prepare the MMU for task: setup PID reg with allocated ASID
 112     If task doesn't have an ASID (never alloc or stolen, get a new ASID)
 113 */
 114 static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
 115                              struct task_struct *tsk)
 116 {
 117 #ifndef CONFIG_SMP
 118         /* PGD cached in MMU reg to avoid 3 mem lookups: task->mm->pgd */
 119         write_aux_reg(ARC_REG_SCRATCH_DATA0, next->pgd);
 120 #endif
 121
 122         get_new_mmu_context(next);
 123 }
 124
 125 /*
 126  * Called at the time of execve() to get a new ASID
 127  * Note the subtlety here: get_new_mmu_context() behaves differently here
 128  * vs. in switch_mm(). Here it always returns a new ASID, because mm has
 129  * an unallocated "initial" value, while in latter, it moves to a new ASID,
 130  * only if it was unallocated
 131  */
 132 #define activate_mm(prev, next)         switch_mm(prev, next, NULL)
 133
 134 static inline void destroy_context(struct mm_struct *mm)
 135 {
 136         mm->context.asid = MM_CTXT_NO_ASID;
 137 }
 138
 139 /* it seemed that deactivate_mm( ) is a reasonable place to do book-keeping
 140  * for retiring-mm. However destroy_context( ) still needs to do that because
 141  * between mm_release( ) = >deactive_mm( ) and
 142  * mmput => .. => __mmdrop( ) => destroy_context( )
 143  * there is a good chance that task gets sched-out/in, making it's ASID valid
 144  * again (this teased me for a whole day).
 145  */
 146 #define deactivate_mm(tsk, mm)   do { } while (0)
 147
 148 #define enter_lazy_tlb(mm, tsk)
 149
 150 #endif /* __ASM_ARC_MMU_CONTEXT_H */