arch/arc/kernel/intc-arcv2.c

   1 /*
   2  * Copyright (C) 2014 Synopsys, Inc. (www.synopsys.com)
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  */
   9
  10 #include <linux/interrupt.h>
  11 #include <linux/module.h>
  12 #include <linux/of.h>
  13 #include <linux/irqdomain.h>
  14 #include <linux/irqchip.h>
  15 #include "../../drivers/irqchip/irqchip.h"
  16 #include <asm/irq.h>
  17
  18 /*
  19  * Early Hardware specific Interrupt setup
  20  * -Called very early (start_kernel -> setup_arch -> setup_processor)
  21  * -Platform Independent (must for any ARC Core)
  22  * -Needed for each CPU (hence not foldable into init_IRQ)
  23  */
  24 void arc_init_IRQ(void)
  25 {
  26         unsigned int tmp;
  27
  28         struct aux_irq_ctrl {
  29 #ifdef CONFIG_CPU_BIG_ENDIAN
  30                 unsigned int res3:18, save_idx_regs:1, res2:1,
  31                              save_u_to_u:1, save_lp_regs:1, save_blink:1,
  32                              res:4, save_nr_gpr_pairs:5;
  33 #else
  34                 unsigned int save_nr_gpr_pairs:5, res:4,
  35                              save_blink:1, save_lp_regs:1, save_u_to_u:1,
  36                              res2:1, save_idx_regs:1, res3:18;
  37 #endif
  38         } ictrl;
  39
  40         *(unsigned int *)&ictrl = 0;
  41
  42         ictrl.save_nr_gpr_pairs = 6;    /* r0 to r11 (r12 saved manually) */
  43         ictrl.save_blink = 1;
  44         ictrl.save_lp_regs = 1;         /* LP_COUNT, LP_START, LP_END */
  45         ictrl.save_u_to_u = 0;          /* user ctxt saved on kernel stack */
  46         ictrl.save_idx_regs = 1;        /* JLI, LDI, EI */
  47
  48         WRITE_AUX(AUX_IRQ_CTRL, ictrl);
  49
  50         /* setup status32, don't enable intr yet as kernel doesn't want */
  51         tmp = read_aux_reg(0xa);
  52         tmp |= ISA_INIT_STATUS_BITS;
  53         tmp &= ~STATUS_IE_MASK;
  54         asm volatile("flag %0   \n"::"r"(tmp));
  55
  56         /*
  57          * ARCv2 core intc provides multiple interrupt priorities (upto 16).
  58          * Typical builds though have only two levels (0-high, 1-low)
  59          * Linux by default uses lower prio 1 for most irqs, reserving 0 for
  60          * NMI style interrupts in future (say perf)
  61          *
  62          * Read the intc BCR to confirm that Linux default priority is avail
  63          * in h/w
  64          *
  65          * Note:
  66          *  IRQ_BCR[27..24] contains N-1 (for N priority levels) and prio level
  67          *  is 0 based.
  68          */
  69         tmp = (read_aux_reg(ARC_REG_IRQ_BCR) >> 24 ) & 0xF;
  70         if (ARCV2_IRQ_DEF_PRIO > tmp)
  71                 panic("Linux default irq prio incorrect\n");
  72 }
  73
  74 static void arcv2_irq_mask(struct irq_data *data)
  75 {
  76         write_aux_reg(AUX_IRQ_SELECT, data->irq);
  77         write_aux_reg(AUX_IRQ_ENABLE, 0);
  78 }
  79
  80 static void arcv2_irq_unmask(struct irq_data *data)
  81 {
  82         write_aux_reg(AUX_IRQ_SELECT, data->irq);
  83         write_aux_reg(AUX_IRQ_ENABLE, 1);
  84 }
  85
  86 void arcv2_irq_enable(struct irq_data *data)
  87 {
  88         /* set default priority */
  89         write_aux_reg(AUX_IRQ_SELECT, data->irq);
  90         write_aux_reg(AUX_IRQ_PRIORITY, ARCV2_IRQ_DEF_PRIO);
  91
  92         /*
  93          * hw auto enables (linux unmask) all by default
  94          * So no need to do IRQ_ENABLE here
  95          * XXX: However OSCI LAN need it
  96          */
  97         write_aux_reg(AUX_IRQ_ENABLE, 1);
  98 }
  99
 100 static struct irq_chip arcv2_irq_chip = {
 101         .name           = "ARCv2 core Intc",
 102         .irq_mask       = arcv2_irq_mask,
 103         .irq_unmask     = arcv2_irq_unmask,
 104         .irq_enable     = arcv2_irq_enable
 105 };
 106
 107 static int arcv2_irq_map(struct irq_domain *d, unsigned int irq,
 108                          irq_hw_number_t hw)
 109 {
 110         if (irq == TIMER0_IRQ || irq == IPI_IRQ)
 111                 irq_set_chip_and_handler(irq, &arcv2_irq_chip, handle_percpu_irq);
 112         else
 113                 irq_set_chip_and_handler(irq, &arcv2_irq_chip, handle_level_irq);
 114
 115         return 0;
 116 }
 117
 118 static const struct irq_domain_ops arcv2_irq_ops = {
 119         .xlate = irq_domain_xlate_onecell,
 120         .map = arcv2_irq_map,
 121 };
 122
 123 static struct irq_domain *root_domain;
 124
 125 static int __init
 126 init_onchip_IRQ(struct device_node *intc, struct device_node *parent)
 127 {
 128         if (parent)
 129                 panic("DeviceTree incore intc not a root irq controller\n");
 130
 131         root_domain = irq_domain_add_legacy(intc, NR_CPU_IRQS, 0, 0,
 132                                             &arcv2_irq_ops, NULL);
 133
 134         if (!root_domain)
 135                 panic("root irq domain not avail\n");
 136
 137         /* with this we don't need to export root_domain */
 138         irq_set_default_host(root_domain);
 139
 140         return 0;
 141 }
 142
 143 IRQCHIP_DECLARE(arc_intc, "snps,archs-intc", init_onchip_IRQ);