arch/arc/kernel/irq.c

   1 /*
   2  * Copyright (C) 2011-12 Synopsys, Inc. (www.synopsys.com)
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  */
   9
  10 #include <linux/interrupt.h>
  11 #include <linux/module.h>
  12 #include <linux/of.h>
  13 #include <linux/irqdomain.h>
  14 #include <linux/irqchip.h>
  15 #include "../../drivers/irqchip/irqchip.h"
  16 #include <asm/sections.h>
  17 #include <asm/irq.h>
  18 #include <asm/mach_desc.h>
  19
  20 /*
  21  * Early Hardware specific Interrupt setup
  22  * -Called very early (start_kernel -> setup_arch -> setup_processor)
  23  * -Platform Independent (must for any ARC700)
  24  * -Needed for each CPU (hence not foldable into init_IRQ)
  25  *
  26  * what it does ?
  27  * -Disable all IRQs (on CPU side)
  28  * -Optionally, setup the High priority Interrupts as Level 2 IRQs
  29  */
  30 void arc_init_IRQ(void)
  31 {
  32         int level_mask = 0;
  33
  34         /* Disable all IRQs: enable them as devices request */
  35         write_aux_reg(AUX_IENABLE, 0);
  36
  37        /* setup any high priority Interrupts (Level2 in ARCompact jargon) */
  38         level_mask |= IS_ENABLED(CONFIG_ARC_IRQ3_LV2) << 3;
  39         level_mask |= IS_ENABLED(CONFIG_ARC_IRQ5_LV2) << 5;
  40         level_mask |= IS_ENABLED(CONFIG_ARC_IRQ6_LV2) << 6;
  41
  42         if (level_mask) {
  43                 pr_info("Level-2 interrupts bitset %x\n", level_mask);
  44                 write_aux_reg(AUX_IRQ_LEV, level_mask);
  45         }
  46 }
  47
  48 /*
  49  * ARC700 core includes a simple on-chip intc supporting
  50  * -per IRQ enable/disable
  51  * -2 levels of interrupts (high/low)
  52  * -all interrupts being level triggered
  53  *
  54  * To reduce platform code, we assume all IRQs directly hooked-up into intc.
  55  * Platforms with external intc, hence cascaded IRQs, are free to over-ride
  56  * below, per IRQ.
  57  */
  58
  59 static void arc_mask_irq(struct irq_data *data)
  60 {
  61         arch_mask_irq(data->irq);
  62 }
  63
  64 static void arc_unmask_irq(struct irq_data *data)
  65 {
  66         arch_unmask_irq(data->irq);
  67 }
  68
  69 static struct irq_chip onchip_intc = {
  70         .name           = "ARC In-core Intc",
  71         .irq_mask       = arc_mask_irq,
  72         .irq_unmask     = arc_unmask_irq,
  73 };
  74
  75 static int arc_intc_domain_map(struct irq_domain *d, unsigned int irq,
  76                                 irq_hw_number_t hw)
  77 {
  78         if (irq == TIMER0_IRQ)
  79                 irq_set_chip_and_handler(irq, &onchip_intc, handle_percpu_irq);
  80         else
  81                 irq_set_chip_and_handler(irq, &onchip_intc, handle_level_irq);
  82
  83         return 0;
  84 }
  85
  86 static const struct irq_domain_ops arc_intc_domain_ops = {
  87         .xlate = irq_domain_xlate_onecell,
  88         .map = arc_intc_domain_map,
  89 };
  90
  91 static struct irq_domain *root_domain;
  92
  93 static int __init
  94 init_onchip_IRQ(struct device_node *intc, struct device_node *parent)
  95 {
  96         if (parent)
  97                 panic("DeviceTree incore intc not a root irq controller\n");
  98
  99         root_domain = irq_domain_add_legacy(intc, NR_CPU_IRQS, 0, 0,
 100                                             &arc_intc_domain_ops, NULL);
 101
 102         if (!root_domain)
 103                 panic("root irq domain not avail\n");
 104
 105         /* with this we don't need to export root_domain */
 106         irq_set_default_host(root_domain);
 107
 108         return 0;
 109 }
 110
 111 IRQCHIP_DECLARE(arc_intc, "snps,arc700-intc", init_onchip_IRQ);
 112
 113 /*
 114  * Late Interrupt system init called from start_kernel for Boot CPU only
 115  *
 116  * Since slab must already be initialized, platforms can start doing any
 117  * needed request_irq( )s
 118  */
 119 void __init init_IRQ(void)
 120 {
 121         /* Any external intc can be setup here */
 122         if (machine_desc->init_irq)
 123                 machine_desc->init_irq();
 124
 125         /* process the entire interrupt tree in one go */
 126         irqchip_init();
 127
 128 #ifdef CONFIG_SMP
 129         /* Master CPU can initialize it's side of IPI */
 130         if (machine_desc->init_smp)
 131                 machine_desc->init_smp(smp_processor_id());
 132 #endif
 133 }
 134
 135 /*
 136  * "C" Entry point for any ARC ISR, called from low level vector handler
 137  * @irq is the vector number read from ICAUSE reg of on-chip intc
 138  */
 139 void arch_do_IRQ(unsigned int irq, struct pt_regs *regs)
 140 {
 141         struct pt_regs *old_regs = set_irq_regs(regs);
 142
 143         irq_enter();
 144         generic_handle_irq(irq);
 145         irq_exit();
 146         set_irq_regs(old_regs);
 147 }
 148
 149 int __init get_hw_config_num_irq(void)
 150 {
 151         uint32_t val = read_aux_reg(ARC_REG_VECBASE_BCR);
 152
 153         switch (val & 0x03) {
 154         case 0:
 155                 return 16;
 156         case 1:
 157                 return 32;
 158         case 2:
 159                 return 8;
 160         default:
 161                 return 0;
 162         }
 163
 164         return 0;
 165 }
 166
 167 /*
 168  * arch_local_irq_enable - Enable interrupts.
 169  *
 170  * 1. Explicitly called to re-enable interrupts
 171  * 2. Implicitly called from spin_unlock_irq, write_unlock_irq etc
 172  *    which maybe in hard ISR itself
 173  *
 174  * Semantics of this function change depending on where it is called from:
 175  *
 176  * -If called from hard-ISR, it must not invert interrupt priorities
 177  *  e.g. suppose TIMER is high priority (Level 2) IRQ
 178  *    Time hard-ISR, timer_interrupt( ) calls spin_unlock_irq several times.
 179  *    Here local_irq_enable( ) shd not re-enable lower priority interrupts
 180  * -If called from soft-ISR, it must re-enable all interrupts
 181  *    soft ISR are low prioity jobs which can be very slow, thus all IRQs
 182  *    must be enabled while they run.
 183  *    Now hardware context wise we may still be in L2 ISR (not done rtie)
 184  *    still we must re-enable both L1 and L2 IRQs
 185  *  Another twist is prev scenario with flow being
 186  *     L1 ISR ==> interrupted by L2 ISR  ==> L2 soft ISR
 187  *     here we must not re-enable Ll as prev Ll Interrupt's h/w context will get
 188  *     over-written (this is deficiency in ARC700 Interrupt mechanism)
 189  */
 190
 191 #ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS    /* Complex version for 2 IRQ levels */
 192
 193 void arch_local_irq_enable(void)
 194 {
 195
 196         unsigned long flags;
 197         flags = arch_local_save_flags();
 198
 199         /* Allow both L1 and L2 at the onset */
 200         flags |= (STATUS_E1_MASK | STATUS_E2_MASK);
 201
 202         /* Called from hard ISR (between irq_enter and irq_exit) */
 203         if (in_irq()) {
 204
 205                 /* If in L2 ISR, don't re-enable any further IRQs as this can
 206                  * cause IRQ priorities to get upside down. e.g. it could allow
 207                  * L1 be taken while in L2 hard ISR which is wrong not only in
 208                  * theory, it can also cause the dreaded L1-L2-L1 scenario
 209                  */
 210                 if (flags & STATUS_A2_MASK)
 211                         flags &= ~(STATUS_E1_MASK | STATUS_E2_MASK);
 212
 213                 /* Even if in L1 ISR, allowe Higher prio L2 IRQs */
 214                 else if (flags & STATUS_A1_MASK)
 215                         flags &= ~(STATUS_E1_MASK);
 216         }
 217
 218         /* called from soft IRQ, ideally we want to re-enable all levels */
 219
 220         else if (in_softirq()) {
 221
 222                 /* However if this is case of L1 interrupted by L2,
 223                  * re-enabling both may cause whaco L1-L2-L1 scenario
 224                  * because ARC700 allows level 1 to interrupt an active L2 ISR
 225                  * Thus we disable both
 226                  * However some code, executing in soft ISR wants some IRQs
 227                  * to be enabled so we re-enable L2 only
 228                  *
 229                  * How do we determine L1 intr by L2
 230                  *  -A2 is set (means in L2 ISR)
 231                  *  -E1 is set in this ISR's pt_regs->status32 which is
 232                  *      saved copy of status32_l2 when l2 ISR happened
 233                  */
 234                 struct pt_regs *pt = get_irq_regs();
 235                 if ((flags & STATUS_A2_MASK) && pt &&
 236                     (pt->status32 & STATUS_A1_MASK)) {
 237                         /*flags &= ~(STATUS_E1_MASK | STATUS_E2_MASK); */
 238                         flags &= ~(STATUS_E1_MASK);
 239                 }
 240         }
 241
 242         arch_local_irq_restore(flags);
 243 }
 244
 245 #else /* ! CONFIG_ARC_COMPACT_IRQ_LEVELS */
 246
 247 /*
 248  * Simpler version for only 1 level of interrupt
 249  * Here we only Worry about Level 1 Bits
 250  */
 251 void arch_local_irq_enable(void)
 252 {
 253         unsigned long flags;
 254
 255         /*
 256          * ARC IDE Drivers tries to re-enable interrupts from hard-isr
 257          * context which is simply wrong
 258          */
 259         if (in_irq()) {
 260                 WARN_ONCE(1, "IRQ enabled from hard-isr");
 261                 return;
 262         }
 263
 264         flags = arch_local_save_flags();
 265         flags |= (STATUS_E1_MASK | STATUS_E2_MASK);
 266         arch_local_irq_restore(flags);
 267 }
 268 #endif
 269 EXPORT_SYMBOL(arch_local_irq_enable);