2 * ARC700 VIPT Cache Management
4 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * vineetg: May 2011: for Non-aliasing VIPT D-cache following can be NOPs
11 * -flush_cache_dup_mm (fork)
12 * -likewise for flush_cache_mm (exit/execve)
13 * -likewise for flush_cache_range,flush_cache_page (munmap, exit, COW-break)
16 * -Now that MMU can support larger pg sz (16K), the determiniation of
17 * aliasing shd not be based on assumption of 8k pg
20 * -optimised version of flush_icache_range( ) for making I/D coherent
21 * when vaddr is available (agnostic of num of aliases)
24 * -Added documentation about I-cache aliasing on ARC700 and the way it
25 * was handled up until MMU V2.
26 * -Spotted a three year old bug when killing the 4 aliases, which needs
27 * bottom 2 bits, so we need to do paddr | {0x00, 0x01, 0x02, 0x03}
28 * instead of paddr | {0x00, 0x01, 0x10, 0x11}
29 * (Rajesh you owe me one now)
32 * -Off-by-one error when computing num_of_lines to flush
33 * This broke signal handling with bionic which uses synthetic sigret stub
36 * -GCC can't generate ZOL for core cache flush loops.
37 * Conv them into iterations based as opposed to while (start < end) types
40 * -In I-cache flush routine we used to chk for aliasing for every line INV.
41 * Instead now we setup routines per cache geometry and invoke them
42 * via function pointers.
45 * -Cache Line flush routines used to flush an extra line beyond end addr
46 * because check was while (end >= start) instead of (end > start)
47 * =Some call sites had to work around by doing -1, -4 etc to end param
48 * =Some callers didnt care. This was spec bad in case of INV routines
49 * which would discard valid data (cause of the horrible ext2 bug
52 * vineetg: June 11th 2008: Fixed flush_icache_range( )
53 * -Since ARC700 caches are not coherent (I$ doesnt snoop D$) both need
54 * to be flushed, which it was not doing.
55 * -load_module( ) passes vmalloc addr (Kernel Virtual Addr) to the API,
56 * however ARC cache maintenance OPs require PHY addr. Thus need to do
58 * -Also added optimisation there, that for range > PAGE SIZE we flush the
59 * entire cache in one shot rather than line by line. For e.g. a module
60 * with Code sz 600k, old code flushed 600k worth of cache (line-by-line),
61 * while cache is only 16 or 32k.
64 #include <linux/module.h>
66 #include <linux/sched.h>
67 #include <linux/cache.h>
68 #include <linux/mmu_context.h>
69 #include <linux/syscalls.h>
70 #include <linux/uaccess.h>
71 #include <linux/pagemap.h>
72 #include <asm/cacheflush.h>
73 #include <asm/cachectl.h>
74 #include <asm/setup.h>
76 /* Instruction cache related Auxiliary registers */
77 #define ARC_REG_IC_BCR 0x77 /* Build Config reg */
78 #define ARC_REG_IC_IVIC 0x10
79 #define ARC_REG_IC_CTRL 0x11
80 #define ARC_REG_IC_IVIL 0x19
81 #if (CONFIG_ARC_MMU_VER > 2)
82 #define ARC_REG_IC_PTAG 0x1E
85 /* Bit val in IC_CTRL */
86 #define IC_CTRL_CACHE_DISABLE 0x1
88 /* Data cache related Auxiliary registers */
89 #define ARC_REG_DC_BCR 0x72 /* Build Config reg */
90 #define ARC_REG_DC_IVDC 0x47
91 #define ARC_REG_DC_CTRL 0x48
92 #define ARC_REG_DC_IVDL 0x4A
93 #define ARC_REG_DC_FLSH 0x4B
94 #define ARC_REG_DC_FLDL 0x4C
95 #if (CONFIG_ARC_MMU_VER > 2)
96 #define ARC_REG_DC_PTAG 0x5C
99 /* Bit val in DC_CTRL */
100 #define DC_CTRL_INV_MODE_FLUSH 0x40
101 #define DC_CTRL_FLUSH_STATUS 0x100
103 char *arc_cache_mumbojumbo(int cpu_id
, char *buf
, int len
)
106 unsigned int c
= smp_processor_id();
108 #define PR_CACHE(p, enb, str) \
111 n += scnprintf(buf + n, len - n, str"\t\t: N/A\n"); \
113 n += scnprintf(buf + n, len - n, \
114 str"\t\t: (%uK) VIPT, %dway set-asc, %ub Line %s\n", \
115 TO_KB((p)->sz), (p)->assoc, (p)->line_len, \
116 enb ? "" : "DISABLED (kernel-build)"); \
119 PR_CACHE(&cpuinfo_arc700
[c
].icache
, IS_ENABLED(CONFIG_ARC_HAS_ICACHE
),
121 PR_CACHE(&cpuinfo_arc700
[c
].dcache
, IS_ENABLED(CONFIG_ARC_HAS_DCACHE
),
128 * Read the Cache Build Confuration Registers, Decode them and save into
129 * the cpuinfo structure for later use.
130 * No Validation done here, simply read/convert the BCRs
132 void __cpuinit
read_decode_cache_bcr(void)
134 struct cpuinfo_arc_cache
*p_ic
, *p_dc
;
135 unsigned int cpu
= smp_processor_id();
137 #ifdef CONFIG_CPU_BIG_ENDIAN
138 unsigned int pad
:12, line_len
:4, sz
:4, config
:4, ver
:8;
140 unsigned int ver
:8, config
:4, sz
:4, line_len
:4, pad
:12;
144 p_ic
= &cpuinfo_arc700
[cpu
].icache
;
145 READ_BCR(ARC_REG_IC_BCR
, ibcr
);
147 if (ibcr
.config
== 0x3)
149 p_ic
->line_len
= 8 << ibcr
.line_len
;
150 p_ic
->sz
= 0x200 << ibcr
.sz
;
151 p_ic
->ver
= ibcr
.ver
;
153 p_dc
= &cpuinfo_arc700
[cpu
].dcache
;
154 READ_BCR(ARC_REG_DC_BCR
, dbcr
);
156 if (dbcr
.config
== 0x2)
158 p_dc
->line_len
= 16 << dbcr
.line_len
;
159 p_dc
->sz
= 0x200 << dbcr
.sz
;
160 p_dc
->ver
= dbcr
.ver
;
164 * 1. Validate the Cache Geomtery (compile time config matches hardware)
165 * 2. If I-cache suffers from aliasing, setup work arounds (difft flush rtn)
166 * (aliasing D-cache configurations are not supported YET)
167 * 3. Enable the Caches, setup default flush mode for D-Cache
168 * 3. Calculate the SHMLBA used by user space
170 void __cpuinit
arc_cache_init(void)
172 unsigned int cpu
= smp_processor_id();
173 struct cpuinfo_arc_cache
*ic
= &cpuinfo_arc700
[cpu
].icache
;
174 struct cpuinfo_arc_cache
*dc
= &cpuinfo_arc700
[cpu
].dcache
;
175 unsigned int dcache_does_alias
, temp
;
178 printk(arc_cache_mumbojumbo(0, str
, sizeof(str
)));
183 #ifdef CONFIG_ARC_HAS_ICACHE
184 /* 1. Confirm some of I-cache params which Linux assumes */
185 if ((ic
->assoc
!= ARC_ICACHE_WAYS
) ||
186 (ic
->line_len
!= ARC_ICACHE_LINE_LEN
)) {
187 panic("Cache H/W doesn't match kernel Config");
189 #if (CONFIG_ARC_MMU_VER > 2)
192 panic("Cache ver doesn't match MMU ver\n");
194 /* For ISS - suggest the toggles to use */
195 pr_err("Use -prop=icache_version=3,-prop=dcache_version=3\n");
201 /* Enable/disable I-Cache */
202 temp
= read_aux_reg(ARC_REG_IC_CTRL
);
204 #ifdef CONFIG_ARC_HAS_ICACHE
205 temp
&= ~IC_CTRL_CACHE_DISABLE
;
207 temp
|= IC_CTRL_CACHE_DISABLE
;
210 write_aux_reg(ARC_REG_IC_CTRL
, temp
);
216 #ifdef CONFIG_ARC_HAS_DCACHE
217 if ((dc
->assoc
!= ARC_DCACHE_WAYS
) ||
218 (dc
->line_len
!= ARC_DCACHE_LINE_LEN
)) {
219 panic("Cache H/W doesn't match kernel Config");
222 dcache_does_alias
= (dc
->sz
/ ARC_DCACHE_WAYS
) > PAGE_SIZE
;
224 /* check for D-Cache aliasing */
225 if (dcache_does_alias
&& !cache_is_vipt_aliasing())
226 panic("Enable CONFIG_ARC_CACHE_VIPT_ALIASING\n");
227 else if (!dcache_does_alias
&& cache_is_vipt_aliasing())
228 panic("Don't need CONFIG_ARC_CACHE_VIPT_ALIASING\n");
231 /* Set the default Invalidate Mode to "simpy discard dirty lines"
232 * as this is more frequent then flush before invalidate
233 * Ofcourse we toggle this default behviour when desired
235 temp
= read_aux_reg(ARC_REG_DC_CTRL
);
236 temp
&= ~DC_CTRL_INV_MODE_FLUSH
;
238 #ifdef CONFIG_ARC_HAS_DCACHE
239 /* Enable D-Cache: Clear Bit 0 */
240 write_aux_reg(ARC_REG_DC_CTRL
, temp
& ~IC_CTRL_CACHE_DISABLE
);
243 write_aux_reg(ARC_REG_DC_FLSH
, 0x1);
244 /* Disable D cache */
245 write_aux_reg(ARC_REG_DC_CTRL
, temp
| IC_CTRL_CACHE_DISABLE
);
253 #define OP_FLUSH_N_INV 0x3
255 #ifdef CONFIG_ARC_HAS_DCACHE
257 /***************************************************************
258 * Machine specific helpers for Entire D-Cache or Per Line ops
261 static inline void wait_for_flush(void)
263 while (read_aux_reg(ARC_REG_DC_CTRL
) & DC_CTRL_FLUSH_STATUS
)
268 * Operation on Entire D-Cache
269 * @cacheop = {OP_INV, OP_FLUSH, OP_FLUSH_N_INV}
270 * Note that constant propagation ensures all the checks are gone
273 static inline void __dc_entire_op(const int cacheop
)
275 unsigned long flags
, tmp
= tmp
;
278 local_irq_save(flags
);
280 if (cacheop
== OP_FLUSH_N_INV
) {
281 /* Dcache provides 2 cmd: FLUSH or INV
282 * INV inturn has sub-modes: DISCARD or FLUSH-BEFORE
283 * flush-n-inv is achieved by INV cmd but with IM=1
284 * Default INV sub-mode is DISCARD, which needs to be toggled
286 tmp
= read_aux_reg(ARC_REG_DC_CTRL
);
287 write_aux_reg(ARC_REG_DC_CTRL
, tmp
| DC_CTRL_INV_MODE_FLUSH
);
290 if (cacheop
& OP_INV
) /* Inv or flush-n-inv use same cmd reg */
291 aux
= ARC_REG_DC_IVDC
;
293 aux
= ARC_REG_DC_FLSH
;
295 write_aux_reg(aux
, 0x1);
297 if (cacheop
& OP_FLUSH
) /* flush / flush-n-inv both wait */
300 /* Switch back the DISCARD ONLY Invalidate mode */
301 if (cacheop
== OP_FLUSH_N_INV
)
302 write_aux_reg(ARC_REG_DC_CTRL
, tmp
& ~DC_CTRL_INV_MODE_FLUSH
);
304 local_irq_restore(flags
);
308 * Per Line Operation on D-Cache
309 * Doesn't deal with type-of-op/IRQ-disabling/waiting-for-flush-to-complete
310 * It's sole purpose is to help gcc generate ZOL
311 * (aliasing VIPT dcache flushing needs both vaddr and paddr)
313 static inline void __dc_line_loop(unsigned long paddr
, unsigned long vaddr
,
314 unsigned long sz
, const int aux_reg
)
318 /* Ensure we properly floor/ceil the non-line aligned/sized requests
319 * and have @paddr - aligned to cache line and integral @num_lines.
320 * This however can be avoided for page sized since:
321 * -@paddr will be cache-line aligned already (being page aligned)
322 * -@sz will be integral multiple of line size (being page sized).
324 if (!(__builtin_constant_p(sz
) && sz
== PAGE_SIZE
)) {
325 sz
+= paddr
& ~DCACHE_LINE_MASK
;
326 paddr
&= DCACHE_LINE_MASK
;
327 vaddr
&= DCACHE_LINE_MASK
;
330 num_lines
= DIV_ROUND_UP(sz
, ARC_DCACHE_LINE_LEN
);
332 #if (CONFIG_ARC_MMU_VER <= 2)
333 paddr
|= (vaddr
>> PAGE_SHIFT
) & 0x1F;
336 while (num_lines
-- > 0) {
337 #if (CONFIG_ARC_MMU_VER > 2)
339 * Just as for I$, in MMU v3, D$ ops also require
340 * "tag" bits in DC_PTAG, "index" bits in FLDL,IVDL ops
342 write_aux_reg(ARC_REG_DC_PTAG
, paddr
);
344 write_aux_reg(aux_reg
, vaddr
);
345 vaddr
+= ARC_DCACHE_LINE_LEN
;
347 /* paddr contains stuffed vaddrs bits */
348 write_aux_reg(aux_reg
, paddr
);
350 paddr
+= ARC_DCACHE_LINE_LEN
;
354 /* For kernel mappings cache operation: index is same as paddr */
355 #define __dc_line_op_k(p, sz, op) __dc_line_op(p, p, sz, op)
358 * D-Cache : Per Line INV (discard or wback+discard) or FLUSH (wback)
360 static inline void __dc_line_op(unsigned long paddr
, unsigned long vaddr
,
361 unsigned long sz
, const int cacheop
)
363 unsigned long flags
, tmp
= tmp
;
366 local_irq_save(flags
);
368 if (cacheop
== OP_FLUSH_N_INV
) {
370 * Dcache provides 2 cmd: FLUSH or INV
371 * INV inturn has sub-modes: DISCARD or FLUSH-BEFORE
372 * flush-n-inv is achieved by INV cmd but with IM=1
373 * Default INV sub-mode is DISCARD, which needs to be toggled
375 tmp
= read_aux_reg(ARC_REG_DC_CTRL
);
376 write_aux_reg(ARC_REG_DC_CTRL
, tmp
| DC_CTRL_INV_MODE_FLUSH
);
379 if (cacheop
& OP_INV
) /* Inv / flush-n-inv use same cmd reg */
380 aux
= ARC_REG_DC_IVDL
;
382 aux
= ARC_REG_DC_FLDL
;
384 __dc_line_loop(paddr
, vaddr
, sz
, aux
);
386 if (cacheop
& OP_FLUSH
) /* flush / flush-n-inv both wait */
389 /* Switch back the DISCARD ONLY Invalidate mode */
390 if (cacheop
== OP_FLUSH_N_INV
)
391 write_aux_reg(ARC_REG_DC_CTRL
, tmp
& ~DC_CTRL_INV_MODE_FLUSH
);
393 local_irq_restore(flags
);
398 #define __dc_entire_op(cacheop)
399 #define __dc_line_op(paddr, vaddr, sz, cacheop)
400 #define __dc_line_op_k(paddr, sz, cacheop)
402 #endif /* CONFIG_ARC_HAS_DCACHE */
405 #ifdef CONFIG_ARC_HAS_ICACHE
408 * I-Cache Aliasing in ARC700 VIPT caches
410 * ARC VIPT I-cache uses vaddr to index into cache and paddr to match the tag.
411 * The orig Cache Management Module "CDU" only required paddr to invalidate a
412 * certain line since it sufficed as index in Non-Aliasing VIPT cache-geometry.
413 * Infact for distinct V1,V2,P: all of {V1-P},{V2-P},{P-P} would end up fetching
414 * the exact same line.
416 * However for larger Caches (way-size > page-size) - i.e. in Aliasing config,
417 * paddr alone could not be used to correctly index the cache.
420 * MMU v1/v2 (Fixed Page Size 8k)
422 * The solution was to provide CDU with these additonal vaddr bits. These
423 * would be bits [x:13], x would depend on cache-geometry, 13 comes from
424 * standard page size of 8k.
425 * H/w folks chose [17:13] to be a future safe range, and moreso these 5 bits
426 * of vaddr could easily be "stuffed" in the paddr as bits [4:0] since the
427 * orig 5 bits of paddr were anyways ignored by CDU line ops, as they
428 * represent the offset within cache-line. The adv of using this "clumsy"
429 * interface for additional info was no new reg was needed in CDU programming
432 * 17:13 represented the max num of bits passable, actual bits needed were
433 * fewer, based on the num-of-aliases possible.
434 * -for 2 alias possibility, only bit 13 needed (32K cache)
435 * -for 4 alias possibility, bits 14:13 needed (64K cache)
440 * This ver of MMU supports variable page sizes (1k-16k): although Linux will
441 * only support 8k (default), 16k and 4k.
442 * However from hardware perspective, smaller page sizes aggrevate aliasing
443 * meaning more vaddr bits needed to disambiguate the cache-line-op ;
444 * the existing scheme of piggybacking won't work for certain configurations.
445 * Two new registers IC_PTAG and DC_PTAG inttoduced.
446 * "tag" bits are provided in PTAG, index bits in existing IVIL/IVDL/FLDL regs
449 /***********************************************************
450 * Machine specific helper for per line I-Cache invalidate.
452 static void __ic_line_inv_vaddr(unsigned long paddr
, unsigned long vaddr
,
459 * Ensure we properly floor/ceil the non-line aligned/sized requests:
460 * However page sized flushes can be compile time optimised.
461 * -@paddr will be cache-line aligned already (being page aligned)
462 * -@sz will be integral multiple of line size (being page sized).
464 if (!(__builtin_constant_p(sz
) && sz
== PAGE_SIZE
)) {
465 sz
+= paddr
& ~ICACHE_LINE_MASK
;
466 paddr
&= ICACHE_LINE_MASK
;
467 vaddr
&= ICACHE_LINE_MASK
;
470 num_lines
= DIV_ROUND_UP(sz
, ARC_ICACHE_LINE_LEN
);
472 #if (CONFIG_ARC_MMU_VER <= 2)
473 /* bits 17:13 of vaddr go as bits 4:0 of paddr */
474 paddr
|= (vaddr
>> PAGE_SHIFT
) & 0x1F;
477 local_irq_save(flags
);
478 while (num_lines
-- > 0) {
479 #if (CONFIG_ARC_MMU_VER > 2)
480 /* tag comes from phy addr */
481 write_aux_reg(ARC_REG_IC_PTAG
, paddr
);
483 /* index bits come from vaddr */
484 write_aux_reg(ARC_REG_IC_IVIL
, vaddr
);
485 vaddr
+= ARC_ICACHE_LINE_LEN
;
487 /* paddr contains stuffed vaddrs bits */
488 write_aux_reg(ARC_REG_IC_IVIL
, paddr
);
490 paddr
+= ARC_ICACHE_LINE_LEN
;
492 local_irq_restore(flags
);
497 #define __ic_line_inv_vaddr(pstart, vstart, sz)
499 #endif /* CONFIG_ARC_HAS_ICACHE */
502 /***********************************************************
507 * Handle cache congruency of kernel and userspace mappings of page when kernel
508 * writes-to/reads-from
510 * The idea is to defer flushing of kernel mapping after a WRITE, possible if:
511 * -dcache is NOT aliasing, hence any U/K-mappings of page are congruent
512 * -U-mapping doesn't exist yet for page (finalised in update_mmu_cache)
513 * -In SMP, if hardware caches are coherent
515 * There's a corollary case, where kernel READs from a userspace mapped page.
516 * If the U-mapping is not congruent to to K-mapping, former needs flushing.
518 void flush_dcache_page(struct page
*page
)
520 struct address_space
*mapping
;
522 if (!cache_is_vipt_aliasing()) {
523 set_bit(PG_arch_1
, &page
->flags
);
527 /* don't handle anon pages here */
528 mapping
= page_mapping(page
);
533 * pagecache page, file not yet mapped to userspace
534 * Make a note that K-mapping is dirty
536 if (!mapping_mapped(mapping
)) {
537 set_bit(PG_arch_1
, &page
->flags
);
538 } else if (page_mapped(page
)) {
540 /* kernel reading from page with U-mapping */
541 void *paddr
= page_address(page
);
542 unsigned long vaddr
= page
->index
<< PAGE_CACHE_SHIFT
;
544 if (addr_not_cache_congruent(paddr
, vaddr
))
545 __flush_dcache_page(paddr
, vaddr
);
548 EXPORT_SYMBOL(flush_dcache_page
);
551 void dma_cache_wback_inv(unsigned long start
, unsigned long sz
)
553 __dc_line_op_k(start
, sz
, OP_FLUSH_N_INV
);
555 EXPORT_SYMBOL(dma_cache_wback_inv
);
557 void dma_cache_inv(unsigned long start
, unsigned long sz
)
559 __dc_line_op_k(start
, sz
, OP_INV
);
561 EXPORT_SYMBOL(dma_cache_inv
);
563 void dma_cache_wback(unsigned long start
, unsigned long sz
)
565 __dc_line_op_k(start
, sz
, OP_FLUSH
);
567 EXPORT_SYMBOL(dma_cache_wback
);
570 * This is API for making I/D Caches consistent when modifying
571 * kernel code (loadable modules, kprobes, kgdb...)
572 * This is called on insmod, with kernel virtual address for CODE of
573 * the module. ARC cache maintenance ops require PHY address thus we
574 * need to convert vmalloc addr to PHY addr
576 void flush_icache_range(unsigned long kstart
, unsigned long kend
)
578 unsigned int tot_sz
, off
, sz
;
579 unsigned long phy
, pfn
;
581 /* printk("Kernel Cache Cohenercy: %lx to %lx\n",kstart, kend); */
583 /* This is not the right API for user virtual address */
584 if (kstart
< TASK_SIZE
) {
585 BUG_ON("Flush icache range for user virtual addr space");
589 /* Shortcut for bigger flush ranges.
590 * Here we don't care if this was kernel virtual or phy addr
592 tot_sz
= kend
- kstart
;
593 if (tot_sz
> PAGE_SIZE
) {
598 /* Case: Kernel Phy addr (0x8000_0000 onwards) */
599 if (likely(kstart
> PAGE_OFFSET
)) {
601 * The 2nd arg despite being paddr will be used to index icache
602 * This is OK since no alternate virtual mappings will exist
603 * given the callers for this case: kprobe/kgdb in built-in
606 __sync_icache_dcache(kstart
, kstart
, kend
- kstart
);
611 * Case: Kernel Vaddr (0x7000_0000 to 0x7fff_ffff)
612 * (1) ARC Cache Maintenance ops only take Phy addr, hence special
613 * handling of kernel vaddr.
615 * (2) Despite @tot_sz being < PAGE_SIZE (bigger cases handled already),
616 * it still needs to handle a 2 page scenario, where the range
617 * straddles across 2 virtual pages and hence need for loop
620 off
= kstart
% PAGE_SIZE
;
621 pfn
= vmalloc_to_pfn((void *)kstart
);
622 phy
= (pfn
<< PAGE_SHIFT
) + off
;
623 sz
= min_t(unsigned int, tot_sz
, PAGE_SIZE
- off
);
624 __sync_icache_dcache(phy
, kstart
, sz
);
631 * General purpose helper to make I and D cache lines consistent.
632 * @paddr is phy addr of region
633 * @vaddr is typically user or kernel vaddr (vmalloc)
634 * Howver in one instance, flush_icache_range() by kprobe (for a breakpt in
635 * builtin kernel code) @vaddr will be paddr only, meaning CDU operation will
636 * use a paddr to index the cache (despite VIPT). This is fine since since a
637 * built-in kernel page will not have any virtual mappings (not even kernel)
638 * kprobe on loadable module is different as it will have kvaddr.
640 void __sync_icache_dcache(unsigned long paddr
, unsigned long vaddr
, int len
)
644 local_irq_save(flags
);
645 __ic_line_inv_vaddr(paddr
, vaddr
, len
);
646 __dc_line_op(paddr
, vaddr
, len
, OP_FLUSH_N_INV
);
647 local_irq_restore(flags
);
650 /* wrapper to compile time eliminate alignment checks in flush loop */
651 void __inv_icache_page(unsigned long paddr
, unsigned long vaddr
)
653 __ic_line_inv_vaddr(paddr
, vaddr
, PAGE_SIZE
);
657 * wrapper to clearout kernel or userspace mappings of a page
658 * For kernel mappings @vaddr == @paddr
660 void ___flush_dcache_page(unsigned long paddr
, unsigned long vaddr
)
662 __dc_line_op(paddr
, vaddr
& PAGE_MASK
, PAGE_SIZE
, OP_FLUSH_N_INV
);
665 void flush_icache_all(void)
669 local_irq_save(flags
);
671 write_aux_reg(ARC_REG_IC_IVIC
, 1);
673 /* lr will not complete till the icache inv operation is not over */
674 read_aux_reg(ARC_REG_IC_CTRL
);
675 local_irq_restore(flags
);
678 noinline
void flush_cache_all(void)
682 local_irq_save(flags
);
685 __dc_entire_op(OP_FLUSH_N_INV
);
687 local_irq_restore(flags
);
691 #ifdef CONFIG_ARC_CACHE_VIPT_ALIASING
693 void flush_cache_mm(struct mm_struct
*mm
)
698 void flush_cache_page(struct vm_area_struct
*vma
, unsigned long u_vaddr
,
701 unsigned int paddr
= pfn
<< PAGE_SHIFT
;
703 __sync_icache_dcache(paddr
, u_vaddr
, PAGE_SIZE
);
706 void flush_cache_range(struct vm_area_struct
*vma
, unsigned long start
,
712 void flush_anon_page(struct vm_area_struct
*vma
, struct page
*page
,
713 unsigned long u_vaddr
)
715 /* TBD: do we really need to clear the kernel mapping */
716 __flush_dcache_page(page_address(page
), u_vaddr
);
717 __flush_dcache_page(page_address(page
), page_address(page
));
723 void copy_user_highpage(struct page
*to
, struct page
*from
,
724 unsigned long u_vaddr
, struct vm_area_struct
*vma
)
726 void *kfrom
= page_address(from
);
727 void *kto
= page_address(to
);
728 int clean_src_k_mappings
= 0;
731 * If SRC page was already mapped in userspace AND it's U-mapping is
732 * not congruent with K-mapping, sync former to physical page so that
733 * K-mapping in memcpy below, sees the right data
735 * Note that while @u_vaddr refers to DST page's userspace vaddr, it is
736 * equally valid for SRC page as well
738 if (page_mapped(from
) && addr_not_cache_congruent(kfrom
, u_vaddr
)) {
739 __flush_dcache_page(kfrom
, u_vaddr
);
740 clean_src_k_mappings
= 1;
743 copy_page(kto
, kfrom
);
746 * Mark DST page K-mapping as dirty for a later finalization by
747 * update_mmu_cache(). Although the finalization could have been done
748 * here as well (given that both vaddr/paddr are available).
749 * But update_mmu_cache() already has code to do that for other
750 * non copied user pages (e.g. read faults which wire in pagecache page
753 set_bit(PG_arch_1
, &to
->flags
);
756 * if SRC was already usermapped and non-congruent to kernel mapping
757 * sync the kernel mapping back to physical page
759 if (clean_src_k_mappings
) {
760 __flush_dcache_page(kfrom
, kfrom
);
762 set_bit(PG_arch_1
, &from
->flags
);
766 void clear_user_page(void *to
, unsigned long u_vaddr
, struct page
*page
)
769 set_bit(PG_arch_1
, &page
->flags
);
773 /**********************************************************************
774 * Explicit Cache flush request from user space via syscall
775 * Needed for JITs which generate code on the fly
777 SYSCALL_DEFINE3(cacheflush
, uint32_t, start
, uint32_t, sz
, uint32_t, flags
)
779 /* TBD: optimize this */
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