2 * TLB Management (flush/create/diagnostics) for ARC700
4 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 * -Reintroduce duplicate PD fixup - some customer chips still have the issue
14 * -No need to flush_cache_page( ) for each call to update_mmu_cache()
15 * some of the LMBench tests improved amazingly
16 * = page-fault thrice as fast (75 usec to 28 usec)
17 * = mmap twice as fast (9.6 msec to 4.6 msec),
18 * = fork (5.3 msec to 3.7 msec)
20 * vineetg: April 2011 :
21 * -MMU v3: PD{0,1} bits layout changed: They don't overlap anymore,
22 * helps avoid a shift when preparing PD0 from PTE
24 * vineetg: April 2011 : Preparing for MMU V3
25 * -MMU v2/v3 BCRs decoded differently
26 * -Remove TLB_SIZE hardcoding as it's variable now: 256 or 512
27 * -tlb_entry_erase( ) can be void
28 * -local_flush_tlb_range( ):
29 * = need not "ceil" @end
30 * = walks MMU only if range spans < 32 entries, as opposed to 256
32 * Vineetg: Sept 10th 2008
33 * -Changes related to MMU v2 (Rel 4.8)
35 * Vineetg: Aug 29th 2008
36 * -In TLB Flush operations (Metal Fix MMU) there is a explict command to
37 * flush Micro-TLBS. If TLB Index Reg is invalid prior to TLBIVUTLB cmd,
38 * it fails. Thus need to load it with ANY valid value before invoking
41 * Vineetg: Aug 21th 2008:
42 * -Reduced the duration of IRQ lockouts in TLB Flush routines
43 * -Multiple copies of TLB erase code seperated into a "single" function
44 * -In TLB Flush routines, interrupt disabling moved UP to retrieve ASID
45 * in interrupt-safe region.
47 * Vineetg: April 23rd Bug #93131
48 * Problem: tlb_flush_kernel_range() doesnt do anything if the range to
49 * flush is more than the size of TLB itself.
51 * Rahul Trivedi : Codito Technologies 2004
54 #include <linux/module.h>
55 #include <asm/arcregs.h>
56 #include <asm/setup.h>
57 #include <asm/mmu_context.h>
60 /* Need for ARC MMU v2
62 * ARC700 MMU-v1 had a Joint-TLB for Code and Data and is 2 way set-assoc.
63 * For a memcpy operation with 3 players (src/dst/code) such that all 3 pages
64 * map into same set, there would be contention for the 2 ways causing severe
67 * Although J-TLB is 2 way set assoc, ARC700 caches J-TLB into uTLBS which has
68 * much higher associativity. u-D-TLB is 8 ways, u-I-TLB is 4 ways.
69 * Given this, the thrasing problem should never happen because once the 3
70 * J-TLB entries are created (even though 3rd will knock out one of the prev
71 * two), the u-D-TLB and u-I-TLB will have what is required to accomplish memcpy
73 * Yet we still see the Thrashing because a J-TLB Write cause flush of u-TLBs.
74 * This is a simple design for keeping them in sync. So what do we do?
75 * The solution which James came up was pretty neat. It utilised the assoc
76 * of uTLBs by not invalidating always but only when absolutely necessary.
78 * - Existing TLB commands work as before
79 * - New command (TLBWriteNI) for TLB write without clearing uTLBs
80 * - New command (TLBIVUTLB) to invalidate uTLBs.
82 * The uTLBs need only be invalidated when pages are being removed from the
83 * OS page table. If a 'victim' TLB entry is being overwritten in the main TLB
84 * as a result of a miss, the removed entry is still allowed to exist in the
85 * uTLBs as it is still valid and present in the OS page table. This allows the
86 * full associativity of the uTLBs to hide the limited associativity of the main
89 * During a miss handler, the new "TLBWriteNI" command is used to load
90 * entries without clearing the uTLBs.
92 * When the OS page table is updated, TLB entries that may be associated with a
93 * removed page are removed (flushed) from the TLB using TLBWrite. In this
94 * circumstance, the uTLBs must also be cleared. This is done by using the
95 * existing TLBWrite command. An explicit IVUTLB is also required for those
96 * corner cases when TLBWrite was not executed at all because the corresp
97 * J-TLB entry got evicted/replaced.
100 /* A copy of the ASID from the PID reg is kept in asid_cache */
101 int asid_cache
= FIRST_ASID
;
103 /* ASID to mm struct mapping. We have one extra entry corresponding to
104 * NO_ASID to save us a compare when clearing the mm entry for old asid
105 * see get_new_mmu_context (asm-arc/mmu_context.h)
107 struct mm_struct
*asid_mm_map
[NUM_ASID
+ 1];
110 * Utility Routine to erase a J-TLB entry
111 * The procedure is to look it up in the MMU. If found, ERASE it by
112 * issuing a TlbWrite CMD with PD0 = PD1 = 0
115 static void __tlb_entry_erase(void)
117 write_aux_reg(ARC_REG_TLBPD1
, 0);
118 write_aux_reg(ARC_REG_TLBPD0
, 0);
119 write_aux_reg(ARC_REG_TLBCOMMAND
, TLBWrite
);
122 static void tlb_entry_erase(unsigned int vaddr_n_asid
)
126 /* Locate the TLB entry for this vaddr + ASID */
127 write_aux_reg(ARC_REG_TLBPD0
, vaddr_n_asid
);
128 write_aux_reg(ARC_REG_TLBCOMMAND
, TLBProbe
);
129 idx
= read_aux_reg(ARC_REG_TLBINDEX
);
131 /* No error means entry found, zero it out */
132 if (likely(!(idx
& TLB_LKUP_ERR
))) {
134 } else { /* Some sort of Error */
136 /* Duplicate entry error */
138 /* TODO we need to handle this case too */
139 pr_emerg("unhandled Duplicate flush for %x\n",
142 /* else entry not found so nothing to do */
146 /****************************************************************************
147 * ARC700 MMU caches recently used J-TLB entries (RAM) as uTLBs (FLOPs)
149 * New IVUTLB cmd in MMU v2 explictly invalidates the uTLB
151 * utlb_invalidate ( )
152 * -For v2 MMU calls Flush uTLB Cmd
153 * -For v1 MMU does nothing (except for Metal Fix v1 MMU)
154 * This is because in v1 TLBWrite itself invalidate uTLBs
155 ***************************************************************************/
157 static void utlb_invalidate(void)
159 #if (CONFIG_ARC_MMU_VER >= 2)
161 #if (CONFIG_ARC_MMU_VER < 3)
162 /* MMU v2 introduced the uTLB Flush command.
163 * There was however an obscure hardware bug, where uTLB flush would
164 * fail when a prior probe for J-TLB (both totally unrelated) would
165 * return lkup err - because the entry didnt exist in MMU.
166 * The Workround was to set Index reg with some valid value, prior to
167 * flush. This was fixed in MMU v3 hence not needed any more
171 /* make sure INDEX Reg is valid */
172 idx
= read_aux_reg(ARC_REG_TLBINDEX
);
174 /* If not write some dummy val */
175 if (unlikely(idx
& TLB_LKUP_ERR
))
176 write_aux_reg(ARC_REG_TLBINDEX
, 0xa);
179 write_aux_reg(ARC_REG_TLBCOMMAND
, TLBIVUTLB
);
185 * Un-conditionally (without lookup) erase the entire MMU contents
188 noinline
void local_flush_tlb_all(void)
192 struct cpuinfo_arc_mmu
*mmu
= &cpuinfo_arc700
[smp_processor_id()].mmu
;
194 local_irq_save(flags
);
196 /* Load PD0 and PD1 with template for a Blank Entry */
197 write_aux_reg(ARC_REG_TLBPD1
, 0);
198 write_aux_reg(ARC_REG_TLBPD0
, 0);
200 for (entry
= 0; entry
< mmu
->num_tlb
; entry
++) {
201 /* write this entry to the TLB */
202 write_aux_reg(ARC_REG_TLBINDEX
, entry
);
203 write_aux_reg(ARC_REG_TLBCOMMAND
, TLBWrite
);
208 local_irq_restore(flags
);
212 * Flush the entrie MM for userland. The fastest way is to move to Next ASID
214 noinline
void local_flush_tlb_mm(struct mm_struct
*mm
)
217 * Small optimisation courtesy IA64
218 * flush_mm called during fork,exit,munmap etc, multiple times as well.
219 * Only for fork( ) do we need to move parent to a new MMU ctxt,
220 * all other cases are NOPs, hence this check.
222 if (atomic_read(&mm
->mm_users
) == 0)
226 * Workaround for Android weirdism:
227 * A binder VMA could end up in a task such that vma->mm != tsk->mm
228 * old code would cause h/w - s/w ASID to get out of sync
230 if (current
->mm
!= mm
)
233 get_new_mmu_context(mm
);
237 * Flush a Range of TLB entries for userland.
238 * @start is inclusive, while @end is exclusive
239 * Difference between this and Kernel Range Flush is
240 * -Here the fastest way (if range is too large) is to move to next ASID
241 * without doing any explicit Shootdown
242 * -In case of kernel Flush, entry has to be shot down explictly
244 void local_flush_tlb_range(struct vm_area_struct
*vma
, unsigned long start
,
250 /* If range @start to @end is more than 32 TLB entries deep,
251 * its better to move to a new ASID rather than searching for
252 * individual entries and then shooting them down
254 * The calc above is rough, doesn't account for unaligned parts,
255 * since this is heuristics based anyways
257 if (unlikely((end
- start
) >= PAGE_SIZE
* 32)) {
258 local_flush_tlb_mm(vma
->vm_mm
);
263 * @start moved to page start: this alone suffices for checking
264 * loop end condition below, w/o need for aligning @end to end
265 * e.g. 2000 to 4001 will anyhow loop twice
269 local_irq_save(flags
);
270 asid
= vma
->vm_mm
->context
.asid
;
272 if (asid
!= NO_ASID
) {
273 while (start
< end
) {
274 tlb_entry_erase(start
| (asid
& 0xff));
281 local_irq_restore(flags
);
284 /* Flush the kernel TLB entries - vmalloc/modules (Global from MMU perspective)
285 * @start, @end interpreted as kvaddr
286 * Interestingly, shared TLB entries can also be flushed using just
287 * @start,@end alone (interpreted as user vaddr), although technically SASID
288 * is also needed. However our smart TLbProbe lookup takes care of that.
290 void local_flush_tlb_kernel_range(unsigned long start
, unsigned long end
)
294 /* exactly same as above, except for TLB entry not taking ASID */
296 if (unlikely((end
- start
) >= PAGE_SIZE
* 32)) {
297 local_flush_tlb_all();
303 local_irq_save(flags
);
304 while (start
< end
) {
305 tlb_entry_erase(start
);
311 local_irq_restore(flags
);
315 * Delete TLB entry in MMU for a given page (??? address)
316 * NOTE One TLB entry contains translation for single PAGE
319 void local_flush_tlb_page(struct vm_area_struct
*vma
, unsigned long page
)
323 /* Note that it is critical that interrupts are DISABLED between
324 * checking the ASID and using it flush the TLB entry
326 local_irq_save(flags
);
328 if (vma
->vm_mm
->context
.asid
!= NO_ASID
) {
329 tlb_entry_erase((page
& PAGE_MASK
) |
330 (vma
->vm_mm
->context
.asid
& 0xff));
334 local_irq_restore(flags
);
338 * Routine to create a TLB entry
340 void create_tlb(struct vm_area_struct
*vma
, unsigned long address
, pte_t
*ptep
)
343 unsigned int idx
, asid_or_sasid
;
344 unsigned long pd0_flags
;
347 * create_tlb() assumes that current->mm == vma->mm, since
348 * -it ASID for TLB entry is fetched from MMU ASID reg (valid for curr)
349 * -completes the lazy write to SASID reg (again valid for curr tsk)
351 * Removing the assumption involves
352 * -Using vma->mm->context{ASID,SASID}, as opposed to MMU reg.
353 * -Fix the TLB paranoid debug code to not trigger false negatives.
354 * -More importantly it makes this handler inconsistent with fast-path
355 * TLB Refill handler which always deals with "current"
357 * Lets see the use cases when current->mm != vma->mm and we land here
358 * 1. execve->copy_strings()->__get_user_pages->handle_mm_fault
359 * Here VM wants to pre-install a TLB entry for user stack while
360 * current->mm still points to pre-execve mm (hence the condition).
361 * However the stack vaddr is soon relocated (randomization) and
362 * move_page_tables() tries to undo that TLB entry.
363 * Thus not creating TLB entry is not any worse.
365 * 2. ptrace(POKETEXT) causes a CoW - debugger(current) inserting a
366 * breakpoint in debugged task. Not creating a TLB now is not
367 * performance critical.
369 * Both the cases above are not good enough for code churn.
371 if (current
->active_mm
!= vma
->vm_mm
)
374 local_irq_save(flags
);
376 tlb_paranoid_check(vma
->vm_mm
->context
.asid
, address
);
378 address
&= PAGE_MASK
;
380 /* update this PTE credentials */
381 pte_val(*ptep
) |= (_PAGE_PRESENT
| _PAGE_ACCESSED
);
383 /* Create HW TLB entry Flags (in PD0) from PTE Flags */
384 #if (CONFIG_ARC_MMU_VER <= 2)
385 pd0_flags
= ((pte_val(*ptep
) & PTE_BITS_IN_PD0
) >> 1);
387 pd0_flags
= ((pte_val(*ptep
) & PTE_BITS_IN_PD0
));
390 /* ASID for this task */
391 asid_or_sasid
= read_aux_reg(ARC_REG_PID
) & 0xff;
393 write_aux_reg(ARC_REG_TLBPD0
, address
| pd0_flags
| asid_or_sasid
);
395 /* Load remaining info in PD1 (Page Frame Addr and Kx/Kw/Kr Flags) */
396 write_aux_reg(ARC_REG_TLBPD1
, (pte_val(*ptep
) & PTE_BITS_IN_PD1
));
398 /* First verify if entry for this vaddr+ASID already exists */
399 write_aux_reg(ARC_REG_TLBCOMMAND
, TLBProbe
);
400 idx
= read_aux_reg(ARC_REG_TLBINDEX
);
403 * If Not already present get a free slot from MMU.
404 * Otherwise, Probe would have located the entry and set INDEX Reg
405 * with existing location. This will cause Write CMD to over-write
406 * existing entry with new PD0 and PD1
408 if (likely(idx
& TLB_LKUP_ERR
))
409 write_aux_reg(ARC_REG_TLBCOMMAND
, TLBGetIndex
);
412 * Commit the Entry to MMU
413 * It doesnt sound safe to use the TLBWriteNI cmd here
414 * which doesn't flush uTLBs. I'd rather be safe than sorry.
416 write_aux_reg(ARC_REG_TLBCOMMAND
, TLBWrite
);
418 local_irq_restore(flags
);
422 * Called at the end of pagefault, for a userspace mapped page
423 * -pre-install the corresponding TLB entry into MMU
424 * -Finalize the delayed D-cache flush of kernel mapping of page due to
425 * flush_dcache_page(), copy_user_page()
427 * Note that flush (when done) involves both WBACK - so physical page is
428 * in sync as well as INV - so any non-congruent aliases don't remain
430 void update_mmu_cache(struct vm_area_struct
*vma
, unsigned long vaddr_unaligned
,
433 unsigned long vaddr
= vaddr_unaligned
& PAGE_MASK
;
434 unsigned long paddr
= pte_val(*ptep
) & PAGE_MASK
;
436 create_tlb(vma
, vaddr
, ptep
);
439 * Exec page : Independent of aliasing/page-color considerations,
440 * since icache doesn't snoop dcache on ARC, any dirty
441 * K-mapping of a code page needs to be wback+inv so that
442 * icache fetch by userspace sees code correctly.
443 * !EXEC page: If K-mapping is NOT congruent to U-mapping, flush it
444 * so userspace sees the right data.
445 * (Avoids the flush for Non-exec + congruent mapping case)
447 if (vma
->vm_flags
& VM_EXEC
|| addr_not_cache_congruent(paddr
, vaddr
)) {
448 struct page
*page
= pfn_to_page(pte_pfn(*ptep
));
450 int dirty
= test_and_clear_bit(PG_arch_1
, &page
->flags
);
452 /* wback + inv dcache lines */
453 __flush_dcache_page(paddr
, paddr
);
455 /* invalidate any existing icache lines */
456 if (vma
->vm_flags
& VM_EXEC
)
457 __inv_icache_page(paddr
, vaddr
);
462 /* Read the Cache Build Confuration Registers, Decode them and save into
463 * the cpuinfo structure for later use.
464 * No Validation is done here, simply read/convert the BCRs
466 void __cpuinit
read_decode_mmu_bcr(void)
469 struct bcr_mmu_1_2
*mmu2
; /* encoded MMU2 attr */
470 struct bcr_mmu_3
*mmu3
; /* encoded MMU3 attr */
471 struct cpuinfo_arc_mmu
*mmu
= &cpuinfo_arc700
[smp_processor_id()].mmu
;
473 tmp
= read_aux_reg(ARC_REG_MMU_BCR
);
474 mmu
->ver
= (tmp
>> 24);
477 mmu2
= (struct bcr_mmu_1_2
*)&tmp
;
478 mmu
->pg_sz
= PAGE_SIZE
;
479 mmu
->sets
= 1 << mmu2
->sets
;
480 mmu
->ways
= 1 << mmu2
->ways
;
481 mmu
->u_dtlb
= mmu2
->u_dtlb
;
482 mmu
->u_itlb
= mmu2
->u_itlb
;
484 mmu3
= (struct bcr_mmu_3
*)&tmp
;
485 mmu
->pg_sz
= 512 << mmu3
->pg_sz
;
486 mmu
->sets
= 1 << mmu3
->sets
;
487 mmu
->ways
= 1 << mmu3
->ways
;
488 mmu
->u_dtlb
= mmu3
->u_dtlb
;
489 mmu
->u_itlb
= mmu3
->u_itlb
;
492 mmu
->num_tlb
= mmu
->sets
* mmu
->ways
;
495 char *arc_mmu_mumbojumbo(int cpu_id
, char *buf
, int len
)
498 struct cpuinfo_arc_mmu
*p_mmu
= &cpuinfo_arc700
[cpu_id
].mmu
;
500 n
+= scnprintf(buf
+ n
, len
- n
, "ARC700 MMU [v%x]\t: %dk PAGE, ",
501 p_mmu
->ver
, TO_KB(p_mmu
->pg_sz
));
503 n
+= scnprintf(buf
+ n
, len
- n
,
504 "J-TLB %d (%dx%d), uDTLB %d, uITLB %d, %s\n",
505 p_mmu
->num_tlb
, p_mmu
->sets
, p_mmu
->ways
,
506 p_mmu
->u_dtlb
, p_mmu
->u_itlb
,
507 __CONFIG_ARC_MMU_SASID_VAL
? "SASID" : "");
512 void __cpuinit
arc_mmu_init(void)
515 struct cpuinfo_arc_mmu
*mmu
= &cpuinfo_arc700
[smp_processor_id()].mmu
;
517 printk(arc_mmu_mumbojumbo(0, str
, sizeof(str
)));
519 /* For efficiency sake, kernel is compile time built for a MMU ver
520 * This must match the hardware it is running on.
521 * Linux built for MMU V2, if run on MMU V1 will break down because V1
522 * hardware doesn't understand cmds such as WriteNI, or IVUTLB
523 * On the other hand, Linux built for V1 if run on MMU V2 will do
524 * un-needed workarounds to prevent memcpy thrashing.
525 * Similarly MMU V3 has new features which won't work on older MMU
527 if (mmu
->ver
!= CONFIG_ARC_MMU_VER
) {
528 panic("MMU ver %d doesn't match kernel built for %d...\n",
529 mmu
->ver
, CONFIG_ARC_MMU_VER
);
532 if (mmu
->pg_sz
!= PAGE_SIZE
)
533 panic("MMU pg size != PAGE_SIZE (%luk)\n", TO_KB(PAGE_SIZE
));
536 * ASID mgmt data structures are compile time init
537 * asid_cache = FIRST_ASID and asid_mm_map[] all zeroes
540 local_flush_tlb_all();
543 write_aux_reg(ARC_REG_PID
, MMU_ENABLE
);
545 /* In smp we use this reg for interrupt 1 scratch */
547 /* swapper_pg_dir is the pgd for the kernel, used by vmalloc */
548 write_aux_reg(ARC_REG_SCRATCH_DATA0
, swapper_pg_dir
);
553 * TLB Programmer's Model uses Linear Indexes: 0 to {255, 511} for 128 x {2,4}
554 * The mapping is Column-first.
555 * --------------------- -----------
556 * |way0|way1|way2|way3| |way0|way1|
557 * --------------------- -----------
558 * [set0] | 0 | 1 | 2 | 3 | | 0 | 1 |
559 * [set1] | 4 | 5 | 6 | 7 | | 2 | 3 |
561 * [set127] | 508| 509| 510| 511| | 254| 255|
562 * --------------------- -----------
563 * For normal operations we don't(must not) care how above works since
564 * MMU cmd getIndex(vaddr) abstracts that out.
565 * However for walking WAYS of a SET, we need to know this
567 #define SET_WAY_TO_IDX(mmu, set, way) ((set) * mmu->ways + (way))
569 /* Handling of Duplicate PD (TLB entry) in MMU.
570 * -Could be due to buggy customer tapeouts or obscure kernel bugs
571 * -MMU complaints not at the time of duplicate PD installation, but at the
572 * time of lookup matching multiple ways.
573 * -Ideally these should never happen - but if they do - workaround by deleting
575 * -Knob to be verbose abt it.(TODO: hook them up to debugfs)
577 volatile int dup_pd_verbose
= 1;/* Be slient abt it or complain (default) */
579 void do_tlb_overlap_fault(unsigned long cause
, unsigned long address
,
580 struct pt_regs
*regs
)
583 unsigned int pd0
[4], pd1
[4]; /* assume max 4 ways */
584 unsigned long flags
, is_valid
;
585 struct cpuinfo_arc_mmu
*mmu
= &cpuinfo_arc700
[smp_processor_id()].mmu
;
587 local_irq_save(flags
);
589 /* re-enable the MMU */
590 write_aux_reg(ARC_REG_PID
, MMU_ENABLE
| read_aux_reg(ARC_REG_PID
));
592 /* loop thru all sets of TLB */
593 for (set
= 0; set
< mmu
->sets
; set
++) {
595 /* read out all the ways of current set */
596 for (way
= 0, is_valid
= 0; way
< mmu
->ways
; way
++) {
597 write_aux_reg(ARC_REG_TLBINDEX
,
598 SET_WAY_TO_IDX(mmu
, set
, way
));
599 write_aux_reg(ARC_REG_TLBCOMMAND
, TLBRead
);
600 pd0
[way
] = read_aux_reg(ARC_REG_TLBPD0
);
601 pd1
[way
] = read_aux_reg(ARC_REG_TLBPD1
);
602 is_valid
|= pd0
[way
] & _PAGE_PRESENT
;
605 /* If all the WAYS in SET are empty, skip to next SET */
609 /* Scan the set for duplicate ways: needs a nested loop */
610 for (way
= 0; way
< mmu
->ways
; way
++) {
614 for (n
= way
+ 1; n
< mmu
->ways
; n
++) {
615 if ((pd0
[way
] & PAGE_MASK
) ==
616 (pd0
[n
] & PAGE_MASK
)) {
618 if (dup_pd_verbose
) {
619 pr_info("Duplicate PD's @"
622 pr_info("TLBPD0[%u]: %08x\n",
627 * clear entry @way and not @n. This is
628 * critical to our optimised loop
630 pd0
[way
] = pd1
[way
] = 0;
631 write_aux_reg(ARC_REG_TLBINDEX
,
632 SET_WAY_TO_IDX(mmu
, set
, way
));
639 local_irq_restore(flags
);
642 /***********************************************************************
643 * Diagnostic Routines
644 * -Called from Low Level TLB Hanlders if things don;t look good
645 **********************************************************************/
647 #ifdef CONFIG_ARC_DBG_TLB_PARANOIA
650 * Low Level ASM TLB handler calls this if it finds that HW and SW ASIDS
653 void print_asid_mismatch(int is_fast_path
)
656 pid_sw
= current
->active_mm
->context
.asid
;
657 pid_hw
= read_aux_reg(ARC_REG_PID
) & 0xff;
659 pr_emerg("ASID Mismatch in %s Path Handler: sw-pid=0x%x hw-pid=0x%x\n",
660 is_fast_path
? "Fast" : "Slow", pid_sw
, pid_hw
);
662 __asm__
__volatile__("flag 1");
665 void tlb_paranoid_check(unsigned int pid_sw
, unsigned long addr
)
669 pid_hw
= read_aux_reg(ARC_REG_PID
) & 0xff;
671 if (addr
< 0x70000000 && ((pid_hw
!= pid_sw
) || (pid_sw
== NO_ASID
)))
672 print_asid_mismatch(0);