arch/arm/Kconfig

   1 config ARM
   2         bool
   3         default y
   4         select HAVE_AOUT
   5         select HAVE_DMA_API_DEBUG
   6         select HAVE_IDE if PCI || ISA || PCMCIA
   7         select HAVE_MEMBLOCK
   8         select RTC_LIB
   9         select SYS_SUPPORTS_APM_EMULATION
  10         select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
  11         select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
  12         select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
  13         select HAVE_ARCH_KGDB
  14         select HAVE_ARCH_TRACEHOOK
  15         select HAVE_KPROBES if !XIP_KERNEL
  16         select HAVE_KRETPROBES if (HAVE_KPROBES)
  17         select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
  18         select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
  19         select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
  20         select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
  21         select ARCH_BINFMT_ELF_RANDOMIZE_PIE
  22         select HAVE_GENERIC_DMA_COHERENT
  23         select HAVE_KERNEL_GZIP
  24         select HAVE_KERNEL_LZO
  25         select HAVE_KERNEL_LZMA
  26         select HAVE_KERNEL_XZ
  27         select HAVE_IRQ_WORK
  28         select HAVE_PERF_EVENTS
  29         select PERF_USE_VMALLOC
  30         select HAVE_REGS_AND_STACK_ACCESS_API
  31         select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
  32         select HAVE_C_RECORDMCOUNT
  33         select HAVE_GENERIC_HARDIRQS
  34         select HARDIRQS_SW_RESEND
  35         select GENERIC_IRQ_PROBE
  36         select GENERIC_IRQ_SHOW
  37         select GENERIC_IRQ_PROBE
  38         select HARDIRQS_SW_RESEND
  39         select CPU_PM if (SUSPEND || CPU_IDLE)
  40         select GENERIC_PCI_IOMAP
  41         select HAVE_BPF_JIT
  42         select GENERIC_SMP_IDLE_THREAD
  43         help
  44           The ARM series is a line of low-power-consumption RISC chip designs
  45           licensed by ARM Ltd and targeted at embedded applications and
  46           handhelds such as the Compaq IPAQ.  ARM-based PCs are no longer
  47           manufactured, but legacy ARM-based PC hardware remains popular in
  48           Europe.  There is an ARM Linux project with a web page at
  49           <http://www.arm.linux.org.uk/>.
  50
  51 config ARM_HAS_SG_CHAIN
  52         bool
  53
  54 config HAVE_PWM
  55         bool
  56
  57 config MIGHT_HAVE_PCI
  58         bool
  59
  60 config SYS_SUPPORTS_APM_EMULATION
  61         bool
  62
  63 config GENERIC_GPIO
  64         bool
  65
  66 config ARCH_USES_GETTIMEOFFSET
  67         bool
  68         default n
  69
  70 config GENERIC_CLOCKEVENTS
  71         bool
  72
  73 config GENERIC_CLOCKEVENTS_BROADCAST
  74         bool
  75         depends on GENERIC_CLOCKEVENTS
  76         default y if SMP
  77
  78 config KTIME_SCALAR
  79         bool
  80         default y
  81
  82 config HAVE_TCM
  83         bool
  84         select GENERIC_ALLOCATOR
  85
  86 config HAVE_PROC_CPU
  87         bool
  88
  89 config NO_IOPORT
  90         bool
  91
  92 config EISA
  93         bool
  94         ---help---
  95           The Extended Industry Standard Architecture (EISA) bus was
  96           developed as an open alternative to the IBM MicroChannel bus.
  97
  98           The EISA bus provided some of the features of the IBM MicroChannel
  99           bus while maintaining backward compatibility with cards made for
 100           the older ISA bus.  The EISA bus saw limited use between 1988 and
 101           1995 when it was made obsolete by the PCI bus.
 102
 103           Say Y here if you are building a kernel for an EISA-based machine.
 104
 105           Otherwise, say N.
 106
 107 config SBUS
 108         bool
 109
 110 config MCA
 111         bool
 112         help
 113           MicroChannel Architecture is found in some IBM PS/2 machines and
 114           laptops.  It is a bus system similar to PCI or ISA. See
 115           <file:Documentation/mca.txt> (and especially the web page given
 116           there) before attempting to build an MCA bus kernel.
 117
 118 config STACKTRACE_SUPPORT
 119         bool
 120         default y
 121
 122 config HAVE_LATENCYTOP_SUPPORT
 123         bool
 124         depends on !SMP
 125         default y
 126
 127 config LOCKDEP_SUPPORT
 128         bool
 129         default y
 130
 131 config TRACE_IRQFLAGS_SUPPORT
 132         bool
 133         default y
 134
 135 config GENERIC_LOCKBREAK
 136         bool
 137         default y
 138         depends on SMP && PREEMPT
 139
 140 config RWSEM_GENERIC_SPINLOCK
 141         bool
 142         default y
 143
 144 config RWSEM_XCHGADD_ALGORITHM
 145         bool
 146
 147 config ARCH_HAS_ILOG2_U32
 148         bool
 149
 150 config ARCH_HAS_ILOG2_U64
 151         bool
 152
 153 config ARCH_HAS_CPUFREQ
 154         bool
 155         help
 156           Internal node to signify that the ARCH has CPUFREQ support
 157           and that the relevant menu configurations are displayed for
 158           it.
 159
 160 config GENERIC_HWEIGHT
 161         bool
 162         default y
 163
 164 config GENERIC_CALIBRATE_DELAY
 165         bool
 166         default y
 167
 168 config ARCH_MAY_HAVE_PC_FDC
 169         bool
 170
 171 config ZONE_DMA
 172         bool
 173
 174 config NEED_DMA_MAP_STATE
 175        def_bool y
 176
 177 config ARCH_HAS_DMA_SET_COHERENT_MASK
 178         bool
 179
 180 config GENERIC_ISA_DMA
 181         bool
 182
 183 config FIQ
 184         bool
 185
 186 config NEED_RET_TO_USER
 187         bool
 188
 189 config ARCH_MTD_XIP
 190         bool
 191
 192 config VECTORS_BASE
 193         hex
 194         default 0xffff0000 if MMU || CPU_HIGH_VECTOR
 195         default DRAM_BASE if REMAP_VECTORS_TO_RAM
 196         default 0x00000000
 197         help
 198           The base address of exception vectors.
 199
 200 config ARM_PATCH_PHYS_VIRT
 201         bool "Patch physical to virtual translations at runtime" if EMBEDDED
 202         default y
 203         depends on !XIP_KERNEL && MMU
 204         depends on !ARCH_REALVIEW || !SPARSEMEM
 205         help
 206           Patch phys-to-virt and virt-to-phys translation functions at
 207           boot and module load time according to the position of the
 208           kernel in system memory.
 209
 210           This can only be used with non-XIP MMU kernels where the base
 211           of physical memory is at a 16MB boundary.
 212
 213           Only disable this option if you know that you do not require
 214           this feature (eg, building a kernel for a single machine) and
 215           you need to shrink the kernel to the minimal size.
 216
 217 config NEED_MACH_IO_H
 218         bool
 219         help
 220           Select this when mach/io.h is required to provide special
 221           definitions for this platform.  The need for mach/io.h should
 222           be avoided when possible.
 223
 224 config NEED_MACH_MEMORY_H
 225         bool
 226         help
 227           Select this when mach/memory.h is required to provide special
 228           definitions for this platform.  The need for mach/memory.h should
 229           be avoided when possible.
 230
 231 config PHYS_OFFSET
 232         hex "Physical address of main memory" if MMU
 233         depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
 234         default DRAM_BASE if !MMU
 235         help
 236           Please provide the physical address corresponding to the
 237           location of main memory in your system.
 238
 239 config GENERIC_BUG
 240         def_bool y
 241         depends on BUG
 242
 243 source "init/Kconfig"
 244
 245 source "kernel/Kconfig.freezer"
 246
 247 menu "System Type"
 248
 249 config MMU
 250         bool "MMU-based Paged Memory Management Support"
 251         default y
 252         help
 253           Select if you want MMU-based virtualised addressing space
 254           support by paged memory management. If unsure, say 'Y'.
 255
 256 #
 257 # The "ARM system type" choice list is ordered alphabetically by option
 258 # text.  Please add new entries in the option alphabetic order.
 259 #
 260 choice
 261         prompt "ARM system type"
 262         default ARCH_VERSATILE
 263
 264 config ARCH_INTEGRATOR
 265         bool "ARM Ltd. Integrator family"
 266         select ARM_AMBA
 267         select ARCH_HAS_CPUFREQ
 268         select CLKDEV_LOOKUP
 269         select HAVE_MACH_CLKDEV
 270         select HAVE_TCM
 271         select ICST
 272         select GENERIC_CLOCKEVENTS
 273         select PLAT_VERSATILE
 274         select PLAT_VERSATILE_FPGA_IRQ
 275         select NEED_MACH_IO_H
 276         select NEED_MACH_MEMORY_H
 277         select SPARSE_IRQ
 278         select MULTI_IRQ_HANDLER
 279         help
 280           Support for ARM's Integrator platform.
 281
 282 config ARCH_REALVIEW
 283         bool "ARM Ltd. RealView family"
 284         select ARM_AMBA
 285         select CLKDEV_LOOKUP
 286         select HAVE_MACH_CLKDEV
 287         select ICST
 288         select GENERIC_CLOCKEVENTS
 289         select ARCH_WANT_OPTIONAL_GPIOLIB
 290         select PLAT_VERSATILE
 291         select PLAT_VERSATILE_CLCD
 292         select ARM_TIMER_SP804
 293         select GPIO_PL061 if GPIOLIB
 294         select NEED_MACH_MEMORY_H
 295         help
 296           This enables support for ARM Ltd RealView boards.
 297
 298 config ARCH_VERSATILE
 299         bool "ARM Ltd. Versatile family"
 300         select ARM_AMBA
 301         select ARM_VIC
 302         select CLKDEV_LOOKUP
 303         select HAVE_MACH_CLKDEV
 304         select ICST
 305         select GENERIC_CLOCKEVENTS
 306         select ARCH_WANT_OPTIONAL_GPIOLIB
 307         select PLAT_VERSATILE
 308         select PLAT_VERSATILE_CLCD
 309         select PLAT_VERSATILE_FPGA_IRQ
 310         select ARM_TIMER_SP804
 311         help
 312           This enables support for ARM Ltd Versatile board.
 313
 314 config ARCH_VEXPRESS
 315         bool "ARM Ltd. Versatile Express family"
 316         select ARCH_WANT_OPTIONAL_GPIOLIB
 317         select ARM_AMBA
 318         select ARM_TIMER_SP804
 319         select CLKDEV_LOOKUP
 320         select HAVE_MACH_CLKDEV
 321         select GENERIC_CLOCKEVENTS
 322         select HAVE_CLK
 323         select HAVE_PATA_PLATFORM
 324         select ICST
 325         select NO_IOPORT
 326         select PLAT_VERSATILE
 327         select PLAT_VERSATILE_CLCD
 328         help
 329           This enables support for the ARM Ltd Versatile Express boards.
 330
 331 config ARCH_AT91
 332         bool "Atmel AT91"
 333         select ARCH_REQUIRE_GPIOLIB
 334         select HAVE_CLK
 335         select CLKDEV_LOOKUP
 336         select IRQ_DOMAIN
 337         select NEED_MACH_IO_H if PCCARD
 338         help
 339           This enables support for systems based on the Atmel AT91RM9200,
 340           AT91SAM9 processors.
 341
 342 config ARCH_BCMRING
 343         bool "Broadcom BCMRING"
 344         depends on MMU
 345         select CPU_V6
 346         select ARM_AMBA
 347         select ARM_TIMER_SP804
 348         select CLKDEV_LOOKUP
 349         select GENERIC_CLOCKEVENTS
 350         select ARCH_WANT_OPTIONAL_GPIOLIB
 351         help
 352           Support for Broadcom's BCMRing platform.
 353
 354 config ARCH_HIGHBANK
 355         bool "Calxeda Highbank-based"
 356         select ARCH_WANT_OPTIONAL_GPIOLIB
 357         select ARM_AMBA
 358         select ARM_GIC
 359         select ARM_TIMER_SP804
 360         select CACHE_L2X0
 361         select CLKDEV_LOOKUP
 362         select CPU_V7
 363         select GENERIC_CLOCKEVENTS
 364         select HAVE_ARM_SCU
 365         select HAVE_SMP
 366         select SPARSE_IRQ
 367         select USE_OF
 368         help
 369           Support for the Calxeda Highbank SoC based boards.
 370
 371 config ARCH_CLPS711X
 372         bool "Cirrus Logic CLPS711x/EP721x-based"
 373         select CPU_ARM720T
 374         select ARCH_USES_GETTIMEOFFSET
 375         select NEED_MACH_MEMORY_H
 376         help
 377           Support for Cirrus Logic 711x/721x based boards.
 378
 379 config ARCH_CNS3XXX
 380         bool "Cavium Networks CNS3XXX family"
 381         select CPU_V6K
 382         select GENERIC_CLOCKEVENTS
 383         select ARM_GIC
 384         select MIGHT_HAVE_CACHE_L2X0
 385         select MIGHT_HAVE_PCI
 386         select PCI_DOMAINS if PCI
 387         help
 388           Support for Cavium Networks CNS3XXX platform.
 389
 390 config ARCH_GEMINI
 391         bool "Cortina Systems Gemini"
 392         select CPU_FA526
 393         select ARCH_REQUIRE_GPIOLIB
 394         select ARCH_USES_GETTIMEOFFSET
 395         help
 396           Support for the Cortina Systems Gemini family SoCs
 397
 398 config ARCH_PRIMA2
 399         bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
 400         select CPU_V7
 401         select NO_IOPORT
 402         select GENERIC_CLOCKEVENTS
 403         select CLKDEV_LOOKUP
 404         select GENERIC_IRQ_CHIP
 405         select MIGHT_HAVE_CACHE_L2X0
 406         select USE_OF
 407         select ZONE_DMA
 408         help
 409           Support for CSR SiRFSoC ARM Cortex A9 Platform
 410
 411 config ARCH_EBSA110
 412         bool "EBSA-110"
 413         select CPU_SA110
 414         select ISA
 415         select NO_IOPORT
 416         select ARCH_USES_GETTIMEOFFSET
 417         select NEED_MACH_IO_H
 418         select NEED_MACH_MEMORY_H
 419         help
 420           This is an evaluation board for the StrongARM processor available
 421           from Digital. It has limited hardware on-board, including an
 422           Ethernet interface, two PCMCIA sockets, two serial ports and a
 423           parallel port.
 424
 425 config ARCH_EP93XX
 426         bool "EP93xx-based"
 427         select CPU_ARM920T
 428         select ARM_AMBA
 429         select ARM_VIC
 430         select CLKDEV_LOOKUP
 431         select ARCH_REQUIRE_GPIOLIB
 432         select ARCH_HAS_HOLES_MEMORYMODEL
 433         select ARCH_USES_GETTIMEOFFSET
 434         select NEED_MACH_MEMORY_H
 435         help
 436           This enables support for the Cirrus EP93xx series of CPUs.
 437
 438 config ARCH_FOOTBRIDGE
 439         bool "FootBridge"
 440         select CPU_SA110
 441         select FOOTBRIDGE
 442         select GENERIC_CLOCKEVENTS
 443         select HAVE_IDE
 444         select NEED_MACH_IO_H
 445         select NEED_MACH_MEMORY_H
 446         help
 447           Support for systems based on the DC21285 companion chip
 448           ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
 449
 450 config ARCH_MXC
 451         bool "Freescale MXC/iMX-based"
 452         select GENERIC_CLOCKEVENTS
 453         select ARCH_REQUIRE_GPIOLIB
 454         select CLKDEV_LOOKUP
 455         select CLKSRC_MMIO
 456         select GENERIC_IRQ_CHIP
 457         select MULTI_IRQ_HANDLER
 458         help
 459           Support for Freescale MXC/iMX-based family of processors
 460
 461 config ARCH_MXS
 462         bool "Freescale MXS-based"
 463         select GENERIC_CLOCKEVENTS
 464         select ARCH_REQUIRE_GPIOLIB
 465         select CLKDEV_LOOKUP
 466         select CLKSRC_MMIO
 467         select HAVE_CLK_PREPARE
 468         help
 469           Support for Freescale MXS-based family of processors
 470
 471 config ARCH_NETX
 472         bool "Hilscher NetX based"
 473         select CLKSRC_MMIO
 474         select CPU_ARM926T
 475         select ARM_VIC
 476         select GENERIC_CLOCKEVENTS
 477         help
 478           This enables support for systems based on the Hilscher NetX Soc
 479
 480 config ARCH_H720X
 481         bool "Hynix HMS720x-based"
 482         select CPU_ARM720T
 483         select ISA_DMA_API
 484         select ARCH_USES_GETTIMEOFFSET
 485         help
 486           This enables support for systems based on the Hynix HMS720x
 487
 488 config ARCH_IOP13XX
 489         bool "IOP13xx-based"
 490         depends on MMU
 491         select CPU_XSC3
 492         select PLAT_IOP
 493         select PCI
 494         select ARCH_SUPPORTS_MSI
 495         select VMSPLIT_1G
 496         select NEED_MACH_IO_H
 497         select NEED_MACH_MEMORY_H
 498         select NEED_RET_TO_USER
 499         help
 500           Support for Intel's IOP13XX (XScale) family of processors.
 501
 502 config ARCH_IOP32X
 503         bool "IOP32x-based"
 504         depends on MMU
 505         select CPU_XSCALE
 506         select NEED_MACH_IO_H
 507         select NEED_RET_TO_USER
 508         select PLAT_IOP
 509         select PCI
 510         select ARCH_REQUIRE_GPIOLIB
 511         help
 512           Support for Intel's 80219 and IOP32X (XScale) family of
 513           processors.
 514
 515 config ARCH_IOP33X
 516         bool "IOP33x-based"
 517         depends on MMU
 518         select CPU_XSCALE
 519         select NEED_MACH_IO_H
 520         select NEED_RET_TO_USER
 521         select PLAT_IOP
 522         select PCI
 523         select ARCH_REQUIRE_GPIOLIB
 524         help
 525           Support for Intel's IOP33X (XScale) family of processors.
 526
 527 config ARCH_IXP23XX
 528         bool "IXP23XX-based"
 529         depends on MMU
 530         select CPU_XSC3
 531         select PCI
 532         select ARCH_USES_GETTIMEOFFSET
 533         select NEED_MACH_IO_H
 534         select NEED_MACH_MEMORY_H
 535         help
 536           Support for Intel's IXP23xx (XScale) family of processors.
 537
 538 config ARCH_IXP2000
 539         bool "IXP2400/2800-based"
 540         depends on MMU
 541         select CPU_XSCALE
 542         select PCI
 543         select ARCH_USES_GETTIMEOFFSET
 544         select NEED_MACH_IO_H
 545         select NEED_MACH_MEMORY_H
 546         help
 547           Support for Intel's IXP2400/2800 (XScale) family of processors.
 548
 549 config ARCH_IXP4XX
 550         bool "IXP4xx-based"
 551         depends on MMU
 552         select ARCH_HAS_DMA_SET_COHERENT_MASK
 553         select CLKSRC_MMIO
 554         select CPU_XSCALE
 555         select GENERIC_GPIO
 556         select GENERIC_CLOCKEVENTS
 557         select MIGHT_HAVE_PCI
 558         select NEED_MACH_IO_H
 559         select DMABOUNCE if PCI
 560         help
 561           Support for Intel's IXP4XX (XScale) family of processors.
 562
 563 config ARCH_DOVE
 564         bool "Marvell Dove"
 565         select CPU_V7
 566         select PCI
 567         select ARCH_REQUIRE_GPIOLIB
 568         select GENERIC_CLOCKEVENTS
 569         select NEED_MACH_IO_H
 570         select PLAT_ORION
 571         help
 572           Support for the Marvell Dove SoC 88AP510
 573
 574 config ARCH_KIRKWOOD
 575         bool "Marvell Kirkwood"
 576         select CPU_FEROCEON
 577         select PCI
 578         select ARCH_REQUIRE_GPIOLIB
 579         select GENERIC_CLOCKEVENTS
 580         select NEED_MACH_IO_H
 581         select PLAT_ORION
 582         help
 583           Support for the following Marvell Kirkwood series SoCs:
 584           88F6180, 88F6192 and 88F6281.
 585
 586 config ARCH_LPC32XX
 587         bool "NXP LPC32XX"
 588         select CLKSRC_MMIO
 589         select CPU_ARM926T
 590         select ARCH_REQUIRE_GPIOLIB
 591         select HAVE_IDE
 592         select ARM_AMBA
 593         select USB_ARCH_HAS_OHCI
 594         select CLKDEV_LOOKUP
 595         select GENERIC_CLOCKEVENTS
 596         help
 597           Support for the NXP LPC32XX family of processors
 598
 599 config ARCH_MV78XX0
 600         bool "Marvell MV78xx0"
 601         select CPU_FEROCEON
 602         select PCI
 603         select ARCH_REQUIRE_GPIOLIB
 604         select GENERIC_CLOCKEVENTS
 605         select NEED_MACH_IO_H
 606         select PLAT_ORION
 607         help
 608           Support for the following Marvell MV78xx0 series SoCs:
 609           MV781x0, MV782x0.
 610
 611 config ARCH_ORION5X
 612         bool "Marvell Orion"
 613         depends on MMU
 614         select CPU_FEROCEON
 615         select PCI
 616         select ARCH_REQUIRE_GPIOLIB
 617         select GENERIC_CLOCKEVENTS
 618         select PLAT_ORION
 619         help
 620           Support for the following Marvell Orion 5x series SoCs:
 621           Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
 622           Orion-2 (5281), Orion-1-90 (6183).
 623
 624 config ARCH_MMP
 625         bool "Marvell PXA168/910/MMP2"
 626         depends on MMU
 627         select ARCH_REQUIRE_GPIOLIB
 628         select CLKDEV_LOOKUP
 629         select GENERIC_CLOCKEVENTS
 630         select GPIO_PXA
 631         select PLAT_PXA
 632         select SPARSE_IRQ
 633         select GENERIC_ALLOCATOR
 634         help
 635           Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
 636
 637 config ARCH_KS8695
 638         bool "Micrel/Kendin KS8695"
 639         select CPU_ARM922T
 640         select ARCH_REQUIRE_GPIOLIB
 641         select ARCH_USES_GETTIMEOFFSET
 642         select NEED_MACH_MEMORY_H
 643         help
 644           Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
 645           System-on-Chip devices.
 646
 647 config ARCH_W90X900
 648         bool "Nuvoton W90X900 CPU"
 649         select CPU_ARM926T
 650         select ARCH_REQUIRE_GPIOLIB
 651         select CLKDEV_LOOKUP
 652         select CLKSRC_MMIO
 653         select GENERIC_CLOCKEVENTS
 654         help
 655           Support for Nuvoton (Winbond logic dept.) ARM9 processor,
 656           At present, the w90x900 has been renamed nuc900, regarding
 657           the ARM series product line, you can login the following
 658           link address to know more.
 659
 660           <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
 661                 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
 662
 663 config ARCH_TEGRA
 664         bool "NVIDIA Tegra"
 665         select CLKDEV_LOOKUP
 666         select CLKSRC_MMIO
 667         select GENERIC_CLOCKEVENTS
 668         select GENERIC_GPIO
 669         select HAVE_CLK
 670         select HAVE_SMP
 671         select MIGHT_HAVE_CACHE_L2X0
 672         select NEED_MACH_IO_H if PCI
 673         select ARCH_HAS_CPUFREQ
 674         help
 675           This enables support for NVIDIA Tegra based systems (Tegra APX,
 676           Tegra 6xx and Tegra 2 series).
 677
 678 config ARCH_PICOXCELL
 679         bool "Picochip picoXcell"
 680         select ARCH_REQUIRE_GPIOLIB
 681         select ARM_PATCH_PHYS_VIRT
 682         select ARM_VIC
 683         select CPU_V6K
 684         select DW_APB_TIMER
 685         select GENERIC_CLOCKEVENTS
 686         select GENERIC_GPIO
 687         select HAVE_TCM
 688         select NO_IOPORT
 689         select SPARSE_IRQ
 690         select USE_OF
 691         help
 692           This enables support for systems based on the Picochip picoXcell
 693           family of Femtocell devices.  The picoxcell support requires device tree
 694           for all boards.
 695
 696 config ARCH_PNX4008
 697         bool "Philips Nexperia PNX4008 Mobile"
 698         select CPU_ARM926T
 699         select CLKDEV_LOOKUP
 700         select ARCH_USES_GETTIMEOFFSET
 701         help
 702           This enables support for Philips PNX4008 mobile platform.
 703
 704 config ARCH_PXA
 705         bool "PXA2xx/PXA3xx-based"
 706         depends on MMU
 707         select ARCH_MTD_XIP
 708         select ARCH_HAS_CPUFREQ
 709         select CLKDEV_LOOKUP
 710         select CLKSRC_MMIO
 711         select ARCH_REQUIRE_GPIOLIB
 712         select GENERIC_CLOCKEVENTS
 713         select GPIO_PXA
 714         select PLAT_PXA
 715         select SPARSE_IRQ
 716         select AUTO_ZRELADDR
 717         select MULTI_IRQ_HANDLER
 718         select ARM_CPU_SUSPEND if PM
 719         select HAVE_IDE
 720         help
 721           Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
 722
 723 config ARCH_MSM
 724         bool "Qualcomm MSM"
 725         select HAVE_CLK
 726         select GENERIC_CLOCKEVENTS
 727         select ARCH_REQUIRE_GPIOLIB
 728         select CLKDEV_LOOKUP
 729         help
 730           Support for Qualcomm MSM/QSD based systems.  This runs on the
 731           apps processor of the MSM/QSD and depends on a shared memory
 732           interface to the modem processor which runs the baseband
 733           stack and controls some vital subsystems
 734           (clock and power control, etc).
 735
 736 config ARCH_SHMOBILE
 737         bool "Renesas SH-Mobile / R-Mobile"
 738         select HAVE_CLK
 739         select CLKDEV_LOOKUP
 740         select HAVE_MACH_CLKDEV
 741         select HAVE_SMP
 742         select GENERIC_CLOCKEVENTS
 743         select MIGHT_HAVE_CACHE_L2X0
 744         select NO_IOPORT
 745         select SPARSE_IRQ
 746         select MULTI_IRQ_HANDLER
 747         select PM_GENERIC_DOMAINS if PM
 748         select NEED_MACH_MEMORY_H
 749         help
 750           Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
 751
 752 config ARCH_RPC
 753         bool "RiscPC"
 754         select ARCH_ACORN
 755         select FIQ
 756         select ARCH_MAY_HAVE_PC_FDC
 757         select HAVE_PATA_PLATFORM
 758         select ISA_DMA_API
 759         select NO_IOPORT
 760         select ARCH_SPARSEMEM_ENABLE
 761         select ARCH_USES_GETTIMEOFFSET
 762         select HAVE_IDE
 763         select NEED_MACH_IO_H
 764         select NEED_MACH_MEMORY_H
 765         help
 766           On the Acorn Risc-PC, Linux can support the internal IDE disk and
 767           CD-ROM interface, serial and parallel port, and the floppy drive.
 768
 769 config ARCH_SA1100
 770         bool "SA1100-based"
 771         select CLKSRC_MMIO
 772         select CPU_SA1100
 773         select ISA
 774         select ARCH_SPARSEMEM_ENABLE
 775         select ARCH_MTD_XIP
 776         select ARCH_HAS_CPUFREQ
 777         select CPU_FREQ
 778         select GENERIC_CLOCKEVENTS
 779         select CLKDEV_LOOKUP
 780         select ARCH_REQUIRE_GPIOLIB
 781         select HAVE_IDE
 782         select NEED_MACH_MEMORY_H
 783         select SPARSE_IRQ
 784         help
 785           Support for StrongARM 11x0 based boards.
 786
 787 config ARCH_S3C24XX
 788         bool "Samsung S3C24XX SoCs"
 789         select GENERIC_GPIO
 790         select ARCH_HAS_CPUFREQ
 791         select HAVE_CLK
 792         select CLKDEV_LOOKUP
 793         select ARCH_USES_GETTIMEOFFSET
 794         select HAVE_S3C2410_I2C if I2C
 795         select HAVE_S3C_RTC if RTC_CLASS
 796         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 797         select NEED_MACH_IO_H
 798         help
 799           Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
 800           and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
 801           (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
 802           Samsung SMDK2410 development board (and derivatives).
 803
 804 config ARCH_S3C64XX
 805         bool "Samsung S3C64XX"
 806         select PLAT_SAMSUNG
 807         select CPU_V6
 808         select ARM_VIC
 809         select HAVE_CLK
 810         select HAVE_TCM
 811         select CLKDEV_LOOKUP
 812         select NO_IOPORT
 813         select ARCH_USES_GETTIMEOFFSET
 814         select ARCH_HAS_CPUFREQ
 815         select ARCH_REQUIRE_GPIOLIB
 816         select SAMSUNG_CLKSRC
 817         select SAMSUNG_IRQ_VIC_TIMER
 818         select S3C_GPIO_TRACK
 819         select S3C_DEV_NAND
 820         select USB_ARCH_HAS_OHCI
 821         select SAMSUNG_GPIOLIB_4BIT
 822         select HAVE_S3C2410_I2C if I2C
 823         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 824         help
 825           Samsung S3C64XX series based systems
 826
 827 config ARCH_S5P64X0
 828         bool "Samsung S5P6440 S5P6450"
 829         select CPU_V6
 830         select GENERIC_GPIO
 831         select HAVE_CLK
 832         select CLKDEV_LOOKUP
 833         select CLKSRC_MMIO
 834         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 835         select GENERIC_CLOCKEVENTS
 836         select HAVE_S3C2410_I2C if I2C
 837         select HAVE_S3C_RTC if RTC_CLASS
 838         help
 839           Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
 840           SMDK6450.
 841
 842 config ARCH_S5PC100
 843         bool "Samsung S5PC100"
 844         select GENERIC_GPIO
 845         select HAVE_CLK
 846         select CLKDEV_LOOKUP
 847         select CPU_V7
 848         select ARCH_USES_GETTIMEOFFSET
 849         select HAVE_S3C2410_I2C if I2C
 850         select HAVE_S3C_RTC if RTC_CLASS
 851         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 852         help
 853           Samsung S5PC100 series based systems
 854
 855 config ARCH_S5PV210
 856         bool "Samsung S5PV210/S5PC110"
 857         select CPU_V7
 858         select ARCH_SPARSEMEM_ENABLE
 859         select ARCH_HAS_HOLES_MEMORYMODEL
 860         select GENERIC_GPIO
 861         select HAVE_CLK
 862         select CLKDEV_LOOKUP
 863         select CLKSRC_MMIO
 864         select ARCH_HAS_CPUFREQ
 865         select GENERIC_CLOCKEVENTS
 866         select HAVE_S3C2410_I2C if I2C
 867         select HAVE_S3C_RTC if RTC_CLASS
 868         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 869         select NEED_MACH_MEMORY_H
 870         help
 871           Samsung S5PV210/S5PC110 series based systems
 872
 873 config ARCH_EXYNOS
 874         bool "SAMSUNG EXYNOS"
 875         select CPU_V7
 876         select ARCH_SPARSEMEM_ENABLE
 877         select ARCH_HAS_HOLES_MEMORYMODEL
 878         select GENERIC_GPIO
 879         select HAVE_CLK
 880         select CLKDEV_LOOKUP
 881         select ARCH_HAS_CPUFREQ
 882         select GENERIC_CLOCKEVENTS
 883         select HAVE_S3C_RTC if RTC_CLASS
 884         select HAVE_S3C2410_I2C if I2C
 885         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 886         select NEED_MACH_MEMORY_H
 887         help
 888           Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
 889
 890 config ARCH_SHARK
 891         bool "Shark"
 892         select CPU_SA110
 893         select ISA
 894         select ISA_DMA
 895         select ZONE_DMA
 896         select PCI
 897         select ARCH_USES_GETTIMEOFFSET
 898         select NEED_MACH_MEMORY_H
 899         select NEED_MACH_IO_H
 900         help
 901           Support for the StrongARM based Digital DNARD machine, also known
 902           as "Shark" (<http://www.shark-linux.de/shark.html>).
 903
 904 config ARCH_U300
 905         bool "ST-Ericsson U300 Series"
 906         depends on MMU
 907         select CLKSRC_MMIO
 908         select CPU_ARM926T
 909         select HAVE_TCM
 910         select ARM_AMBA
 911         select ARM_PATCH_PHYS_VIRT
 912         select ARM_VIC
 913         select GENERIC_CLOCKEVENTS
 914         select CLKDEV_LOOKUP
 915         select HAVE_MACH_CLKDEV
 916         select GENERIC_GPIO
 917         select ARCH_REQUIRE_GPIOLIB
 918         help
 919           Support for ST-Ericsson U300 series mobile platforms.
 920
 921 config ARCH_U8500
 922         bool "ST-Ericsson U8500 Series"
 923         depends on MMU
 924         select CPU_V7
 925         select ARM_AMBA
 926         select GENERIC_CLOCKEVENTS
 927         select CLKDEV_LOOKUP
 928         select ARCH_REQUIRE_GPIOLIB
 929         select ARCH_HAS_CPUFREQ
 930         select HAVE_SMP
 931         select MIGHT_HAVE_CACHE_L2X0
 932         help
 933           Support for ST-Ericsson's Ux500 architecture
 934
 935 config ARCH_NOMADIK
 936         bool "STMicroelectronics Nomadik"
 937         select ARM_AMBA
 938         select ARM_VIC
 939         select CPU_ARM926T
 940         select CLKDEV_LOOKUP
 941         select GENERIC_CLOCKEVENTS
 942         select MIGHT_HAVE_CACHE_L2X0
 943         select ARCH_REQUIRE_GPIOLIB
 944         help
 945           Support for the Nomadik platform by ST-Ericsson
 946
 947 config ARCH_DAVINCI
 948         bool "TI DaVinci"
 949         select GENERIC_CLOCKEVENTS
 950         select ARCH_REQUIRE_GPIOLIB
 951         select ZONE_DMA
 952         select HAVE_IDE
 953         select CLKDEV_LOOKUP
 954         select GENERIC_ALLOCATOR
 955         select GENERIC_IRQ_CHIP
 956         select ARCH_HAS_HOLES_MEMORYMODEL
 957         help
 958           Support for TI's DaVinci platform.
 959
 960 config ARCH_OMAP
 961         bool "TI OMAP"
 962         select HAVE_CLK
 963         select ARCH_REQUIRE_GPIOLIB
 964         select ARCH_HAS_CPUFREQ
 965         select CLKSRC_MMIO
 966         select GENERIC_CLOCKEVENTS
 967         select ARCH_HAS_HOLES_MEMORYMODEL
 968         help
 969           Support for TI's OMAP platform (OMAP1/2/3/4).
 970
 971 config PLAT_SPEAR
 972         bool "ST SPEAr"
 973         select ARM_AMBA
 974         select ARCH_REQUIRE_GPIOLIB
 975         select CLKDEV_LOOKUP
 976         select CLKSRC_MMIO
 977         select GENERIC_CLOCKEVENTS
 978         select HAVE_CLK
 979         help
 980           Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
 981
 982 config ARCH_VT8500
 983         bool "VIA/WonderMedia 85xx"
 984         select CPU_ARM926T
 985         select GENERIC_GPIO
 986         select ARCH_HAS_CPUFREQ
 987         select GENERIC_CLOCKEVENTS
 988         select ARCH_REQUIRE_GPIOLIB
 989         select HAVE_PWM
 990         help
 991           Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
 992
 993 config ARCH_ZYNQ
 994         bool "Xilinx Zynq ARM Cortex A9 Platform"
 995         select CPU_V7
 996         select GENERIC_CLOCKEVENTS
 997         select CLKDEV_LOOKUP
 998         select ARM_GIC
 999         select ARM_AMBA
1000         select ICST
1001         select MIGHT_HAVE_CACHE_L2X0
1002         select USE_OF
1003         help
1004           Support for Xilinx Zynq ARM Cortex A9 Platform
1005 endchoice
1006
1007 #
1008 # This is sorted alphabetically by mach-* pathname.  However, plat-*
1009 # Kconfigs may be included either alphabetically (according to the
1010 # plat- suffix) or along side the corresponding mach-* source.
1011 #
1012 source "arch/arm/mach-at91/Kconfig"
1013
1014 source "arch/arm/mach-bcmring/Kconfig"
1015
1016 source "arch/arm/mach-clps711x/Kconfig"
1017
1018 source "arch/arm/mach-cns3xxx/Kconfig"
1019
1020 source "arch/arm/mach-davinci/Kconfig"
1021
1022 source "arch/arm/mach-dove/Kconfig"
1023
1024 source "arch/arm/mach-ep93xx/Kconfig"
1025
1026 source "arch/arm/mach-footbridge/Kconfig"
1027
1028 source "arch/arm/mach-gemini/Kconfig"
1029
1030 source "arch/arm/mach-h720x/Kconfig"
1031
1032 source "arch/arm/mach-integrator/Kconfig"
1033
1034 source "arch/arm/mach-iop32x/Kconfig"
1035
1036 source "arch/arm/mach-iop33x/Kconfig"
1037
1038 source "arch/arm/mach-iop13xx/Kconfig"
1039
1040 source "arch/arm/mach-ixp4xx/Kconfig"
1041
1042 source "arch/arm/mach-ixp2000/Kconfig"
1043
1044 source "arch/arm/mach-ixp23xx/Kconfig"
1045
1046 source "arch/arm/mach-kirkwood/Kconfig"
1047
1048 source "arch/arm/mach-ks8695/Kconfig"
1049
1050 source "arch/arm/mach-lpc32xx/Kconfig"
1051
1052 source "arch/arm/mach-msm/Kconfig"
1053
1054 source "arch/arm/mach-mv78xx0/Kconfig"
1055
1056 source "arch/arm/plat-mxc/Kconfig"
1057
1058 source "arch/arm/mach-mxs/Kconfig"
1059
1060 source "arch/arm/mach-netx/Kconfig"
1061
1062 source "arch/arm/mach-nomadik/Kconfig"
1063 source "arch/arm/plat-nomadik/Kconfig"
1064
1065 source "arch/arm/plat-omap/Kconfig"
1066
1067 source "arch/arm/mach-omap1/Kconfig"
1068
1069 source "arch/arm/mach-omap2/Kconfig"
1070
1071 source "arch/arm/mach-orion5x/Kconfig"
1072
1073 source "arch/arm/mach-pxa/Kconfig"
1074 source "arch/arm/plat-pxa/Kconfig"
1075
1076 source "arch/arm/mach-mmp/Kconfig"
1077
1078 source "arch/arm/mach-realview/Kconfig"
1079
1080 source "arch/arm/mach-sa1100/Kconfig"
1081
1082 source "arch/arm/plat-samsung/Kconfig"
1083 source "arch/arm/plat-s3c24xx/Kconfig"
1084 source "arch/arm/plat-s5p/Kconfig"
1085
1086 source "arch/arm/plat-spear/Kconfig"
1087
1088 source "arch/arm/mach-s3c24xx/Kconfig"
1089 if ARCH_S3C24XX
1090 source "arch/arm/mach-s3c2412/Kconfig"
1091 source "arch/arm/mach-s3c2440/Kconfig"
1092 endif
1093
1094 if ARCH_S3C64XX
1095 source "arch/arm/mach-s3c64xx/Kconfig"
1096 endif
1097
1098 source "arch/arm/mach-s5p64x0/Kconfig"
1099
1100 source "arch/arm/mach-s5pc100/Kconfig"
1101
1102 source "arch/arm/mach-s5pv210/Kconfig"
1103
1104 source "arch/arm/mach-exynos/Kconfig"
1105
1106 source "arch/arm/mach-shmobile/Kconfig"
1107
1108 source "arch/arm/mach-tegra/Kconfig"
1109
1110 source "arch/arm/mach-u300/Kconfig"
1111
1112 source "arch/arm/mach-ux500/Kconfig"
1113
1114 source "arch/arm/mach-versatile/Kconfig"
1115
1116 source "arch/arm/mach-vexpress/Kconfig"
1117 source "arch/arm/plat-versatile/Kconfig"
1118
1119 source "arch/arm/mach-vt8500/Kconfig"
1120
1121 source "arch/arm/mach-w90x900/Kconfig"
1122
1123 # Definitions to make life easier
1124 config ARCH_ACORN
1125         bool
1126
1127 config PLAT_IOP
1128         bool
1129         select GENERIC_CLOCKEVENTS
1130
1131 config PLAT_ORION
1132         bool
1133         select CLKSRC_MMIO
1134         select GENERIC_IRQ_CHIP
1135
1136 config PLAT_PXA
1137         bool
1138
1139 config PLAT_VERSATILE
1140         bool
1141
1142 config ARM_TIMER_SP804
1143         bool
1144         select CLKSRC_MMIO
1145         select HAVE_SCHED_CLOCK
1146
1147 source arch/arm/mm/Kconfig
1148
1149 config ARM_NR_BANKS
1150         int
1151         default 16 if ARCH_EP93XX
1152         default 8
1153
1154 config IWMMXT
1155         bool "Enable iWMMXt support"
1156         depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1157         default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1158         help
1159           Enable support for iWMMXt context switching at run time if
1160           running on a CPU that supports it.
1161
1162 config XSCALE_PMU
1163         bool
1164         depends on CPU_XSCALE
1165         default y
1166
1167 config CPU_HAS_PMU
1168         depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1169                    (!ARCH_OMAP3 || OMAP3_EMU)
1170         default y
1171         bool
1172
1173 config MULTI_IRQ_HANDLER
1174         bool
1175         help
1176           Allow each machine to specify it's own IRQ handler at run time.
1177
1178 if !MMU
1179 source "arch/arm/Kconfig-nommu"
1180 endif
1181
1182 config ARM_ERRATA_326103
1183         bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1184         depends on CPU_V6
1185         help
1186           Executing a SWP instruction to read-only memory does not set bit 11
1187           of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1188           treat the access as a read, preventing a COW from occurring and
1189           causing the faulting task to livelock.
1190
1191 config ARM_ERRATA_411920
1192         bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1193         depends on CPU_V6 || CPU_V6K
1194         help
1195           Invalidation of the Instruction Cache operation can
1196           fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1197           It does not affect the MPCore. This option enables the ARM Ltd.
1198           recommended workaround.
1199
1200 config ARM_ERRATA_430973
1201         bool "ARM errata: Stale prediction on replaced interworking branch"
1202         depends on CPU_V7
1203         help
1204           This option enables the workaround for the 430973 Cortex-A8
1205           (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1206           interworking branch is replaced with another code sequence at the
1207           same virtual address, whether due to self-modifying code or virtual
1208           to physical address re-mapping, Cortex-A8 does not recover from the
1209           stale interworking branch prediction. This results in Cortex-A8
1210           executing the new code sequence in the incorrect ARM or Thumb state.
1211           The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1212           and also flushes the branch target cache at every context switch.
1213           Note that setting specific bits in the ACTLR register may not be
1214           available in non-secure mode.
1215
1216 config ARM_ERRATA_458693
1217         bool "ARM errata: Processor deadlock when a false hazard is created"
1218         depends on CPU_V7
1219         help
1220           This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1221           erratum. For very specific sequences of memory operations, it is
1222           possible for a hazard condition intended for a cache line to instead
1223           be incorrectly associated with a different cache line. This false
1224           hazard might then cause a processor deadlock. The workaround enables
1225           the L1 caching of the NEON accesses and disables the PLD instruction
1226           in the ACTLR register. Note that setting specific bits in the ACTLR
1227           register may not be available in non-secure mode.
1228
1229 config ARM_ERRATA_460075
1230         bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1231         depends on CPU_V7
1232         help
1233           This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1234           erratum. Any asynchronous access to the L2 cache may encounter a
1235           situation in which recent store transactions to the L2 cache are lost
1236           and overwritten with stale memory contents from external memory. The
1237           workaround disables the write-allocate mode for the L2 cache via the
1238           ACTLR register. Note that setting specific bits in the ACTLR register
1239           may not be available in non-secure mode.
1240
1241 config ARM_ERRATA_742230
1242         bool "ARM errata: DMB operation may be faulty"
1243         depends on CPU_V7 && SMP
1244         help
1245           This option enables the workaround for the 742230 Cortex-A9
1246           (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1247           between two write operations may not ensure the correct visibility
1248           ordering of the two writes. This workaround sets a specific bit in
1249           the diagnostic register of the Cortex-A9 which causes the DMB
1250           instruction to behave as a DSB, ensuring the correct behaviour of
1251           the two writes.
1252
1253 config ARM_ERRATA_742231
1254         bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1255         depends on CPU_V7 && SMP
1256         help
1257           This option enables the workaround for the 742231 Cortex-A9
1258           (r2p0..r2p2) erratum. Under certain conditions, specific to the
1259           Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1260           accessing some data located in the same cache line, may get corrupted
1261           data due to bad handling of the address hazard when the line gets
1262           replaced from one of the CPUs at the same time as another CPU is
1263           accessing it. This workaround sets specific bits in the diagnostic
1264           register of the Cortex-A9 which reduces the linefill issuing
1265           capabilities of the processor.
1266
1267 config PL310_ERRATA_588369
1268         bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1269         depends on CACHE_L2X0
1270         help
1271            The PL310 L2 cache controller implements three types of Clean &
1272            Invalidate maintenance operations: by Physical Address
1273            (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1274            They are architecturally defined to behave as the execution of a
1275            clean operation followed immediately by an invalidate operation,
1276            both performing to the same memory location. This functionality
1277            is not correctly implemented in PL310 as clean lines are not
1278            invalidated as a result of these operations.
1279
1280 config ARM_ERRATA_720789
1281         bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1282         depends on CPU_V7
1283         help
1284           This option enables the workaround for the 720789 Cortex-A9 (prior to
1285           r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1286           broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1287           As a consequence of this erratum, some TLB entries which should be
1288           invalidated are not, resulting in an incoherency in the system page
1289           tables. The workaround changes the TLB flushing routines to invalidate
1290           entries regardless of the ASID.
1291
1292 config PL310_ERRATA_727915
1293         bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1294         depends on CACHE_L2X0
1295         help
1296           PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1297           operation (offset 0x7FC). This operation runs in background so that
1298           PL310 can handle normal accesses while it is in progress. Under very
1299           rare circumstances, due to this erratum, write data can be lost when
1300           PL310 treats a cacheable write transaction during a Clean &
1301           Invalidate by Way operation.
1302
1303 config ARM_ERRATA_743622
1304         bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1305         depends on CPU_V7
1306         help
1307           This option enables the workaround for the 743622 Cortex-A9
1308           (r2p*) erratum. Under very rare conditions, a faulty
1309           optimisation in the Cortex-A9 Store Buffer may lead to data
1310           corruption. This workaround sets a specific bit in the diagnostic
1311           register of the Cortex-A9 which disables the Store Buffer
1312           optimisation, preventing the defect from occurring. This has no
1313           visible impact on the overall performance or power consumption of the
1314           processor.
1315
1316 config ARM_ERRATA_751472
1317         bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1318         depends on CPU_V7
1319         help
1320           This option enables the workaround for the 751472 Cortex-A9 (prior
1321           to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1322           completion of a following broadcasted operation if the second
1323           operation is received by a CPU before the ICIALLUIS has completed,
1324           potentially leading to corrupted entries in the cache or TLB.
1325
1326 config PL310_ERRATA_753970
1327         bool "PL310 errata: cache sync operation may be faulty"
1328         depends on CACHE_PL310
1329         help
1330           This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1331
1332           Under some condition the effect of cache sync operation on
1333           the store buffer still remains when the operation completes.
1334           This means that the store buffer is always asked to drain and
1335           this prevents it from merging any further writes. The workaround
1336           is to replace the normal offset of cache sync operation (0x730)
1337           by another offset targeting an unmapped PL310 register 0x740.
1338           This has the same effect as the cache sync operation: store buffer
1339           drain and waiting for all buffers empty.
1340
1341 config ARM_ERRATA_754322
1342         bool "ARM errata: possible faulty MMU translations following an ASID switch"
1343         depends on CPU_V7
1344         help
1345           This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1346           r3p*) erratum. A speculative memory access may cause a page table walk
1347           which starts prior to an ASID switch but completes afterwards. This
1348           can populate the micro-TLB with a stale entry which may be hit with
1349           the new ASID. This workaround places two dsb instructions in the mm
1350           switching code so that no page table walks can cross the ASID switch.
1351
1352 config ARM_ERRATA_754327
1353         bool "ARM errata: no automatic Store Buffer drain"
1354         depends on CPU_V7 && SMP
1355         help
1356           This option enables the workaround for the 754327 Cortex-A9 (prior to
1357           r2p0) erratum. The Store Buffer does not have any automatic draining
1358           mechanism and therefore a livelock may occur if an external agent
1359           continuously polls a memory location waiting to observe an update.
1360           This workaround defines cpu_relax() as smp_mb(), preventing correctly
1361           written polling loops from denying visibility of updates to memory.
1362
1363 config ARM_ERRATA_364296
1364         bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1365         depends on CPU_V6 && !SMP
1366         help
1367           This options enables the workaround for the 364296 ARM1136
1368           r0p2 erratum (possible cache data corruption with
1369           hit-under-miss enabled). It sets the undocumented bit 31 in
1370           the auxiliary control register and the FI bit in the control
1371           register, thus disabling hit-under-miss without putting the
1372           processor into full low interrupt latency mode. ARM11MPCore
1373           is not affected.
1374
1375 config ARM_ERRATA_764369
1376         bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1377         depends on CPU_V7 && SMP
1378         help
1379           This option enables the workaround for erratum 764369
1380           affecting Cortex-A9 MPCore with two or more processors (all
1381           current revisions). Under certain timing circumstances, a data
1382           cache line maintenance operation by MVA targeting an Inner
1383           Shareable memory region may fail to proceed up to either the
1384           Point of Coherency or to the Point of Unification of the
1385           system. This workaround adds a DSB instruction before the
1386           relevant cache maintenance functions and sets a specific bit
1387           in the diagnostic control register of the SCU.
1388
1389 config PL310_ERRATA_769419
1390         bool "PL310 errata: no automatic Store Buffer drain"
1391         depends on CACHE_L2X0
1392         help
1393           On revisions of the PL310 prior to r3p2, the Store Buffer does
1394           not automatically drain. This can cause normal, non-cacheable
1395           writes to be retained when the memory system is idle, leading
1396           to suboptimal I/O performance for drivers using coherent DMA.
1397           This option adds a write barrier to the cpu_idle loop so that,
1398           on systems with an outer cache, the store buffer is drained
1399           explicitly.
1400
1401 endmenu
1402
1403 source "arch/arm/common/Kconfig"
1404
1405 menu "Bus support"
1406
1407 config ARM_AMBA
1408         bool
1409
1410 config ISA
1411         bool
1412         help
1413           Find out whether you have ISA slots on your motherboard.  ISA is the
1414           name of a bus system, i.e. the way the CPU talks to the other stuff
1415           inside your box.  Other bus systems are PCI, EISA, MicroChannel
1416           (MCA) or VESA.  ISA is an older system, now being displaced by PCI;
1417           newer boards don't support it.  If you have ISA, say Y, otherwise N.
1418
1419 # Select ISA DMA controller support
1420 config ISA_DMA
1421         bool
1422         select ISA_DMA_API
1423
1424 # Select ISA DMA interface
1425 config ISA_DMA_API
1426         bool
1427
1428 config PCI
1429         bool "PCI support" if MIGHT_HAVE_PCI
1430         help
1431           Find out whether you have a PCI motherboard. PCI is the name of a
1432           bus system, i.e. the way the CPU talks to the other stuff inside
1433           your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1434           VESA. If you have PCI, say Y, otherwise N.
1435
1436 config PCI_DOMAINS
1437         bool
1438         depends on PCI
1439
1440 config PCI_NANOENGINE
1441         bool "BSE nanoEngine PCI support"
1442         depends on SA1100_NANOENGINE
1443         help
1444           Enable PCI on the BSE nanoEngine board.
1445
1446 config PCI_SYSCALL
1447         def_bool PCI
1448
1449 # Select the host bridge type
1450 config PCI_HOST_VIA82C505
1451         bool
1452         depends on PCI && ARCH_SHARK
1453         default y
1454
1455 config PCI_HOST_ITE8152
1456         bool
1457         depends on PCI && MACH_ARMCORE
1458         default y
1459         select DMABOUNCE
1460
1461 source "drivers/pci/Kconfig"
1462
1463 source "drivers/pcmcia/Kconfig"
1464
1465 endmenu
1466
1467 menu "Kernel Features"
1468
1469 source "kernel/time/Kconfig"
1470
1471 config HAVE_SMP
1472         bool
1473         help
1474           This option should be selected by machines which have an SMP-
1475           capable CPU.
1476
1477           The only effect of this option is to make the SMP-related
1478           options available to the user for configuration.
1479
1480 config SMP
1481         bool "Symmetric Multi-Processing"
1482         depends on CPU_V6K || CPU_V7
1483         depends on GENERIC_CLOCKEVENTS
1484         depends on HAVE_SMP
1485         depends on MMU
1486         select USE_GENERIC_SMP_HELPERS
1487         select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1488         help
1489           This enables support for systems with more than one CPU. If you have
1490           a system with only one CPU, like most personal computers, say N. If
1491           you have a system with more than one CPU, say Y.
1492
1493           If you say N here, the kernel will run on single and multiprocessor
1494           machines, but will use only one CPU of a multiprocessor machine. If
1495           you say Y here, the kernel will run on many, but not all, single
1496           processor machines. On a single processor machine, the kernel will
1497           run faster if you say N here.
1498
1499           See also <file:Documentation/x86/i386/IO-APIC.txt>,
1500           <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1501           <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1502
1503           If you don't know what to do here, say N.
1504
1505 config SMP_ON_UP
1506         bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1507         depends on EXPERIMENTAL
1508         depends on SMP && !XIP_KERNEL
1509         default y
1510         help
1511           SMP kernels contain instructions which fail on non-SMP processors.
1512           Enabling this option allows the kernel to modify itself to make
1513           these instructions safe.  Disabling it allows about 1K of space
1514           savings.
1515
1516           If you don't know what to do here, say Y.
1517
1518 config ARM_CPU_TOPOLOGY
1519         bool "Support cpu topology definition"
1520         depends on SMP && CPU_V7
1521         default y
1522         help
1523           Support ARM cpu topology definition. The MPIDR register defines
1524           affinity between processors which is then used to describe the cpu
1525           topology of an ARM System.
1526
1527 config SCHED_MC
1528         bool "Multi-core scheduler support"
1529         depends on ARM_CPU_TOPOLOGY
1530         help
1531           Multi-core scheduler support improves the CPU scheduler's decision
1532           making when dealing with multi-core CPU chips at a cost of slightly
1533           increased overhead in some places. If unsure say N here.
1534
1535 config SCHED_SMT
1536         bool "SMT scheduler support"
1537         depends on ARM_CPU_TOPOLOGY
1538         help
1539           Improves the CPU scheduler's decision making when dealing with
1540           MultiThreading at a cost of slightly increased overhead in some
1541           places. If unsure say N here.
1542
1543 config HAVE_ARM_SCU
1544         bool
1545         help
1546           This option enables support for the ARM system coherency unit
1547
1548 config ARM_ARCH_TIMER
1549         bool "Architected timer support"
1550         depends on CPU_V7
1551         help
1552           This option enables support for the ARM architected timer
1553
1554 config HAVE_ARM_TWD
1555         bool
1556         depends on SMP
1557         help
1558           This options enables support for the ARM timer and watchdog unit
1559
1560 choice
1561         prompt "Memory split"
1562         default VMSPLIT_3G
1563         help
1564           Select the desired split between kernel and user memory.
1565
1566           If you are not absolutely sure what you are doing, leave this
1567           option alone!
1568
1569         config VMSPLIT_3G
1570                 bool "3G/1G user/kernel split"
1571         config VMSPLIT_2G
1572                 bool "2G/2G user/kernel split"
1573         config VMSPLIT_1G
1574                 bool "1G/3G user/kernel split"
1575 endchoice
1576
1577 config PAGE_OFFSET
1578         hex
1579         default 0x40000000 if VMSPLIT_1G
1580         default 0x80000000 if VMSPLIT_2G
1581         default 0xC0000000
1582
1583 config NR_CPUS
1584         int "Maximum number of CPUs (2-32)"
1585         range 2 32
1586         depends on SMP
1587         default "4"
1588
1589 config HOTPLUG_CPU
1590         bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1591         depends on SMP && HOTPLUG && EXPERIMENTAL
1592         help
1593           Say Y here to experiment with turning CPUs off and on.  CPUs
1594           can be controlled through /sys/devices/system/cpu.
1595
1596 config LOCAL_TIMERS
1597         bool "Use local timer interrupts"
1598         depends on SMP
1599         default y
1600         select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1601         help
1602           Enable support for local timers on SMP platforms, rather then the
1603           legacy IPI broadcast method.  Local timers allows the system
1604           accounting to be spread across the timer interval, preventing a
1605           "thundering herd" at every timer tick.
1606
1607 config ARCH_NR_GPIO
1608         int
1609         default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1610         default 355 if ARCH_U8500
1611         default 264 if MACH_H4700
1612         default 0
1613         help
1614           Maximum number of GPIOs in the system.
1615
1616           If unsure, leave the default value.
1617
1618 source kernel/Kconfig.preempt
1619
1620 config HZ
1621         int
1622         default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1623                 ARCH_S5PV210 || ARCH_EXYNOS4
1624         default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1625         default AT91_TIMER_HZ if ARCH_AT91
1626         default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1627         default 100
1628
1629 config THUMB2_KERNEL
1630         bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1631         depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1632         select AEABI
1633         select ARM_ASM_UNIFIED
1634         select ARM_UNWIND
1635         help
1636           By enabling this option, the kernel will be compiled in
1637           Thumb-2 mode. A compiler/assembler that understand the unified
1638           ARM-Thumb syntax is needed.
1639
1640           If unsure, say N.
1641
1642 config THUMB2_AVOID_R_ARM_THM_JUMP11
1643         bool "Work around buggy Thumb-2 short branch relocations in gas"
1644         depends on THUMB2_KERNEL && MODULES
1645         default y
1646         help
1647           Various binutils versions can resolve Thumb-2 branches to
1648           locally-defined, preemptible global symbols as short-range "b.n"
1649           branch instructions.
1650
1651           This is a problem, because there's no guarantee the final
1652           destination of the symbol, or any candidate locations for a
1653           trampoline, are within range of the branch.  For this reason, the
1654           kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1655           relocation in modules at all, and it makes little sense to add
1656           support.
1657
1658           The symptom is that the kernel fails with an "unsupported
1659           relocation" error when loading some modules.
1660
1661           Until fixed tools are available, passing
1662           -fno-optimize-sibling-calls to gcc should prevent gcc generating
1663           code which hits this problem, at the cost of a bit of extra runtime
1664           stack usage in some cases.
1665
1666           The problem is described in more detail at:
1667               https://bugs.launchpad.net/binutils-linaro/+bug/725126
1668
1669           Only Thumb-2 kernels are affected.
1670
1671           Unless you are sure your tools don't have this problem, say Y.
1672
1673 config ARM_ASM_UNIFIED
1674         bool
1675
1676 config AEABI
1677         bool "Use the ARM EABI to compile the kernel"
1678         help
1679           This option allows for the kernel to be compiled using the latest
1680           ARM ABI (aka EABI).  This is only useful if you are using a user
1681           space environment that is also compiled with EABI.
1682
1683           Since there are major incompatibilities between the legacy ABI and
1684           EABI, especially with regard to structure member alignment, this
1685           option also changes the kernel syscall calling convention to
1686           disambiguate both ABIs and allow for backward compatibility support
1687           (selected with CONFIG_OABI_COMPAT).
1688
1689           To use this you need GCC version 4.0.0 or later.
1690
1691 config OABI_COMPAT
1692         bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1693         depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1694         default y
1695         help
1696           This option preserves the old syscall interface along with the
1697           new (ARM EABI) one. It also provides a compatibility layer to
1698           intercept syscalls that have structure arguments which layout
1699           in memory differs between the legacy ABI and the new ARM EABI
1700           (only for non "thumb" binaries). This option adds a tiny
1701           overhead to all syscalls and produces a slightly larger kernel.
1702           If you know you'll be using only pure EABI user space then you
1703           can say N here. If this option is not selected and you attempt
1704           to execute a legacy ABI binary then the result will be
1705           UNPREDICTABLE (in fact it can be predicted that it won't work
1706           at all). If in doubt say Y.
1707
1708 config ARCH_HAS_HOLES_MEMORYMODEL
1709         bool
1710
1711 config ARCH_SPARSEMEM_ENABLE
1712         bool
1713
1714 config ARCH_SPARSEMEM_DEFAULT
1715         def_bool ARCH_SPARSEMEM_ENABLE
1716
1717 config ARCH_SELECT_MEMORY_MODEL
1718         def_bool ARCH_SPARSEMEM_ENABLE
1719
1720 config HAVE_ARCH_PFN_VALID
1721         def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1722
1723 config HIGHMEM
1724         bool "High Memory Support"
1725         depends on MMU
1726         help
1727           The address space of ARM processors is only 4 Gigabytes large
1728           and it has to accommodate user address space, kernel address
1729           space as well as some memory mapped IO. That means that, if you
1730           have a large amount of physical memory and/or IO, not all of the
1731           memory can be "permanently mapped" by the kernel. The physical
1732           memory that is not permanently mapped is called "high memory".
1733
1734           Depending on the selected kernel/user memory split, minimum
1735           vmalloc space and actual amount of RAM, you may not need this
1736           option which should result in a slightly faster kernel.
1737
1738           If unsure, say n.
1739
1740 config HIGHPTE
1741         bool "Allocate 2nd-level pagetables from highmem"
1742         depends on HIGHMEM
1743
1744 config HW_PERF_EVENTS
1745         bool "Enable hardware performance counter support for perf events"
1746         depends on PERF_EVENTS && CPU_HAS_PMU
1747         default y
1748         help
1749           Enable hardware performance counter support for perf events. If
1750           disabled, perf events will use software events only.
1751
1752 source "mm/Kconfig"
1753
1754 config FORCE_MAX_ZONEORDER
1755         int "Maximum zone order" if ARCH_SHMOBILE
1756         range 11 64 if ARCH_SHMOBILE
1757         default "9" if SA1111
1758         default "11"
1759         help
1760           The kernel memory allocator divides physically contiguous memory
1761           blocks into "zones", where each zone is a power of two number of
1762           pages.  This option selects the largest power of two that the kernel
1763           keeps in the memory allocator.  If you need to allocate very large
1764           blocks of physically contiguous memory, then you may need to
1765           increase this value.
1766
1767           This config option is actually maximum order plus one. For example,
1768           a value of 11 means that the largest free memory block is 2^10 pages.
1769
1770 config LEDS
1771         bool "Timer and CPU usage LEDs"
1772         depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1773                    ARCH_EBSA285 || ARCH_INTEGRATOR || \
1774                    ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1775                    ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1776                    ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1777                    ARCH_AT91 || ARCH_DAVINCI || \
1778                    ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1779         help
1780           If you say Y here, the LEDs on your machine will be used
1781           to provide useful information about your current system status.
1782
1783           If you are compiling a kernel for a NetWinder or EBSA-285, you will
1784           be able to select which LEDs are active using the options below. If
1785           you are compiling a kernel for the EBSA-110 or the LART however, the
1786           red LED will simply flash regularly to indicate that the system is
1787           still functional. It is safe to say Y here if you have a CATS
1788           system, but the driver will do nothing.
1789
1790 config LEDS_TIMER
1791         bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1792                             OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1793                             || MACH_OMAP_PERSEUS2
1794         depends on LEDS
1795         depends on !GENERIC_CLOCKEVENTS
1796         default y if ARCH_EBSA110
1797         help
1798           If you say Y here, one of the system LEDs (the green one on the
1799           NetWinder, the amber one on the EBSA285, or the red one on the LART)
1800           will flash regularly to indicate that the system is still
1801           operational. This is mainly useful to kernel hackers who are
1802           debugging unstable kernels.
1803
1804           The LART uses the same LED for both Timer LED and CPU usage LED
1805           functions. You may choose to use both, but the Timer LED function
1806           will overrule the CPU usage LED.
1807
1808 config LEDS_CPU
1809         bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1810                         !ARCH_OMAP) \
1811                         || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1812                         || MACH_OMAP_PERSEUS2
1813         depends on LEDS
1814         help
1815           If you say Y here, the red LED will be used to give a good real
1816           time indication of CPU usage, by lighting whenever the idle task
1817           is not currently executing.
1818
1819           The LART uses the same LED for both Timer LED and CPU usage LED
1820           functions. You may choose to use both, but the Timer LED function
1821           will overrule the CPU usage LED.
1822
1823 config ALIGNMENT_TRAP
1824         bool
1825         depends on CPU_CP15_MMU
1826         default y if !ARCH_EBSA110
1827         select HAVE_PROC_CPU if PROC_FS
1828         help
1829           ARM processors cannot fetch/store information which is not
1830           naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1831           address divisible by 4. On 32-bit ARM processors, these non-aligned
1832           fetch/store instructions will be emulated in software if you say
1833           here, which has a severe performance impact. This is necessary for
1834           correct operation of some network protocols. With an IP-only
1835           configuration it is safe to say N, otherwise say Y.
1836
1837 config UACCESS_WITH_MEMCPY
1838         bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1839         depends on MMU && EXPERIMENTAL
1840         default y if CPU_FEROCEON
1841         help
1842           Implement faster copy_to_user and clear_user methods for CPU
1843           cores where a 8-word STM instruction give significantly higher
1844           memory write throughput than a sequence of individual 32bit stores.
1845
1846           A possible side effect is a slight increase in scheduling latency
1847           between threads sharing the same address space if they invoke
1848           such copy operations with large buffers.
1849
1850           However, if the CPU data cache is using a write-allocate mode,
1851           this option is unlikely to provide any performance gain.
1852
1853 config SECCOMP
1854         bool
1855         prompt "Enable seccomp to safely compute untrusted bytecode"
1856         ---help---
1857           This kernel feature is useful for number crunching applications
1858           that may need to compute untrusted bytecode during their
1859           execution. By using pipes or other transports made available to
1860           the process as file descriptors supporting the read/write
1861           syscalls, it's possible to isolate those applications in
1862           their own address space using seccomp. Once seccomp is
1863           enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1864           and the task is only allowed to execute a few safe syscalls
1865           defined by each seccomp mode.
1866
1867 config CC_STACKPROTECTOR
1868         bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1869         depends on EXPERIMENTAL
1870         help
1871           This option turns on the -fstack-protector GCC feature. This
1872           feature puts, at the beginning of functions, a canary value on
1873           the stack just before the return address, and validates
1874           the value just before actually returning.  Stack based buffer
1875           overflows (that need to overwrite this return address) now also
1876           overwrite the canary, which gets detected and the attack is then
1877           neutralized via a kernel panic.
1878           This feature requires gcc version 4.2 or above.
1879
1880 config DEPRECATED_PARAM_STRUCT
1881         bool "Provide old way to pass kernel parameters"
1882         help
1883           This was deprecated in 2001 and announced to live on for 5 years.
1884           Some old boot loaders still use this way.
1885
1886 endmenu
1887
1888 menu "Boot options"
1889
1890 config USE_OF
1891         bool "Flattened Device Tree support"
1892         select OF
1893         select OF_EARLY_FLATTREE
1894         select IRQ_DOMAIN
1895         help
1896           Include support for flattened device tree machine descriptions.
1897
1898 # Compressed boot loader in ROM.  Yes, we really want to ask about
1899 # TEXT and BSS so we preserve their values in the config files.
1900 config ZBOOT_ROM_TEXT
1901         hex "Compressed ROM boot loader base address"
1902         default "0"
1903         help
1904           The physical address at which the ROM-able zImage is to be
1905           placed in the target.  Platforms which normally make use of
1906           ROM-able zImage formats normally set this to a suitable
1907           value in their defconfig file.
1908
1909           If ZBOOT_ROM is not enabled, this has no effect.
1910
1911 config ZBOOT_ROM_BSS
1912         hex "Compressed ROM boot loader BSS address"
1913         default "0"
1914         help
1915           The base address of an area of read/write memory in the target
1916           for the ROM-able zImage which must be available while the
1917           decompressor is running. It must be large enough to hold the
1918           entire decompressed kernel plus an additional 128 KiB.
1919           Platforms which normally make use of ROM-able zImage formats
1920           normally set this to a suitable value in their defconfig file.
1921
1922           If ZBOOT_ROM is not enabled, this has no effect.
1923
1924 config ZBOOT_ROM
1925         bool "Compressed boot loader in ROM/flash"
1926         depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1927         help
1928           Say Y here if you intend to execute your compressed kernel image
1929           (zImage) directly from ROM or flash.  If unsure, say N.
1930
1931 choice
1932         prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1933         depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1934         default ZBOOT_ROM_NONE
1935         help
1936           Include experimental SD/MMC loading code in the ROM-able zImage.
1937           With this enabled it is possible to write the the ROM-able zImage
1938           kernel image to an MMC or SD card and boot the kernel straight
1939           from the reset vector. At reset the processor Mask ROM will load
1940           the first part of the the ROM-able zImage which in turn loads the
1941           rest the kernel image to RAM.
1942
1943 config ZBOOT_ROM_NONE
1944         bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1945         help
1946           Do not load image from SD or MMC
1947
1948 config ZBOOT_ROM_MMCIF
1949         bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1950         help
1951           Load image from MMCIF hardware block.
1952
1953 config ZBOOT_ROM_SH_MOBILE_SDHI
1954         bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1955         help
1956           Load image from SDHI hardware block
1957
1958 endchoice
1959
1960 config ARM_APPENDED_DTB
1961         bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1962         depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1963         help
1964           With this option, the boot code will look for a device tree binary
1965           (DTB) appended to zImage
1966           (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1967
1968           This is meant as a backward compatibility convenience for those
1969           systems with a bootloader that can't be upgraded to accommodate
1970           the documented boot protocol using a device tree.
1971
1972           Beware that there is very little in terms of protection against
1973           this option being confused by leftover garbage in memory that might
1974           look like a DTB header after a reboot if no actual DTB is appended
1975           to zImage.  Do not leave this option active in a production kernel
1976           if you don't intend to always append a DTB.  Proper passing of the
1977           location into r2 of a bootloader provided DTB is always preferable
1978           to this option.
1979
1980 config ARM_ATAG_DTB_COMPAT
1981         bool "Supplement the appended DTB with traditional ATAG information"
1982         depends on ARM_APPENDED_DTB
1983         help
1984           Some old bootloaders can't be updated to a DTB capable one, yet
1985           they provide ATAGs with memory configuration, the ramdisk address,
1986           the kernel cmdline string, etc.  Such information is dynamically
1987           provided by the bootloader and can't always be stored in a static
1988           DTB.  To allow a device tree enabled kernel to be used with such
1989           bootloaders, this option allows zImage to extract the information
1990           from the ATAG list and store it at run time into the appended DTB.
1991
1992 config CMDLINE
1993         string "Default kernel command string"
1994         default ""
1995         help
1996           On some architectures (EBSA110 and CATS), there is currently no way
1997           for the boot loader to pass arguments to the kernel. For these
1998           architectures, you should supply some command-line options at build
1999           time by entering them here. As a minimum, you should specify the
2000           memory size and the root device (e.g., mem=64M root=/dev/nfs).
2001
2002 choice
2003         prompt "Kernel command line type" if CMDLINE != ""
2004         default CMDLINE_FROM_BOOTLOADER
2005
2006 config CMDLINE_FROM_BOOTLOADER
2007         bool "Use bootloader kernel arguments if available"
2008         help
2009           Uses the command-line options passed by the boot loader. If
2010           the boot loader doesn't provide any, the default kernel command
2011           string provided in CMDLINE will be used.
2012
2013 config CMDLINE_EXTEND
2014         bool "Extend bootloader kernel arguments"
2015         help
2016           The command-line arguments provided by the boot loader will be
2017           appended to the default kernel command string.
2018
2019 config CMDLINE_FORCE
2020         bool "Always use the default kernel command string"
2021         help
2022           Always use the default kernel command string, even if the boot
2023           loader passes other arguments to the kernel.
2024           This is useful if you cannot or don't want to change the
2025           command-line options your boot loader passes to the kernel.
2026 endchoice
2027
2028 config XIP_KERNEL
2029         bool "Kernel Execute-In-Place from ROM"
2030         depends on !ZBOOT_ROM && !ARM_LPAE
2031         help
2032           Execute-In-Place allows the kernel to run from non-volatile storage
2033           directly addressable by the CPU, such as NOR flash. This saves RAM
2034           space since the text section of the kernel is not loaded from flash
2035           to RAM.  Read-write sections, such as the data section and stack,
2036           are still copied to RAM.  The XIP kernel is not compressed since
2037           it has to run directly from flash, so it will take more space to
2038           store it.  The flash address used to link the kernel object files,
2039           and for storing it, is configuration dependent. Therefore, if you
2040           say Y here, you must know the proper physical address where to
2041           store the kernel image depending on your own flash memory usage.
2042
2043           Also note that the make target becomes "make xipImage" rather than
2044           "make zImage" or "make Image".  The final kernel binary to put in
2045           ROM memory will be arch/arm/boot/xipImage.
2046
2047           If unsure, say N.
2048
2049 config XIP_PHYS_ADDR
2050         hex "XIP Kernel Physical Location"
2051         depends on XIP_KERNEL
2052         default "0x00080000"
2053         help
2054           This is the physical address in your flash memory the kernel will
2055           be linked for and stored to.  This address is dependent on your
2056           own flash usage.
2057
2058 config KEXEC
2059         bool "Kexec system call (EXPERIMENTAL)"
2060         depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2061         help
2062           kexec is a system call that implements the ability to shutdown your
2063           current kernel, and to start another kernel.  It is like a reboot
2064           but it is independent of the system firmware.   And like a reboot
2065           you can start any kernel with it, not just Linux.
2066
2067           It is an ongoing process to be certain the hardware in a machine
2068           is properly shutdown, so do not be surprised if this code does not
2069           initially work for you.  It may help to enable device hotplugging
2070           support.
2071
2072 config ATAGS_PROC
2073         bool "Export atags in procfs"
2074         depends on KEXEC
2075         default y
2076         help
2077           Should the atags used to boot the kernel be exported in an "atags"
2078           file in procfs. Useful with kexec.
2079
2080 config CRASH_DUMP
2081         bool "Build kdump crash kernel (EXPERIMENTAL)"
2082         depends on EXPERIMENTAL
2083         help
2084           Generate crash dump after being started by kexec. This should
2085           be normally only set in special crash dump kernels which are
2086           loaded in the main kernel with kexec-tools into a specially
2087           reserved region and then later executed after a crash by
2088           kdump/kexec. The crash dump kernel must be compiled to a
2089           memory address not used by the main kernel
2090
2091           For more details see Documentation/kdump/kdump.txt
2092
2093 config AUTO_ZRELADDR
2094         bool "Auto calculation of the decompressed kernel image address"
2095         depends on !ZBOOT_ROM && !ARCH_U300
2096         help
2097           ZRELADDR is the physical address where the decompressed kernel
2098           image will be placed. If AUTO_ZRELADDR is selected, the address
2099           will be determined at run-time by masking the current IP with
2100           0xf8000000. This assumes the zImage being placed in the first 128MB
2101           from start of memory.
2102
2103 endmenu
2104
2105 menu "CPU Power Management"
2106
2107 if ARCH_HAS_CPUFREQ
2108
2109 source "drivers/cpufreq/Kconfig"
2110
2111 config CPU_FREQ_IMX
2112         tristate "CPUfreq driver for i.MX CPUs"
2113         depends on ARCH_MXC && CPU_FREQ
2114         help
2115           This enables the CPUfreq driver for i.MX CPUs.
2116
2117 config CPU_FREQ_SA1100
2118         bool
2119
2120 config CPU_FREQ_SA1110
2121         bool
2122
2123 config CPU_FREQ_INTEGRATOR
2124         tristate "CPUfreq driver for ARM Integrator CPUs"
2125         depends on ARCH_INTEGRATOR && CPU_FREQ
2126         default y
2127         help
2128           This enables the CPUfreq driver for ARM Integrator CPUs.
2129
2130           For details, take a look at <file:Documentation/cpu-freq>.
2131
2132           If in doubt, say Y.
2133
2134 config CPU_FREQ_PXA
2135         bool
2136         depends on CPU_FREQ && ARCH_PXA && PXA25x
2137         default y
2138         select CPU_FREQ_TABLE
2139         select CPU_FREQ_DEFAULT_GOV_USERSPACE
2140
2141 config CPU_FREQ_S3C
2142         bool
2143         help
2144           Internal configuration node for common cpufreq on Samsung SoC
2145
2146 config CPU_FREQ_S3C24XX
2147         bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2148         depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
2149         select CPU_FREQ_S3C
2150         help
2151           This enables the CPUfreq driver for the Samsung S3C24XX family
2152           of CPUs.
2153
2154           For details, take a look at <file:Documentation/cpu-freq>.
2155
2156           If in doubt, say N.
2157
2158 config CPU_FREQ_S3C24XX_PLL
2159         bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2160         depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2161         help
2162           Compile in support for changing the PLL frequency from the
2163           S3C24XX series CPUfreq driver. The PLL takes time to settle
2164           after a frequency change, so by default it is not enabled.
2165
2166           This also means that the PLL tables for the selected CPU(s) will
2167           be built which may increase the size of the kernel image.
2168
2169 config CPU_FREQ_S3C24XX_DEBUG
2170         bool "Debug CPUfreq Samsung driver core"
2171         depends on CPU_FREQ_S3C24XX
2172         help
2173           Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2174
2175 config CPU_FREQ_S3C24XX_IODEBUG
2176         bool "Debug CPUfreq Samsung driver IO timing"
2177         depends on CPU_FREQ_S3C24XX
2178         help
2179           Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2180
2181 config CPU_FREQ_S3C24XX_DEBUGFS
2182         bool "Export debugfs for CPUFreq"
2183         depends on CPU_FREQ_S3C24XX && DEBUG_FS
2184         help
2185           Export status information via debugfs.
2186
2187 endif
2188
2189 source "drivers/cpuidle/Kconfig"
2190
2191 endmenu
2192
2193 menu "Floating point emulation"
2194
2195 comment "At least one emulation must be selected"
2196
2197 config FPE_NWFPE
2198         bool "NWFPE math emulation"
2199         depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2200         ---help---
2201           Say Y to include the NWFPE floating point emulator in the kernel.
2202           This is necessary to run most binaries. Linux does not currently
2203           support floating point hardware so you need to say Y here even if
2204           your machine has an FPA or floating point co-processor podule.
2205
2206           You may say N here if you are going to load the Acorn FPEmulator
2207           early in the bootup.
2208
2209 config FPE_NWFPE_XP
2210         bool "Support extended precision"
2211         depends on FPE_NWFPE
2212         help
2213           Say Y to include 80-bit support in the kernel floating-point
2214           emulator.  Otherwise, only 32 and 64-bit support is compiled in.
2215           Note that gcc does not generate 80-bit operations by default,
2216           so in most cases this option only enlarges the size of the
2217           floating point emulator without any good reason.
2218
2219           You almost surely want to say N here.
2220
2221 config FPE_FASTFPE
2222         bool "FastFPE math emulation (EXPERIMENTAL)"
2223         depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2224         ---help---
2225           Say Y here to include the FAST floating point emulator in the kernel.
2226           This is an experimental much faster emulator which now also has full
2227           precision for the mantissa.  It does not support any exceptions.
2228           It is very simple, and approximately 3-6 times faster than NWFPE.
2229
2230           It should be sufficient for most programs.  It may be not suitable
2231           for scientific calculations, but you have to check this for yourself.
2232           If you do not feel you need a faster FP emulation you should better
2233           choose NWFPE.
2234
2235 config VFP
2236         bool "VFP-format floating point maths"
2237         depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2238         help
2239           Say Y to include VFP support code in the kernel. This is needed
2240           if your hardware includes a VFP unit.
2241
2242           Please see <file:Documentation/arm/VFP/release-notes.txt> for
2243           release notes and additional status information.
2244
2245           Say N if your target does not have VFP hardware.
2246
2247 config VFPv3
2248         bool
2249         depends on VFP
2250         default y if CPU_V7
2251
2252 config NEON
2253         bool "Advanced SIMD (NEON) Extension support"
2254         depends on VFPv3 && CPU_V7
2255         help
2256           Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2257           Extension.
2258
2259 endmenu
2260
2261 menu "Userspace binary formats"
2262
2263 source "fs/Kconfig.binfmt"
2264
2265 config ARTHUR
2266         tristate "RISC OS personality"
2267         depends on !AEABI
2268         help
2269           Say Y here to include the kernel code necessary if you want to run
2270           Acorn RISC OS/Arthur binaries under Linux. This code is still very
2271           experimental; if this sounds frightening, say N and sleep in peace.
2272           You can also say M here to compile this support as a module (which
2273           will be called arthur).
2274
2275 endmenu
2276
2277 menu "Power management options"
2278
2279 source "kernel/power/Kconfig"
2280
2281 config ARCH_SUSPEND_POSSIBLE
2282         depends on !ARCH_S5PC100
2283         depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2284                 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
2285         def_bool y
2286
2287 config ARM_CPU_SUSPEND
2288         def_bool PM_SLEEP
2289
2290 endmenu
2291
2292 source "net/Kconfig"
2293
2294 source "drivers/Kconfig"
2295
2296 source "fs/Kconfig"
2297
2298 source "arch/arm/Kconfig.debug"
2299
2300 source "security/Kconfig"
2301
2302 source "crypto/Kconfig"
2303
2304 source "lib/Kconfig"