4 select ARCH_HAVE_CUSTOM_GPIO_H
6 select HAVE_DMA_API_DEBUG
7 select HAVE_IDE if PCI || ISA || PCMCIA
9 select HAVE_DMA_CONTIGUOUS if (CPU_V6 || CPU_V6K || CPU_V7)
12 select SYS_SUPPORTS_APM_EMULATION
13 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
14 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
15 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
17 select HAVE_ARCH_TRACEHOOK
18 select HAVE_KPROBES if !XIP_KERNEL
19 select HAVE_KRETPROBES if (HAVE_KPROBES)
20 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
21 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
22 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
23 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
24 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
25 select HAVE_GENERIC_DMA_COHERENT
26 select HAVE_KERNEL_GZIP
27 select HAVE_KERNEL_LZO
28 select HAVE_KERNEL_LZMA
31 select HAVE_PERF_EVENTS
32 select PERF_USE_VMALLOC
33 select HAVE_REGS_AND_STACK_ACCESS_API
34 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
35 select HAVE_C_RECORDMCOUNT
36 select HAVE_GENERIC_HARDIRQS
37 select HARDIRQS_SW_RESEND
38 select GENERIC_IRQ_PROBE
39 select GENERIC_IRQ_SHOW
40 select GENERIC_IRQ_PROBE
41 select HARDIRQS_SW_RESEND
42 select CPU_PM if (SUSPEND || CPU_IDLE)
43 select GENERIC_PCI_IOMAP
45 select GENERIC_SMP_IDLE_THREAD
47 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
49 The ARM series is a line of low-power-consumption RISC chip designs
50 licensed by ARM Ltd and targeted at embedded applications and
51 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
52 manufactured, but legacy ARM-based PC hardware remains popular in
53 Europe. There is an ARM Linux project with a web page at
54 <http://www.arm.linux.org.uk/>.
56 config ARM_HAS_SG_CHAIN
59 config NEED_SG_DMA_LENGTH
62 config ARM_DMA_USE_IOMMU
63 select NEED_SG_DMA_LENGTH
64 select ARM_HAS_SG_CHAIN
73 config SYS_SUPPORTS_APM_EMULATION
81 select GENERIC_ALLOCATOR
92 The Extended Industry Standard Architecture (EISA) bus was
93 developed as an open alternative to the IBM MicroChannel bus.
95 The EISA bus provided some of the features of the IBM MicroChannel
96 bus while maintaining backward compatibility with cards made for
97 the older ISA bus. The EISA bus saw limited use between 1988 and
98 1995 when it was made obsolete by the PCI bus.
100 Say Y here if you are building a kernel for an EISA-based machine.
107 config STACKTRACE_SUPPORT
111 config HAVE_LATENCYTOP_SUPPORT
116 config LOCKDEP_SUPPORT
120 config TRACE_IRQFLAGS_SUPPORT
124 config GENERIC_LOCKBREAK
127 depends on SMP && PREEMPT
129 config RWSEM_GENERIC_SPINLOCK
133 config RWSEM_XCHGADD_ALGORITHM
136 config ARCH_HAS_ILOG2_U32
139 config ARCH_HAS_ILOG2_U64
142 config ARCH_HAS_CPUFREQ
145 Internal node to signify that the ARCH has CPUFREQ support
146 and that the relevant menu configurations are displayed for
149 config GENERIC_HWEIGHT
153 config GENERIC_CALIBRATE_DELAY
157 config ARCH_MAY_HAVE_PC_FDC
163 config NEED_DMA_MAP_STATE
166 config ARCH_HAS_DMA_SET_COHERENT_MASK
169 config GENERIC_ISA_DMA
175 config NEED_RET_TO_USER
183 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
184 default DRAM_BASE if REMAP_VECTORS_TO_RAM
187 The base address of exception vectors.
189 config ARM_PATCH_PHYS_VIRT
190 bool "Patch physical to virtual translations at runtime" if EMBEDDED
192 depends on !XIP_KERNEL && MMU
193 depends on !ARCH_REALVIEW || !SPARSEMEM
195 Patch phys-to-virt and virt-to-phys translation functions at
196 boot and module load time according to the position of the
197 kernel in system memory.
199 This can only be used with non-XIP MMU kernels where the base
200 of physical memory is at a 16MB boundary.
202 Only disable this option if you know that you do not require
203 this feature (eg, building a kernel for a single machine) and
204 you need to shrink the kernel to the minimal size.
206 config NEED_MACH_IO_H
209 Select this when mach/io.h is required to provide special
210 definitions for this platform. The need for mach/io.h should
211 be avoided when possible.
213 config NEED_MACH_MEMORY_H
216 Select this when mach/memory.h is required to provide special
217 definitions for this platform. The need for mach/memory.h should
218 be avoided when possible.
221 hex "Physical address of main memory" if MMU
222 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
223 default DRAM_BASE if !MMU
225 Please provide the physical address corresponding to the
226 location of main memory in your system.
232 source "init/Kconfig"
234 source "kernel/Kconfig.freezer"
239 bool "MMU-based Paged Memory Management Support"
242 Select if you want MMU-based virtualised addressing space
243 support by paged memory management. If unsure, say 'Y'.
246 # The "ARM system type" choice list is ordered alphabetically by option
247 # text. Please add new entries in the option alphabetic order.
250 prompt "ARM system type"
251 default ARCH_VERSATILE
253 config ARCH_INTEGRATOR
254 bool "ARM Ltd. Integrator family"
256 select ARCH_HAS_CPUFREQ
258 select HAVE_MACH_CLKDEV
261 select GENERIC_CLOCKEVENTS
262 select PLAT_VERSATILE
263 select PLAT_VERSATILE_FPGA_IRQ
264 select NEED_MACH_IO_H
265 select NEED_MACH_MEMORY_H
267 select MULTI_IRQ_HANDLER
269 Support for ARM's Integrator platform.
272 bool "ARM Ltd. RealView family"
275 select HAVE_MACH_CLKDEV
277 select GENERIC_CLOCKEVENTS
278 select ARCH_WANT_OPTIONAL_GPIOLIB
279 select PLAT_VERSATILE
280 select PLAT_VERSATILE_CLCD
281 select ARM_TIMER_SP804
282 select GPIO_PL061 if GPIOLIB
283 select NEED_MACH_MEMORY_H
285 This enables support for ARM Ltd RealView boards.
287 config ARCH_VERSATILE
288 bool "ARM Ltd. Versatile family"
292 select HAVE_MACH_CLKDEV
294 select GENERIC_CLOCKEVENTS
295 select ARCH_WANT_OPTIONAL_GPIOLIB
296 select NEED_MACH_IO_H if PCI
297 select PLAT_VERSATILE
298 select PLAT_VERSATILE_CLCD
299 select PLAT_VERSATILE_FPGA_IRQ
300 select ARM_TIMER_SP804
302 This enables support for ARM Ltd Versatile board.
305 bool "ARM Ltd. Versatile Express family"
306 select ARCH_WANT_OPTIONAL_GPIOLIB
308 select ARM_TIMER_SP804
310 select HAVE_MACH_CLKDEV
311 select GENERIC_CLOCKEVENTS
313 select HAVE_PATA_PLATFORM
316 select PLAT_VERSATILE
317 select PLAT_VERSATILE_CLCD
319 This enables support for the ARM Ltd Versatile Express boards.
323 select ARCH_REQUIRE_GPIOLIB
327 select NEED_MACH_IO_H if PCCARD
329 This enables support for systems based on Atmel
330 AT91RM9200 and AT91SAM9* processors.
333 bool "Broadcom BCMRING"
337 select ARM_TIMER_SP804
339 select GENERIC_CLOCKEVENTS
340 select ARCH_WANT_OPTIONAL_GPIOLIB
342 Support for Broadcom's BCMRing platform.
345 bool "Calxeda Highbank-based"
346 select ARCH_WANT_OPTIONAL_GPIOLIB
349 select ARM_TIMER_SP804
353 select GENERIC_CLOCKEVENTS
359 Support for the Calxeda Highbank SoC based boards.
362 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
364 select ARCH_USES_GETTIMEOFFSET
365 select NEED_MACH_MEMORY_H
367 Support for Cirrus Logic 711x/721x/731x based boards.
370 bool "Cavium Networks CNS3XXX family"
372 select GENERIC_CLOCKEVENTS
374 select MIGHT_HAVE_CACHE_L2X0
375 select MIGHT_HAVE_PCI
376 select PCI_DOMAINS if PCI
378 Support for Cavium Networks CNS3XXX platform.
381 bool "Cortina Systems Gemini"
383 select ARCH_REQUIRE_GPIOLIB
384 select ARCH_USES_GETTIMEOFFSET
386 Support for the Cortina Systems Gemini family SoCs
389 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
392 select ARCH_WANT_OPTIONAL_GPIOLIB
393 select GENERIC_CLOCKEVENTS
395 select GENERIC_IRQ_CHIP
396 select MIGHT_HAVE_CACHE_L2X0
402 Support for CSR SiRFSoC ARM Cortex A9 Platform
409 select ARCH_USES_GETTIMEOFFSET
410 select NEED_MACH_IO_H
411 select NEED_MACH_MEMORY_H
413 This is an evaluation board for the StrongARM processor available
414 from Digital. It has limited hardware on-board, including an
415 Ethernet interface, two PCMCIA sockets, two serial ports and a
424 select ARCH_REQUIRE_GPIOLIB
425 select ARCH_HAS_HOLES_MEMORYMODEL
426 select ARCH_USES_GETTIMEOFFSET
427 select NEED_MACH_MEMORY_H
429 This enables support for the Cirrus EP93xx series of CPUs.
431 config ARCH_FOOTBRIDGE
435 select GENERIC_CLOCKEVENTS
437 select NEED_MACH_IO_H
438 select NEED_MACH_MEMORY_H
440 Support for systems based on the DC21285 companion chip
441 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
444 bool "Freescale MXC/iMX-based"
445 select GENERIC_CLOCKEVENTS
446 select ARCH_REQUIRE_GPIOLIB
449 select GENERIC_IRQ_CHIP
450 select MULTI_IRQ_HANDLER
452 Support for Freescale MXC/iMX-based family of processors
455 bool "Freescale MXS-based"
456 select GENERIC_CLOCKEVENTS
457 select ARCH_REQUIRE_GPIOLIB
461 select HAVE_CLK_PREPARE
465 Support for Freescale MXS-based family of processors
468 bool "Hilscher NetX based"
472 select GENERIC_CLOCKEVENTS
474 This enables support for systems based on the Hilscher NetX Soc
477 bool "Hynix HMS720x-based"
480 select ARCH_USES_GETTIMEOFFSET
482 This enables support for systems based on the Hynix HMS720x
490 select ARCH_SUPPORTS_MSI
492 select NEED_MACH_IO_H
493 select NEED_MACH_MEMORY_H
494 select NEED_RET_TO_USER
496 Support for Intel's IOP13XX (XScale) family of processors.
502 select NEED_MACH_IO_H
503 select NEED_RET_TO_USER
506 select ARCH_REQUIRE_GPIOLIB
508 Support for Intel's 80219 and IOP32X (XScale) family of
515 select NEED_MACH_IO_H
516 select NEED_RET_TO_USER
519 select ARCH_REQUIRE_GPIOLIB
521 Support for Intel's IOP33X (XScale) family of processors.
526 select ARCH_HAS_DMA_SET_COHERENT_MASK
529 select ARCH_REQUIRE_GPIOLIB
530 select GENERIC_CLOCKEVENTS
531 select MIGHT_HAVE_PCI
532 select NEED_MACH_IO_H
533 select DMABOUNCE if PCI
535 Support for Intel's IXP4XX (XScale) family of processors.
541 select ARCH_REQUIRE_GPIOLIB
542 select GENERIC_CLOCKEVENTS
543 select NEED_MACH_IO_H
546 Support for the Marvell Dove SoC 88AP510
549 bool "Marvell Kirkwood"
552 select ARCH_REQUIRE_GPIOLIB
553 select GENERIC_CLOCKEVENTS
554 select NEED_MACH_IO_H
557 Support for the following Marvell Kirkwood series SoCs:
558 88F6180, 88F6192 and 88F6281.
564 select ARCH_REQUIRE_GPIOLIB
567 select USB_ARCH_HAS_OHCI
569 select GENERIC_CLOCKEVENTS
572 Support for the NXP LPC32XX family of processors
575 bool "Marvell MV78xx0"
578 select ARCH_REQUIRE_GPIOLIB
579 select GENERIC_CLOCKEVENTS
580 select NEED_MACH_IO_H
583 Support for the following Marvell MV78xx0 series SoCs:
591 select ARCH_REQUIRE_GPIOLIB
592 select GENERIC_CLOCKEVENTS
593 select NEED_MACH_IO_H
596 Support for the following Marvell Orion 5x series SoCs:
597 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
598 Orion-2 (5281), Orion-1-90 (6183).
601 bool "Marvell PXA168/910/MMP2"
603 select ARCH_REQUIRE_GPIOLIB
605 select GENERIC_CLOCKEVENTS
610 select GENERIC_ALLOCATOR
612 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
615 bool "Micrel/Kendin KS8695"
617 select ARCH_REQUIRE_GPIOLIB
618 select ARCH_USES_GETTIMEOFFSET
619 select NEED_MACH_MEMORY_H
621 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
622 System-on-Chip devices.
625 bool "Nuvoton W90X900 CPU"
627 select ARCH_REQUIRE_GPIOLIB
630 select GENERIC_CLOCKEVENTS
632 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
633 At present, the w90x900 has been renamed nuc900, regarding
634 the ARM series product line, you can login the following
635 link address to know more.
637 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
638 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
644 select GENERIC_CLOCKEVENTS
648 select MIGHT_HAVE_CACHE_L2X0
649 select NEED_MACH_IO_H if PCI
650 select ARCH_HAS_CPUFREQ
652 This enables support for NVIDIA Tegra based systems (Tegra APX,
653 Tegra 6xx and Tegra 2 series).
655 config ARCH_PICOXCELL
656 bool "Picochip picoXcell"
657 select ARCH_REQUIRE_GPIOLIB
658 select ARM_PATCH_PHYS_VIRT
662 select GENERIC_CLOCKEVENTS
669 This enables support for systems based on the Picochip picoXcell
670 family of Femtocell devices. The picoxcell support requires device tree
674 bool "Philips Nexperia PNX4008 Mobile"
677 select ARCH_USES_GETTIMEOFFSET
679 This enables support for Philips PNX4008 mobile platform.
682 bool "PXA2xx/PXA3xx-based"
685 select ARCH_HAS_CPUFREQ
688 select ARCH_REQUIRE_GPIOLIB
689 select GENERIC_CLOCKEVENTS
694 select MULTI_IRQ_HANDLER
695 select ARM_CPU_SUSPEND if PM
698 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
703 select GENERIC_CLOCKEVENTS
704 select ARCH_REQUIRE_GPIOLIB
707 Support for Qualcomm MSM/QSD based systems. This runs on the
708 apps processor of the MSM/QSD and depends on a shared memory
709 interface to the modem processor which runs the baseband
710 stack and controls some vital subsystems
711 (clock and power control, etc).
714 bool "Renesas SH-Mobile / R-Mobile"
717 select HAVE_MACH_CLKDEV
719 select GENERIC_CLOCKEVENTS
720 select MIGHT_HAVE_CACHE_L2X0
723 select MULTI_IRQ_HANDLER
724 select PM_GENERIC_DOMAINS if PM
725 select NEED_MACH_MEMORY_H
727 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
733 select ARCH_MAY_HAVE_PC_FDC
734 select HAVE_PATA_PLATFORM
737 select ARCH_SPARSEMEM_ENABLE
738 select ARCH_USES_GETTIMEOFFSET
740 select NEED_MACH_IO_H
741 select NEED_MACH_MEMORY_H
743 On the Acorn Risc-PC, Linux can support the internal IDE disk and
744 CD-ROM interface, serial and parallel port, and the floppy drive.
751 select ARCH_SPARSEMEM_ENABLE
753 select ARCH_HAS_CPUFREQ
755 select GENERIC_CLOCKEVENTS
757 select ARCH_REQUIRE_GPIOLIB
759 select NEED_MACH_MEMORY_H
762 Support for StrongARM 11x0 based boards.
765 bool "Samsung S3C24XX SoCs"
767 select ARCH_HAS_CPUFREQ
770 select ARCH_USES_GETTIMEOFFSET
771 select HAVE_S3C2410_I2C if I2C
772 select HAVE_S3C_RTC if RTC_CLASS
773 select HAVE_S3C2410_WATCHDOG if WATCHDOG
774 select NEED_MACH_IO_H
776 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
777 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
778 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
779 Samsung SMDK2410 development board (and derivatives).
782 bool "Samsung S3C64XX"
790 select ARCH_USES_GETTIMEOFFSET
791 select ARCH_HAS_CPUFREQ
792 select ARCH_REQUIRE_GPIOLIB
793 select SAMSUNG_CLKSRC
794 select SAMSUNG_IRQ_VIC_TIMER
795 select S3C_GPIO_TRACK
797 select USB_ARCH_HAS_OHCI
798 select SAMSUNG_GPIOLIB_4BIT
799 select HAVE_S3C2410_I2C if I2C
800 select HAVE_S3C2410_WATCHDOG if WATCHDOG
802 Samsung S3C64XX series based systems
805 bool "Samsung S5P6440 S5P6450"
811 select HAVE_S3C2410_WATCHDOG if WATCHDOG
812 select GENERIC_CLOCKEVENTS
813 select HAVE_S3C2410_I2C if I2C
814 select HAVE_S3C_RTC if RTC_CLASS
816 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
820 bool "Samsung S5PC100"
825 select ARCH_USES_GETTIMEOFFSET
826 select HAVE_S3C2410_I2C if I2C
827 select HAVE_S3C_RTC if RTC_CLASS
828 select HAVE_S3C2410_WATCHDOG if WATCHDOG
830 Samsung S5PC100 series based systems
833 bool "Samsung S5PV210/S5PC110"
835 select ARCH_SPARSEMEM_ENABLE
836 select ARCH_HAS_HOLES_MEMORYMODEL
841 select ARCH_HAS_CPUFREQ
842 select GENERIC_CLOCKEVENTS
843 select HAVE_S3C2410_I2C if I2C
844 select HAVE_S3C_RTC if RTC_CLASS
845 select HAVE_S3C2410_WATCHDOG if WATCHDOG
846 select NEED_MACH_MEMORY_H
848 Samsung S5PV210/S5PC110 series based systems
851 bool "SAMSUNG EXYNOS"
853 select ARCH_SPARSEMEM_ENABLE
854 select ARCH_HAS_HOLES_MEMORYMODEL
858 select ARCH_HAS_CPUFREQ
859 select GENERIC_CLOCKEVENTS
860 select HAVE_S3C_RTC if RTC_CLASS
861 select HAVE_S3C2410_I2C if I2C
862 select HAVE_S3C2410_WATCHDOG if WATCHDOG
863 select NEED_MACH_MEMORY_H
865 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
874 select ARCH_USES_GETTIMEOFFSET
875 select NEED_MACH_MEMORY_H
876 select NEED_MACH_IO_H
878 Support for the StrongARM based Digital DNARD machine, also known
879 as "Shark" (<http://www.shark-linux.de/shark.html>).
882 bool "ST-Ericsson U300 Series"
888 select ARM_PATCH_PHYS_VIRT
890 select GENERIC_CLOCKEVENTS
892 select HAVE_MACH_CLKDEV
894 select ARCH_REQUIRE_GPIOLIB
896 Support for ST-Ericsson U300 series mobile platforms.
899 bool "ST-Ericsson U8500 Series"
903 select GENERIC_CLOCKEVENTS
905 select ARCH_REQUIRE_GPIOLIB
906 select ARCH_HAS_CPUFREQ
908 select MIGHT_HAVE_CACHE_L2X0
910 Support for ST-Ericsson's Ux500 architecture
913 bool "STMicroelectronics Nomadik"
918 select GENERIC_CLOCKEVENTS
920 select MIGHT_HAVE_CACHE_L2X0
921 select ARCH_REQUIRE_GPIOLIB
923 Support for the Nomadik platform by ST-Ericsson
927 select GENERIC_CLOCKEVENTS
928 select ARCH_REQUIRE_GPIOLIB
932 select GENERIC_ALLOCATOR
933 select GENERIC_IRQ_CHIP
934 select ARCH_HAS_HOLES_MEMORYMODEL
936 Support for TI's DaVinci platform.
941 select ARCH_REQUIRE_GPIOLIB
942 select ARCH_HAS_CPUFREQ
944 select GENERIC_CLOCKEVENTS
945 select ARCH_HAS_HOLES_MEMORYMODEL
947 Support for TI's OMAP platform (OMAP1/2/3/4).
952 select ARCH_REQUIRE_GPIOLIB
956 select GENERIC_CLOCKEVENTS
959 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
962 bool "VIA/WonderMedia 85xx"
965 select ARCH_HAS_CPUFREQ
966 select GENERIC_CLOCKEVENTS
967 select ARCH_REQUIRE_GPIOLIB
970 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
973 bool "Xilinx Zynq ARM Cortex A9 Platform"
975 select GENERIC_CLOCKEVENTS
980 select MIGHT_HAVE_CACHE_L2X0
983 Support for Xilinx Zynq ARM Cortex A9 Platform
987 # This is sorted alphabetically by mach-* pathname. However, plat-*
988 # Kconfigs may be included either alphabetically (according to the
989 # plat- suffix) or along side the corresponding mach-* source.
991 source "arch/arm/mach-at91/Kconfig"
993 source "arch/arm/mach-bcmring/Kconfig"
995 source "arch/arm/mach-clps711x/Kconfig"
997 source "arch/arm/mach-cns3xxx/Kconfig"
999 source "arch/arm/mach-davinci/Kconfig"
1001 source "arch/arm/mach-dove/Kconfig"
1003 source "arch/arm/mach-ep93xx/Kconfig"
1005 source "arch/arm/mach-footbridge/Kconfig"
1007 source "arch/arm/mach-gemini/Kconfig"
1009 source "arch/arm/mach-h720x/Kconfig"
1011 source "arch/arm/mach-integrator/Kconfig"
1013 source "arch/arm/mach-iop32x/Kconfig"
1015 source "arch/arm/mach-iop33x/Kconfig"
1017 source "arch/arm/mach-iop13xx/Kconfig"
1019 source "arch/arm/mach-ixp4xx/Kconfig"
1021 source "arch/arm/mach-kirkwood/Kconfig"
1023 source "arch/arm/mach-ks8695/Kconfig"
1025 source "arch/arm/mach-lpc32xx/Kconfig"
1027 source "arch/arm/mach-msm/Kconfig"
1029 source "arch/arm/mach-mv78xx0/Kconfig"
1031 source "arch/arm/plat-mxc/Kconfig"
1033 source "arch/arm/mach-mxs/Kconfig"
1035 source "arch/arm/mach-netx/Kconfig"
1037 source "arch/arm/mach-nomadik/Kconfig"
1038 source "arch/arm/plat-nomadik/Kconfig"
1040 source "arch/arm/plat-omap/Kconfig"
1042 source "arch/arm/mach-omap1/Kconfig"
1044 source "arch/arm/mach-omap2/Kconfig"
1046 source "arch/arm/mach-orion5x/Kconfig"
1048 source "arch/arm/mach-pxa/Kconfig"
1049 source "arch/arm/plat-pxa/Kconfig"
1051 source "arch/arm/mach-mmp/Kconfig"
1053 source "arch/arm/mach-realview/Kconfig"
1055 source "arch/arm/mach-sa1100/Kconfig"
1057 source "arch/arm/plat-samsung/Kconfig"
1058 source "arch/arm/plat-s3c24xx/Kconfig"
1060 source "arch/arm/plat-spear/Kconfig"
1062 source "arch/arm/mach-s3c24xx/Kconfig"
1064 source "arch/arm/mach-s3c2412/Kconfig"
1065 source "arch/arm/mach-s3c2440/Kconfig"
1069 source "arch/arm/mach-s3c64xx/Kconfig"
1072 source "arch/arm/mach-s5p64x0/Kconfig"
1074 source "arch/arm/mach-s5pc100/Kconfig"
1076 source "arch/arm/mach-s5pv210/Kconfig"
1078 source "arch/arm/mach-exynos/Kconfig"
1080 source "arch/arm/mach-shmobile/Kconfig"
1082 source "arch/arm/mach-tegra/Kconfig"
1084 source "arch/arm/mach-u300/Kconfig"
1086 source "arch/arm/mach-ux500/Kconfig"
1088 source "arch/arm/mach-versatile/Kconfig"
1090 source "arch/arm/mach-vexpress/Kconfig"
1091 source "arch/arm/plat-versatile/Kconfig"
1093 source "arch/arm/mach-vt8500/Kconfig"
1095 source "arch/arm/mach-w90x900/Kconfig"
1097 # Definitions to make life easier
1103 select GENERIC_CLOCKEVENTS
1108 select GENERIC_IRQ_CHIP
1114 config PLAT_VERSATILE
1117 config ARM_TIMER_SP804
1120 select HAVE_SCHED_CLOCK
1122 source arch/arm/mm/Kconfig
1126 default 16 if ARCH_EP93XX
1130 bool "Enable iWMMXt support"
1131 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1132 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1134 Enable support for iWMMXt context switching at run time if
1135 running on a CPU that supports it.
1139 depends on CPU_XSCALE
1143 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1144 (!ARCH_OMAP3 || OMAP3_EMU)
1148 config MULTI_IRQ_HANDLER
1151 Allow each machine to specify it's own IRQ handler at run time.
1154 source "arch/arm/Kconfig-nommu"
1157 config ARM_ERRATA_326103
1158 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1161 Executing a SWP instruction to read-only memory does not set bit 11
1162 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1163 treat the access as a read, preventing a COW from occurring and
1164 causing the faulting task to livelock.
1166 config ARM_ERRATA_411920
1167 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1168 depends on CPU_V6 || CPU_V6K
1170 Invalidation of the Instruction Cache operation can
1171 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1172 It does not affect the MPCore. This option enables the ARM Ltd.
1173 recommended workaround.
1175 config ARM_ERRATA_430973
1176 bool "ARM errata: Stale prediction on replaced interworking branch"
1179 This option enables the workaround for the 430973 Cortex-A8
1180 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1181 interworking branch is replaced with another code sequence at the
1182 same virtual address, whether due to self-modifying code or virtual
1183 to physical address re-mapping, Cortex-A8 does not recover from the
1184 stale interworking branch prediction. This results in Cortex-A8
1185 executing the new code sequence in the incorrect ARM or Thumb state.
1186 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1187 and also flushes the branch target cache at every context switch.
1188 Note that setting specific bits in the ACTLR register may not be
1189 available in non-secure mode.
1191 config ARM_ERRATA_458693
1192 bool "ARM errata: Processor deadlock when a false hazard is created"
1195 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1196 erratum. For very specific sequences of memory operations, it is
1197 possible for a hazard condition intended for a cache line to instead
1198 be incorrectly associated with a different cache line. This false
1199 hazard might then cause a processor deadlock. The workaround enables
1200 the L1 caching of the NEON accesses and disables the PLD instruction
1201 in the ACTLR register. Note that setting specific bits in the ACTLR
1202 register may not be available in non-secure mode.
1204 config ARM_ERRATA_460075
1205 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1208 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1209 erratum. Any asynchronous access to the L2 cache may encounter a
1210 situation in which recent store transactions to the L2 cache are lost
1211 and overwritten with stale memory contents from external memory. The
1212 workaround disables the write-allocate mode for the L2 cache via the
1213 ACTLR register. Note that setting specific bits in the ACTLR register
1214 may not be available in non-secure mode.
1216 config ARM_ERRATA_742230
1217 bool "ARM errata: DMB operation may be faulty"
1218 depends on CPU_V7 && SMP
1220 This option enables the workaround for the 742230 Cortex-A9
1221 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1222 between two write operations may not ensure the correct visibility
1223 ordering of the two writes. This workaround sets a specific bit in
1224 the diagnostic register of the Cortex-A9 which causes the DMB
1225 instruction to behave as a DSB, ensuring the correct behaviour of
1228 config ARM_ERRATA_742231
1229 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1230 depends on CPU_V7 && SMP
1232 This option enables the workaround for the 742231 Cortex-A9
1233 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1234 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1235 accessing some data located in the same cache line, may get corrupted
1236 data due to bad handling of the address hazard when the line gets
1237 replaced from one of the CPUs at the same time as another CPU is
1238 accessing it. This workaround sets specific bits in the diagnostic
1239 register of the Cortex-A9 which reduces the linefill issuing
1240 capabilities of the processor.
1242 config PL310_ERRATA_588369
1243 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1244 depends on CACHE_L2X0
1246 The PL310 L2 cache controller implements three types of Clean &
1247 Invalidate maintenance operations: by Physical Address
1248 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1249 They are architecturally defined to behave as the execution of a
1250 clean operation followed immediately by an invalidate operation,
1251 both performing to the same memory location. This functionality
1252 is not correctly implemented in PL310 as clean lines are not
1253 invalidated as a result of these operations.
1255 config ARM_ERRATA_720789
1256 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1259 This option enables the workaround for the 720789 Cortex-A9 (prior to
1260 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1261 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1262 As a consequence of this erratum, some TLB entries which should be
1263 invalidated are not, resulting in an incoherency in the system page
1264 tables. The workaround changes the TLB flushing routines to invalidate
1265 entries regardless of the ASID.
1267 config PL310_ERRATA_727915
1268 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1269 depends on CACHE_L2X0
1271 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1272 operation (offset 0x7FC). This operation runs in background so that
1273 PL310 can handle normal accesses while it is in progress. Under very
1274 rare circumstances, due to this erratum, write data can be lost when
1275 PL310 treats a cacheable write transaction during a Clean &
1276 Invalidate by Way operation.
1278 config ARM_ERRATA_743622
1279 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1282 This option enables the workaround for the 743622 Cortex-A9
1283 (r2p*) erratum. Under very rare conditions, a faulty
1284 optimisation in the Cortex-A9 Store Buffer may lead to data
1285 corruption. This workaround sets a specific bit in the diagnostic
1286 register of the Cortex-A9 which disables the Store Buffer
1287 optimisation, preventing the defect from occurring. This has no
1288 visible impact on the overall performance or power consumption of the
1291 config ARM_ERRATA_751472
1292 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1295 This option enables the workaround for the 751472 Cortex-A9 (prior
1296 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1297 completion of a following broadcasted operation if the second
1298 operation is received by a CPU before the ICIALLUIS has completed,
1299 potentially leading to corrupted entries in the cache or TLB.
1301 config PL310_ERRATA_753970
1302 bool "PL310 errata: cache sync operation may be faulty"
1303 depends on CACHE_PL310
1305 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1307 Under some condition the effect of cache sync operation on
1308 the store buffer still remains when the operation completes.
1309 This means that the store buffer is always asked to drain and
1310 this prevents it from merging any further writes. The workaround
1311 is to replace the normal offset of cache sync operation (0x730)
1312 by another offset targeting an unmapped PL310 register 0x740.
1313 This has the same effect as the cache sync operation: store buffer
1314 drain and waiting for all buffers empty.
1316 config ARM_ERRATA_754322
1317 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1320 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1321 r3p*) erratum. A speculative memory access may cause a page table walk
1322 which starts prior to an ASID switch but completes afterwards. This
1323 can populate the micro-TLB with a stale entry which may be hit with
1324 the new ASID. This workaround places two dsb instructions in the mm
1325 switching code so that no page table walks can cross the ASID switch.
1327 config ARM_ERRATA_754327
1328 bool "ARM errata: no automatic Store Buffer drain"
1329 depends on CPU_V7 && SMP
1331 This option enables the workaround for the 754327 Cortex-A9 (prior to
1332 r2p0) erratum. The Store Buffer does not have any automatic draining
1333 mechanism and therefore a livelock may occur if an external agent
1334 continuously polls a memory location waiting to observe an update.
1335 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1336 written polling loops from denying visibility of updates to memory.
1338 config ARM_ERRATA_364296
1339 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1340 depends on CPU_V6 && !SMP
1342 This options enables the workaround for the 364296 ARM1136
1343 r0p2 erratum (possible cache data corruption with
1344 hit-under-miss enabled). It sets the undocumented bit 31 in
1345 the auxiliary control register and the FI bit in the control
1346 register, thus disabling hit-under-miss without putting the
1347 processor into full low interrupt latency mode. ARM11MPCore
1350 config ARM_ERRATA_764369
1351 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1352 depends on CPU_V7 && SMP
1354 This option enables the workaround for erratum 764369
1355 affecting Cortex-A9 MPCore with two or more processors (all
1356 current revisions). Under certain timing circumstances, a data
1357 cache line maintenance operation by MVA targeting an Inner
1358 Shareable memory region may fail to proceed up to either the
1359 Point of Coherency or to the Point of Unification of the
1360 system. This workaround adds a DSB instruction before the
1361 relevant cache maintenance functions and sets a specific bit
1362 in the diagnostic control register of the SCU.
1364 config PL310_ERRATA_769419
1365 bool "PL310 errata: no automatic Store Buffer drain"
1366 depends on CACHE_L2X0
1368 On revisions of the PL310 prior to r3p2, the Store Buffer does
1369 not automatically drain. This can cause normal, non-cacheable
1370 writes to be retained when the memory system is idle, leading
1371 to suboptimal I/O performance for drivers using coherent DMA.
1372 This option adds a write barrier to the cpu_idle loop so that,
1373 on systems with an outer cache, the store buffer is drained
1378 source "arch/arm/common/Kconfig"
1388 Find out whether you have ISA slots on your motherboard. ISA is the
1389 name of a bus system, i.e. the way the CPU talks to the other stuff
1390 inside your box. Other bus systems are PCI, EISA, MicroChannel
1391 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1392 newer boards don't support it. If you have ISA, say Y, otherwise N.
1394 # Select ISA DMA controller support
1399 # Select ISA DMA interface
1404 bool "PCI support" if MIGHT_HAVE_PCI
1406 Find out whether you have a PCI motherboard. PCI is the name of a
1407 bus system, i.e. the way the CPU talks to the other stuff inside
1408 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1409 VESA. If you have PCI, say Y, otherwise N.
1415 config PCI_NANOENGINE
1416 bool "BSE nanoEngine PCI support"
1417 depends on SA1100_NANOENGINE
1419 Enable PCI on the BSE nanoEngine board.
1424 # Select the host bridge type
1425 config PCI_HOST_VIA82C505
1427 depends on PCI && ARCH_SHARK
1430 config PCI_HOST_ITE8152
1432 depends on PCI && MACH_ARMCORE
1436 source "drivers/pci/Kconfig"
1438 source "drivers/pcmcia/Kconfig"
1442 menu "Kernel Features"
1447 This option should be selected by machines which have an SMP-
1450 The only effect of this option is to make the SMP-related
1451 options available to the user for configuration.
1454 bool "Symmetric Multi-Processing"
1455 depends on CPU_V6K || CPU_V7
1456 depends on GENERIC_CLOCKEVENTS
1459 select USE_GENERIC_SMP_HELPERS
1460 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1462 This enables support for systems with more than one CPU. If you have
1463 a system with only one CPU, like most personal computers, say N. If
1464 you have a system with more than one CPU, say Y.
1466 If you say N here, the kernel will run on single and multiprocessor
1467 machines, but will use only one CPU of a multiprocessor machine. If
1468 you say Y here, the kernel will run on many, but not all, single
1469 processor machines. On a single processor machine, the kernel will
1470 run faster if you say N here.
1472 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1473 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1474 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1476 If you don't know what to do here, say N.
1479 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1480 depends on EXPERIMENTAL
1481 depends on SMP && !XIP_KERNEL
1484 SMP kernels contain instructions which fail on non-SMP processors.
1485 Enabling this option allows the kernel to modify itself to make
1486 these instructions safe. Disabling it allows about 1K of space
1489 If you don't know what to do here, say Y.
1491 config ARM_CPU_TOPOLOGY
1492 bool "Support cpu topology definition"
1493 depends on SMP && CPU_V7
1496 Support ARM cpu topology definition. The MPIDR register defines
1497 affinity between processors which is then used to describe the cpu
1498 topology of an ARM System.
1501 bool "Multi-core scheduler support"
1502 depends on ARM_CPU_TOPOLOGY
1504 Multi-core scheduler support improves the CPU scheduler's decision
1505 making when dealing with multi-core CPU chips at a cost of slightly
1506 increased overhead in some places. If unsure say N here.
1509 bool "SMT scheduler support"
1510 depends on ARM_CPU_TOPOLOGY
1512 Improves the CPU scheduler's decision making when dealing with
1513 MultiThreading at a cost of slightly increased overhead in some
1514 places. If unsure say N here.
1519 This option enables support for the ARM system coherency unit
1521 config ARM_ARCH_TIMER
1522 bool "Architected timer support"
1525 This option enables support for the ARM architected timer
1531 This options enables support for the ARM timer and watchdog unit
1534 prompt "Memory split"
1537 Select the desired split between kernel and user memory.
1539 If you are not absolutely sure what you are doing, leave this
1543 bool "3G/1G user/kernel split"
1545 bool "2G/2G user/kernel split"
1547 bool "1G/3G user/kernel split"
1552 default 0x40000000 if VMSPLIT_1G
1553 default 0x80000000 if VMSPLIT_2G
1557 int "Maximum number of CPUs (2-32)"
1563 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1564 depends on SMP && HOTPLUG && EXPERIMENTAL
1566 Say Y here to experiment with turning CPUs off and on. CPUs
1567 can be controlled through /sys/devices/system/cpu.
1570 bool "Use local timer interrupts"
1573 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1575 Enable support for local timers on SMP platforms, rather then the
1576 legacy IPI broadcast method. Local timers allows the system
1577 accounting to be spread across the timer interval, preventing a
1578 "thundering herd" at every timer tick.
1582 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1583 default 355 if ARCH_U8500
1584 default 264 if MACH_H4700
1587 Maximum number of GPIOs in the system.
1589 If unsure, leave the default value.
1591 source kernel/Kconfig.preempt
1595 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1596 ARCH_S5PV210 || ARCH_EXYNOS4
1597 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1598 default AT91_TIMER_HZ if ARCH_AT91
1599 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1602 config THUMB2_KERNEL
1603 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1604 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1606 select ARM_ASM_UNIFIED
1609 By enabling this option, the kernel will be compiled in
1610 Thumb-2 mode. A compiler/assembler that understand the unified
1611 ARM-Thumb syntax is needed.
1615 config THUMB2_AVOID_R_ARM_THM_JUMP11
1616 bool "Work around buggy Thumb-2 short branch relocations in gas"
1617 depends on THUMB2_KERNEL && MODULES
1620 Various binutils versions can resolve Thumb-2 branches to
1621 locally-defined, preemptible global symbols as short-range "b.n"
1622 branch instructions.
1624 This is a problem, because there's no guarantee the final
1625 destination of the symbol, or any candidate locations for a
1626 trampoline, are within range of the branch. For this reason, the
1627 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1628 relocation in modules at all, and it makes little sense to add
1631 The symptom is that the kernel fails with an "unsupported
1632 relocation" error when loading some modules.
1634 Until fixed tools are available, passing
1635 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1636 code which hits this problem, at the cost of a bit of extra runtime
1637 stack usage in some cases.
1639 The problem is described in more detail at:
1640 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1642 Only Thumb-2 kernels are affected.
1644 Unless you are sure your tools don't have this problem, say Y.
1646 config ARM_ASM_UNIFIED
1650 bool "Use the ARM EABI to compile the kernel"
1652 This option allows for the kernel to be compiled using the latest
1653 ARM ABI (aka EABI). This is only useful if you are using a user
1654 space environment that is also compiled with EABI.
1656 Since there are major incompatibilities between the legacy ABI and
1657 EABI, especially with regard to structure member alignment, this
1658 option also changes the kernel syscall calling convention to
1659 disambiguate both ABIs and allow for backward compatibility support
1660 (selected with CONFIG_OABI_COMPAT).
1662 To use this you need GCC version 4.0.0 or later.
1665 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1666 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1669 This option preserves the old syscall interface along with the
1670 new (ARM EABI) one. It also provides a compatibility layer to
1671 intercept syscalls that have structure arguments which layout
1672 in memory differs between the legacy ABI and the new ARM EABI
1673 (only for non "thumb" binaries). This option adds a tiny
1674 overhead to all syscalls and produces a slightly larger kernel.
1675 If you know you'll be using only pure EABI user space then you
1676 can say N here. If this option is not selected and you attempt
1677 to execute a legacy ABI binary then the result will be
1678 UNPREDICTABLE (in fact it can be predicted that it won't work
1679 at all). If in doubt say Y.
1681 config ARCH_HAS_HOLES_MEMORYMODEL
1684 config ARCH_SPARSEMEM_ENABLE
1687 config ARCH_SPARSEMEM_DEFAULT
1688 def_bool ARCH_SPARSEMEM_ENABLE
1690 config ARCH_SELECT_MEMORY_MODEL
1691 def_bool ARCH_SPARSEMEM_ENABLE
1693 config HAVE_ARCH_PFN_VALID
1694 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1697 bool "High Memory Support"
1700 The address space of ARM processors is only 4 Gigabytes large
1701 and it has to accommodate user address space, kernel address
1702 space as well as some memory mapped IO. That means that, if you
1703 have a large amount of physical memory and/or IO, not all of the
1704 memory can be "permanently mapped" by the kernel. The physical
1705 memory that is not permanently mapped is called "high memory".
1707 Depending on the selected kernel/user memory split, minimum
1708 vmalloc space and actual amount of RAM, you may not need this
1709 option which should result in a slightly faster kernel.
1714 bool "Allocate 2nd-level pagetables from highmem"
1717 config HW_PERF_EVENTS
1718 bool "Enable hardware performance counter support for perf events"
1719 depends on PERF_EVENTS && CPU_HAS_PMU
1722 Enable hardware performance counter support for perf events. If
1723 disabled, perf events will use software events only.
1727 config FORCE_MAX_ZONEORDER
1728 int "Maximum zone order" if ARCH_SHMOBILE
1729 range 11 64 if ARCH_SHMOBILE
1730 default "9" if SA1111
1733 The kernel memory allocator divides physically contiguous memory
1734 blocks into "zones", where each zone is a power of two number of
1735 pages. This option selects the largest power of two that the kernel
1736 keeps in the memory allocator. If you need to allocate very large
1737 blocks of physically contiguous memory, then you may need to
1738 increase this value.
1740 This config option is actually maximum order plus one. For example,
1741 a value of 11 means that the largest free memory block is 2^10 pages.
1744 bool "Timer and CPU usage LEDs"
1745 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1746 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1747 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1748 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1749 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1750 ARCH_AT91 || ARCH_DAVINCI || \
1751 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1753 If you say Y here, the LEDs on your machine will be used
1754 to provide useful information about your current system status.
1756 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1757 be able to select which LEDs are active using the options below. If
1758 you are compiling a kernel for the EBSA-110 or the LART however, the
1759 red LED will simply flash regularly to indicate that the system is
1760 still functional. It is safe to say Y here if you have a CATS
1761 system, but the driver will do nothing.
1764 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1765 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1766 || MACH_OMAP_PERSEUS2
1768 depends on !GENERIC_CLOCKEVENTS
1769 default y if ARCH_EBSA110
1771 If you say Y here, one of the system LEDs (the green one on the
1772 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1773 will flash regularly to indicate that the system is still
1774 operational. This is mainly useful to kernel hackers who are
1775 debugging unstable kernels.
1777 The LART uses the same LED for both Timer LED and CPU usage LED
1778 functions. You may choose to use both, but the Timer LED function
1779 will overrule the CPU usage LED.
1782 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1784 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1785 || MACH_OMAP_PERSEUS2
1788 If you say Y here, the red LED will be used to give a good real
1789 time indication of CPU usage, by lighting whenever the idle task
1790 is not currently executing.
1792 The LART uses the same LED for both Timer LED and CPU usage LED
1793 functions. You may choose to use both, but the Timer LED function
1794 will overrule the CPU usage LED.
1796 config ALIGNMENT_TRAP
1798 depends on CPU_CP15_MMU
1799 default y if !ARCH_EBSA110
1800 select HAVE_PROC_CPU if PROC_FS
1802 ARM processors cannot fetch/store information which is not
1803 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1804 address divisible by 4. On 32-bit ARM processors, these non-aligned
1805 fetch/store instructions will be emulated in software if you say
1806 here, which has a severe performance impact. This is necessary for
1807 correct operation of some network protocols. With an IP-only
1808 configuration it is safe to say N, otherwise say Y.
1810 config UACCESS_WITH_MEMCPY
1811 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1812 depends on MMU && EXPERIMENTAL
1813 default y if CPU_FEROCEON
1815 Implement faster copy_to_user and clear_user methods for CPU
1816 cores where a 8-word STM instruction give significantly higher
1817 memory write throughput than a sequence of individual 32bit stores.
1819 A possible side effect is a slight increase in scheduling latency
1820 between threads sharing the same address space if they invoke
1821 such copy operations with large buffers.
1823 However, if the CPU data cache is using a write-allocate mode,
1824 this option is unlikely to provide any performance gain.
1828 prompt "Enable seccomp to safely compute untrusted bytecode"
1830 This kernel feature is useful for number crunching applications
1831 that may need to compute untrusted bytecode during their
1832 execution. By using pipes or other transports made available to
1833 the process as file descriptors supporting the read/write
1834 syscalls, it's possible to isolate those applications in
1835 their own address space using seccomp. Once seccomp is
1836 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1837 and the task is only allowed to execute a few safe syscalls
1838 defined by each seccomp mode.
1840 config CC_STACKPROTECTOR
1841 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1842 depends on EXPERIMENTAL
1844 This option turns on the -fstack-protector GCC feature. This
1845 feature puts, at the beginning of functions, a canary value on
1846 the stack just before the return address, and validates
1847 the value just before actually returning. Stack based buffer
1848 overflows (that need to overwrite this return address) now also
1849 overwrite the canary, which gets detected and the attack is then
1850 neutralized via a kernel panic.
1851 This feature requires gcc version 4.2 or above.
1853 config DEPRECATED_PARAM_STRUCT
1854 bool "Provide old way to pass kernel parameters"
1856 This was deprecated in 2001 and announced to live on for 5 years.
1857 Some old boot loaders still use this way.
1864 bool "Flattened Device Tree support"
1866 select OF_EARLY_FLATTREE
1869 Include support for flattened device tree machine descriptions.
1871 # Compressed boot loader in ROM. Yes, we really want to ask about
1872 # TEXT and BSS so we preserve their values in the config files.
1873 config ZBOOT_ROM_TEXT
1874 hex "Compressed ROM boot loader base address"
1877 The physical address at which the ROM-able zImage is to be
1878 placed in the target. Platforms which normally make use of
1879 ROM-able zImage formats normally set this to a suitable
1880 value in their defconfig file.
1882 If ZBOOT_ROM is not enabled, this has no effect.
1884 config ZBOOT_ROM_BSS
1885 hex "Compressed ROM boot loader BSS address"
1888 The base address of an area of read/write memory in the target
1889 for the ROM-able zImage which must be available while the
1890 decompressor is running. It must be large enough to hold the
1891 entire decompressed kernel plus an additional 128 KiB.
1892 Platforms which normally make use of ROM-able zImage formats
1893 normally set this to a suitable value in their defconfig file.
1895 If ZBOOT_ROM is not enabled, this has no effect.
1898 bool "Compressed boot loader in ROM/flash"
1899 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1901 Say Y here if you intend to execute your compressed kernel image
1902 (zImage) directly from ROM or flash. If unsure, say N.
1905 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1906 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1907 default ZBOOT_ROM_NONE
1909 Include experimental SD/MMC loading code in the ROM-able zImage.
1910 With this enabled it is possible to write the ROM-able zImage
1911 kernel image to an MMC or SD card and boot the kernel straight
1912 from the reset vector. At reset the processor Mask ROM will load
1913 the first part of the ROM-able zImage which in turn loads the
1914 rest the kernel image to RAM.
1916 config ZBOOT_ROM_NONE
1917 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1919 Do not load image from SD or MMC
1921 config ZBOOT_ROM_MMCIF
1922 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1924 Load image from MMCIF hardware block.
1926 config ZBOOT_ROM_SH_MOBILE_SDHI
1927 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1929 Load image from SDHI hardware block
1933 config ARM_APPENDED_DTB
1934 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1935 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1937 With this option, the boot code will look for a device tree binary
1938 (DTB) appended to zImage
1939 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1941 This is meant as a backward compatibility convenience for those
1942 systems with a bootloader that can't be upgraded to accommodate
1943 the documented boot protocol using a device tree.
1945 Beware that there is very little in terms of protection against
1946 this option being confused by leftover garbage in memory that might
1947 look like a DTB header after a reboot if no actual DTB is appended
1948 to zImage. Do not leave this option active in a production kernel
1949 if you don't intend to always append a DTB. Proper passing of the
1950 location into r2 of a bootloader provided DTB is always preferable
1953 config ARM_ATAG_DTB_COMPAT
1954 bool "Supplement the appended DTB with traditional ATAG information"
1955 depends on ARM_APPENDED_DTB
1957 Some old bootloaders can't be updated to a DTB capable one, yet
1958 they provide ATAGs with memory configuration, the ramdisk address,
1959 the kernel cmdline string, etc. Such information is dynamically
1960 provided by the bootloader and can't always be stored in a static
1961 DTB. To allow a device tree enabled kernel to be used with such
1962 bootloaders, this option allows zImage to extract the information
1963 from the ATAG list and store it at run time into the appended DTB.
1966 string "Default kernel command string"
1969 On some architectures (EBSA110 and CATS), there is currently no way
1970 for the boot loader to pass arguments to the kernel. For these
1971 architectures, you should supply some command-line options at build
1972 time by entering them here. As a minimum, you should specify the
1973 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1976 prompt "Kernel command line type" if CMDLINE != ""
1977 default CMDLINE_FROM_BOOTLOADER
1979 config CMDLINE_FROM_BOOTLOADER
1980 bool "Use bootloader kernel arguments if available"
1982 Uses the command-line options passed by the boot loader. If
1983 the boot loader doesn't provide any, the default kernel command
1984 string provided in CMDLINE will be used.
1986 config CMDLINE_EXTEND
1987 bool "Extend bootloader kernel arguments"
1989 The command-line arguments provided by the boot loader will be
1990 appended to the default kernel command string.
1992 config CMDLINE_FORCE
1993 bool "Always use the default kernel command string"
1995 Always use the default kernel command string, even if the boot
1996 loader passes other arguments to the kernel.
1997 This is useful if you cannot or don't want to change the
1998 command-line options your boot loader passes to the kernel.
2002 bool "Kernel Execute-In-Place from ROM"
2003 depends on !ZBOOT_ROM && !ARM_LPAE
2005 Execute-In-Place allows the kernel to run from non-volatile storage
2006 directly addressable by the CPU, such as NOR flash. This saves RAM
2007 space since the text section of the kernel is not loaded from flash
2008 to RAM. Read-write sections, such as the data section and stack,
2009 are still copied to RAM. The XIP kernel is not compressed since
2010 it has to run directly from flash, so it will take more space to
2011 store it. The flash address used to link the kernel object files,
2012 and for storing it, is configuration dependent. Therefore, if you
2013 say Y here, you must know the proper physical address where to
2014 store the kernel image depending on your own flash memory usage.
2016 Also note that the make target becomes "make xipImage" rather than
2017 "make zImage" or "make Image". The final kernel binary to put in
2018 ROM memory will be arch/arm/boot/xipImage.
2022 config XIP_PHYS_ADDR
2023 hex "XIP Kernel Physical Location"
2024 depends on XIP_KERNEL
2025 default "0x00080000"
2027 This is the physical address in your flash memory the kernel will
2028 be linked for and stored to. This address is dependent on your
2032 bool "Kexec system call (EXPERIMENTAL)"
2033 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2035 kexec is a system call that implements the ability to shutdown your
2036 current kernel, and to start another kernel. It is like a reboot
2037 but it is independent of the system firmware. And like a reboot
2038 you can start any kernel with it, not just Linux.
2040 It is an ongoing process to be certain the hardware in a machine
2041 is properly shutdown, so do not be surprised if this code does not
2042 initially work for you. It may help to enable device hotplugging
2046 bool "Export atags in procfs"
2050 Should the atags used to boot the kernel be exported in an "atags"
2051 file in procfs. Useful with kexec.
2054 bool "Build kdump crash kernel (EXPERIMENTAL)"
2055 depends on EXPERIMENTAL
2057 Generate crash dump after being started by kexec. This should
2058 be normally only set in special crash dump kernels which are
2059 loaded in the main kernel with kexec-tools into a specially
2060 reserved region and then later executed after a crash by
2061 kdump/kexec. The crash dump kernel must be compiled to a
2062 memory address not used by the main kernel
2064 For more details see Documentation/kdump/kdump.txt
2066 config AUTO_ZRELADDR
2067 bool "Auto calculation of the decompressed kernel image address"
2068 depends on !ZBOOT_ROM && !ARCH_U300
2070 ZRELADDR is the physical address where the decompressed kernel
2071 image will be placed. If AUTO_ZRELADDR is selected, the address
2072 will be determined at run-time by masking the current IP with
2073 0xf8000000. This assumes the zImage being placed in the first 128MB
2074 from start of memory.
2078 menu "CPU Power Management"
2082 source "drivers/cpufreq/Kconfig"
2085 tristate "CPUfreq driver for i.MX CPUs"
2086 depends on ARCH_MXC && CPU_FREQ
2088 This enables the CPUfreq driver for i.MX CPUs.
2090 config CPU_FREQ_SA1100
2093 config CPU_FREQ_SA1110
2096 config CPU_FREQ_INTEGRATOR
2097 tristate "CPUfreq driver for ARM Integrator CPUs"
2098 depends on ARCH_INTEGRATOR && CPU_FREQ
2101 This enables the CPUfreq driver for ARM Integrator CPUs.
2103 For details, take a look at <file:Documentation/cpu-freq>.
2109 depends on CPU_FREQ && ARCH_PXA && PXA25x
2111 select CPU_FREQ_TABLE
2112 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2117 Internal configuration node for common cpufreq on Samsung SoC
2119 config CPU_FREQ_S3C24XX
2120 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2121 depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
2124 This enables the CPUfreq driver for the Samsung S3C24XX family
2127 For details, take a look at <file:Documentation/cpu-freq>.
2131 config CPU_FREQ_S3C24XX_PLL
2132 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2133 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2135 Compile in support for changing the PLL frequency from the
2136 S3C24XX series CPUfreq driver. The PLL takes time to settle
2137 after a frequency change, so by default it is not enabled.
2139 This also means that the PLL tables for the selected CPU(s) will
2140 be built which may increase the size of the kernel image.
2142 config CPU_FREQ_S3C24XX_DEBUG
2143 bool "Debug CPUfreq Samsung driver core"
2144 depends on CPU_FREQ_S3C24XX
2146 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2148 config CPU_FREQ_S3C24XX_IODEBUG
2149 bool "Debug CPUfreq Samsung driver IO timing"
2150 depends on CPU_FREQ_S3C24XX
2152 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2154 config CPU_FREQ_S3C24XX_DEBUGFS
2155 bool "Export debugfs for CPUFreq"
2156 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2158 Export status information via debugfs.
2162 source "drivers/cpuidle/Kconfig"
2166 menu "Floating point emulation"
2168 comment "At least one emulation must be selected"
2171 bool "NWFPE math emulation"
2172 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2174 Say Y to include the NWFPE floating point emulator in the kernel.
2175 This is necessary to run most binaries. Linux does not currently
2176 support floating point hardware so you need to say Y here even if
2177 your machine has an FPA or floating point co-processor podule.
2179 You may say N here if you are going to load the Acorn FPEmulator
2180 early in the bootup.
2183 bool "Support extended precision"
2184 depends on FPE_NWFPE
2186 Say Y to include 80-bit support in the kernel floating-point
2187 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2188 Note that gcc does not generate 80-bit operations by default,
2189 so in most cases this option only enlarges the size of the
2190 floating point emulator without any good reason.
2192 You almost surely want to say N here.
2195 bool "FastFPE math emulation (EXPERIMENTAL)"
2196 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2198 Say Y here to include the FAST floating point emulator in the kernel.
2199 This is an experimental much faster emulator which now also has full
2200 precision for the mantissa. It does not support any exceptions.
2201 It is very simple, and approximately 3-6 times faster than NWFPE.
2203 It should be sufficient for most programs. It may be not suitable
2204 for scientific calculations, but you have to check this for yourself.
2205 If you do not feel you need a faster FP emulation you should better
2209 bool "VFP-format floating point maths"
2210 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2212 Say Y to include VFP support code in the kernel. This is needed
2213 if your hardware includes a VFP unit.
2215 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2216 release notes and additional status information.
2218 Say N if your target does not have VFP hardware.
2226 bool "Advanced SIMD (NEON) Extension support"
2227 depends on VFPv3 && CPU_V7
2229 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2234 menu "Userspace binary formats"
2236 source "fs/Kconfig.binfmt"
2239 tristate "RISC OS personality"
2242 Say Y here to include the kernel code necessary if you want to run
2243 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2244 experimental; if this sounds frightening, say N and sleep in peace.
2245 You can also say M here to compile this support as a module (which
2246 will be called arthur).
2250 menu "Power management options"
2252 source "kernel/power/Kconfig"
2254 config ARCH_SUSPEND_POSSIBLE
2255 depends on !ARCH_S5PC100 && !ARCH_TEGRA
2256 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2257 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2260 config ARM_CPU_SUSPEND
2265 source "net/Kconfig"
2267 source "drivers/Kconfig"
2271 source "arch/arm/Kconfig.debug"
2273 source "security/Kconfig"
2275 source "crypto/Kconfig"
2277 source "lib/Kconfig"