arch/arm/Kconfig

   1 config ARM
   2         bool
   3         default y
   4         select ARCH_HAVE_CUSTOM_GPIO_H
   5         select HAVE_AOUT
   6         select HAVE_DMA_API_DEBUG
   7         select HAVE_IDE if PCI || ISA || PCMCIA
   8         select HAVE_DMA_ATTRS
   9         select HAVE_DMA_CONTIGUOUS if (CPU_V6 || CPU_V6K || CPU_V7)
  10         select HAVE_MEMBLOCK
  11         select RTC_LIB
  12         select SYS_SUPPORTS_APM_EMULATION
  13         select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
  14         select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
  15         select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
  16         select HAVE_ARCH_KGDB
  17         select HAVE_ARCH_TRACEHOOK
  18         select HAVE_KPROBES if !XIP_KERNEL
  19         select HAVE_KRETPROBES if (HAVE_KPROBES)
  20         select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
  21         select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
  22         select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
  23         select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
  24         select ARCH_BINFMT_ELF_RANDOMIZE_PIE
  25         select HAVE_GENERIC_DMA_COHERENT
  26         select HAVE_KERNEL_GZIP
  27         select HAVE_KERNEL_LZO
  28         select HAVE_KERNEL_LZMA
  29         select HAVE_KERNEL_XZ
  30         select HAVE_IRQ_WORK
  31         select HAVE_PERF_EVENTS
  32         select PERF_USE_VMALLOC
  33         select HAVE_REGS_AND_STACK_ACCESS_API
  34         select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
  35         select HAVE_C_RECORDMCOUNT
  36         select HAVE_GENERIC_HARDIRQS
  37         select HARDIRQS_SW_RESEND
  38         select GENERIC_IRQ_PROBE
  39         select GENERIC_IRQ_SHOW
  40         select GENERIC_IRQ_PROBE
  41         select HARDIRQS_SW_RESEND
  42         select CPU_PM if (SUSPEND || CPU_IDLE)
  43         select GENERIC_PCI_IOMAP
  44         select HAVE_BPF_JIT
  45         select GENERIC_SMP_IDLE_THREAD
  46         select KTIME_SCALAR
  47         select GENERIC_CLOCKEVENTS_BROADCAST if SMP
  48         help
  49           The ARM series is a line of low-power-consumption RISC chip designs
  50           licensed by ARM Ltd and targeted at embedded applications and
  51           handhelds such as the Compaq IPAQ.  ARM-based PCs are no longer
  52           manufactured, but legacy ARM-based PC hardware remains popular in
  53           Europe.  There is an ARM Linux project with a web page at
  54           <http://www.arm.linux.org.uk/>.
  55
  56 config ARM_HAS_SG_CHAIN
  57         bool
  58
  59 config NEED_SG_DMA_LENGTH
  60         bool
  61
  62 config ARM_DMA_USE_IOMMU
  63         select NEED_SG_DMA_LENGTH
  64         select ARM_HAS_SG_CHAIN
  65         bool
  66
  67 config HAVE_PWM
  68         bool
  69
  70 config MIGHT_HAVE_PCI
  71         bool
  72
  73 config SYS_SUPPORTS_APM_EMULATION
  74         bool
  75
  76 config GENERIC_GPIO
  77         bool
  78
  79 config HAVE_TCM
  80         bool
  81         select GENERIC_ALLOCATOR
  82
  83 config HAVE_PROC_CPU
  84         bool
  85
  86 config NO_IOPORT
  87         bool
  88
  89 config EISA
  90         bool
  91         ---help---
  92           The Extended Industry Standard Architecture (EISA) bus was
  93           developed as an open alternative to the IBM MicroChannel bus.
  94
  95           The EISA bus provided some of the features of the IBM MicroChannel
  96           bus while maintaining backward compatibility with cards made for
  97           the older ISA bus.  The EISA bus saw limited use between 1988 and
  98           1995 when it was made obsolete by the PCI bus.
  99
 100           Say Y here if you are building a kernel for an EISA-based machine.
 101
 102           Otherwise, say N.
 103
 104 config SBUS
 105         bool
 106
 107 config STACKTRACE_SUPPORT
 108         bool
 109         default y
 110
 111 config HAVE_LATENCYTOP_SUPPORT
 112         bool
 113         depends on !SMP
 114         default y
 115
 116 config LOCKDEP_SUPPORT
 117         bool
 118         default y
 119
 120 config TRACE_IRQFLAGS_SUPPORT
 121         bool
 122         default y
 123
 124 config GENERIC_LOCKBREAK
 125         bool
 126         default y
 127         depends on SMP && PREEMPT
 128
 129 config RWSEM_GENERIC_SPINLOCK
 130         bool
 131         default y
 132
 133 config RWSEM_XCHGADD_ALGORITHM
 134         bool
 135
 136 config ARCH_HAS_ILOG2_U32
 137         bool
 138
 139 config ARCH_HAS_ILOG2_U64
 140         bool
 141
 142 config ARCH_HAS_CPUFREQ
 143         bool
 144         help
 145           Internal node to signify that the ARCH has CPUFREQ support
 146           and that the relevant menu configurations are displayed for
 147           it.
 148
 149 config GENERIC_HWEIGHT
 150         bool
 151         default y
 152
 153 config GENERIC_CALIBRATE_DELAY
 154         bool
 155         default y
 156
 157 config ARCH_MAY_HAVE_PC_FDC
 158         bool
 159
 160 config ZONE_DMA
 161         bool
 162
 163 config NEED_DMA_MAP_STATE
 164        def_bool y
 165
 166 config ARCH_HAS_DMA_SET_COHERENT_MASK
 167         bool
 168
 169 config GENERIC_ISA_DMA
 170         bool
 171
 172 config FIQ
 173         bool
 174
 175 config NEED_RET_TO_USER
 176         bool
 177
 178 config ARCH_MTD_XIP
 179         bool
 180
 181 config VECTORS_BASE
 182         hex
 183         default 0xffff0000 if MMU || CPU_HIGH_VECTOR
 184         default DRAM_BASE if REMAP_VECTORS_TO_RAM
 185         default 0x00000000
 186         help
 187           The base address of exception vectors.
 188
 189 config ARM_PATCH_PHYS_VIRT
 190         bool "Patch physical to virtual translations at runtime" if EMBEDDED
 191         default y
 192         depends on !XIP_KERNEL && MMU
 193         depends on !ARCH_REALVIEW || !SPARSEMEM
 194         help
 195           Patch phys-to-virt and virt-to-phys translation functions at
 196           boot and module load time according to the position of the
 197           kernel in system memory.
 198
 199           This can only be used with non-XIP MMU kernels where the base
 200           of physical memory is at a 16MB boundary.
 201
 202           Only disable this option if you know that you do not require
 203           this feature (eg, building a kernel for a single machine) and
 204           you need to shrink the kernel to the minimal size.
 205
 206 config NEED_MACH_IO_H
 207         bool
 208         help
 209           Select this when mach/io.h is required to provide special
 210           definitions for this platform.  The need for mach/io.h should
 211           be avoided when possible.
 212
 213 config NEED_MACH_MEMORY_H
 214         bool
 215         help
 216           Select this when mach/memory.h is required to provide special
 217           definitions for this platform.  The need for mach/memory.h should
 218           be avoided when possible.
 219
 220 config PHYS_OFFSET
 221         hex "Physical address of main memory" if MMU
 222         depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
 223         default DRAM_BASE if !MMU
 224         help
 225           Please provide the physical address corresponding to the
 226           location of main memory in your system.
 227
 228 config GENERIC_BUG
 229         def_bool y
 230         depends on BUG
 231
 232 source "init/Kconfig"
 233
 234 source "kernel/Kconfig.freezer"
 235
 236 menu "System Type"
 237
 238 config MMU
 239         bool "MMU-based Paged Memory Management Support"
 240         default y
 241         help
 242           Select if you want MMU-based virtualised addressing space
 243           support by paged memory management. If unsure, say 'Y'.
 244
 245 #
 246 # The "ARM system type" choice list is ordered alphabetically by option
 247 # text.  Please add new entries in the option alphabetic order.
 248 #
 249 choice
 250         prompt "ARM system type"
 251         default ARCH_VERSATILE
 252
 253 config ARCH_INTEGRATOR
 254         bool "ARM Ltd. Integrator family"
 255         select ARM_AMBA
 256         select ARCH_HAS_CPUFREQ
 257         select CLKDEV_LOOKUP
 258         select HAVE_MACH_CLKDEV
 259         select HAVE_TCM
 260         select ICST
 261         select GENERIC_CLOCKEVENTS
 262         select PLAT_VERSATILE
 263         select PLAT_VERSATILE_FPGA_IRQ
 264         select NEED_MACH_IO_H
 265         select NEED_MACH_MEMORY_H
 266         select SPARSE_IRQ
 267         select MULTI_IRQ_HANDLER
 268         help
 269           Support for ARM's Integrator platform.
 270
 271 config ARCH_REALVIEW
 272         bool "ARM Ltd. RealView family"
 273         select ARM_AMBA
 274         select CLKDEV_LOOKUP
 275         select HAVE_MACH_CLKDEV
 276         select ICST
 277         select GENERIC_CLOCKEVENTS
 278         select ARCH_WANT_OPTIONAL_GPIOLIB
 279         select PLAT_VERSATILE
 280         select PLAT_VERSATILE_CLCD
 281         select ARM_TIMER_SP804
 282         select GPIO_PL061 if GPIOLIB
 283         select NEED_MACH_MEMORY_H
 284         help
 285           This enables support for ARM Ltd RealView boards.
 286
 287 config ARCH_VERSATILE
 288         bool "ARM Ltd. Versatile family"
 289         select ARM_AMBA
 290         select ARM_VIC
 291         select CLKDEV_LOOKUP
 292         select HAVE_MACH_CLKDEV
 293         select ICST
 294         select GENERIC_CLOCKEVENTS
 295         select ARCH_WANT_OPTIONAL_GPIOLIB
 296         select NEED_MACH_IO_H if PCI
 297         select PLAT_VERSATILE
 298         select PLAT_VERSATILE_CLCD
 299         select PLAT_VERSATILE_FPGA_IRQ
 300         select ARM_TIMER_SP804
 301         help
 302           This enables support for ARM Ltd Versatile board.
 303
 304 config ARCH_VEXPRESS
 305         bool "ARM Ltd. Versatile Express family"
 306         select ARCH_WANT_OPTIONAL_GPIOLIB
 307         select ARM_AMBA
 308         select ARM_TIMER_SP804
 309         select CLKDEV_LOOKUP
 310         select HAVE_MACH_CLKDEV
 311         select GENERIC_CLOCKEVENTS
 312         select HAVE_CLK
 313         select HAVE_PATA_PLATFORM
 314         select ICST
 315         select NO_IOPORT
 316         select PLAT_VERSATILE
 317         select PLAT_VERSATILE_CLCD
 318         help
 319           This enables support for the ARM Ltd Versatile Express boards.
 320
 321 config ARCH_AT91
 322         bool "Atmel AT91"
 323         select ARCH_REQUIRE_GPIOLIB
 324         select HAVE_CLK
 325         select CLKDEV_LOOKUP
 326         select IRQ_DOMAIN
 327         select NEED_MACH_IO_H if PCCARD
 328         help
 329           This enables support for systems based on Atmel
 330           AT91RM9200 and AT91SAM9* processors.
 331
 332 config ARCH_BCMRING
 333         bool "Broadcom BCMRING"
 334         depends on MMU
 335         select CPU_V6
 336         select ARM_AMBA
 337         select ARM_TIMER_SP804
 338         select CLKDEV_LOOKUP
 339         select GENERIC_CLOCKEVENTS
 340         select ARCH_WANT_OPTIONAL_GPIOLIB
 341         help
 342           Support for Broadcom's BCMRing platform.
 343
 344 config ARCH_HIGHBANK
 345         bool "Calxeda Highbank-based"
 346         select ARCH_WANT_OPTIONAL_GPIOLIB
 347         select ARM_AMBA
 348         select ARM_GIC
 349         select ARM_TIMER_SP804
 350         select CACHE_L2X0
 351         select CLKDEV_LOOKUP
 352         select CPU_V7
 353         select GENERIC_CLOCKEVENTS
 354         select HAVE_ARM_SCU
 355         select HAVE_SMP
 356         select SPARSE_IRQ
 357         select USE_OF
 358         help
 359           Support for the Calxeda Highbank SoC based boards.
 360
 361 config ARCH_CLPS711X
 362         bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
 363         select CPU_ARM720T
 364         select ARCH_USES_GETTIMEOFFSET
 365         select NEED_MACH_MEMORY_H
 366         help
 367           Support for Cirrus Logic 711x/721x/731x based boards.
 368
 369 config ARCH_CNS3XXX
 370         bool "Cavium Networks CNS3XXX family"
 371         select CPU_V6K
 372         select GENERIC_CLOCKEVENTS
 373         select ARM_GIC
 374         select MIGHT_HAVE_CACHE_L2X0
 375         select MIGHT_HAVE_PCI
 376         select PCI_DOMAINS if PCI
 377         help
 378           Support for Cavium Networks CNS3XXX platform.
 379
 380 config ARCH_GEMINI
 381         bool "Cortina Systems Gemini"
 382         select CPU_FA526
 383         select ARCH_REQUIRE_GPIOLIB
 384         select ARCH_USES_GETTIMEOFFSET
 385         help
 386           Support for the Cortina Systems Gemini family SoCs
 387
 388 config ARCH_PRIMA2
 389         bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
 390         select CPU_V7
 391         select NO_IOPORT
 392         select GENERIC_CLOCKEVENTS
 393         select CLKDEV_LOOKUP
 394         select GENERIC_IRQ_CHIP
 395         select MIGHT_HAVE_CACHE_L2X0
 396         select PINCTRL
 397         select PINCTRL_SIRF
 398         select USE_OF
 399         select ZONE_DMA
 400         help
 401           Support for CSR SiRFSoC ARM Cortex A9 Platform
 402
 403 config ARCH_EBSA110
 404         bool "EBSA-110"
 405         select CPU_SA110
 406         select ISA
 407         select NO_IOPORT
 408         select ARCH_USES_GETTIMEOFFSET
 409         select NEED_MACH_IO_H
 410         select NEED_MACH_MEMORY_H
 411         help
 412           This is an evaluation board for the StrongARM processor available
 413           from Digital. It has limited hardware on-board, including an
 414           Ethernet interface, two PCMCIA sockets, two serial ports and a
 415           parallel port.
 416
 417 config ARCH_EP93XX
 418         bool "EP93xx-based"
 419         select CPU_ARM920T
 420         select ARM_AMBA
 421         select ARM_VIC
 422         select CLKDEV_LOOKUP
 423         select ARCH_REQUIRE_GPIOLIB
 424         select ARCH_HAS_HOLES_MEMORYMODEL
 425         select ARCH_USES_GETTIMEOFFSET
 426         select NEED_MACH_MEMORY_H
 427         help
 428           This enables support for the Cirrus EP93xx series of CPUs.
 429
 430 config ARCH_FOOTBRIDGE
 431         bool "FootBridge"
 432         select CPU_SA110
 433         select FOOTBRIDGE
 434         select GENERIC_CLOCKEVENTS
 435         select HAVE_IDE
 436         select NEED_MACH_IO_H
 437         select NEED_MACH_MEMORY_H
 438         help
 439           Support for systems based on the DC21285 companion chip
 440           ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
 441
 442 config ARCH_MXC
 443         bool "Freescale MXC/iMX-based"
 444         select GENERIC_CLOCKEVENTS
 445         select ARCH_REQUIRE_GPIOLIB
 446         select CLKDEV_LOOKUP
 447         select CLKSRC_MMIO
 448         select GENERIC_IRQ_CHIP
 449         select MULTI_IRQ_HANDLER
 450         help
 451           Support for Freescale MXC/iMX-based family of processors
 452
 453 config ARCH_MXS
 454         bool "Freescale MXS-based"
 455         select GENERIC_CLOCKEVENTS
 456         select ARCH_REQUIRE_GPIOLIB
 457         select CLKDEV_LOOKUP
 458         select CLKSRC_MMIO
 459         select COMMON_CLK
 460         select HAVE_CLK_PREPARE
 461         select PINCTRL
 462         select USE_OF
 463         help
 464           Support for Freescale MXS-based family of processors
 465
 466 config ARCH_NETX
 467         bool "Hilscher NetX based"
 468         select CLKSRC_MMIO
 469         select CPU_ARM926T
 470         select ARM_VIC
 471         select GENERIC_CLOCKEVENTS
 472         help
 473           This enables support for systems based on the Hilscher NetX Soc
 474
 475 config ARCH_H720X
 476         bool "Hynix HMS720x-based"
 477         select CPU_ARM720T
 478         select ISA_DMA_API
 479         select ARCH_USES_GETTIMEOFFSET
 480         help
 481           This enables support for systems based on the Hynix HMS720x
 482
 483 config ARCH_IOP13XX
 484         bool "IOP13xx-based"
 485         depends on MMU
 486         select CPU_XSC3
 487         select PLAT_IOP
 488         select PCI
 489         select ARCH_SUPPORTS_MSI
 490         select VMSPLIT_1G
 491         select NEED_MACH_IO_H
 492         select NEED_MACH_MEMORY_H
 493         select NEED_RET_TO_USER
 494         help
 495           Support for Intel's IOP13XX (XScale) family of processors.
 496
 497 config ARCH_IOP32X
 498         bool "IOP32x-based"
 499         depends on MMU
 500         select CPU_XSCALE
 501         select NEED_MACH_IO_H
 502         select NEED_RET_TO_USER
 503         select PLAT_IOP
 504         select PCI
 505         select ARCH_REQUIRE_GPIOLIB
 506         help
 507           Support for Intel's 80219 and IOP32X (XScale) family of
 508           processors.
 509
 510 config ARCH_IOP33X
 511         bool "IOP33x-based"
 512         depends on MMU
 513         select CPU_XSCALE
 514         select NEED_MACH_IO_H
 515         select NEED_RET_TO_USER
 516         select PLAT_IOP
 517         select PCI
 518         select ARCH_REQUIRE_GPIOLIB
 519         help
 520           Support for Intel's IOP33X (XScale) family of processors.
 521
 522 config ARCH_IXP4XX
 523         bool "IXP4xx-based"
 524         depends on MMU
 525         select ARCH_HAS_DMA_SET_COHERENT_MASK
 526         select CLKSRC_MMIO
 527         select CPU_XSCALE
 528         select ARCH_REQUIRE_GPIOLIB
 529         select GENERIC_CLOCKEVENTS
 530         select MIGHT_HAVE_PCI
 531         select NEED_MACH_IO_H
 532         select DMABOUNCE if PCI
 533         help
 534           Support for Intel's IXP4XX (XScale) family of processors.
 535
 536 config ARCH_MVEBU
 537         bool "Marvell SOCs with Device Tree support"
 538         select GENERIC_CLOCKEVENTS
 539         select MULTI_IRQ_HANDLER
 540         select SPARSE_IRQ
 541         select CLKSRC_MMIO
 542         select GENERIC_IRQ_CHIP
 543         select IRQ_DOMAIN
 544         select COMMON_CLK
 545         help
 546           Support for the Marvell SoC Family with device tree support
 547
 548 config ARCH_DOVE
 549         bool "Marvell Dove"
 550         select CPU_V7
 551         select PCI
 552         select ARCH_REQUIRE_GPIOLIB
 553         select GENERIC_CLOCKEVENTS
 554         select NEED_MACH_IO_H
 555         select PLAT_ORION
 556         help
 557           Support for the Marvell Dove SoC 88AP510
 558
 559 config ARCH_KIRKWOOD
 560         bool "Marvell Kirkwood"
 561         select CPU_FEROCEON
 562         select PCI
 563         select ARCH_REQUIRE_GPIOLIB
 564         select GENERIC_CLOCKEVENTS
 565         select NEED_MACH_IO_H
 566         select PLAT_ORION
 567         help
 568           Support for the following Marvell Kirkwood series SoCs:
 569           88F6180, 88F6192 and 88F6281.
 570
 571 config ARCH_LPC32XX
 572         bool "NXP LPC32XX"
 573         select CLKSRC_MMIO
 574         select CPU_ARM926T
 575         select ARCH_REQUIRE_GPIOLIB
 576         select HAVE_IDE
 577         select ARM_AMBA
 578         select USB_ARCH_HAS_OHCI
 579         select CLKDEV_LOOKUP
 580         select GENERIC_CLOCKEVENTS
 581         select USE_OF
 582         help
 583           Support for the NXP LPC32XX family of processors
 584
 585 config ARCH_MV78XX0
 586         bool "Marvell MV78xx0"
 587         select CPU_FEROCEON
 588         select PCI
 589         select ARCH_REQUIRE_GPIOLIB
 590         select GENERIC_CLOCKEVENTS
 591         select NEED_MACH_IO_H
 592         select PLAT_ORION
 593         help
 594           Support for the following Marvell MV78xx0 series SoCs:
 595           MV781x0, MV782x0.
 596
 597 config ARCH_ORION5X
 598         bool "Marvell Orion"
 599         depends on MMU
 600         select CPU_FEROCEON
 601         select PCI
 602         select ARCH_REQUIRE_GPIOLIB
 603         select GENERIC_CLOCKEVENTS
 604         select NEED_MACH_IO_H
 605         select PLAT_ORION
 606         help
 607           Support for the following Marvell Orion 5x series SoCs:
 608           Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
 609           Orion-2 (5281), Orion-1-90 (6183).
 610
 611 config ARCH_MMP
 612         bool "Marvell PXA168/910/MMP2"
 613         depends on MMU
 614         select ARCH_REQUIRE_GPIOLIB
 615         select CLKDEV_LOOKUP
 616         select GENERIC_CLOCKEVENTS
 617         select GPIO_PXA
 618         select IRQ_DOMAIN
 619         select PLAT_PXA
 620         select SPARSE_IRQ
 621         select GENERIC_ALLOCATOR
 622         help
 623           Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
 624
 625 config ARCH_KS8695
 626         bool "Micrel/Kendin KS8695"
 627         select CPU_ARM922T
 628         select ARCH_REQUIRE_GPIOLIB
 629         select ARCH_USES_GETTIMEOFFSET
 630         select NEED_MACH_MEMORY_H
 631         help
 632           Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
 633           System-on-Chip devices.
 634
 635 config ARCH_W90X900
 636         bool "Nuvoton W90X900 CPU"
 637         select CPU_ARM926T
 638         select ARCH_REQUIRE_GPIOLIB
 639         select CLKDEV_LOOKUP
 640         select CLKSRC_MMIO
 641         select GENERIC_CLOCKEVENTS
 642         help
 643           Support for Nuvoton (Winbond logic dept.) ARM9 processor,
 644           At present, the w90x900 has been renamed nuc900, regarding
 645           the ARM series product line, you can login the following
 646           link address to know more.
 647
 648           <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
 649                 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
 650
 651 config ARCH_TEGRA
 652         bool "NVIDIA Tegra"
 653         select CLKDEV_LOOKUP
 654         select CLKSRC_MMIO
 655         select GENERIC_CLOCKEVENTS
 656         select GENERIC_GPIO
 657         select HAVE_CLK
 658         select HAVE_SMP
 659         select MIGHT_HAVE_CACHE_L2X0
 660         select NEED_MACH_IO_H if PCI
 661         select ARCH_HAS_CPUFREQ
 662         help
 663           This enables support for NVIDIA Tegra based systems (Tegra APX,
 664           Tegra 6xx and Tegra 2 series).
 665
 666 config ARCH_PICOXCELL
 667         bool "Picochip picoXcell"
 668         select ARCH_REQUIRE_GPIOLIB
 669         select ARM_PATCH_PHYS_VIRT
 670         select ARM_VIC
 671         select CPU_V6K
 672         select DW_APB_TIMER
 673         select GENERIC_CLOCKEVENTS
 674         select GENERIC_GPIO
 675         select HAVE_TCM
 676         select NO_IOPORT
 677         select SPARSE_IRQ
 678         select USE_OF
 679         help
 680           This enables support for systems based on the Picochip picoXcell
 681           family of Femtocell devices.  The picoxcell support requires device tree
 682           for all boards.
 683
 684 config ARCH_PNX4008
 685         bool "Philips Nexperia PNX4008 Mobile"
 686         select CPU_ARM926T
 687         select CLKDEV_LOOKUP
 688         select ARCH_USES_GETTIMEOFFSET
 689         help
 690           This enables support for Philips PNX4008 mobile platform.
 691
 692 config ARCH_PXA
 693         bool "PXA2xx/PXA3xx-based"
 694         depends on MMU
 695         select ARCH_MTD_XIP
 696         select ARCH_HAS_CPUFREQ
 697         select CLKDEV_LOOKUP
 698         select CLKSRC_MMIO
 699         select ARCH_REQUIRE_GPIOLIB
 700         select GENERIC_CLOCKEVENTS
 701         select GPIO_PXA
 702         select PLAT_PXA
 703         select SPARSE_IRQ
 704         select AUTO_ZRELADDR
 705         select MULTI_IRQ_HANDLER
 706         select ARM_CPU_SUSPEND if PM
 707         select HAVE_IDE
 708         help
 709           Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
 710
 711 config ARCH_MSM
 712         bool "Qualcomm MSM"
 713         select HAVE_CLK
 714         select GENERIC_CLOCKEVENTS
 715         select ARCH_REQUIRE_GPIOLIB
 716         select CLKDEV_LOOKUP
 717         help
 718           Support for Qualcomm MSM/QSD based systems.  This runs on the
 719           apps processor of the MSM/QSD and depends on a shared memory
 720           interface to the modem processor which runs the baseband
 721           stack and controls some vital subsystems
 722           (clock and power control, etc).
 723
 724 config ARCH_SHMOBILE
 725         bool "Renesas SH-Mobile / R-Mobile"
 726         select HAVE_CLK
 727         select CLKDEV_LOOKUP
 728         select HAVE_MACH_CLKDEV
 729         select HAVE_SMP
 730         select GENERIC_CLOCKEVENTS
 731         select MIGHT_HAVE_CACHE_L2X0
 732         select NO_IOPORT
 733         select SPARSE_IRQ
 734         select MULTI_IRQ_HANDLER
 735         select PM_GENERIC_DOMAINS if PM
 736         select NEED_MACH_MEMORY_H
 737         help
 738           Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
 739
 740 config ARCH_RPC
 741         bool "RiscPC"
 742         select ARCH_ACORN
 743         select FIQ
 744         select ARCH_MAY_HAVE_PC_FDC
 745         select HAVE_PATA_PLATFORM
 746         select ISA_DMA_API
 747         select NO_IOPORT
 748         select ARCH_SPARSEMEM_ENABLE
 749         select ARCH_USES_GETTIMEOFFSET
 750         select HAVE_IDE
 751         select NEED_MACH_IO_H
 752         select NEED_MACH_MEMORY_H
 753         help
 754           On the Acorn Risc-PC, Linux can support the internal IDE disk and
 755           CD-ROM interface, serial and parallel port, and the floppy drive.
 756
 757 config ARCH_SA1100
 758         bool "SA1100-based"
 759         select CLKSRC_MMIO
 760         select CPU_SA1100
 761         select ISA
 762         select ARCH_SPARSEMEM_ENABLE
 763         select ARCH_MTD_XIP
 764         select ARCH_HAS_CPUFREQ
 765         select CPU_FREQ
 766         select GENERIC_CLOCKEVENTS
 767         select CLKDEV_LOOKUP
 768         select ARCH_REQUIRE_GPIOLIB
 769         select HAVE_IDE
 770         select NEED_MACH_MEMORY_H
 771         select SPARSE_IRQ
 772         help
 773           Support for StrongARM 11x0 based boards.
 774
 775 config ARCH_S3C24XX
 776         bool "Samsung S3C24XX SoCs"
 777         select GENERIC_GPIO
 778         select ARCH_HAS_CPUFREQ
 779         select HAVE_CLK
 780         select CLKDEV_LOOKUP
 781         select ARCH_USES_GETTIMEOFFSET
 782         select HAVE_S3C2410_I2C if I2C
 783         select HAVE_S3C_RTC if RTC_CLASS
 784         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 785         select NEED_MACH_IO_H
 786         help
 787           Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
 788           and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
 789           (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
 790           Samsung SMDK2410 development board (and derivatives).
 791
 792 config ARCH_S3C64XX
 793         bool "Samsung S3C64XX"
 794         select PLAT_SAMSUNG
 795         select CPU_V6
 796         select ARM_VIC
 797         select HAVE_CLK
 798         select HAVE_TCM
 799         select CLKDEV_LOOKUP
 800         select NO_IOPORT
 801         select ARCH_USES_GETTIMEOFFSET
 802         select ARCH_HAS_CPUFREQ
 803         select ARCH_REQUIRE_GPIOLIB
 804         select SAMSUNG_CLKSRC
 805         select SAMSUNG_IRQ_VIC_TIMER
 806         select S3C_GPIO_TRACK
 807         select S3C_DEV_NAND
 808         select USB_ARCH_HAS_OHCI
 809         select SAMSUNG_GPIOLIB_4BIT
 810         select HAVE_S3C2410_I2C if I2C
 811         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 812         help
 813           Samsung S3C64XX series based systems
 814
 815 config ARCH_S5P64X0
 816         bool "Samsung S5P6440 S5P6450"
 817         select CPU_V6
 818         select GENERIC_GPIO
 819         select HAVE_CLK
 820         select CLKDEV_LOOKUP
 821         select CLKSRC_MMIO
 822         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 823         select GENERIC_CLOCKEVENTS
 824         select HAVE_S3C2410_I2C if I2C
 825         select HAVE_S3C_RTC if RTC_CLASS
 826         help
 827           Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
 828           SMDK6450.
 829
 830 config ARCH_S5PC100
 831         bool "Samsung S5PC100"
 832         select GENERIC_GPIO
 833         select HAVE_CLK
 834         select CLKDEV_LOOKUP
 835         select CPU_V7
 836         select ARCH_USES_GETTIMEOFFSET
 837         select HAVE_S3C2410_I2C if I2C
 838         select HAVE_S3C_RTC if RTC_CLASS
 839         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 840         help
 841           Samsung S5PC100 series based systems
 842
 843 config ARCH_S5PV210
 844         bool "Samsung S5PV210/S5PC110"
 845         select CPU_V7
 846         select ARCH_SPARSEMEM_ENABLE
 847         select ARCH_HAS_HOLES_MEMORYMODEL
 848         select GENERIC_GPIO
 849         select HAVE_CLK
 850         select CLKDEV_LOOKUP
 851         select CLKSRC_MMIO
 852         select ARCH_HAS_CPUFREQ
 853         select GENERIC_CLOCKEVENTS
 854         select HAVE_S3C2410_I2C if I2C
 855         select HAVE_S3C_RTC if RTC_CLASS
 856         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 857         select NEED_MACH_MEMORY_H
 858         help
 859           Samsung S5PV210/S5PC110 series based systems
 860
 861 config ARCH_EXYNOS
 862         bool "SAMSUNG EXYNOS"
 863         select CPU_V7
 864         select ARCH_SPARSEMEM_ENABLE
 865         select ARCH_HAS_HOLES_MEMORYMODEL
 866         select GENERIC_GPIO
 867         select HAVE_CLK
 868         select CLKDEV_LOOKUP
 869         select ARCH_HAS_CPUFREQ
 870         select GENERIC_CLOCKEVENTS
 871         select HAVE_S3C_RTC if RTC_CLASS
 872         select HAVE_S3C2410_I2C if I2C
 873         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 874         select NEED_MACH_MEMORY_H
 875         help
 876           Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
 877
 878 config ARCH_SHARK
 879         bool "Shark"
 880         select CPU_SA110
 881         select ISA
 882         select ISA_DMA
 883         select ZONE_DMA
 884         select PCI
 885         select ARCH_USES_GETTIMEOFFSET
 886         select NEED_MACH_MEMORY_H
 887         select NEED_MACH_IO_H
 888         help
 889           Support for the StrongARM based Digital DNARD machine, also known
 890           as "Shark" (<http://www.shark-linux.de/shark.html>).
 891
 892 config ARCH_U300
 893         bool "ST-Ericsson U300 Series"
 894         depends on MMU
 895         select CLKSRC_MMIO
 896         select CPU_ARM926T
 897         select HAVE_TCM
 898         select ARM_AMBA
 899         select ARM_PATCH_PHYS_VIRT
 900         select ARM_VIC
 901         select GENERIC_CLOCKEVENTS
 902         select CLKDEV_LOOKUP
 903         select HAVE_MACH_CLKDEV
 904         select GENERIC_GPIO
 905         select ARCH_REQUIRE_GPIOLIB
 906         help
 907           Support for ST-Ericsson U300 series mobile platforms.
 908
 909 config ARCH_U8500
 910         bool "ST-Ericsson U8500 Series"
 911         depends on MMU
 912         select CPU_V7
 913         select ARM_AMBA
 914         select GENERIC_CLOCKEVENTS
 915         select CLKDEV_LOOKUP
 916         select ARCH_REQUIRE_GPIOLIB
 917         select ARCH_HAS_CPUFREQ
 918         select HAVE_SMP
 919         select MIGHT_HAVE_CACHE_L2X0
 920         help
 921           Support for ST-Ericsson's Ux500 architecture
 922
 923 config ARCH_NOMADIK
 924         bool "STMicroelectronics Nomadik"
 925         select ARM_AMBA
 926         select ARM_VIC
 927         select CPU_ARM926T
 928         select CLKDEV_LOOKUP
 929         select GENERIC_CLOCKEVENTS
 930         select PINCTRL
 931         select MIGHT_HAVE_CACHE_L2X0
 932         select ARCH_REQUIRE_GPIOLIB
 933         help
 934           Support for the Nomadik platform by ST-Ericsson
 935
 936 config ARCH_DAVINCI
 937         bool "TI DaVinci"
 938         select GENERIC_CLOCKEVENTS
 939         select ARCH_REQUIRE_GPIOLIB
 940         select ZONE_DMA
 941         select HAVE_IDE
 942         select CLKDEV_LOOKUP
 943         select GENERIC_ALLOCATOR
 944         select GENERIC_IRQ_CHIP
 945         select ARCH_HAS_HOLES_MEMORYMODEL
 946         help
 947           Support for TI's DaVinci platform.
 948
 949 config ARCH_OMAP
 950         bool "TI OMAP"
 951         select HAVE_CLK
 952         select ARCH_REQUIRE_GPIOLIB
 953         select ARCH_HAS_CPUFREQ
 954         select CLKSRC_MMIO
 955         select GENERIC_CLOCKEVENTS
 956         select ARCH_HAS_HOLES_MEMORYMODEL
 957         help
 958           Support for TI's OMAP platform (OMAP1/2/3/4).
 959
 960 config PLAT_SPEAR
 961         bool "ST SPEAr"
 962         select ARM_AMBA
 963         select ARCH_REQUIRE_GPIOLIB
 964         select CLKDEV_LOOKUP
 965         select COMMON_CLK
 966         select CLKSRC_MMIO
 967         select GENERIC_CLOCKEVENTS
 968         select HAVE_CLK
 969         help
 970           Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
 971
 972 config ARCH_VT8500
 973         bool "VIA/WonderMedia 85xx"
 974         select CPU_ARM926T
 975         select GENERIC_GPIO
 976         select ARCH_HAS_CPUFREQ
 977         select GENERIC_CLOCKEVENTS
 978         select ARCH_REQUIRE_GPIOLIB
 979         select HAVE_PWM
 980         help
 981           Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
 982
 983 config ARCH_ZYNQ
 984         bool "Xilinx Zynq ARM Cortex A9 Platform"
 985         select CPU_V7
 986         select GENERIC_CLOCKEVENTS
 987         select CLKDEV_LOOKUP
 988         select ARM_GIC
 989         select ARM_AMBA
 990         select ICST
 991         select MIGHT_HAVE_CACHE_L2X0
 992         select USE_OF
 993         help
 994           Support for Xilinx Zynq ARM Cortex A9 Platform
 995 endchoice
 996
 997 #
 998 # This is sorted alphabetically by mach-* pathname.  However, plat-*
 999 # Kconfigs may be included either alphabetically (according to the
1000 # plat- suffix) or along side the corresponding mach-* source.
1001 #
1002 source "arch/arm/mach-mvebu/Kconfig"
1003
1004 source "arch/arm/mach-at91/Kconfig"
1005
1006 source "arch/arm/mach-bcmring/Kconfig"
1007
1008 source "arch/arm/mach-clps711x/Kconfig"
1009
1010 source "arch/arm/mach-cns3xxx/Kconfig"
1011
1012 source "arch/arm/mach-davinci/Kconfig"
1013
1014 source "arch/arm/mach-dove/Kconfig"
1015
1016 source "arch/arm/mach-ep93xx/Kconfig"
1017
1018 source "arch/arm/mach-footbridge/Kconfig"
1019
1020 source "arch/arm/mach-gemini/Kconfig"
1021
1022 source "arch/arm/mach-h720x/Kconfig"
1023
1024 source "arch/arm/mach-integrator/Kconfig"
1025
1026 source "arch/arm/mach-iop32x/Kconfig"
1027
1028 source "arch/arm/mach-iop33x/Kconfig"
1029
1030 source "arch/arm/mach-iop13xx/Kconfig"
1031
1032 source "arch/arm/mach-ixp4xx/Kconfig"
1033
1034 source "arch/arm/mach-kirkwood/Kconfig"
1035
1036 source "arch/arm/mach-ks8695/Kconfig"
1037
1038 source "arch/arm/mach-lpc32xx/Kconfig"
1039
1040 source "arch/arm/mach-msm/Kconfig"
1041
1042 source "arch/arm/mach-mv78xx0/Kconfig"
1043
1044 source "arch/arm/plat-mxc/Kconfig"
1045
1046 source "arch/arm/mach-mxs/Kconfig"
1047
1048 source "arch/arm/mach-netx/Kconfig"
1049
1050 source "arch/arm/mach-nomadik/Kconfig"
1051 source "arch/arm/plat-nomadik/Kconfig"
1052
1053 source "arch/arm/plat-omap/Kconfig"
1054
1055 source "arch/arm/mach-omap1/Kconfig"
1056
1057 source "arch/arm/mach-omap2/Kconfig"
1058
1059 source "arch/arm/mach-orion5x/Kconfig"
1060
1061 source "arch/arm/mach-pxa/Kconfig"
1062 source "arch/arm/plat-pxa/Kconfig"
1063
1064 source "arch/arm/mach-mmp/Kconfig"
1065
1066 source "arch/arm/mach-realview/Kconfig"
1067
1068 source "arch/arm/mach-sa1100/Kconfig"
1069
1070 source "arch/arm/plat-samsung/Kconfig"
1071 source "arch/arm/plat-s3c24xx/Kconfig"
1072
1073 source "arch/arm/plat-spear/Kconfig"
1074
1075 source "arch/arm/mach-s3c24xx/Kconfig"
1076 if ARCH_S3C24XX
1077 source "arch/arm/mach-s3c2412/Kconfig"
1078 source "arch/arm/mach-s3c2440/Kconfig"
1079 endif
1080
1081 if ARCH_S3C64XX
1082 source "arch/arm/mach-s3c64xx/Kconfig"
1083 endif
1084
1085 source "arch/arm/mach-s5p64x0/Kconfig"
1086
1087 source "arch/arm/mach-s5pc100/Kconfig"
1088
1089 source "arch/arm/mach-s5pv210/Kconfig"
1090
1091 source "arch/arm/mach-exynos/Kconfig"
1092
1093 source "arch/arm/mach-shmobile/Kconfig"
1094
1095 source "arch/arm/mach-tegra/Kconfig"
1096
1097 source "arch/arm/mach-u300/Kconfig"
1098
1099 source "arch/arm/mach-ux500/Kconfig"
1100
1101 source "arch/arm/mach-versatile/Kconfig"
1102
1103 source "arch/arm/mach-vexpress/Kconfig"
1104 source "arch/arm/plat-versatile/Kconfig"
1105
1106 source "arch/arm/mach-vt8500/Kconfig"
1107
1108 source "arch/arm/mach-w90x900/Kconfig"
1109
1110 # Definitions to make life easier
1111 config ARCH_ACORN
1112         bool
1113
1114 config PLAT_IOP
1115         bool
1116         select GENERIC_CLOCKEVENTS
1117
1118 config PLAT_ORION
1119         bool
1120         select CLKSRC_MMIO
1121         select GENERIC_IRQ_CHIP
1122         select COMMON_CLK
1123
1124 config PLAT_PXA
1125         bool
1126
1127 config PLAT_VERSATILE
1128         bool
1129
1130 config ARM_TIMER_SP804
1131         bool
1132         select CLKSRC_MMIO
1133         select HAVE_SCHED_CLOCK
1134
1135 source arch/arm/mm/Kconfig
1136
1137 config ARM_NR_BANKS
1138         int
1139         default 16 if ARCH_EP93XX
1140         default 8
1141
1142 config IWMMXT
1143         bool "Enable iWMMXt support"
1144         depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1145         default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1146         help
1147           Enable support for iWMMXt context switching at run time if
1148           running on a CPU that supports it.
1149
1150 config XSCALE_PMU
1151         bool
1152         depends on CPU_XSCALE
1153         default y
1154
1155 config CPU_HAS_PMU
1156         depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1157                    (!ARCH_OMAP3 || OMAP3_EMU)
1158         default y
1159         bool
1160
1161 config MULTI_IRQ_HANDLER
1162         bool
1163         help
1164           Allow each machine to specify it's own IRQ handler at run time.
1165
1166 if !MMU
1167 source "arch/arm/Kconfig-nommu"
1168 endif
1169
1170 config ARM_ERRATA_326103
1171         bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1172         depends on CPU_V6
1173         help
1174           Executing a SWP instruction to read-only memory does not set bit 11
1175           of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1176           treat the access as a read, preventing a COW from occurring and
1177           causing the faulting task to livelock.
1178
1179 config ARM_ERRATA_411920
1180         bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1181         depends on CPU_V6 || CPU_V6K
1182         help
1183           Invalidation of the Instruction Cache operation can
1184           fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1185           It does not affect the MPCore. This option enables the ARM Ltd.
1186           recommended workaround.
1187
1188 config ARM_ERRATA_430973
1189         bool "ARM errata: Stale prediction on replaced interworking branch"
1190         depends on CPU_V7
1191         help
1192           This option enables the workaround for the 430973 Cortex-A8
1193           (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1194           interworking branch is replaced with another code sequence at the
1195           same virtual address, whether due to self-modifying code or virtual
1196           to physical address re-mapping, Cortex-A8 does not recover from the
1197           stale interworking branch prediction. This results in Cortex-A8
1198           executing the new code sequence in the incorrect ARM or Thumb state.
1199           The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1200           and also flushes the branch target cache at every context switch.
1201           Note that setting specific bits in the ACTLR register may not be
1202           available in non-secure mode.
1203
1204 config ARM_ERRATA_458693
1205         bool "ARM errata: Processor deadlock when a false hazard is created"
1206         depends on CPU_V7
1207         help
1208           This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1209           erratum. For very specific sequences of memory operations, it is
1210           possible for a hazard condition intended for a cache line to instead
1211           be incorrectly associated with a different cache line. This false
1212           hazard might then cause a processor deadlock. The workaround enables
1213           the L1 caching of the NEON accesses and disables the PLD instruction
1214           in the ACTLR register. Note that setting specific bits in the ACTLR
1215           register may not be available in non-secure mode.
1216
1217 config ARM_ERRATA_460075
1218         bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1219         depends on CPU_V7
1220         help
1221           This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1222           erratum. Any asynchronous access to the L2 cache may encounter a
1223           situation in which recent store transactions to the L2 cache are lost
1224           and overwritten with stale memory contents from external memory. The
1225           workaround disables the write-allocate mode for the L2 cache via the
1226           ACTLR register. Note that setting specific bits in the ACTLR register
1227           may not be available in non-secure mode.
1228
1229 config ARM_ERRATA_742230
1230         bool "ARM errata: DMB operation may be faulty"
1231         depends on CPU_V7 && SMP
1232         help
1233           This option enables the workaround for the 742230 Cortex-A9
1234           (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1235           between two write operations may not ensure the correct visibility
1236           ordering of the two writes. This workaround sets a specific bit in
1237           the diagnostic register of the Cortex-A9 which causes the DMB
1238           instruction to behave as a DSB, ensuring the correct behaviour of
1239           the two writes.
1240
1241 config ARM_ERRATA_742231
1242         bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1243         depends on CPU_V7 && SMP
1244         help
1245           This option enables the workaround for the 742231 Cortex-A9
1246           (r2p0..r2p2) erratum. Under certain conditions, specific to the
1247           Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1248           accessing some data located in the same cache line, may get corrupted
1249           data due to bad handling of the address hazard when the line gets
1250           replaced from one of the CPUs at the same time as another CPU is
1251           accessing it. This workaround sets specific bits in the diagnostic
1252           register of the Cortex-A9 which reduces the linefill issuing
1253           capabilities of the processor.
1254
1255 config PL310_ERRATA_588369
1256         bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1257         depends on CACHE_L2X0
1258         help
1259            The PL310 L2 cache controller implements three types of Clean &
1260            Invalidate maintenance operations: by Physical Address
1261            (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1262            They are architecturally defined to behave as the execution of a
1263            clean operation followed immediately by an invalidate operation,
1264            both performing to the same memory location. This functionality
1265            is not correctly implemented in PL310 as clean lines are not
1266            invalidated as a result of these operations.
1267
1268 config ARM_ERRATA_720789
1269         bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1270         depends on CPU_V7
1271         help
1272           This option enables the workaround for the 720789 Cortex-A9 (prior to
1273           r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1274           broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1275           As a consequence of this erratum, some TLB entries which should be
1276           invalidated are not, resulting in an incoherency in the system page
1277           tables. The workaround changes the TLB flushing routines to invalidate
1278           entries regardless of the ASID.
1279
1280 config PL310_ERRATA_727915
1281         bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1282         depends on CACHE_L2X0
1283         help
1284           PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1285           operation (offset 0x7FC). This operation runs in background so that
1286           PL310 can handle normal accesses while it is in progress. Under very
1287           rare circumstances, due to this erratum, write data can be lost when
1288           PL310 treats a cacheable write transaction during a Clean &
1289           Invalidate by Way operation.
1290
1291 config ARM_ERRATA_743622
1292         bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1293         depends on CPU_V7
1294         help
1295           This option enables the workaround for the 743622 Cortex-A9
1296           (r2p*) erratum. Under very rare conditions, a faulty
1297           optimisation in the Cortex-A9 Store Buffer may lead to data
1298           corruption. This workaround sets a specific bit in the diagnostic
1299           register of the Cortex-A9 which disables the Store Buffer
1300           optimisation, preventing the defect from occurring. This has no
1301           visible impact on the overall performance or power consumption of the
1302           processor.
1303
1304 config ARM_ERRATA_751472
1305         bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1306         depends on CPU_V7
1307         help
1308           This option enables the workaround for the 751472 Cortex-A9 (prior
1309           to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1310           completion of a following broadcasted operation if the second
1311           operation is received by a CPU before the ICIALLUIS has completed,
1312           potentially leading to corrupted entries in the cache or TLB.
1313
1314 config PL310_ERRATA_753970
1315         bool "PL310 errata: cache sync operation may be faulty"
1316         depends on CACHE_PL310
1317         help
1318           This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1319
1320           Under some condition the effect of cache sync operation on
1321           the store buffer still remains when the operation completes.
1322           This means that the store buffer is always asked to drain and
1323           this prevents it from merging any further writes. The workaround
1324           is to replace the normal offset of cache sync operation (0x730)
1325           by another offset targeting an unmapped PL310 register 0x740.
1326           This has the same effect as the cache sync operation: store buffer
1327           drain and waiting for all buffers empty.
1328
1329 config ARM_ERRATA_754322
1330         bool "ARM errata: possible faulty MMU translations following an ASID switch"
1331         depends on CPU_V7
1332         help
1333           This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1334           r3p*) erratum. A speculative memory access may cause a page table walk
1335           which starts prior to an ASID switch but completes afterwards. This
1336           can populate the micro-TLB with a stale entry which may be hit with
1337           the new ASID. This workaround places two dsb instructions in the mm
1338           switching code so that no page table walks can cross the ASID switch.
1339
1340 config ARM_ERRATA_754327
1341         bool "ARM errata: no automatic Store Buffer drain"
1342         depends on CPU_V7 && SMP
1343         help
1344           This option enables the workaround for the 754327 Cortex-A9 (prior to
1345           r2p0) erratum. The Store Buffer does not have any automatic draining
1346           mechanism and therefore a livelock may occur if an external agent
1347           continuously polls a memory location waiting to observe an update.
1348           This workaround defines cpu_relax() as smp_mb(), preventing correctly
1349           written polling loops from denying visibility of updates to memory.
1350
1351 config ARM_ERRATA_364296
1352         bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1353         depends on CPU_V6 && !SMP
1354         help
1355           This options enables the workaround for the 364296 ARM1136
1356           r0p2 erratum (possible cache data corruption with
1357           hit-under-miss enabled). It sets the undocumented bit 31 in
1358           the auxiliary control register and the FI bit in the control
1359           register, thus disabling hit-under-miss without putting the
1360           processor into full low interrupt latency mode. ARM11MPCore
1361           is not affected.
1362
1363 config ARM_ERRATA_764369
1364         bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1365         depends on CPU_V7 && SMP
1366         help
1367           This option enables the workaround for erratum 764369
1368           affecting Cortex-A9 MPCore with two or more processors (all
1369           current revisions). Under certain timing circumstances, a data
1370           cache line maintenance operation by MVA targeting an Inner
1371           Shareable memory region may fail to proceed up to either the
1372           Point of Coherency or to the Point of Unification of the
1373           system. This workaround adds a DSB instruction before the
1374           relevant cache maintenance functions and sets a specific bit
1375           in the diagnostic control register of the SCU.
1376
1377 config PL310_ERRATA_769419
1378         bool "PL310 errata: no automatic Store Buffer drain"
1379         depends on CACHE_L2X0
1380         help
1381           On revisions of the PL310 prior to r3p2, the Store Buffer does
1382           not automatically drain. This can cause normal, non-cacheable
1383           writes to be retained when the memory system is idle, leading
1384           to suboptimal I/O performance for drivers using coherent DMA.
1385           This option adds a write barrier to the cpu_idle loop so that,
1386           on systems with an outer cache, the store buffer is drained
1387           explicitly.
1388
1389 endmenu
1390
1391 source "arch/arm/common/Kconfig"
1392
1393 menu "Bus support"
1394
1395 config ARM_AMBA
1396         bool
1397
1398 config ISA
1399         bool
1400         help
1401           Find out whether you have ISA slots on your motherboard.  ISA is the
1402           name of a bus system, i.e. the way the CPU talks to the other stuff
1403           inside your box.  Other bus systems are PCI, EISA, MicroChannel
1404           (MCA) or VESA.  ISA is an older system, now being displaced by PCI;
1405           newer boards don't support it.  If you have ISA, say Y, otherwise N.
1406
1407 # Select ISA DMA controller support
1408 config ISA_DMA
1409         bool
1410         select ISA_DMA_API
1411
1412 # Select ISA DMA interface
1413 config ISA_DMA_API
1414         bool
1415
1416 config PCI
1417         bool "PCI support" if MIGHT_HAVE_PCI
1418         help
1419           Find out whether you have a PCI motherboard. PCI is the name of a
1420           bus system, i.e. the way the CPU talks to the other stuff inside
1421           your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1422           VESA. If you have PCI, say Y, otherwise N.
1423
1424 config PCI_DOMAINS
1425         bool
1426         depends on PCI
1427
1428 config PCI_NANOENGINE
1429         bool "BSE nanoEngine PCI support"
1430         depends on SA1100_NANOENGINE
1431         help
1432           Enable PCI on the BSE nanoEngine board.
1433
1434 config PCI_SYSCALL
1435         def_bool PCI
1436
1437 # Select the host bridge type
1438 config PCI_HOST_VIA82C505
1439         bool
1440         depends on PCI && ARCH_SHARK
1441         default y
1442
1443 config PCI_HOST_ITE8152
1444         bool
1445         depends on PCI && MACH_ARMCORE
1446         default y
1447         select DMABOUNCE
1448
1449 source "drivers/pci/Kconfig"
1450
1451 source "drivers/pcmcia/Kconfig"
1452
1453 endmenu
1454
1455 menu "Kernel Features"
1456
1457 config HAVE_SMP
1458         bool
1459         help
1460           This option should be selected by machines which have an SMP-
1461           capable CPU.
1462
1463           The only effect of this option is to make the SMP-related
1464           options available to the user for configuration.
1465
1466 config SMP
1467         bool "Symmetric Multi-Processing"
1468         depends on CPU_V6K || CPU_V7
1469         depends on GENERIC_CLOCKEVENTS
1470         depends on HAVE_SMP
1471         depends on MMU
1472         select USE_GENERIC_SMP_HELPERS
1473         select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1474         help
1475           This enables support for systems with more than one CPU. If you have
1476           a system with only one CPU, like most personal computers, say N. If
1477           you have a system with more than one CPU, say Y.
1478
1479           If you say N here, the kernel will run on single and multiprocessor
1480           machines, but will use only one CPU of a multiprocessor machine. If
1481           you say Y here, the kernel will run on many, but not all, single
1482           processor machines. On a single processor machine, the kernel will
1483           run faster if you say N here.
1484
1485           See also <file:Documentation/x86/i386/IO-APIC.txt>,
1486           <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1487           <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1488
1489           If you don't know what to do here, say N.
1490
1491 config SMP_ON_UP
1492         bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1493         depends on EXPERIMENTAL
1494         depends on SMP && !XIP_KERNEL
1495         default y
1496         help
1497           SMP kernels contain instructions which fail on non-SMP processors.
1498           Enabling this option allows the kernel to modify itself to make
1499           these instructions safe.  Disabling it allows about 1K of space
1500           savings.
1501
1502           If you don't know what to do here, say Y.
1503
1504 config ARM_CPU_TOPOLOGY
1505         bool "Support cpu topology definition"
1506         depends on SMP && CPU_V7
1507         default y
1508         help
1509           Support ARM cpu topology definition. The MPIDR register defines
1510           affinity between processors which is then used to describe the cpu
1511           topology of an ARM System.
1512
1513 config SCHED_MC
1514         bool "Multi-core scheduler support"
1515         depends on ARM_CPU_TOPOLOGY
1516         help
1517           Multi-core scheduler support improves the CPU scheduler's decision
1518           making when dealing with multi-core CPU chips at a cost of slightly
1519           increased overhead in some places. If unsure say N here.
1520
1521 config SCHED_SMT
1522         bool "SMT scheduler support"
1523         depends on ARM_CPU_TOPOLOGY
1524         help
1525           Improves the CPU scheduler's decision making when dealing with
1526           MultiThreading at a cost of slightly increased overhead in some
1527           places. If unsure say N here.
1528
1529 config HAVE_ARM_SCU
1530         bool
1531         help
1532           This option enables support for the ARM system coherency unit
1533
1534 config ARM_ARCH_TIMER
1535         bool "Architected timer support"
1536         depends on CPU_V7
1537         help
1538           This option enables support for the ARM architected timer
1539
1540 config HAVE_ARM_TWD
1541         bool
1542         depends on SMP
1543         help
1544           This options enables support for the ARM timer and watchdog unit
1545
1546 choice
1547         prompt "Memory split"
1548         default VMSPLIT_3G
1549         help
1550           Select the desired split between kernel and user memory.
1551
1552           If you are not absolutely sure what you are doing, leave this
1553           option alone!
1554
1555         config VMSPLIT_3G
1556                 bool "3G/1G user/kernel split"
1557         config VMSPLIT_2G
1558                 bool "2G/2G user/kernel split"
1559         config VMSPLIT_1G
1560                 bool "1G/3G user/kernel split"
1561 endchoice
1562
1563 config PAGE_OFFSET
1564         hex
1565         default 0x40000000 if VMSPLIT_1G
1566         default 0x80000000 if VMSPLIT_2G
1567         default 0xC0000000
1568
1569 config NR_CPUS
1570         int "Maximum number of CPUs (2-32)"
1571         range 2 32
1572         depends on SMP
1573         default "4"
1574
1575 config HOTPLUG_CPU
1576         bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1577         depends on SMP && HOTPLUG && EXPERIMENTAL
1578         help
1579           Say Y here to experiment with turning CPUs off and on.  CPUs
1580           can be controlled through /sys/devices/system/cpu.
1581
1582 config LOCAL_TIMERS
1583         bool "Use local timer interrupts"
1584         depends on SMP
1585         default y
1586         select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1587         help
1588           Enable support for local timers on SMP platforms, rather then the
1589           legacy IPI broadcast method.  Local timers allows the system
1590           accounting to be spread across the timer interval, preventing a
1591           "thundering herd" at every timer tick.
1592
1593 config ARCH_NR_GPIO
1594         int
1595         default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1596         default 355 if ARCH_U8500
1597         default 264 if MACH_H4700
1598         default 512 if SOC_OMAP5
1599         default 0
1600         help
1601           Maximum number of GPIOs in the system.
1602
1603           If unsure, leave the default value.
1604
1605 source kernel/Kconfig.preempt
1606
1607 config HZ
1608         int
1609         default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1610                 ARCH_S5PV210 || ARCH_EXYNOS4
1611         default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1612         default AT91_TIMER_HZ if ARCH_AT91
1613         default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1614         default 100
1615
1616 config THUMB2_KERNEL
1617         bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1618         depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1619         select AEABI
1620         select ARM_ASM_UNIFIED
1621         select ARM_UNWIND
1622         help
1623           By enabling this option, the kernel will be compiled in
1624           Thumb-2 mode. A compiler/assembler that understand the unified
1625           ARM-Thumb syntax is needed.
1626
1627           If unsure, say N.
1628
1629 config THUMB2_AVOID_R_ARM_THM_JUMP11
1630         bool "Work around buggy Thumb-2 short branch relocations in gas"
1631         depends on THUMB2_KERNEL && MODULES
1632         default y
1633         help
1634           Various binutils versions can resolve Thumb-2 branches to
1635           locally-defined, preemptible global symbols as short-range "b.n"
1636           branch instructions.
1637
1638           This is a problem, because there's no guarantee the final
1639           destination of the symbol, or any candidate locations for a
1640           trampoline, are within range of the branch.  For this reason, the
1641           kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1642           relocation in modules at all, and it makes little sense to add
1643           support.
1644
1645           The symptom is that the kernel fails with an "unsupported
1646           relocation" error when loading some modules.
1647
1648           Until fixed tools are available, passing
1649           -fno-optimize-sibling-calls to gcc should prevent gcc generating
1650           code which hits this problem, at the cost of a bit of extra runtime
1651           stack usage in some cases.
1652
1653           The problem is described in more detail at:
1654               https://bugs.launchpad.net/binutils-linaro/+bug/725126
1655
1656           Only Thumb-2 kernels are affected.
1657
1658           Unless you are sure your tools don't have this problem, say Y.
1659
1660 config ARM_ASM_UNIFIED
1661         bool
1662
1663 config AEABI
1664         bool "Use the ARM EABI to compile the kernel"
1665         help
1666           This option allows for the kernel to be compiled using the latest
1667           ARM ABI (aka EABI).  This is only useful if you are using a user
1668           space environment that is also compiled with EABI.
1669
1670           Since there are major incompatibilities between the legacy ABI and
1671           EABI, especially with regard to structure member alignment, this
1672           option also changes the kernel syscall calling convention to
1673           disambiguate both ABIs and allow for backward compatibility support
1674           (selected with CONFIG_OABI_COMPAT).
1675
1676           To use this you need GCC version 4.0.0 or later.
1677
1678 config OABI_COMPAT
1679         bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1680         depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1681         default y
1682         help
1683           This option preserves the old syscall interface along with the
1684           new (ARM EABI) one. It also provides a compatibility layer to
1685           intercept syscalls that have structure arguments which layout
1686           in memory differs between the legacy ABI and the new ARM EABI
1687           (only for non "thumb" binaries). This option adds a tiny
1688           overhead to all syscalls and produces a slightly larger kernel.
1689           If you know you'll be using only pure EABI user space then you
1690           can say N here. If this option is not selected and you attempt
1691           to execute a legacy ABI binary then the result will be
1692           UNPREDICTABLE (in fact it can be predicted that it won't work
1693           at all). If in doubt say Y.
1694
1695 config ARCH_HAS_HOLES_MEMORYMODEL
1696         bool
1697
1698 config ARCH_SPARSEMEM_ENABLE
1699         bool
1700
1701 config ARCH_SPARSEMEM_DEFAULT
1702         def_bool ARCH_SPARSEMEM_ENABLE
1703
1704 config ARCH_SELECT_MEMORY_MODEL
1705         def_bool ARCH_SPARSEMEM_ENABLE
1706
1707 config HAVE_ARCH_PFN_VALID
1708         def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1709
1710 config HIGHMEM
1711         bool "High Memory Support"
1712         depends on MMU
1713         help
1714           The address space of ARM processors is only 4 Gigabytes large
1715           and it has to accommodate user address space, kernel address
1716           space as well as some memory mapped IO. That means that, if you
1717           have a large amount of physical memory and/or IO, not all of the
1718           memory can be "permanently mapped" by the kernel. The physical
1719           memory that is not permanently mapped is called "high memory".
1720
1721           Depending on the selected kernel/user memory split, minimum
1722           vmalloc space and actual amount of RAM, you may not need this
1723           option which should result in a slightly faster kernel.
1724
1725           If unsure, say n.
1726
1727 config HIGHPTE
1728         bool "Allocate 2nd-level pagetables from highmem"
1729         depends on HIGHMEM
1730
1731 config HW_PERF_EVENTS
1732         bool "Enable hardware performance counter support for perf events"
1733         depends on PERF_EVENTS && CPU_HAS_PMU
1734         default y
1735         help
1736           Enable hardware performance counter support for perf events. If
1737           disabled, perf events will use software events only.
1738
1739 source "mm/Kconfig"
1740
1741 config FORCE_MAX_ZONEORDER
1742         int "Maximum zone order" if ARCH_SHMOBILE
1743         range 11 64 if ARCH_SHMOBILE
1744         default "9" if SA1111
1745         default "11"
1746         help
1747           The kernel memory allocator divides physically contiguous memory
1748           blocks into "zones", where each zone is a power of two number of
1749           pages.  This option selects the largest power of two that the kernel
1750           keeps in the memory allocator.  If you need to allocate very large
1751           blocks of physically contiguous memory, then you may need to
1752           increase this value.
1753
1754           This config option is actually maximum order plus one. For example,
1755           a value of 11 means that the largest free memory block is 2^10 pages.
1756
1757 config LEDS
1758         bool "Timer and CPU usage LEDs"
1759         depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1760                    ARCH_EBSA285 || ARCH_INTEGRATOR || \
1761                    ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1762                    ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1763                    ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1764                    ARCH_AT91 || ARCH_DAVINCI || \
1765                    ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1766         help
1767           If you say Y here, the LEDs on your machine will be used
1768           to provide useful information about your current system status.
1769
1770           If you are compiling a kernel for a NetWinder or EBSA-285, you will
1771           be able to select which LEDs are active using the options below. If
1772           you are compiling a kernel for the EBSA-110 or the LART however, the
1773           red LED will simply flash regularly to indicate that the system is
1774           still functional. It is safe to say Y here if you have a CATS
1775           system, but the driver will do nothing.
1776
1777 config LEDS_TIMER
1778         bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1779                             OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1780                             || MACH_OMAP_PERSEUS2
1781         depends on LEDS
1782         depends on !GENERIC_CLOCKEVENTS
1783         default y if ARCH_EBSA110
1784         help
1785           If you say Y here, one of the system LEDs (the green one on the
1786           NetWinder, the amber one on the EBSA285, or the red one on the LART)
1787           will flash regularly to indicate that the system is still
1788           operational. This is mainly useful to kernel hackers who are
1789           debugging unstable kernels.
1790
1791           The LART uses the same LED for both Timer LED and CPU usage LED
1792           functions. You may choose to use both, but the Timer LED function
1793           will overrule the CPU usage LED.
1794
1795 config LEDS_CPU
1796         bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1797                         !ARCH_OMAP) \
1798                         || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1799                         || MACH_OMAP_PERSEUS2
1800         depends on LEDS
1801         help
1802           If you say Y here, the red LED will be used to give a good real
1803           time indication of CPU usage, by lighting whenever the idle task
1804           is not currently executing.
1805
1806           The LART uses the same LED for both Timer LED and CPU usage LED
1807           functions. You may choose to use both, but the Timer LED function
1808           will overrule the CPU usage LED.
1809
1810 config ALIGNMENT_TRAP
1811         bool
1812         depends on CPU_CP15_MMU
1813         default y if !ARCH_EBSA110
1814         select HAVE_PROC_CPU if PROC_FS
1815         help
1816           ARM processors cannot fetch/store information which is not
1817           naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1818           address divisible by 4. On 32-bit ARM processors, these non-aligned
1819           fetch/store instructions will be emulated in software if you say
1820           here, which has a severe performance impact. This is necessary for
1821           correct operation of some network protocols. With an IP-only
1822           configuration it is safe to say N, otherwise say Y.
1823
1824 config UACCESS_WITH_MEMCPY
1825         bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1826         depends on MMU && EXPERIMENTAL
1827         default y if CPU_FEROCEON
1828         help
1829           Implement faster copy_to_user and clear_user methods for CPU
1830           cores where a 8-word STM instruction give significantly higher
1831           memory write throughput than a sequence of individual 32bit stores.
1832
1833           A possible side effect is a slight increase in scheduling latency
1834           between threads sharing the same address space if they invoke
1835           such copy operations with large buffers.
1836
1837           However, if the CPU data cache is using a write-allocate mode,
1838           this option is unlikely to provide any performance gain.
1839
1840 config SECCOMP
1841         bool
1842         prompt "Enable seccomp to safely compute untrusted bytecode"
1843         ---help---
1844           This kernel feature is useful for number crunching applications
1845           that may need to compute untrusted bytecode during their
1846           execution. By using pipes or other transports made available to
1847           the process as file descriptors supporting the read/write
1848           syscalls, it's possible to isolate those applications in
1849           their own address space using seccomp. Once seccomp is
1850           enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1851           and the task is only allowed to execute a few safe syscalls
1852           defined by each seccomp mode.
1853
1854 config CC_STACKPROTECTOR
1855         bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1856         depends on EXPERIMENTAL
1857         help
1858           This option turns on the -fstack-protector GCC feature. This
1859           feature puts, at the beginning of functions, a canary value on
1860           the stack just before the return address, and validates
1861           the value just before actually returning.  Stack based buffer
1862           overflows (that need to overwrite this return address) now also
1863           overwrite the canary, which gets detected and the attack is then
1864           neutralized via a kernel panic.
1865           This feature requires gcc version 4.2 or above.
1866
1867 config DEPRECATED_PARAM_STRUCT
1868         bool "Provide old way to pass kernel parameters"
1869         help
1870           This was deprecated in 2001 and announced to live on for 5 years.
1871           Some old boot loaders still use this way.
1872
1873 endmenu
1874
1875 menu "Boot options"
1876
1877 config USE_OF
1878         bool "Flattened Device Tree support"
1879         select OF
1880         select OF_EARLY_FLATTREE
1881         select IRQ_DOMAIN
1882         help
1883           Include support for flattened device tree machine descriptions.
1884
1885 # Compressed boot loader in ROM.  Yes, we really want to ask about
1886 # TEXT and BSS so we preserve their values in the config files.
1887 config ZBOOT_ROM_TEXT
1888         hex "Compressed ROM boot loader base address"
1889         default "0"
1890         help
1891           The physical address at which the ROM-able zImage is to be
1892           placed in the target.  Platforms which normally make use of
1893           ROM-able zImage formats normally set this to a suitable
1894           value in their defconfig file.
1895
1896           If ZBOOT_ROM is not enabled, this has no effect.
1897
1898 config ZBOOT_ROM_BSS
1899         hex "Compressed ROM boot loader BSS address"
1900         default "0"
1901         help
1902           The base address of an area of read/write memory in the target
1903           for the ROM-able zImage which must be available while the
1904           decompressor is running. It must be large enough to hold the
1905           entire decompressed kernel plus an additional 128 KiB.
1906           Platforms which normally make use of ROM-able zImage formats
1907           normally set this to a suitable value in their defconfig file.
1908
1909           If ZBOOT_ROM is not enabled, this has no effect.
1910
1911 config ZBOOT_ROM
1912         bool "Compressed boot loader in ROM/flash"
1913         depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1914         help
1915           Say Y here if you intend to execute your compressed kernel image
1916           (zImage) directly from ROM or flash.  If unsure, say N.
1917
1918 choice
1919         prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1920         depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1921         default ZBOOT_ROM_NONE
1922         help
1923           Include experimental SD/MMC loading code in the ROM-able zImage.
1924           With this enabled it is possible to write the ROM-able zImage
1925           kernel image to an MMC or SD card and boot the kernel straight
1926           from the reset vector. At reset the processor Mask ROM will load
1927           the first part of the ROM-able zImage which in turn loads the
1928           rest the kernel image to RAM.
1929
1930 config ZBOOT_ROM_NONE
1931         bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1932         help
1933           Do not load image from SD or MMC
1934
1935 config ZBOOT_ROM_MMCIF
1936         bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1937         help
1938           Load image from MMCIF hardware block.
1939
1940 config ZBOOT_ROM_SH_MOBILE_SDHI
1941         bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1942         help
1943           Load image from SDHI hardware block
1944
1945 endchoice
1946
1947 config ARM_APPENDED_DTB
1948         bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1949         depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1950         help
1951           With this option, the boot code will look for a device tree binary
1952           (DTB) appended to zImage
1953           (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1954
1955           This is meant as a backward compatibility convenience for those
1956           systems with a bootloader that can't be upgraded to accommodate
1957           the documented boot protocol using a device tree.
1958
1959           Beware that there is very little in terms of protection against
1960           this option being confused by leftover garbage in memory that might
1961           look like a DTB header after a reboot if no actual DTB is appended
1962           to zImage.  Do not leave this option active in a production kernel
1963           if you don't intend to always append a DTB.  Proper passing of the
1964           location into r2 of a bootloader provided DTB is always preferable
1965           to this option.
1966
1967 config ARM_ATAG_DTB_COMPAT
1968         bool "Supplement the appended DTB with traditional ATAG information"
1969         depends on ARM_APPENDED_DTB
1970         help
1971           Some old bootloaders can't be updated to a DTB capable one, yet
1972           they provide ATAGs with memory configuration, the ramdisk address,
1973           the kernel cmdline string, etc.  Such information is dynamically
1974           provided by the bootloader and can't always be stored in a static
1975           DTB.  To allow a device tree enabled kernel to be used with such
1976           bootloaders, this option allows zImage to extract the information
1977           from the ATAG list and store it at run time into the appended DTB.
1978
1979 config CMDLINE
1980         string "Default kernel command string"
1981         default ""
1982         help
1983           On some architectures (EBSA110 and CATS), there is currently no way
1984           for the boot loader to pass arguments to the kernel. For these
1985           architectures, you should supply some command-line options at build
1986           time by entering them here. As a minimum, you should specify the
1987           memory size and the root device (e.g., mem=64M root=/dev/nfs).
1988
1989 choice
1990         prompt "Kernel command line type" if CMDLINE != ""
1991         default CMDLINE_FROM_BOOTLOADER
1992
1993 config CMDLINE_FROM_BOOTLOADER
1994         bool "Use bootloader kernel arguments if available"
1995         help
1996           Uses the command-line options passed by the boot loader. If
1997           the boot loader doesn't provide any, the default kernel command
1998           string provided in CMDLINE will be used.
1999
2000 config CMDLINE_EXTEND
2001         bool "Extend bootloader kernel arguments"
2002         help
2003           The command-line arguments provided by the boot loader will be
2004           appended to the default kernel command string.
2005
2006 config CMDLINE_FORCE
2007         bool "Always use the default kernel command string"
2008         help
2009           Always use the default kernel command string, even if the boot
2010           loader passes other arguments to the kernel.
2011           This is useful if you cannot or don't want to change the
2012           command-line options your boot loader passes to the kernel.
2013 endchoice
2014
2015 config XIP_KERNEL
2016         bool "Kernel Execute-In-Place from ROM"
2017         depends on !ZBOOT_ROM && !ARM_LPAE
2018         help
2019           Execute-In-Place allows the kernel to run from non-volatile storage
2020           directly addressable by the CPU, such as NOR flash. This saves RAM
2021           space since the text section of the kernel is not loaded from flash
2022           to RAM.  Read-write sections, such as the data section and stack,
2023           are still copied to RAM.  The XIP kernel is not compressed since
2024           it has to run directly from flash, so it will take more space to
2025           store it.  The flash address used to link the kernel object files,
2026           and for storing it, is configuration dependent. Therefore, if you
2027           say Y here, you must know the proper physical address where to
2028           store the kernel image depending on your own flash memory usage.
2029
2030           Also note that the make target becomes "make xipImage" rather than
2031           "make zImage" or "make Image".  The final kernel binary to put in
2032           ROM memory will be arch/arm/boot/xipImage.
2033
2034           If unsure, say N.
2035
2036 config XIP_PHYS_ADDR
2037         hex "XIP Kernel Physical Location"
2038         depends on XIP_KERNEL
2039         default "0x00080000"
2040         help
2041           This is the physical address in your flash memory the kernel will
2042           be linked for and stored to.  This address is dependent on your
2043           own flash usage.
2044
2045 config KEXEC
2046         bool "Kexec system call (EXPERIMENTAL)"
2047         depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2048         help
2049           kexec is a system call that implements the ability to shutdown your
2050           current kernel, and to start another kernel.  It is like a reboot
2051           but it is independent of the system firmware.   And like a reboot
2052           you can start any kernel with it, not just Linux.
2053
2054           It is an ongoing process to be certain the hardware in a machine
2055           is properly shutdown, so do not be surprised if this code does not
2056           initially work for you.  It may help to enable device hotplugging
2057           support.
2058
2059 config ATAGS_PROC
2060         bool "Export atags in procfs"
2061         depends on KEXEC
2062         default y
2063         help
2064           Should the atags used to boot the kernel be exported in an "atags"
2065           file in procfs. Useful with kexec.
2066
2067 config CRASH_DUMP
2068         bool "Build kdump crash kernel (EXPERIMENTAL)"
2069         depends on EXPERIMENTAL
2070         help
2071           Generate crash dump after being started by kexec. This should
2072           be normally only set in special crash dump kernels which are
2073           loaded in the main kernel with kexec-tools into a specially
2074           reserved region and then later executed after a crash by
2075           kdump/kexec. The crash dump kernel must be compiled to a
2076           memory address not used by the main kernel
2077
2078           For more details see Documentation/kdump/kdump.txt
2079
2080 config AUTO_ZRELADDR
2081         bool "Auto calculation of the decompressed kernel image address"
2082         depends on !ZBOOT_ROM && !ARCH_U300
2083         help
2084           ZRELADDR is the physical address where the decompressed kernel
2085           image will be placed. If AUTO_ZRELADDR is selected, the address
2086           will be determined at run-time by masking the current IP with
2087           0xf8000000. This assumes the zImage being placed in the first 128MB
2088           from start of memory.
2089
2090 endmenu
2091
2092 menu "CPU Power Management"
2093
2094 if ARCH_HAS_CPUFREQ
2095
2096 source "drivers/cpufreq/Kconfig"
2097
2098 config CPU_FREQ_IMX
2099         tristate "CPUfreq driver for i.MX CPUs"
2100         depends on ARCH_MXC && CPU_FREQ
2101         help
2102           This enables the CPUfreq driver for i.MX CPUs.
2103
2104 config CPU_FREQ_SA1100
2105         bool
2106
2107 config CPU_FREQ_SA1110
2108         bool
2109
2110 config CPU_FREQ_INTEGRATOR
2111         tristate "CPUfreq driver for ARM Integrator CPUs"
2112         depends on ARCH_INTEGRATOR && CPU_FREQ
2113         default y
2114         help
2115           This enables the CPUfreq driver for ARM Integrator CPUs.
2116
2117           For details, take a look at <file:Documentation/cpu-freq>.
2118
2119           If in doubt, say Y.
2120
2121 config CPU_FREQ_PXA
2122         bool
2123         depends on CPU_FREQ && ARCH_PXA && PXA25x
2124         default y
2125         select CPU_FREQ_TABLE
2126         select CPU_FREQ_DEFAULT_GOV_USERSPACE
2127
2128 config CPU_FREQ_S3C
2129         bool
2130         help
2131           Internal configuration node for common cpufreq on Samsung SoC
2132
2133 config CPU_FREQ_S3C24XX
2134         bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2135         depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
2136         select CPU_FREQ_S3C
2137         help
2138           This enables the CPUfreq driver for the Samsung S3C24XX family
2139           of CPUs.
2140
2141           For details, take a look at <file:Documentation/cpu-freq>.
2142
2143           If in doubt, say N.
2144
2145 config CPU_FREQ_S3C24XX_PLL
2146         bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2147         depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2148         help
2149           Compile in support for changing the PLL frequency from the
2150           S3C24XX series CPUfreq driver. The PLL takes time to settle
2151           after a frequency change, so by default it is not enabled.
2152
2153           This also means that the PLL tables for the selected CPU(s) will
2154           be built which may increase the size of the kernel image.
2155
2156 config CPU_FREQ_S3C24XX_DEBUG
2157         bool "Debug CPUfreq Samsung driver core"
2158         depends on CPU_FREQ_S3C24XX
2159         help
2160           Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2161
2162 config CPU_FREQ_S3C24XX_IODEBUG
2163         bool "Debug CPUfreq Samsung driver IO timing"
2164         depends on CPU_FREQ_S3C24XX
2165         help
2166           Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2167
2168 config CPU_FREQ_S3C24XX_DEBUGFS
2169         bool "Export debugfs for CPUFreq"
2170         depends on CPU_FREQ_S3C24XX && DEBUG_FS
2171         help
2172           Export status information via debugfs.
2173
2174 endif
2175
2176 source "drivers/cpuidle/Kconfig"
2177
2178 endmenu
2179
2180 menu "Floating point emulation"
2181
2182 comment "At least one emulation must be selected"
2183
2184 config FPE_NWFPE
2185         bool "NWFPE math emulation"
2186         depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2187         ---help---
2188           Say Y to include the NWFPE floating point emulator in the kernel.
2189           This is necessary to run most binaries. Linux does not currently
2190           support floating point hardware so you need to say Y here even if
2191           your machine has an FPA or floating point co-processor podule.
2192
2193           You may say N here if you are going to load the Acorn FPEmulator
2194           early in the bootup.
2195
2196 config FPE_NWFPE_XP
2197         bool "Support extended precision"
2198         depends on FPE_NWFPE
2199         help
2200           Say Y to include 80-bit support in the kernel floating-point
2201           emulator.  Otherwise, only 32 and 64-bit support is compiled in.
2202           Note that gcc does not generate 80-bit operations by default,
2203           so in most cases this option only enlarges the size of the
2204           floating point emulator without any good reason.
2205
2206           You almost surely want to say N here.
2207
2208 config FPE_FASTFPE
2209         bool "FastFPE math emulation (EXPERIMENTAL)"
2210         depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2211         ---help---
2212           Say Y here to include the FAST floating point emulator in the kernel.
2213           This is an experimental much faster emulator which now also has full
2214           precision for the mantissa.  It does not support any exceptions.
2215           It is very simple, and approximately 3-6 times faster than NWFPE.
2216
2217           It should be sufficient for most programs.  It may be not suitable
2218           for scientific calculations, but you have to check this for yourself.
2219           If you do not feel you need a faster FP emulation you should better
2220           choose NWFPE.
2221
2222 config VFP
2223         bool "VFP-format floating point maths"
2224         depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2225         help
2226           Say Y to include VFP support code in the kernel. This is needed
2227           if your hardware includes a VFP unit.
2228
2229           Please see <file:Documentation/arm/VFP/release-notes.txt> for
2230           release notes and additional status information.
2231
2232           Say N if your target does not have VFP hardware.
2233
2234 config VFPv3
2235         bool
2236         depends on VFP
2237         default y if CPU_V7
2238
2239 config NEON
2240         bool "Advanced SIMD (NEON) Extension support"
2241         depends on VFPv3 && CPU_V7
2242         help
2243           Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2244           Extension.
2245
2246 endmenu
2247
2248 menu "Userspace binary formats"
2249
2250 source "fs/Kconfig.binfmt"
2251
2252 config ARTHUR
2253         tristate "RISC OS personality"
2254         depends on !AEABI
2255         help
2256           Say Y here to include the kernel code necessary if you want to run
2257           Acorn RISC OS/Arthur binaries under Linux. This code is still very
2258           experimental; if this sounds frightening, say N and sleep in peace.
2259           You can also say M here to compile this support as a module (which
2260           will be called arthur).
2261
2262 endmenu
2263
2264 menu "Power management options"
2265
2266 source "kernel/power/Kconfig"
2267
2268 config ARCH_SUSPEND_POSSIBLE
2269         depends on !ARCH_S5PC100 && !ARCH_TEGRA
2270         depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2271                 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2272         def_bool y
2273
2274 config ARM_CPU_SUSPEND
2275         def_bool PM_SLEEP
2276
2277 endmenu
2278
2279 source "net/Kconfig"
2280
2281 source "drivers/Kconfig"
2282
2283 source "fs/Kconfig"
2284
2285 source "arch/arm/Kconfig.debug"
2286
2287 source "security/Kconfig"
2288
2289 source "crypto/Kconfig"
2290
2291 source "lib/Kconfig"