arch/arm/Kconfig

   1 config ARM
   2         bool
   3         default y
   4         select HAVE_AOUT
   5         select HAVE_DMA_API_DEBUG
   6         select HAVE_IDE if PCI || ISA || PCMCIA
   7         select HAVE_DMA_ATTRS
   8         select HAVE_MEMBLOCK
   9         select RTC_LIB
  10         select SYS_SUPPORTS_APM_EMULATION
  11         select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
  12         select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
  13         select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
  14         select HAVE_ARCH_KGDB
  15         select HAVE_KPROBES if !XIP_KERNEL
  16         select HAVE_KRETPROBES if (HAVE_KPROBES)
  17         select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
  18         select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
  19         select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
  20         select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
  21         select ARCH_BINFMT_ELF_RANDOMIZE_PIE
  22         select HAVE_GENERIC_DMA_COHERENT
  23         select HAVE_KERNEL_GZIP
  24         select HAVE_KERNEL_LZO
  25         select HAVE_KERNEL_LZMA
  26         select HAVE_KERNEL_XZ
  27         select HAVE_IRQ_WORK
  28         select HAVE_PERF_EVENTS
  29         select PERF_USE_VMALLOC
  30         select HAVE_REGS_AND_STACK_ACCESS_API
  31         select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
  32         select HAVE_C_RECORDMCOUNT
  33         select HAVE_GENERIC_HARDIRQS
  34         select GENERIC_IRQ_SHOW
  35         select CPU_PM if (SUSPEND || CPU_IDLE)
  36         select GENERIC_PCI_IOMAP
  37         select HAVE_BPF_JIT if NET
  38         help
  39           The ARM series is a line of low-power-consumption RISC chip designs
  40           licensed by ARM Ltd and targeted at embedded applications and
  41           handhelds such as the Compaq IPAQ.  ARM-based PCs are no longer
  42           manufactured, but legacy ARM-based PC hardware remains popular in
  43           Europe.  There is an ARM Linux project with a web page at
  44           <http://www.arm.linux.org.uk/>.
  45
  46 config ARM_HAS_SG_CHAIN
  47         bool
  48
  49 config NEED_SG_DMA_LENGTH
  50         bool
  51
  52 config ARM_DMA_USE_IOMMU
  53         select NEED_SG_DMA_LENGTH
  54         select ARM_HAS_SG_CHAIN
  55         bool
  56
  57 config HAVE_PWM
  58         bool
  59
  60 config MIGHT_HAVE_PCI
  61         bool
  62
  63 config SYS_SUPPORTS_APM_EMULATION
  64         bool
  65
  66 config GENERIC_GPIO
  67         bool
  68
  69 config ARCH_USES_GETTIMEOFFSET
  70         bool
  71         default n
  72
  73 config GENERIC_CLOCKEVENTS
  74         bool
  75
  76 config GENERIC_CLOCKEVENTS_BROADCAST
  77         bool
  78         depends on GENERIC_CLOCKEVENTS
  79         default y if SMP
  80
  81 config KTIME_SCALAR
  82         bool
  83         default y
  84
  85 config HAVE_TCM
  86         bool
  87         select GENERIC_ALLOCATOR
  88
  89 config HAVE_PROC_CPU
  90         bool
  91
  92 config NO_IOPORT
  93         bool
  94
  95 config EISA
  96         bool
  97         ---help---
  98           The Extended Industry Standard Architecture (EISA) bus was
  99           developed as an open alternative to the IBM MicroChannel bus.
 100
 101           The EISA bus provided some of the features of the IBM MicroChannel
 102           bus while maintaining backward compatibility with cards made for
 103           the older ISA bus.  The EISA bus saw limited use between 1988 and
 104           1995 when it was made obsolete by the PCI bus.
 105
 106           Say Y here if you are building a kernel for an EISA-based machine.
 107
 108           Otherwise, say N.
 109
 110 config SBUS
 111         bool
 112
 113 config MCA
 114         bool
 115         help
 116           MicroChannel Architecture is found in some IBM PS/2 machines and
 117           laptops.  It is a bus system similar to PCI or ISA. See
 118           <file:Documentation/mca.txt> (and especially the web page given
 119           there) before attempting to build an MCA bus kernel.
 120
 121 config STACKTRACE_SUPPORT
 122         bool
 123         default y
 124
 125 config HAVE_LATENCYTOP_SUPPORT
 126         bool
 127         depends on !SMP
 128         default y
 129
 130 config LOCKDEP_SUPPORT
 131         bool
 132         default y
 133
 134 config TRACE_IRQFLAGS_SUPPORT
 135         bool
 136         default y
 137
 138 config HARDIRQS_SW_RESEND
 139         bool
 140         default y
 141
 142 config GENERIC_IRQ_PROBE
 143         bool
 144         default y
 145
 146 config GENERIC_LOCKBREAK
 147         bool
 148         default y
 149         depends on SMP && PREEMPT
 150
 151 config RWSEM_GENERIC_SPINLOCK
 152         bool
 153         default y
 154
 155 config RWSEM_XCHGADD_ALGORITHM
 156         bool
 157
 158 config ARCH_HAS_ILOG2_U32
 159         bool
 160
 161 config ARCH_HAS_ILOG2_U64
 162         bool
 163
 164 config ARCH_HAS_CPUFREQ
 165         bool
 166         help
 167           Internal node to signify that the ARCH has CPUFREQ support
 168           and that the relevant menu configurations are displayed for
 169           it.
 170
 171 config ARCH_HAS_CPU_IDLE_WAIT
 172        def_bool y
 173
 174 config GENERIC_HWEIGHT
 175         bool
 176         default y
 177
 178 config GENERIC_CALIBRATE_DELAY
 179         bool
 180         default y
 181
 182 config ARCH_MAY_HAVE_PC_FDC
 183         bool
 184
 185 config ZONE_DMA
 186         bool
 187
 188 config NEED_DMA_MAP_STATE
 189        def_bool y
 190
 191 config ARCH_HAS_DMA_SET_COHERENT_MASK
 192         bool
 193
 194 config GENERIC_ISA_DMA
 195         bool
 196
 197 config FIQ
 198         bool
 199
 200 config NEED_RET_TO_USER
 201         bool
 202
 203 config ARCH_MTD_XIP
 204         bool
 205
 206 config VECTORS_BASE
 207         hex
 208         default 0xffff0000 if MMU || CPU_HIGH_VECTOR
 209         default DRAM_BASE if REMAP_VECTORS_TO_RAM
 210         default 0x00000000
 211         help
 212           The base address of exception vectors.
 213
 214 config ARM_PATCH_PHYS_VIRT
 215         bool "Patch physical to virtual translations at runtime" if EMBEDDED
 216         default y
 217         depends on !XIP_KERNEL && MMU
 218         depends on !ARCH_REALVIEW || !SPARSEMEM
 219         help
 220           Patch phys-to-virt and virt-to-phys translation functions at
 221           boot and module load time according to the position of the
 222           kernel in system memory.
 223
 224           This can only be used with non-XIP MMU kernels where the base
 225           of physical memory is at a 16MB boundary.
 226
 227           Only disable this option if you know that you do not require
 228           this feature (eg, building a kernel for a single machine) and
 229           you need to shrink the kernel to the minimal size.
 230
 231 config NEED_MACH_IO_H
 232         bool
 233         help
 234           Select this when mach/io.h is required to provide special
 235           definitions for this platform.  The need for mach/io.h should
 236           be avoided when possible.
 237
 238 config NEED_MACH_MEMORY_H
 239         bool
 240         help
 241           Select this when mach/memory.h is required to provide special
 242           definitions for this platform.  The need for mach/memory.h should
 243           be avoided when possible.
 244
 245 config PHYS_OFFSET
 246         hex "Physical address of main memory" if MMU
 247         depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
 248         default DRAM_BASE if !MMU
 249         help
 250           Please provide the physical address corresponding to the
 251           location of main memory in your system.
 252
 253 config GENERIC_BUG
 254         def_bool y
 255         depends on BUG
 256
 257 source "init/Kconfig"
 258
 259 source "kernel/Kconfig.freezer"
 260
 261 menu "System Type"
 262
 263 config MMU
 264         bool "MMU-based Paged Memory Management Support"
 265         default y
 266         help
 267           Select if you want MMU-based virtualised addressing space
 268           support by paged memory management. If unsure, say 'Y'.
 269
 270 #
 271 # The "ARM system type" choice list is ordered alphabetically by option
 272 # text.  Please add new entries in the option alphabetic order.
 273 #
 274 choice
 275         prompt "ARM system type"
 276         default ARCH_VERSATILE
 277
 278 config ARCH_INTEGRATOR
 279         bool "ARM Ltd. Integrator family"
 280         select ARM_AMBA
 281         select ARCH_HAS_CPUFREQ
 282         select CLKDEV_LOOKUP
 283         select HAVE_MACH_CLKDEV
 284         select HAVE_TCM
 285         select ICST
 286         select GENERIC_CLOCKEVENTS
 287         select PLAT_VERSATILE
 288         select PLAT_VERSATILE_FPGA_IRQ
 289         select NEED_MACH_IO_H
 290         select NEED_MACH_MEMORY_H
 291         select SPARSE_IRQ
 292         help
 293           Support for ARM's Integrator platform.
 294
 295 config ARCH_REALVIEW
 296         bool "ARM Ltd. RealView family"
 297         select ARM_AMBA
 298         select CLKDEV_LOOKUP
 299         select HAVE_MACH_CLKDEV
 300         select ICST
 301         select GENERIC_CLOCKEVENTS
 302         select ARCH_WANT_OPTIONAL_GPIOLIB
 303         select PLAT_VERSATILE
 304         select PLAT_VERSATILE_CLCD
 305         select ARM_TIMER_SP804
 306         select GPIO_PL061 if GPIOLIB
 307         select NEED_MACH_MEMORY_H
 308         help
 309           This enables support for ARM Ltd RealView boards.
 310
 311 config ARCH_VERSATILE
 312         bool "ARM Ltd. Versatile family"
 313         select ARM_AMBA
 314         select ARM_VIC
 315         select CLKDEV_LOOKUP
 316         select HAVE_MACH_CLKDEV
 317         select ICST
 318         select GENERIC_CLOCKEVENTS
 319         select ARCH_WANT_OPTIONAL_GPIOLIB
 320         select PLAT_VERSATILE
 321         select PLAT_VERSATILE_CLCD
 322         select PLAT_VERSATILE_FPGA_IRQ
 323         select ARM_TIMER_SP804
 324         help
 325           This enables support for ARM Ltd Versatile board.
 326
 327 config ARCH_VEXPRESS
 328         bool "ARM Ltd. Versatile Express family"
 329         select ARCH_WANT_OPTIONAL_GPIOLIB
 330         select ARM_AMBA
 331         select ARM_TIMER_SP804
 332         select CLKDEV_LOOKUP
 333         select HAVE_MACH_CLKDEV
 334         select GENERIC_CLOCKEVENTS
 335         select HAVE_CLK
 336         select HAVE_PATA_PLATFORM
 337         select ICST
 338         select NO_IOPORT
 339         select PLAT_VERSATILE
 340         select PLAT_VERSATILE_CLCD
 341         help
 342           This enables support for the ARM Ltd Versatile Express boards.
 343
 344 config ARCH_AT91
 345         bool "Atmel AT91"
 346         select ARCH_REQUIRE_GPIOLIB
 347         select HAVE_CLK
 348         select CLKDEV_LOOKUP
 349         select IRQ_DOMAIN
 350         select NEED_MACH_IO_H if PCCARD
 351         help
 352           This enables support for systems based on the Atmel AT91RM9200,
 353           AT91SAM9 processors.
 354
 355 config ARCH_BCMRING
 356         bool "Broadcom BCMRING"
 357         depends on MMU
 358         select CPU_V6
 359         select ARM_AMBA
 360         select ARM_TIMER_SP804
 361         select CLKDEV_LOOKUP
 362         select GENERIC_CLOCKEVENTS
 363         select ARCH_WANT_OPTIONAL_GPIOLIB
 364         help
 365           Support for Broadcom's BCMRing platform.
 366
 367 config ARCH_HIGHBANK
 368         bool "Calxeda Highbank-based"
 369         select ARCH_WANT_OPTIONAL_GPIOLIB
 370         select ARM_AMBA
 371         select ARM_GIC
 372         select ARM_TIMER_SP804
 373         select CACHE_L2X0
 374         select CLKDEV_LOOKUP
 375         select CPU_V7
 376         select GENERIC_CLOCKEVENTS
 377         select HAVE_ARM_SCU
 378         select HAVE_SMP
 379         select SPARSE_IRQ
 380         select USE_OF
 381         help
 382           Support for the Calxeda Highbank SoC based boards.
 383
 384 config ARCH_CLPS711X
 385         bool "Cirrus Logic CLPS711x/EP721x-based"
 386         select CPU_ARM720T
 387         select ARCH_USES_GETTIMEOFFSET
 388         select NEED_MACH_MEMORY_H
 389         help
 390           Support for Cirrus Logic 711x/721x based boards.
 391
 392 config ARCH_CNS3XXX
 393         bool "Cavium Networks CNS3XXX family"
 394         select CPU_V6K
 395         select GENERIC_CLOCKEVENTS
 396         select ARM_GIC
 397         select MIGHT_HAVE_CACHE_L2X0
 398         select MIGHT_HAVE_PCI
 399         select PCI_DOMAINS if PCI
 400         help
 401           Support for Cavium Networks CNS3XXX platform.
 402
 403 config ARCH_GEMINI
 404         bool "Cortina Systems Gemini"
 405         select CPU_FA526
 406         select ARCH_REQUIRE_GPIOLIB
 407         select ARCH_USES_GETTIMEOFFSET
 408         help
 409           Support for the Cortina Systems Gemini family SoCs
 410
 411 config ARCH_PRIMA2
 412         bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
 413         select CPU_V7
 414         select NO_IOPORT
 415         select GENERIC_CLOCKEVENTS
 416         select CLKDEV_LOOKUP
 417         select GENERIC_IRQ_CHIP
 418         select MIGHT_HAVE_CACHE_L2X0
 419         select USE_OF
 420         select ZONE_DMA
 421         help
 422           Support for CSR SiRFSoC ARM Cortex A9 Platform
 423
 424 config ARCH_EBSA110
 425         bool "EBSA-110"
 426         select CPU_SA110
 427         select ISA
 428         select NO_IOPORT
 429         select ARCH_USES_GETTIMEOFFSET
 430         select NEED_MACH_IO_H
 431         select NEED_MACH_MEMORY_H
 432         help
 433           This is an evaluation board for the StrongARM processor available
 434           from Digital. It has limited hardware on-board, including an
 435           Ethernet interface, two PCMCIA sockets, two serial ports and a
 436           parallel port.
 437
 438 config ARCH_EP93XX
 439         bool "EP93xx-based"
 440         select CPU_ARM920T
 441         select ARM_AMBA
 442         select ARM_VIC
 443         select CLKDEV_LOOKUP
 444         select ARCH_REQUIRE_GPIOLIB
 445         select ARCH_HAS_HOLES_MEMORYMODEL
 446         select ARCH_USES_GETTIMEOFFSET
 447         select NEED_MACH_MEMORY_H
 448         help
 449           This enables support for the Cirrus EP93xx series of CPUs.
 450
 451 config ARCH_FOOTBRIDGE
 452         bool "FootBridge"
 453         select CPU_SA110
 454         select FOOTBRIDGE
 455         select GENERIC_CLOCKEVENTS
 456         select HAVE_IDE
 457         select NEED_MACH_IO_H
 458         select NEED_MACH_MEMORY_H
 459         help
 460           Support for systems based on the DC21285 companion chip
 461           ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
 462
 463 config ARCH_MXC
 464         bool "Freescale MXC/iMX-based"
 465         select GENERIC_CLOCKEVENTS
 466         select ARCH_REQUIRE_GPIOLIB
 467         select CLKDEV_LOOKUP
 468         select CLKSRC_MMIO
 469         select GENERIC_IRQ_CHIP
 470         select MULTI_IRQ_HANDLER
 471         help
 472           Support for Freescale MXC/iMX-based family of processors
 473
 474 config ARCH_MXS
 475         bool "Freescale MXS-based"
 476         select GENERIC_CLOCKEVENTS
 477         select ARCH_REQUIRE_GPIOLIB
 478         select CLKDEV_LOOKUP
 479         select CLKSRC_MMIO
 480         select HAVE_CLK_PREPARE
 481         help
 482           Support for Freescale MXS-based family of processors
 483
 484 config ARCH_NETX
 485         bool "Hilscher NetX based"
 486         select CLKSRC_MMIO
 487         select CPU_ARM926T
 488         select ARM_VIC
 489         select GENERIC_CLOCKEVENTS
 490         help
 491           This enables support for systems based on the Hilscher NetX Soc
 492
 493 config ARCH_H720X
 494         bool "Hynix HMS720x-based"
 495         select CPU_ARM720T
 496         select ISA_DMA_API
 497         select ARCH_USES_GETTIMEOFFSET
 498         help
 499           This enables support for systems based on the Hynix HMS720x
 500
 501 config ARCH_IOP13XX
 502         bool "IOP13xx-based"
 503         depends on MMU
 504         select CPU_XSC3
 505         select PLAT_IOP
 506         select PCI
 507         select ARCH_SUPPORTS_MSI
 508         select VMSPLIT_1G
 509         select NEED_MACH_IO_H
 510         select NEED_MACH_MEMORY_H
 511         select NEED_RET_TO_USER
 512         help
 513           Support for Intel's IOP13XX (XScale) family of processors.
 514
 515 config ARCH_IOP32X
 516         bool "IOP32x-based"
 517         depends on MMU
 518         select CPU_XSCALE
 519         select NEED_MACH_IO_H
 520         select NEED_RET_TO_USER
 521         select PLAT_IOP
 522         select PCI
 523         select ARCH_REQUIRE_GPIOLIB
 524         help
 525           Support for Intel's 80219 and IOP32X (XScale) family of
 526           processors.
 527
 528 config ARCH_IOP33X
 529         bool "IOP33x-based"
 530         depends on MMU
 531         select CPU_XSCALE
 532         select NEED_MACH_IO_H
 533         select NEED_RET_TO_USER
 534         select PLAT_IOP
 535         select PCI
 536         select ARCH_REQUIRE_GPIOLIB
 537         help
 538           Support for Intel's IOP33X (XScale) family of processors.
 539
 540 config ARCH_IXP23XX
 541         bool "IXP23XX-based"
 542         depends on MMU
 543         select CPU_XSC3
 544         select PCI
 545         select ARCH_USES_GETTIMEOFFSET
 546         select NEED_MACH_IO_H
 547         select NEED_MACH_MEMORY_H
 548         help
 549           Support for Intel's IXP23xx (XScale) family of processors.
 550
 551 config ARCH_IXP2000
 552         bool "IXP2400/2800-based"
 553         depends on MMU
 554         select CPU_XSCALE
 555         select PCI
 556         select ARCH_USES_GETTIMEOFFSET
 557         select NEED_MACH_IO_H
 558         select NEED_MACH_MEMORY_H
 559         help
 560           Support for Intel's IXP2400/2800 (XScale) family of processors.
 561
 562 config ARCH_IXP4XX
 563         bool "IXP4xx-based"
 564         depends on MMU
 565         select ARCH_HAS_DMA_SET_COHERENT_MASK
 566         select CLKSRC_MMIO
 567         select CPU_XSCALE
 568         select GENERIC_GPIO
 569         select GENERIC_CLOCKEVENTS
 570         select MIGHT_HAVE_PCI
 571         select NEED_MACH_IO_H
 572         select DMABOUNCE if PCI
 573         help
 574           Support for Intel's IXP4XX (XScale) family of processors.
 575
 576 config ARCH_DOVE
 577         bool "Marvell Dove"
 578         select CPU_V7
 579         select PCI
 580         select ARCH_REQUIRE_GPIOLIB
 581         select GENERIC_CLOCKEVENTS
 582         select NEED_MACH_IO_H
 583         select PLAT_ORION
 584         help
 585           Support for the Marvell Dove SoC 88AP510
 586
 587 config ARCH_KIRKWOOD
 588         bool "Marvell Kirkwood"
 589         select CPU_FEROCEON
 590         select PCI
 591         select ARCH_REQUIRE_GPIOLIB
 592         select GENERIC_CLOCKEVENTS
 593         select NEED_MACH_IO_H
 594         select PLAT_ORION
 595         help
 596           Support for the following Marvell Kirkwood series SoCs:
 597           88F6180, 88F6192 and 88F6281.
 598
 599 config ARCH_LPC32XX
 600         bool "NXP LPC32XX"
 601         select CLKSRC_MMIO
 602         select CPU_ARM926T
 603         select ARCH_REQUIRE_GPIOLIB
 604         select HAVE_IDE
 605         select ARM_AMBA
 606         select USB_ARCH_HAS_OHCI
 607         select CLKDEV_LOOKUP
 608         select GENERIC_CLOCKEVENTS
 609         help
 610           Support for the NXP LPC32XX family of processors
 611
 612 config ARCH_MV78XX0
 613         bool "Marvell MV78xx0"
 614         select CPU_FEROCEON
 615         select PCI
 616         select ARCH_REQUIRE_GPIOLIB
 617         select GENERIC_CLOCKEVENTS
 618         select NEED_MACH_IO_H
 619         select PLAT_ORION
 620         help
 621           Support for the following Marvell MV78xx0 series SoCs:
 622           MV781x0, MV782x0.
 623
 624 config ARCH_ORION5X
 625         bool "Marvell Orion"
 626         depends on MMU
 627         select CPU_FEROCEON
 628         select PCI
 629         select ARCH_REQUIRE_GPIOLIB
 630         select GENERIC_CLOCKEVENTS
 631         select PLAT_ORION
 632         help
 633           Support for the following Marvell Orion 5x series SoCs:
 634           Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
 635           Orion-2 (5281), Orion-1-90 (6183).
 636
 637 config ARCH_MMP
 638         bool "Marvell PXA168/910/MMP2"
 639         depends on MMU
 640         select ARCH_REQUIRE_GPIOLIB
 641         select CLKDEV_LOOKUP
 642         select GENERIC_CLOCKEVENTS
 643         select GPIO_PXA
 644         select TICK_ONESHOT
 645         select PLAT_PXA
 646         select SPARSE_IRQ
 647         select GENERIC_ALLOCATOR
 648         help
 649           Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
 650
 651 config ARCH_KS8695
 652         bool "Micrel/Kendin KS8695"
 653         select CPU_ARM922T
 654         select ARCH_REQUIRE_GPIOLIB
 655         select ARCH_USES_GETTIMEOFFSET
 656         select NEED_MACH_MEMORY_H
 657         help
 658           Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
 659           System-on-Chip devices.
 660
 661 config ARCH_W90X900
 662         bool "Nuvoton W90X900 CPU"
 663         select CPU_ARM926T
 664         select ARCH_REQUIRE_GPIOLIB
 665         select CLKDEV_LOOKUP
 666         select CLKSRC_MMIO
 667         select GENERIC_CLOCKEVENTS
 668         help
 669           Support for Nuvoton (Winbond logic dept.) ARM9 processor,
 670           At present, the w90x900 has been renamed nuc900, regarding
 671           the ARM series product line, you can login the following
 672           link address to know more.
 673
 674           <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
 675                 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
 676
 677 config ARCH_TEGRA
 678         bool "NVIDIA Tegra"
 679         select CLKDEV_LOOKUP
 680         select CLKSRC_MMIO
 681         select GENERIC_CLOCKEVENTS
 682         select GENERIC_GPIO
 683         select HAVE_CLK
 684         select HAVE_SMP
 685         select MIGHT_HAVE_CACHE_L2X0
 686         select NEED_MACH_IO_H if PCI
 687         select ARCH_HAS_CPUFREQ
 688         help
 689           This enables support for NVIDIA Tegra based systems (Tegra APX,
 690           Tegra 6xx and Tegra 2 series).
 691
 692 config ARCH_PICOXCELL
 693         bool "Picochip picoXcell"
 694         select ARCH_REQUIRE_GPIOLIB
 695         select ARM_PATCH_PHYS_VIRT
 696         select ARM_VIC
 697         select CPU_V6K
 698         select DW_APB_TIMER
 699         select GENERIC_CLOCKEVENTS
 700         select GENERIC_GPIO
 701         select HAVE_TCM
 702         select NO_IOPORT
 703         select SPARSE_IRQ
 704         select USE_OF
 705         help
 706           This enables support for systems based on the Picochip picoXcell
 707           family of Femtocell devices.  The picoxcell support requires device tree
 708           for all boards.
 709
 710 config ARCH_PNX4008
 711         bool "Philips Nexperia PNX4008 Mobile"
 712         select CPU_ARM926T
 713         select CLKDEV_LOOKUP
 714         select ARCH_USES_GETTIMEOFFSET
 715         help
 716           This enables support for Philips PNX4008 mobile platform.
 717
 718 config ARCH_PXA
 719         bool "PXA2xx/PXA3xx-based"
 720         depends on MMU
 721         select ARCH_MTD_XIP
 722         select ARCH_HAS_CPUFREQ
 723         select CLKDEV_LOOKUP
 724         select CLKSRC_MMIO
 725         select ARCH_REQUIRE_GPIOLIB
 726         select GENERIC_CLOCKEVENTS
 727         select GPIO_PXA
 728         select TICK_ONESHOT
 729         select PLAT_PXA
 730         select SPARSE_IRQ
 731         select AUTO_ZRELADDR
 732         select MULTI_IRQ_HANDLER
 733         select ARM_CPU_SUSPEND if PM
 734         select HAVE_IDE
 735         help
 736           Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
 737
 738 config ARCH_MSM
 739         bool "Qualcomm MSM"
 740         select HAVE_CLK
 741         select GENERIC_CLOCKEVENTS
 742         select ARCH_REQUIRE_GPIOLIB
 743         select CLKDEV_LOOKUP
 744         help
 745           Support for Qualcomm MSM/QSD based systems.  This runs on the
 746           apps processor of the MSM/QSD and depends on a shared memory
 747           interface to the modem processor which runs the baseband
 748           stack and controls some vital subsystems
 749           (clock and power control, etc).
 750
 751 config ARCH_SHMOBILE
 752         bool "Renesas SH-Mobile / R-Mobile"
 753         select HAVE_CLK
 754         select CLKDEV_LOOKUP
 755         select HAVE_MACH_CLKDEV
 756         select HAVE_SMP
 757         select GENERIC_CLOCKEVENTS
 758         select MIGHT_HAVE_CACHE_L2X0
 759         select NO_IOPORT
 760         select SPARSE_IRQ
 761         select MULTI_IRQ_HANDLER
 762         select PM_GENERIC_DOMAINS if PM
 763         select NEED_MACH_MEMORY_H
 764         help
 765           Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
 766
 767 config ARCH_RPC
 768         bool "RiscPC"
 769         select ARCH_ACORN
 770         select FIQ
 771         select ARCH_MAY_HAVE_PC_FDC
 772         select HAVE_PATA_PLATFORM
 773         select ISA_DMA_API
 774         select NO_IOPORT
 775         select ARCH_SPARSEMEM_ENABLE
 776         select ARCH_USES_GETTIMEOFFSET
 777         select HAVE_IDE
 778         select NEED_MACH_IO_H
 779         select NEED_MACH_MEMORY_H
 780         help
 781           On the Acorn Risc-PC, Linux can support the internal IDE disk and
 782           CD-ROM interface, serial and parallel port, and the floppy drive.
 783
 784 config ARCH_SA1100
 785         bool "SA1100-based"
 786         select CLKSRC_MMIO
 787         select CPU_SA1100
 788         select ISA
 789         select ARCH_SPARSEMEM_ENABLE
 790         select ARCH_MTD_XIP
 791         select ARCH_HAS_CPUFREQ
 792         select CPU_FREQ
 793         select GENERIC_CLOCKEVENTS
 794         select CLKDEV_LOOKUP
 795         select TICK_ONESHOT
 796         select ARCH_REQUIRE_GPIOLIB
 797         select HAVE_IDE
 798         select NEED_MACH_MEMORY_H
 799         select SPARSE_IRQ
 800         help
 801           Support for StrongARM 11x0 based boards.
 802
 803 config ARCH_S3C24XX
 804         bool "Samsung S3C24XX SoCs"
 805         select GENERIC_GPIO
 806         select ARCH_HAS_CPUFREQ
 807         select HAVE_CLK
 808         select CLKDEV_LOOKUP
 809         select ARCH_USES_GETTIMEOFFSET
 810         select HAVE_S3C2410_I2C if I2C
 811         select HAVE_S3C_RTC if RTC_CLASS
 812         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 813         select NEED_MACH_IO_H
 814         help
 815           Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
 816           and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
 817           (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
 818           Samsung SMDK2410 development board (and derivatives).
 819
 820 config ARCH_S3C64XX
 821         bool "Samsung S3C64XX"
 822         select PLAT_SAMSUNG
 823         select CPU_V6
 824         select ARM_VIC
 825         select HAVE_CLK
 826         select HAVE_TCM
 827         select CLKDEV_LOOKUP
 828         select NO_IOPORT
 829         select ARCH_USES_GETTIMEOFFSET
 830         select ARCH_HAS_CPUFREQ
 831         select ARCH_REQUIRE_GPIOLIB
 832         select SAMSUNG_CLKSRC
 833         select SAMSUNG_IRQ_VIC_TIMER
 834         select S3C_GPIO_TRACK
 835         select S3C_DEV_NAND
 836         select USB_ARCH_HAS_OHCI
 837         select SAMSUNG_GPIOLIB_4BIT
 838         select HAVE_S3C2410_I2C if I2C
 839         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 840         help
 841           Samsung S3C64XX series based systems
 842
 843 config ARCH_S5P64X0
 844         bool "Samsung S5P6440 S5P6450"
 845         select CPU_V6
 846         select GENERIC_GPIO
 847         select HAVE_CLK
 848         select CLKDEV_LOOKUP
 849         select CLKSRC_MMIO
 850         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 851         select GENERIC_CLOCKEVENTS
 852         select HAVE_S3C2410_I2C if I2C
 853         select HAVE_S3C_RTC if RTC_CLASS
 854         help
 855           Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
 856           SMDK6450.
 857
 858 config ARCH_S5PC100
 859         bool "Samsung S5PC100"
 860         select GENERIC_GPIO
 861         select HAVE_CLK
 862         select CLKDEV_LOOKUP
 863         select CPU_V7
 864         select ARCH_USES_GETTIMEOFFSET
 865         select HAVE_S3C2410_I2C if I2C
 866         select HAVE_S3C_RTC if RTC_CLASS
 867         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 868         help
 869           Samsung S5PC100 series based systems
 870
 871 config ARCH_S5PV210
 872         bool "Samsung S5PV210/S5PC110"
 873         select CPU_V7
 874         select ARCH_SPARSEMEM_ENABLE
 875         select ARCH_HAS_HOLES_MEMORYMODEL
 876         select GENERIC_GPIO
 877         select HAVE_CLK
 878         select CLKDEV_LOOKUP
 879         select CLKSRC_MMIO
 880         select ARCH_HAS_CPUFREQ
 881         select GENERIC_CLOCKEVENTS
 882         select HAVE_S3C2410_I2C if I2C
 883         select HAVE_S3C_RTC if RTC_CLASS
 884         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 885         select NEED_MACH_MEMORY_H
 886         help
 887           Samsung S5PV210/S5PC110 series based systems
 888
 889 config ARCH_EXYNOS
 890         bool "SAMSUNG EXYNOS"
 891         select CPU_V7
 892         select ARCH_SPARSEMEM_ENABLE
 893         select ARCH_HAS_HOLES_MEMORYMODEL
 894         select GENERIC_GPIO
 895         select HAVE_CLK
 896         select CLKDEV_LOOKUP
 897         select ARCH_HAS_CPUFREQ
 898         select GENERIC_CLOCKEVENTS
 899         select HAVE_S3C_RTC if RTC_CLASS
 900         select HAVE_S3C2410_I2C if I2C
 901         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 902         select NEED_MACH_MEMORY_H
 903         help
 904           Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
 905
 906 config ARCH_SHARK
 907         bool "Shark"
 908         select CPU_SA110
 909         select ISA
 910         select ISA_DMA
 911         select ZONE_DMA
 912         select PCI
 913         select ARCH_USES_GETTIMEOFFSET
 914         select NEED_MACH_MEMORY_H
 915         select NEED_MACH_IO_H
 916         help
 917           Support for the StrongARM based Digital DNARD machine, also known
 918           as "Shark" (<http://www.shark-linux.de/shark.html>).
 919
 920 config ARCH_U300
 921         bool "ST-Ericsson U300 Series"
 922         depends on MMU
 923         select CLKSRC_MMIO
 924         select CPU_ARM926T
 925         select HAVE_TCM
 926         select ARM_AMBA
 927         select ARM_PATCH_PHYS_VIRT
 928         select ARM_VIC
 929         select GENERIC_CLOCKEVENTS
 930         select CLKDEV_LOOKUP
 931         select HAVE_MACH_CLKDEV
 932         select GENERIC_GPIO
 933         select ARCH_REQUIRE_GPIOLIB
 934         help
 935           Support for ST-Ericsson U300 series mobile platforms.
 936
 937 config ARCH_U8500
 938         bool "ST-Ericsson U8500 Series"
 939         depends on MMU
 940         select CPU_V7
 941         select ARM_AMBA
 942         select GENERIC_CLOCKEVENTS
 943         select CLKDEV_LOOKUP
 944         select ARCH_REQUIRE_GPIOLIB
 945         select ARCH_HAS_CPUFREQ
 946         select HAVE_SMP
 947         select MIGHT_HAVE_CACHE_L2X0
 948         help
 949           Support for ST-Ericsson's Ux500 architecture
 950
 951 config ARCH_NOMADIK
 952         bool "STMicroelectronics Nomadik"
 953         select ARM_AMBA
 954         select ARM_VIC
 955         select CPU_ARM926T
 956         select CLKDEV_LOOKUP
 957         select GENERIC_CLOCKEVENTS
 958         select MIGHT_HAVE_CACHE_L2X0
 959         select ARCH_REQUIRE_GPIOLIB
 960         help
 961           Support for the Nomadik platform by ST-Ericsson
 962
 963 config ARCH_DAVINCI
 964         bool "TI DaVinci"
 965         select GENERIC_CLOCKEVENTS
 966         select ARCH_REQUIRE_GPIOLIB
 967         select ZONE_DMA
 968         select HAVE_IDE
 969         select CLKDEV_LOOKUP
 970         select GENERIC_ALLOCATOR
 971         select GENERIC_IRQ_CHIP
 972         select ARCH_HAS_HOLES_MEMORYMODEL
 973         help
 974           Support for TI's DaVinci platform.
 975
 976 config ARCH_OMAP
 977         bool "TI OMAP"
 978         select HAVE_CLK
 979         select ARCH_REQUIRE_GPIOLIB
 980         select ARCH_HAS_CPUFREQ
 981         select CLKSRC_MMIO
 982         select GENERIC_CLOCKEVENTS
 983         select ARCH_HAS_HOLES_MEMORYMODEL
 984         help
 985           Support for TI's OMAP platform (OMAP1/2/3/4).
 986
 987 config PLAT_SPEAR
 988         bool "ST SPEAr"
 989         select ARM_AMBA
 990         select ARCH_REQUIRE_GPIOLIB
 991         select CLKDEV_LOOKUP
 992         select CLKSRC_MMIO
 993         select GENERIC_CLOCKEVENTS
 994         select HAVE_CLK
 995         help
 996           Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
 997
 998 config ARCH_VT8500
 999         bool "VIA/WonderMedia 85xx"
1000         select CPU_ARM926T
1001         select GENERIC_GPIO
1002         select ARCH_HAS_CPUFREQ
1003         select GENERIC_CLOCKEVENTS
1004         select ARCH_REQUIRE_GPIOLIB
1005         select HAVE_PWM
1006         help
1007           Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
1008
1009 config ARCH_ZYNQ
1010         bool "Xilinx Zynq ARM Cortex A9 Platform"
1011         select CPU_V7
1012         select GENERIC_CLOCKEVENTS
1013         select CLKDEV_LOOKUP
1014         select ARM_GIC
1015         select ARM_AMBA
1016         select ICST
1017         select MIGHT_HAVE_CACHE_L2X0
1018         select USE_OF
1019         help
1020           Support for Xilinx Zynq ARM Cortex A9 Platform
1021 endchoice
1022
1023 #
1024 # This is sorted alphabetically by mach-* pathname.  However, plat-*
1025 # Kconfigs may be included either alphabetically (according to the
1026 # plat- suffix) or along side the corresponding mach-* source.
1027 #
1028 source "arch/arm/mach-at91/Kconfig"
1029
1030 source "arch/arm/mach-bcmring/Kconfig"
1031
1032 source "arch/arm/mach-clps711x/Kconfig"
1033
1034 source "arch/arm/mach-cns3xxx/Kconfig"
1035
1036 source "arch/arm/mach-davinci/Kconfig"
1037
1038 source "arch/arm/mach-dove/Kconfig"
1039
1040 source "arch/arm/mach-ep93xx/Kconfig"
1041
1042 source "arch/arm/mach-footbridge/Kconfig"
1043
1044 source "arch/arm/mach-gemini/Kconfig"
1045
1046 source "arch/arm/mach-h720x/Kconfig"
1047
1048 source "arch/arm/mach-integrator/Kconfig"
1049
1050 source "arch/arm/mach-iop32x/Kconfig"
1051
1052 source "arch/arm/mach-iop33x/Kconfig"
1053
1054 source "arch/arm/mach-iop13xx/Kconfig"
1055
1056 source "arch/arm/mach-ixp4xx/Kconfig"
1057
1058 source "arch/arm/mach-ixp2000/Kconfig"
1059
1060 source "arch/arm/mach-ixp23xx/Kconfig"
1061
1062 source "arch/arm/mach-kirkwood/Kconfig"
1063
1064 source "arch/arm/mach-ks8695/Kconfig"
1065
1066 source "arch/arm/mach-lpc32xx/Kconfig"
1067
1068 source "arch/arm/mach-msm/Kconfig"
1069
1070 source "arch/arm/mach-mv78xx0/Kconfig"
1071
1072 source "arch/arm/plat-mxc/Kconfig"
1073
1074 source "arch/arm/mach-mxs/Kconfig"
1075
1076 source "arch/arm/mach-netx/Kconfig"
1077
1078 source "arch/arm/mach-nomadik/Kconfig"
1079 source "arch/arm/plat-nomadik/Kconfig"
1080
1081 source "arch/arm/plat-omap/Kconfig"
1082
1083 source "arch/arm/mach-omap1/Kconfig"
1084
1085 source "arch/arm/mach-omap2/Kconfig"
1086
1087 source "arch/arm/mach-orion5x/Kconfig"
1088
1089 source "arch/arm/mach-pxa/Kconfig"
1090 source "arch/arm/plat-pxa/Kconfig"
1091
1092 source "arch/arm/mach-mmp/Kconfig"
1093
1094 source "arch/arm/mach-realview/Kconfig"
1095
1096 source "arch/arm/mach-sa1100/Kconfig"
1097
1098 source "arch/arm/plat-samsung/Kconfig"
1099 source "arch/arm/plat-s3c24xx/Kconfig"
1100 source "arch/arm/plat-s5p/Kconfig"
1101
1102 source "arch/arm/plat-spear/Kconfig"
1103
1104 source "arch/arm/mach-s3c24xx/Kconfig"
1105 if ARCH_S3C24XX
1106 source "arch/arm/mach-s3c2412/Kconfig"
1107 source "arch/arm/mach-s3c2440/Kconfig"
1108 endif
1109
1110 if ARCH_S3C64XX
1111 source "arch/arm/mach-s3c64xx/Kconfig"
1112 endif
1113
1114 source "arch/arm/mach-s5p64x0/Kconfig"
1115
1116 source "arch/arm/mach-s5pc100/Kconfig"
1117
1118 source "arch/arm/mach-s5pv210/Kconfig"
1119
1120 source "arch/arm/mach-exynos/Kconfig"
1121
1122 source "arch/arm/mach-shmobile/Kconfig"
1123
1124 source "arch/arm/mach-tegra/Kconfig"
1125
1126 source "arch/arm/mach-u300/Kconfig"
1127
1128 source "arch/arm/mach-ux500/Kconfig"
1129
1130 source "arch/arm/mach-versatile/Kconfig"
1131
1132 source "arch/arm/mach-vexpress/Kconfig"
1133 source "arch/arm/plat-versatile/Kconfig"
1134
1135 source "arch/arm/mach-vt8500/Kconfig"
1136
1137 source "arch/arm/mach-w90x900/Kconfig"
1138
1139 # Definitions to make life easier
1140 config ARCH_ACORN
1141         bool
1142
1143 config PLAT_IOP
1144         bool
1145         select GENERIC_CLOCKEVENTS
1146
1147 config PLAT_ORION
1148         bool
1149         select CLKSRC_MMIO
1150         select GENERIC_IRQ_CHIP
1151
1152 config PLAT_PXA
1153         bool
1154
1155 config PLAT_VERSATILE
1156         bool
1157
1158 config ARM_TIMER_SP804
1159         bool
1160         select CLKSRC_MMIO
1161         select HAVE_SCHED_CLOCK
1162
1163 source arch/arm/mm/Kconfig
1164
1165 config ARM_NR_BANKS
1166         int
1167         default 16 if ARCH_EP93XX
1168         default 8
1169
1170 config IWMMXT
1171         bool "Enable iWMMXt support"
1172         depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1173         default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1174         help
1175           Enable support for iWMMXt context switching at run time if
1176           running on a CPU that supports it.
1177
1178 config XSCALE_PMU
1179         bool
1180         depends on CPU_XSCALE
1181         default y
1182
1183 config CPU_HAS_PMU
1184         depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1185                    (!ARCH_OMAP3 || OMAP3_EMU)
1186         default y
1187         bool
1188
1189 config MULTI_IRQ_HANDLER
1190         bool
1191         help
1192           Allow each machine to specify it's own IRQ handler at run time.
1193
1194 if !MMU
1195 source "arch/arm/Kconfig-nommu"
1196 endif
1197
1198 config ARM_ERRATA_326103
1199         bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1200         depends on CPU_V6
1201         help
1202           Executing a SWP instruction to read-only memory does not set bit 11
1203           of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1204           treat the access as a read, preventing a COW from occurring and
1205           causing the faulting task to livelock.
1206
1207 config ARM_ERRATA_411920
1208         bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1209         depends on CPU_V6 || CPU_V6K
1210         help
1211           Invalidation of the Instruction Cache operation can
1212           fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1213           It does not affect the MPCore. This option enables the ARM Ltd.
1214           recommended workaround.
1215
1216 config ARM_ERRATA_430973
1217         bool "ARM errata: Stale prediction on replaced interworking branch"
1218         depends on CPU_V7
1219         help
1220           This option enables the workaround for the 430973 Cortex-A8
1221           (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1222           interworking branch is replaced with another code sequence at the
1223           same virtual address, whether due to self-modifying code or virtual
1224           to physical address re-mapping, Cortex-A8 does not recover from the
1225           stale interworking branch prediction. This results in Cortex-A8
1226           executing the new code sequence in the incorrect ARM or Thumb state.
1227           The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1228           and also flushes the branch target cache at every context switch.
1229           Note that setting specific bits in the ACTLR register may not be
1230           available in non-secure mode.
1231
1232 config ARM_ERRATA_458693
1233         bool "ARM errata: Processor deadlock when a false hazard is created"
1234         depends on CPU_V7
1235         help
1236           This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1237           erratum. For very specific sequences of memory operations, it is
1238           possible for a hazard condition intended for a cache line to instead
1239           be incorrectly associated with a different cache line. This false
1240           hazard might then cause a processor deadlock. The workaround enables
1241           the L1 caching of the NEON accesses and disables the PLD instruction
1242           in the ACTLR register. Note that setting specific bits in the ACTLR
1243           register may not be available in non-secure mode.
1244
1245 config ARM_ERRATA_460075
1246         bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1247         depends on CPU_V7
1248         help
1249           This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1250           erratum. Any asynchronous access to the L2 cache may encounter a
1251           situation in which recent store transactions to the L2 cache are lost
1252           and overwritten with stale memory contents from external memory. The
1253           workaround disables the write-allocate mode for the L2 cache via the
1254           ACTLR register. Note that setting specific bits in the ACTLR register
1255           may not be available in non-secure mode.
1256
1257 config ARM_ERRATA_742230
1258         bool "ARM errata: DMB operation may be faulty"
1259         depends on CPU_V7 && SMP
1260         help
1261           This option enables the workaround for the 742230 Cortex-A9
1262           (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1263           between two write operations may not ensure the correct visibility
1264           ordering of the two writes. This workaround sets a specific bit in
1265           the diagnostic register of the Cortex-A9 which causes the DMB
1266           instruction to behave as a DSB, ensuring the correct behaviour of
1267           the two writes.
1268
1269 config ARM_ERRATA_742231
1270         bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1271         depends on CPU_V7 && SMP
1272         help
1273           This option enables the workaround for the 742231 Cortex-A9
1274           (r2p0..r2p2) erratum. Under certain conditions, specific to the
1275           Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1276           accessing some data located in the same cache line, may get corrupted
1277           data due to bad handling of the address hazard when the line gets
1278           replaced from one of the CPUs at the same time as another CPU is
1279           accessing it. This workaround sets specific bits in the diagnostic
1280           register of the Cortex-A9 which reduces the linefill issuing
1281           capabilities of the processor.
1282
1283 config PL310_ERRATA_588369
1284         bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1285         depends on CACHE_L2X0
1286         help
1287            The PL310 L2 cache controller implements three types of Clean &
1288            Invalidate maintenance operations: by Physical Address
1289            (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1290            They are architecturally defined to behave as the execution of a
1291            clean operation followed immediately by an invalidate operation,
1292            both performing to the same memory location. This functionality
1293            is not correctly implemented in PL310 as clean lines are not
1294            invalidated as a result of these operations.
1295
1296 config ARM_ERRATA_720789
1297         bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1298         depends on CPU_V7
1299         help
1300           This option enables the workaround for the 720789 Cortex-A9 (prior to
1301           r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1302           broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1303           As a consequence of this erratum, some TLB entries which should be
1304           invalidated are not, resulting in an incoherency in the system page
1305           tables. The workaround changes the TLB flushing routines to invalidate
1306           entries regardless of the ASID.
1307
1308 config PL310_ERRATA_727915
1309         bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1310         depends on CACHE_L2X0
1311         help
1312           PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1313           operation (offset 0x7FC). This operation runs in background so that
1314           PL310 can handle normal accesses while it is in progress. Under very
1315           rare circumstances, due to this erratum, write data can be lost when
1316           PL310 treats a cacheable write transaction during a Clean &
1317           Invalidate by Way operation.
1318
1319 config ARM_ERRATA_743622
1320         bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1321         depends on CPU_V7
1322         help
1323           This option enables the workaround for the 743622 Cortex-A9
1324           (r2p*) erratum. Under very rare conditions, a faulty
1325           optimisation in the Cortex-A9 Store Buffer may lead to data
1326           corruption. This workaround sets a specific bit in the diagnostic
1327           register of the Cortex-A9 which disables the Store Buffer
1328           optimisation, preventing the defect from occurring. This has no
1329           visible impact on the overall performance or power consumption of the
1330           processor.
1331
1332 config ARM_ERRATA_751472
1333         bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1334         depends on CPU_V7
1335         help
1336           This option enables the workaround for the 751472 Cortex-A9 (prior
1337           to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1338           completion of a following broadcasted operation if the second
1339           operation is received by a CPU before the ICIALLUIS has completed,
1340           potentially leading to corrupted entries in the cache or TLB.
1341
1342 config PL310_ERRATA_753970
1343         bool "PL310 errata: cache sync operation may be faulty"
1344         depends on CACHE_PL310
1345         help
1346           This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1347
1348           Under some condition the effect of cache sync operation on
1349           the store buffer still remains when the operation completes.
1350           This means that the store buffer is always asked to drain and
1351           this prevents it from merging any further writes. The workaround
1352           is to replace the normal offset of cache sync operation (0x730)
1353           by another offset targeting an unmapped PL310 register 0x740.
1354           This has the same effect as the cache sync operation: store buffer
1355           drain and waiting for all buffers empty.
1356
1357 config ARM_ERRATA_754322
1358         bool "ARM errata: possible faulty MMU translations following an ASID switch"
1359         depends on CPU_V7
1360         help
1361           This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1362           r3p*) erratum. A speculative memory access may cause a page table walk
1363           which starts prior to an ASID switch but completes afterwards. This
1364           can populate the micro-TLB with a stale entry which may be hit with
1365           the new ASID. This workaround places two dsb instructions in the mm
1366           switching code so that no page table walks can cross the ASID switch.
1367
1368 config ARM_ERRATA_754327
1369         bool "ARM errata: no automatic Store Buffer drain"
1370         depends on CPU_V7 && SMP
1371         help
1372           This option enables the workaround for the 754327 Cortex-A9 (prior to
1373           r2p0) erratum. The Store Buffer does not have any automatic draining
1374           mechanism and therefore a livelock may occur if an external agent
1375           continuously polls a memory location waiting to observe an update.
1376           This workaround defines cpu_relax() as smp_mb(), preventing correctly
1377           written polling loops from denying visibility of updates to memory.
1378
1379 config ARM_ERRATA_364296
1380         bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1381         depends on CPU_V6 && !SMP
1382         help
1383           This options enables the workaround for the 364296 ARM1136
1384           r0p2 erratum (possible cache data corruption with
1385           hit-under-miss enabled). It sets the undocumented bit 31 in
1386           the auxiliary control register and the FI bit in the control
1387           register, thus disabling hit-under-miss without putting the
1388           processor into full low interrupt latency mode. ARM11MPCore
1389           is not affected.
1390
1391 config ARM_ERRATA_764369
1392         bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1393         depends on CPU_V7 && SMP
1394         help
1395           This option enables the workaround for erratum 764369
1396           affecting Cortex-A9 MPCore with two or more processors (all
1397           current revisions). Under certain timing circumstances, a data
1398           cache line maintenance operation by MVA targeting an Inner
1399           Shareable memory region may fail to proceed up to either the
1400           Point of Coherency or to the Point of Unification of the
1401           system. This workaround adds a DSB instruction before the
1402           relevant cache maintenance functions and sets a specific bit
1403           in the diagnostic control register of the SCU.
1404
1405 config PL310_ERRATA_769419
1406         bool "PL310 errata: no automatic Store Buffer drain"
1407         depends on CACHE_L2X0
1408         help
1409           On revisions of the PL310 prior to r3p2, the Store Buffer does
1410           not automatically drain. This can cause normal, non-cacheable
1411           writes to be retained when the memory system is idle, leading
1412           to suboptimal I/O performance for drivers using coherent DMA.
1413           This option adds a write barrier to the cpu_idle loop so that,
1414           on systems with an outer cache, the store buffer is drained
1415           explicitly.
1416
1417 endmenu
1418
1419 source "arch/arm/common/Kconfig"
1420
1421 menu "Bus support"
1422
1423 config ARM_AMBA
1424         bool
1425
1426 config ISA
1427         bool
1428         help
1429           Find out whether you have ISA slots on your motherboard.  ISA is the
1430           name of a bus system, i.e. the way the CPU talks to the other stuff
1431           inside your box.  Other bus systems are PCI, EISA, MicroChannel
1432           (MCA) or VESA.  ISA is an older system, now being displaced by PCI;
1433           newer boards don't support it.  If you have ISA, say Y, otherwise N.
1434
1435 # Select ISA DMA controller support
1436 config ISA_DMA
1437         bool
1438         select ISA_DMA_API
1439
1440 # Select ISA DMA interface
1441 config ISA_DMA_API
1442         bool
1443
1444 config PCI
1445         bool "PCI support" if MIGHT_HAVE_PCI
1446         help
1447           Find out whether you have a PCI motherboard. PCI is the name of a
1448           bus system, i.e. the way the CPU talks to the other stuff inside
1449           your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1450           VESA. If you have PCI, say Y, otherwise N.
1451
1452 config PCI_DOMAINS
1453         bool
1454         depends on PCI
1455
1456 config PCI_NANOENGINE
1457         bool "BSE nanoEngine PCI support"
1458         depends on SA1100_NANOENGINE
1459         help
1460           Enable PCI on the BSE nanoEngine board.
1461
1462 config PCI_SYSCALL
1463         def_bool PCI
1464
1465 # Select the host bridge type
1466 config PCI_HOST_VIA82C505
1467         bool
1468         depends on PCI && ARCH_SHARK
1469         default y
1470
1471 config PCI_HOST_ITE8152
1472         bool
1473         depends on PCI && MACH_ARMCORE
1474         default y
1475         select DMABOUNCE
1476
1477 source "drivers/pci/Kconfig"
1478
1479 source "drivers/pcmcia/Kconfig"
1480
1481 endmenu
1482
1483 menu "Kernel Features"
1484
1485 source "kernel/time/Kconfig"
1486
1487 config HAVE_SMP
1488         bool
1489         help
1490           This option should be selected by machines which have an SMP-
1491           capable CPU.
1492
1493           The only effect of this option is to make the SMP-related
1494           options available to the user for configuration.
1495
1496 config SMP
1497         bool "Symmetric Multi-Processing"
1498         depends on CPU_V6K || CPU_V7
1499         depends on GENERIC_CLOCKEVENTS
1500         depends on HAVE_SMP
1501         depends on MMU
1502         select USE_GENERIC_SMP_HELPERS
1503         select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1504         help
1505           This enables support for systems with more than one CPU. If you have
1506           a system with only one CPU, like most personal computers, say N. If
1507           you have a system with more than one CPU, say Y.
1508
1509           If you say N here, the kernel will run on single and multiprocessor
1510           machines, but will use only one CPU of a multiprocessor machine. If
1511           you say Y here, the kernel will run on many, but not all, single
1512           processor machines. On a single processor machine, the kernel will
1513           run faster if you say N here.
1514
1515           See also <file:Documentation/x86/i386/IO-APIC.txt>,
1516           <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1517           <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1518
1519           If you don't know what to do here, say N.
1520
1521 config SMP_ON_UP
1522         bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1523         depends on EXPERIMENTAL
1524         depends on SMP && !XIP_KERNEL
1525         default y
1526         help
1527           SMP kernels contain instructions which fail on non-SMP processors.
1528           Enabling this option allows the kernel to modify itself to make
1529           these instructions safe.  Disabling it allows about 1K of space
1530           savings.
1531
1532           If you don't know what to do here, say Y.
1533
1534 config ARM_CPU_TOPOLOGY
1535         bool "Support cpu topology definition"
1536         depends on SMP && CPU_V7
1537         default y
1538         help
1539           Support ARM cpu topology definition. The MPIDR register defines
1540           affinity between processors which is then used to describe the cpu
1541           topology of an ARM System.
1542
1543 config SCHED_MC
1544         bool "Multi-core scheduler support"
1545         depends on ARM_CPU_TOPOLOGY
1546         help
1547           Multi-core scheduler support improves the CPU scheduler's decision
1548           making when dealing with multi-core CPU chips at a cost of slightly
1549           increased overhead in some places. If unsure say N here.
1550
1551 config SCHED_SMT
1552         bool "SMT scheduler support"
1553         depends on ARM_CPU_TOPOLOGY
1554         help
1555           Improves the CPU scheduler's decision making when dealing with
1556           MultiThreading at a cost of slightly increased overhead in some
1557           places. If unsure say N here.
1558
1559 config HAVE_ARM_SCU
1560         bool
1561         help
1562           This option enables support for the ARM system coherency unit
1563
1564 config HAVE_ARM_TWD
1565         bool
1566         depends on SMP
1567         select TICK_ONESHOT
1568         help
1569           This options enables support for the ARM timer and watchdog unit
1570
1571 choice
1572         prompt "Memory split"
1573         default VMSPLIT_3G
1574         help
1575           Select the desired split between kernel and user memory.
1576
1577           If you are not absolutely sure what you are doing, leave this
1578           option alone!
1579
1580         config VMSPLIT_3G
1581                 bool "3G/1G user/kernel split"
1582         config VMSPLIT_2G
1583                 bool "2G/2G user/kernel split"
1584         config VMSPLIT_1G
1585                 bool "1G/3G user/kernel split"
1586 endchoice
1587
1588 config PAGE_OFFSET
1589         hex
1590         default 0x40000000 if VMSPLIT_1G
1591         default 0x80000000 if VMSPLIT_2G
1592         default 0xC0000000
1593
1594 config NR_CPUS
1595         int "Maximum number of CPUs (2-32)"
1596         range 2 32
1597         depends on SMP
1598         default "4"
1599
1600 config HOTPLUG_CPU
1601         bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1602         depends on SMP && HOTPLUG && EXPERIMENTAL
1603         help
1604           Say Y here to experiment with turning CPUs off and on.  CPUs
1605           can be controlled through /sys/devices/system/cpu.
1606
1607 config LOCAL_TIMERS
1608         bool "Use local timer interrupts"
1609         depends on SMP
1610         default y
1611         select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1612         help
1613           Enable support for local timers on SMP platforms, rather then the
1614           legacy IPI broadcast method.  Local timers allows the system
1615           accounting to be spread across the timer interval, preventing a
1616           "thundering herd" at every timer tick.
1617
1618 config ARCH_NR_GPIO
1619         int
1620         default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1621         default 355 if ARCH_U8500
1622         default 264 if MACH_H4700
1623         default 0
1624         help
1625           Maximum number of GPIOs in the system.
1626
1627           If unsure, leave the default value.
1628
1629 source kernel/Kconfig.preempt
1630
1631 config HZ
1632         int
1633         default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1634                 ARCH_S5PV210 || ARCH_EXYNOS4
1635         default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1636         default AT91_TIMER_HZ if ARCH_AT91
1637         default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1638         default 100
1639
1640 config THUMB2_KERNEL
1641         bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1642         depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1643         select AEABI
1644         select ARM_ASM_UNIFIED
1645         select ARM_UNWIND
1646         help
1647           By enabling this option, the kernel will be compiled in
1648           Thumb-2 mode. A compiler/assembler that understand the unified
1649           ARM-Thumb syntax is needed.
1650
1651           If unsure, say N.
1652
1653 config THUMB2_AVOID_R_ARM_THM_JUMP11
1654         bool "Work around buggy Thumb-2 short branch relocations in gas"
1655         depends on THUMB2_KERNEL && MODULES
1656         default y
1657         help
1658           Various binutils versions can resolve Thumb-2 branches to
1659           locally-defined, preemptible global symbols as short-range "b.n"
1660           branch instructions.
1661
1662           This is a problem, because there's no guarantee the final
1663           destination of the symbol, or any candidate locations for a
1664           trampoline, are within range of the branch.  For this reason, the
1665           kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1666           relocation in modules at all, and it makes little sense to add
1667           support.
1668
1669           The symptom is that the kernel fails with an "unsupported
1670           relocation" error when loading some modules.
1671
1672           Until fixed tools are available, passing
1673           -fno-optimize-sibling-calls to gcc should prevent gcc generating
1674           code which hits this problem, at the cost of a bit of extra runtime
1675           stack usage in some cases.
1676
1677           The problem is described in more detail at:
1678               https://bugs.launchpad.net/binutils-linaro/+bug/725126
1679
1680           Only Thumb-2 kernels are affected.
1681
1682           Unless you are sure your tools don't have this problem, say Y.
1683
1684 config ARM_ASM_UNIFIED
1685         bool
1686
1687 config AEABI
1688         bool "Use the ARM EABI to compile the kernel"
1689         help
1690           This option allows for the kernel to be compiled using the latest
1691           ARM ABI (aka EABI).  This is only useful if you are using a user
1692           space environment that is also compiled with EABI.
1693
1694           Since there are major incompatibilities between the legacy ABI and
1695           EABI, especially with regard to structure member alignment, this
1696           option also changes the kernel syscall calling convention to
1697           disambiguate both ABIs and allow for backward compatibility support
1698           (selected with CONFIG_OABI_COMPAT).
1699
1700           To use this you need GCC version 4.0.0 or later.
1701
1702 config OABI_COMPAT
1703         bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1704         depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1705         default y
1706         help
1707           This option preserves the old syscall interface along with the
1708           new (ARM EABI) one. It also provides a compatibility layer to
1709           intercept syscalls that have structure arguments which layout
1710           in memory differs between the legacy ABI and the new ARM EABI
1711           (only for non "thumb" binaries). This option adds a tiny
1712           overhead to all syscalls and produces a slightly larger kernel.
1713           If you know you'll be using only pure EABI user space then you
1714           can say N here. If this option is not selected and you attempt
1715           to execute a legacy ABI binary then the result will be
1716           UNPREDICTABLE (in fact it can be predicted that it won't work
1717           at all). If in doubt say Y.
1718
1719 config ARCH_HAS_HOLES_MEMORYMODEL
1720         bool
1721
1722 config ARCH_SPARSEMEM_ENABLE
1723         bool
1724
1725 config ARCH_SPARSEMEM_DEFAULT
1726         def_bool ARCH_SPARSEMEM_ENABLE
1727
1728 config ARCH_SELECT_MEMORY_MODEL
1729         def_bool ARCH_SPARSEMEM_ENABLE
1730
1731 config HAVE_ARCH_PFN_VALID
1732         def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1733
1734 config HIGHMEM
1735         bool "High Memory Support"
1736         depends on MMU
1737         help
1738           The address space of ARM processors is only 4 Gigabytes large
1739           and it has to accommodate user address space, kernel address
1740           space as well as some memory mapped IO. That means that, if you
1741           have a large amount of physical memory and/or IO, not all of the
1742           memory can be "permanently mapped" by the kernel. The physical
1743           memory that is not permanently mapped is called "high memory".
1744
1745           Depending on the selected kernel/user memory split, minimum
1746           vmalloc space and actual amount of RAM, you may not need this
1747           option which should result in a slightly faster kernel.
1748
1749           If unsure, say n.
1750
1751 config HIGHPTE
1752         bool "Allocate 2nd-level pagetables from highmem"
1753         depends on HIGHMEM
1754
1755 config HW_PERF_EVENTS
1756         bool "Enable hardware performance counter support for perf events"
1757         depends on PERF_EVENTS && CPU_HAS_PMU
1758         default y
1759         help
1760           Enable hardware performance counter support for perf events. If
1761           disabled, perf events will use software events only.
1762
1763 source "mm/Kconfig"
1764
1765 config FORCE_MAX_ZONEORDER
1766         int "Maximum zone order" if ARCH_SHMOBILE
1767         range 11 64 if ARCH_SHMOBILE
1768         default "9" if SA1111
1769         default "11"
1770         help
1771           The kernel memory allocator divides physically contiguous memory
1772           blocks into "zones", where each zone is a power of two number of
1773           pages.  This option selects the largest power of two that the kernel
1774           keeps in the memory allocator.  If you need to allocate very large
1775           blocks of physically contiguous memory, then you may need to
1776           increase this value.
1777
1778           This config option is actually maximum order plus one. For example,
1779           a value of 11 means that the largest free memory block is 2^10 pages.
1780
1781 config LEDS
1782         bool "Timer and CPU usage LEDs"
1783         depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1784                    ARCH_EBSA285 || ARCH_INTEGRATOR || \
1785                    ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1786                    ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1787                    ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1788                    ARCH_AT91 || ARCH_DAVINCI || \
1789                    ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1790         help
1791           If you say Y here, the LEDs on your machine will be used
1792           to provide useful information about your current system status.
1793
1794           If you are compiling a kernel for a NetWinder or EBSA-285, you will
1795           be able to select which LEDs are active using the options below. If
1796           you are compiling a kernel for the EBSA-110 or the LART however, the
1797           red LED will simply flash regularly to indicate that the system is
1798           still functional. It is safe to say Y here if you have a CATS
1799           system, but the driver will do nothing.
1800
1801 config LEDS_TIMER
1802         bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1803                             OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1804                             || MACH_OMAP_PERSEUS2
1805         depends on LEDS
1806         depends on !GENERIC_CLOCKEVENTS
1807         default y if ARCH_EBSA110
1808         help
1809           If you say Y here, one of the system LEDs (the green one on the
1810           NetWinder, the amber one on the EBSA285, or the red one on the LART)
1811           will flash regularly to indicate that the system is still
1812           operational. This is mainly useful to kernel hackers who are
1813           debugging unstable kernels.
1814
1815           The LART uses the same LED for both Timer LED and CPU usage LED
1816           functions. You may choose to use both, but the Timer LED function
1817           will overrule the CPU usage LED.
1818
1819 config LEDS_CPU
1820         bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1821                         !ARCH_OMAP) \
1822                         || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1823                         || MACH_OMAP_PERSEUS2
1824         depends on LEDS
1825         help
1826           If you say Y here, the red LED will be used to give a good real
1827           time indication of CPU usage, by lighting whenever the idle task
1828           is not currently executing.
1829
1830           The LART uses the same LED for both Timer LED and CPU usage LED
1831           functions. You may choose to use both, but the Timer LED function
1832           will overrule the CPU usage LED.
1833
1834 config ALIGNMENT_TRAP
1835         bool
1836         depends on CPU_CP15_MMU
1837         default y if !ARCH_EBSA110
1838         select HAVE_PROC_CPU if PROC_FS
1839         help
1840           ARM processors cannot fetch/store information which is not
1841           naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1842           address divisible by 4. On 32-bit ARM processors, these non-aligned
1843           fetch/store instructions will be emulated in software if you say
1844           here, which has a severe performance impact. This is necessary for
1845           correct operation of some network protocols. With an IP-only
1846           configuration it is safe to say N, otherwise say Y.
1847
1848 config UACCESS_WITH_MEMCPY
1849         bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1850         depends on MMU && EXPERIMENTAL
1851         default y if CPU_FEROCEON
1852         help
1853           Implement faster copy_to_user and clear_user methods for CPU
1854           cores where a 8-word STM instruction give significantly higher
1855           memory write throughput than a sequence of individual 32bit stores.
1856
1857           A possible side effect is a slight increase in scheduling latency
1858           between threads sharing the same address space if they invoke
1859           such copy operations with large buffers.
1860
1861           However, if the CPU data cache is using a write-allocate mode,
1862           this option is unlikely to provide any performance gain.
1863
1864 config SECCOMP
1865         bool
1866         prompt "Enable seccomp to safely compute untrusted bytecode"
1867         ---help---
1868           This kernel feature is useful for number crunching applications
1869           that may need to compute untrusted bytecode during their
1870           execution. By using pipes or other transports made available to
1871           the process as file descriptors supporting the read/write
1872           syscalls, it's possible to isolate those applications in
1873           their own address space using seccomp. Once seccomp is
1874           enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1875           and the task is only allowed to execute a few safe syscalls
1876           defined by each seccomp mode.
1877
1878 config CC_STACKPROTECTOR
1879         bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1880         depends on EXPERIMENTAL
1881         help
1882           This option turns on the -fstack-protector GCC feature. This
1883           feature puts, at the beginning of functions, a canary value on
1884           the stack just before the return address, and validates
1885           the value just before actually returning.  Stack based buffer
1886           overflows (that need to overwrite this return address) now also
1887           overwrite the canary, which gets detected and the attack is then
1888           neutralized via a kernel panic.
1889           This feature requires gcc version 4.2 or above.
1890
1891 config DEPRECATED_PARAM_STRUCT
1892         bool "Provide old way to pass kernel parameters"
1893         help
1894           This was deprecated in 2001 and announced to live on for 5 years.
1895           Some old boot loaders still use this way.
1896
1897 endmenu
1898
1899 menu "Boot options"
1900
1901 config USE_OF
1902         bool "Flattened Device Tree support"
1903         select OF
1904         select OF_EARLY_FLATTREE
1905         select IRQ_DOMAIN
1906         help
1907           Include support for flattened device tree machine descriptions.
1908
1909 # Compressed boot loader in ROM.  Yes, we really want to ask about
1910 # TEXT and BSS so we preserve their values in the config files.
1911 config ZBOOT_ROM_TEXT
1912         hex "Compressed ROM boot loader base address"
1913         default "0"
1914         help
1915           The physical address at which the ROM-able zImage is to be
1916           placed in the target.  Platforms which normally make use of
1917           ROM-able zImage formats normally set this to a suitable
1918           value in their defconfig file.
1919
1920           If ZBOOT_ROM is not enabled, this has no effect.
1921
1922 config ZBOOT_ROM_BSS
1923         hex "Compressed ROM boot loader BSS address"
1924         default "0"
1925         help
1926           The base address of an area of read/write memory in the target
1927           for the ROM-able zImage which must be available while the
1928           decompressor is running. It must be large enough to hold the
1929           entire decompressed kernel plus an additional 128 KiB.
1930           Platforms which normally make use of ROM-able zImage formats
1931           normally set this to a suitable value in their defconfig file.
1932
1933           If ZBOOT_ROM is not enabled, this has no effect.
1934
1935 config ZBOOT_ROM
1936         bool "Compressed boot loader in ROM/flash"
1937         depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1938         help
1939           Say Y here if you intend to execute your compressed kernel image
1940           (zImage) directly from ROM or flash.  If unsure, say N.
1941
1942 choice
1943         prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1944         depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1945         default ZBOOT_ROM_NONE
1946         help
1947           Include experimental SD/MMC loading code in the ROM-able zImage.
1948           With this enabled it is possible to write the the ROM-able zImage
1949           kernel image to an MMC or SD card and boot the kernel straight
1950           from the reset vector. At reset the processor Mask ROM will load
1951           the first part of the the ROM-able zImage which in turn loads the
1952           rest the kernel image to RAM.
1953
1954 config ZBOOT_ROM_NONE
1955         bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1956         help
1957           Do not load image from SD or MMC
1958
1959 config ZBOOT_ROM_MMCIF
1960         bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1961         help
1962           Load image from MMCIF hardware block.
1963
1964 config ZBOOT_ROM_SH_MOBILE_SDHI
1965         bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1966         help
1967           Load image from SDHI hardware block
1968
1969 endchoice
1970
1971 config ARM_APPENDED_DTB
1972         bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1973         depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1974         help
1975           With this option, the boot code will look for a device tree binary
1976           (DTB) appended to zImage
1977           (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1978
1979           This is meant as a backward compatibility convenience for those
1980           systems with a bootloader that can't be upgraded to accommodate
1981           the documented boot protocol using a device tree.
1982
1983           Beware that there is very little in terms of protection against
1984           this option being confused by leftover garbage in memory that might
1985           look like a DTB header after a reboot if no actual DTB is appended
1986           to zImage.  Do not leave this option active in a production kernel
1987           if you don't intend to always append a DTB.  Proper passing of the
1988           location into r2 of a bootloader provided DTB is always preferable
1989           to this option.
1990
1991 config ARM_ATAG_DTB_COMPAT
1992         bool "Supplement the appended DTB with traditional ATAG information"
1993         depends on ARM_APPENDED_DTB
1994         help
1995           Some old bootloaders can't be updated to a DTB capable one, yet
1996           they provide ATAGs with memory configuration, the ramdisk address,
1997           the kernel cmdline string, etc.  Such information is dynamically
1998           provided by the bootloader and can't always be stored in a static
1999           DTB.  To allow a device tree enabled kernel to be used with such
2000           bootloaders, this option allows zImage to extract the information
2001           from the ATAG list and store it at run time into the appended DTB.
2002
2003 config CMDLINE
2004         string "Default kernel command string"
2005         default ""
2006         help
2007           On some architectures (EBSA110 and CATS), there is currently no way
2008           for the boot loader to pass arguments to the kernel. For these
2009           architectures, you should supply some command-line options at build
2010           time by entering them here. As a minimum, you should specify the
2011           memory size and the root device (e.g., mem=64M root=/dev/nfs).
2012
2013 choice
2014         prompt "Kernel command line type" if CMDLINE != ""
2015         default CMDLINE_FROM_BOOTLOADER
2016
2017 config CMDLINE_FROM_BOOTLOADER
2018         bool "Use bootloader kernel arguments if available"
2019         help
2020           Uses the command-line options passed by the boot loader. If
2021           the boot loader doesn't provide any, the default kernel command
2022           string provided in CMDLINE will be used.
2023
2024 config CMDLINE_EXTEND
2025         bool "Extend bootloader kernel arguments"
2026         help
2027           The command-line arguments provided by the boot loader will be
2028           appended to the default kernel command string.
2029
2030 config CMDLINE_FORCE
2031         bool "Always use the default kernel command string"
2032         help
2033           Always use the default kernel command string, even if the boot
2034           loader passes other arguments to the kernel.
2035           This is useful if you cannot or don't want to change the
2036           command-line options your boot loader passes to the kernel.
2037 endchoice
2038
2039 config XIP_KERNEL
2040         bool "Kernel Execute-In-Place from ROM"
2041         depends on !ZBOOT_ROM && !ARM_LPAE
2042         help
2043           Execute-In-Place allows the kernel to run from non-volatile storage
2044           directly addressable by the CPU, such as NOR flash. This saves RAM
2045           space since the text section of the kernel is not loaded from flash
2046           to RAM.  Read-write sections, such as the data section and stack,
2047           are still copied to RAM.  The XIP kernel is not compressed since
2048           it has to run directly from flash, so it will take more space to
2049           store it.  The flash address used to link the kernel object files,
2050           and for storing it, is configuration dependent. Therefore, if you
2051           say Y here, you must know the proper physical address where to
2052           store the kernel image depending on your own flash memory usage.
2053
2054           Also note that the make target becomes "make xipImage" rather than
2055           "make zImage" or "make Image".  The final kernel binary to put in
2056           ROM memory will be arch/arm/boot/xipImage.
2057
2058           If unsure, say N.
2059
2060 config XIP_PHYS_ADDR
2061         hex "XIP Kernel Physical Location"
2062         depends on XIP_KERNEL
2063         default "0x00080000"
2064         help
2065           This is the physical address in your flash memory the kernel will
2066           be linked for and stored to.  This address is dependent on your
2067           own flash usage.
2068
2069 config KEXEC
2070         bool "Kexec system call (EXPERIMENTAL)"
2071         depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2072         help
2073           kexec is a system call that implements the ability to shutdown your
2074           current kernel, and to start another kernel.  It is like a reboot
2075           but it is independent of the system firmware.   And like a reboot
2076           you can start any kernel with it, not just Linux.
2077
2078           It is an ongoing process to be certain the hardware in a machine
2079           is properly shutdown, so do not be surprised if this code does not
2080           initially work for you.  It may help to enable device hotplugging
2081           support.
2082
2083 config ATAGS_PROC
2084         bool "Export atags in procfs"
2085         depends on KEXEC
2086         default y
2087         help
2088           Should the atags used to boot the kernel be exported in an "atags"
2089           file in procfs. Useful with kexec.
2090
2091 config CRASH_DUMP
2092         bool "Build kdump crash kernel (EXPERIMENTAL)"
2093         depends on EXPERIMENTAL
2094         help
2095           Generate crash dump after being started by kexec. This should
2096           be normally only set in special crash dump kernels which are
2097           loaded in the main kernel with kexec-tools into a specially
2098           reserved region and then later executed after a crash by
2099           kdump/kexec. The crash dump kernel must be compiled to a
2100           memory address not used by the main kernel
2101
2102           For more details see Documentation/kdump/kdump.txt
2103
2104 config AUTO_ZRELADDR
2105         bool "Auto calculation of the decompressed kernel image address"
2106         depends on !ZBOOT_ROM && !ARCH_U300
2107         help
2108           ZRELADDR is the physical address where the decompressed kernel
2109           image will be placed. If AUTO_ZRELADDR is selected, the address
2110           will be determined at run-time by masking the current IP with
2111           0xf8000000. This assumes the zImage being placed in the first 128MB
2112           from start of memory.
2113
2114 endmenu
2115
2116 menu "CPU Power Management"
2117
2118 if ARCH_HAS_CPUFREQ
2119
2120 source "drivers/cpufreq/Kconfig"
2121
2122 config CPU_FREQ_IMX
2123         tristate "CPUfreq driver for i.MX CPUs"
2124         depends on ARCH_MXC && CPU_FREQ
2125         help
2126           This enables the CPUfreq driver for i.MX CPUs.
2127
2128 config CPU_FREQ_SA1100
2129         bool
2130
2131 config CPU_FREQ_SA1110
2132         bool
2133
2134 config CPU_FREQ_INTEGRATOR
2135         tristate "CPUfreq driver for ARM Integrator CPUs"
2136         depends on ARCH_INTEGRATOR && CPU_FREQ
2137         default y
2138         help
2139           This enables the CPUfreq driver for ARM Integrator CPUs.
2140
2141           For details, take a look at <file:Documentation/cpu-freq>.
2142
2143           If in doubt, say Y.
2144
2145 config CPU_FREQ_PXA
2146         bool
2147         depends on CPU_FREQ && ARCH_PXA && PXA25x
2148         default y
2149         select CPU_FREQ_TABLE
2150         select CPU_FREQ_DEFAULT_GOV_USERSPACE
2151
2152 config CPU_FREQ_S3C
2153         bool
2154         help
2155           Internal configuration node for common cpufreq on Samsung SoC
2156
2157 config CPU_FREQ_S3C24XX
2158         bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2159         depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
2160         select CPU_FREQ_S3C
2161         help
2162           This enables the CPUfreq driver for the Samsung S3C24XX family
2163           of CPUs.
2164
2165           For details, take a look at <file:Documentation/cpu-freq>.
2166
2167           If in doubt, say N.
2168
2169 config CPU_FREQ_S3C24XX_PLL
2170         bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2171         depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2172         help
2173           Compile in support for changing the PLL frequency from the
2174           S3C24XX series CPUfreq driver. The PLL takes time to settle
2175           after a frequency change, so by default it is not enabled.
2176
2177           This also means that the PLL tables for the selected CPU(s) will
2178           be built which may increase the size of the kernel image.
2179
2180 config CPU_FREQ_S3C24XX_DEBUG
2181         bool "Debug CPUfreq Samsung driver core"
2182         depends on CPU_FREQ_S3C24XX
2183         help
2184           Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2185
2186 config CPU_FREQ_S3C24XX_IODEBUG
2187         bool "Debug CPUfreq Samsung driver IO timing"
2188         depends on CPU_FREQ_S3C24XX
2189         help
2190           Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2191
2192 config CPU_FREQ_S3C24XX_DEBUGFS
2193         bool "Export debugfs for CPUFreq"
2194         depends on CPU_FREQ_S3C24XX && DEBUG_FS
2195         help
2196           Export status information via debugfs.
2197
2198 endif
2199
2200 source "drivers/cpuidle/Kconfig"
2201
2202 endmenu
2203
2204 menu "Floating point emulation"
2205
2206 comment "At least one emulation must be selected"
2207
2208 config FPE_NWFPE
2209         bool "NWFPE math emulation"
2210         depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2211         ---help---
2212           Say Y to include the NWFPE floating point emulator in the kernel.
2213           This is necessary to run most binaries. Linux does not currently
2214           support floating point hardware so you need to say Y here even if
2215           your machine has an FPA or floating point co-processor podule.
2216
2217           You may say N here if you are going to load the Acorn FPEmulator
2218           early in the bootup.
2219
2220 config FPE_NWFPE_XP
2221         bool "Support extended precision"
2222         depends on FPE_NWFPE
2223         help
2224           Say Y to include 80-bit support in the kernel floating-point
2225           emulator.  Otherwise, only 32 and 64-bit support is compiled in.
2226           Note that gcc does not generate 80-bit operations by default,
2227           so in most cases this option only enlarges the size of the
2228           floating point emulator without any good reason.
2229
2230           You almost surely want to say N here.
2231
2232 config FPE_FASTFPE
2233         bool "FastFPE math emulation (EXPERIMENTAL)"
2234         depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2235         ---help---
2236           Say Y here to include the FAST floating point emulator in the kernel.
2237           This is an experimental much faster emulator which now also has full
2238           precision for the mantissa.  It does not support any exceptions.
2239           It is very simple, and approximately 3-6 times faster than NWFPE.
2240
2241           It should be sufficient for most programs.  It may be not suitable
2242           for scientific calculations, but you have to check this for yourself.
2243           If you do not feel you need a faster FP emulation you should better
2244           choose NWFPE.
2245
2246 config VFP
2247         bool "VFP-format floating point maths"
2248         depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2249         help
2250           Say Y to include VFP support code in the kernel. This is needed
2251           if your hardware includes a VFP unit.
2252
2253           Please see <file:Documentation/arm/VFP/release-notes.txt> for
2254           release notes and additional status information.
2255
2256           Say N if your target does not have VFP hardware.
2257
2258 config VFPv3
2259         bool
2260         depends on VFP
2261         default y if CPU_V7
2262
2263 config NEON
2264         bool "Advanced SIMD (NEON) Extension support"
2265         depends on VFPv3 && CPU_V7
2266         help
2267           Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2268           Extension.
2269
2270 endmenu
2271
2272 menu "Userspace binary formats"
2273
2274 source "fs/Kconfig.binfmt"
2275
2276 config ARTHUR
2277         tristate "RISC OS personality"
2278         depends on !AEABI
2279         help
2280           Say Y here to include the kernel code necessary if you want to run
2281           Acorn RISC OS/Arthur binaries under Linux. This code is still very
2282           experimental; if this sounds frightening, say N and sleep in peace.
2283           You can also say M here to compile this support as a module (which
2284           will be called arthur).
2285
2286 endmenu
2287
2288 menu "Power management options"
2289
2290 source "kernel/power/Kconfig"
2291
2292 config ARCH_SUSPEND_POSSIBLE
2293         depends on !ARCH_S5PC100
2294         depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2295                 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
2296         def_bool y
2297
2298 config ARM_CPU_SUSPEND
2299         def_bool PM_SLEEP
2300
2301 endmenu
2302
2303 source "net/Kconfig"
2304
2305 source "drivers/Kconfig"
2306
2307 source "fs/Kconfig"
2308
2309 source "arch/arm/Kconfig.debug"
2310
2311 source "security/Kconfig"
2312
2313 source "crypto/Kconfig"
2314
2315 source "lib/Kconfig"