arch/arm/Kconfig

   1 config ARM
   2         bool
   3         default y
   4         select ARCH_BINFMT_ELF_RANDOMIZE_PIE
   5         select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
   6         select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
   7         select ARCH_HAVE_CUSTOM_GPIO_H
   8         select ARCH_WANT_IPC_PARSE_VERSION
   9         select BUILDTIME_EXTABLE_SORT if MMU
  10         select CLONE_BACKWARDS
  11         select CPU_PM if (SUSPEND || CPU_IDLE)
  12         select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
  13         select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
  14         select GENERIC_CLOCKEVENTS_BROADCAST if SMP
  15         select GENERIC_IDLE_POLL_SETUP
  16         select GENERIC_IRQ_PROBE
  17         select GENERIC_IRQ_SHOW
  18         select GENERIC_PCI_IOMAP
  19         select GENERIC_SCHED_CLOCK
  20         select GENERIC_SMP_IDLE_THREAD
  21         select GENERIC_STRNCPY_FROM_USER
  22         select GENERIC_STRNLEN_USER
  23         select HARDIRQS_SW_RESEND
  24         select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
  25         select HAVE_ARCH_KGDB
  26         select HAVE_ARCH_SECCOMP_FILTER
  27         select HAVE_ARCH_TRACEHOOK
  28         select HAVE_BPF_JIT
  29         select HAVE_CONTEXT_TRACKING
  30         select HAVE_C_RECORDMCOUNT
  31         select HAVE_DEBUG_KMEMLEAK
  32         select HAVE_DMA_API_DEBUG
  33         select HAVE_DMA_ATTRS
  34         select HAVE_DMA_CONTIGUOUS if MMU
  35         select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
  36         select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
  37         select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
  38         select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
  39         select HAVE_GENERIC_DMA_COHERENT
  40         select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
  41         select HAVE_IDE if PCI || ISA || PCMCIA
  42         select HAVE_IRQ_TIME_ACCOUNTING
  43         select HAVE_KERNEL_GZIP
  44         select HAVE_KERNEL_LZ4
  45         select HAVE_KERNEL_LZMA
  46         select HAVE_KERNEL_LZO
  47         select HAVE_KERNEL_XZ
  48         select HAVE_KPROBES if !XIP_KERNEL
  49         select HAVE_KRETPROBES if (HAVE_KPROBES)
  50         select HAVE_MEMBLOCK
  51         select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
  52         select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
  53         select HAVE_PERF_EVENTS
  54         select HAVE_REGS_AND_STACK_ACCESS_API
  55         select HAVE_SYSCALL_TRACEPOINTS
  56         select HAVE_UID16
  57         select HAVE_VIRT_CPU_ACCOUNTING_GEN
  58         select IRQ_FORCED_THREADING
  59         select KTIME_SCALAR
  60         select MODULES_USE_ELF_REL
  61         select OLD_SIGACTION
  62         select OLD_SIGSUSPEND3
  63         select PERF_USE_VMALLOC
  64         select RTC_LIB
  65         select SYS_SUPPORTS_APM_EMULATION
  66         # Above selects are sorted alphabetically; please add new ones
  67         # according to that.  Thanks.
  68         help
  69           The ARM series is a line of low-power-consumption RISC chip designs
  70           licensed by ARM Ltd and targeted at embedded applications and
  71           handhelds such as the Compaq IPAQ.  ARM-based PCs are no longer
  72           manufactured, but legacy ARM-based PC hardware remains popular in
  73           Europe.  There is an ARM Linux project with a web page at
  74           <http://www.arm.linux.org.uk/>.
  75
  76 config ARM_HAS_SG_CHAIN
  77         bool
  78
  79 config NEED_SG_DMA_LENGTH
  80         bool
  81
  82 config ARM_DMA_USE_IOMMU
  83         bool
  84         select ARM_HAS_SG_CHAIN
  85         select NEED_SG_DMA_LENGTH
  86
  87 if ARM_DMA_USE_IOMMU
  88
  89 config ARM_DMA_IOMMU_ALIGNMENT
  90         int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
  91         range 4 9
  92         default 8
  93         help
  94           DMA mapping framework by default aligns all buffers to the smallest
  95           PAGE_SIZE order which is greater than or equal to the requested buffer
  96           size. This works well for buffers up to a few hundreds kilobytes, but
  97           for larger buffers it just a waste of address space. Drivers which has
  98           relatively small addressing window (like 64Mib) might run out of
  99           virtual space with just a few allocations.
 100
 101           With this parameter you can specify the maximum PAGE_SIZE order for
 102           DMA IOMMU buffers. Larger buffers will be aligned only to this
 103           specified order. The order is expressed as a power of two multiplied
 104           by the PAGE_SIZE.
 105
 106 endif
 107
 108 config HAVE_PWM
 109         bool
 110
 111 config MIGHT_HAVE_PCI
 112         bool
 113
 114 config SYS_SUPPORTS_APM_EMULATION
 115         bool
 116
 117 config HAVE_TCM
 118         bool
 119         select GENERIC_ALLOCATOR
 120
 121 config HAVE_PROC_CPU
 122         bool
 123
 124 config NO_IOPORT
 125         bool
 126
 127 config EISA
 128         bool
 129         ---help---
 130           The Extended Industry Standard Architecture (EISA) bus was
 131           developed as an open alternative to the IBM MicroChannel bus.
 132
 133           The EISA bus provided some of the features of the IBM MicroChannel
 134           bus while maintaining backward compatibility with cards made for
 135           the older ISA bus.  The EISA bus saw limited use between 1988 and
 136           1995 when it was made obsolete by the PCI bus.
 137
 138           Say Y here if you are building a kernel for an EISA-based machine.
 139
 140           Otherwise, say N.
 141
 142 config SBUS
 143         bool
 144
 145 config STACKTRACE_SUPPORT
 146         bool
 147         default y
 148
 149 config HAVE_LATENCYTOP_SUPPORT
 150         bool
 151         depends on !SMP
 152         default y
 153
 154 config LOCKDEP_SUPPORT
 155         bool
 156         default y
 157
 158 config TRACE_IRQFLAGS_SUPPORT
 159         bool
 160         default y
 161
 162 config RWSEM_GENERIC_SPINLOCK
 163         bool
 164         default y
 165
 166 config RWSEM_XCHGADD_ALGORITHM
 167         bool
 168
 169 config ARCH_HAS_ILOG2_U32
 170         bool
 171
 172 config ARCH_HAS_ILOG2_U64
 173         bool
 174
 175 config ARCH_HAS_CPUFREQ
 176         bool
 177         help
 178           Internal node to signify that the ARCH has CPUFREQ support
 179           and that the relevant menu configurations are displayed for
 180           it.
 181
 182 config ARCH_HAS_BANDGAP
 183         bool
 184
 185 config GENERIC_HWEIGHT
 186         bool
 187         default y
 188
 189 config GENERIC_CALIBRATE_DELAY
 190         bool
 191         default y
 192
 193 config ARCH_MAY_HAVE_PC_FDC
 194         bool
 195
 196 config ZONE_DMA
 197         bool
 198
 199 config NEED_DMA_MAP_STATE
 200        def_bool y
 201
 202 config ARCH_HAS_DMA_SET_COHERENT_MASK
 203         bool
 204
 205 config GENERIC_ISA_DMA
 206         bool
 207
 208 config FIQ
 209         bool
 210
 211 config NEED_RET_TO_USER
 212         bool
 213
 214 config ARCH_MTD_XIP
 215         bool
 216
 217 config VECTORS_BASE
 218         hex
 219         default 0xffff0000 if MMU || CPU_HIGH_VECTOR
 220         default DRAM_BASE if REMAP_VECTORS_TO_RAM
 221         default 0x00000000
 222         help
 223           The base address of exception vectors.  This must be two pages
 224           in size.
 225
 226 config ARM_PATCH_PHYS_VIRT
 227         bool "Patch physical to virtual translations at runtime" if EMBEDDED
 228         default y
 229         depends on !XIP_KERNEL && MMU
 230         depends on !ARCH_REALVIEW || !SPARSEMEM
 231         help
 232           Patch phys-to-virt and virt-to-phys translation functions at
 233           boot and module load time according to the position of the
 234           kernel in system memory.
 235
 236           This can only be used with non-XIP MMU kernels where the base
 237           of physical memory is at a 16MB boundary.
 238
 239           Only disable this option if you know that you do not require
 240           this feature (eg, building a kernel for a single machine) and
 241           you need to shrink the kernel to the minimal size.
 242
 243 config NEED_MACH_GPIO_H
 244         bool
 245         help
 246           Select this when mach/gpio.h is required to provide special
 247           definitions for this platform. The need for mach/gpio.h should
 248           be avoided when possible.
 249
 250 config NEED_MACH_IO_H
 251         bool
 252         help
 253           Select this when mach/io.h is required to provide special
 254           definitions for this platform.  The need for mach/io.h should
 255           be avoided when possible.
 256
 257 config NEED_MACH_MEMORY_H
 258         bool
 259         help
 260           Select this when mach/memory.h is required to provide special
 261           definitions for this platform.  The need for mach/memory.h should
 262           be avoided when possible.
 263
 264 config PHYS_OFFSET
 265         hex "Physical address of main memory" if MMU
 266         depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
 267         default DRAM_BASE if !MMU
 268         help
 269           Please provide the physical address corresponding to the
 270           location of main memory in your system.
 271
 272 config GENERIC_BUG
 273         def_bool y
 274         depends on BUG
 275
 276 source "init/Kconfig"
 277
 278 source "kernel/Kconfig.freezer"
 279
 280 menu "System Type"
 281
 282 config MMU
 283         bool "MMU-based Paged Memory Management Support"
 284         default y
 285         help
 286           Select if you want MMU-based virtualised addressing space
 287           support by paged memory management. If unsure, say 'Y'.
 288
 289 #
 290 # The "ARM system type" choice list is ordered alphabetically by option
 291 # text.  Please add new entries in the option alphabetic order.
 292 #
 293 choice
 294         prompt "ARM system type"
 295         default ARCH_VERSATILE if !MMU
 296         default ARCH_MULTIPLATFORM if MMU
 297
 298 config ARCH_MULTIPLATFORM
 299         bool "Allow multiple platforms to be selected"
 300         depends on MMU
 301         select ARM_PATCH_PHYS_VIRT
 302         select AUTO_ZRELADDR
 303         select COMMON_CLK
 304         select MULTI_IRQ_HANDLER
 305         select SPARSE_IRQ
 306         select USE_OF
 307
 308 config ARCH_INTEGRATOR
 309         bool "ARM Ltd. Integrator family"
 310         select ARCH_HAS_CPUFREQ
 311         select ARM_AMBA
 312         select COMMON_CLK
 313         select COMMON_CLK_VERSATILE
 314         select GENERIC_CLOCKEVENTS
 315         select HAVE_TCM
 316         select ICST
 317         select MULTI_IRQ_HANDLER
 318         select NEED_MACH_MEMORY_H
 319         select PLAT_VERSATILE
 320         select SPARSE_IRQ
 321         select USE_OF
 322         select VERSATILE_FPGA_IRQ
 323         help
 324           Support for ARM's Integrator platform.
 325
 326 config ARCH_REALVIEW
 327         bool "ARM Ltd. RealView family"
 328         select ARCH_WANT_OPTIONAL_GPIOLIB
 329         select ARM_AMBA
 330         select ARM_TIMER_SP804
 331         select COMMON_CLK
 332         select COMMON_CLK_VERSATILE
 333         select GENERIC_CLOCKEVENTS
 334         select GPIO_PL061 if GPIOLIB
 335         select ICST
 336         select NEED_MACH_MEMORY_H
 337         select PLAT_VERSATILE
 338         select PLAT_VERSATILE_CLCD
 339         help
 340           This enables support for ARM Ltd RealView boards.
 341
 342 config ARCH_VERSATILE
 343         bool "ARM Ltd. Versatile family"
 344         select ARCH_WANT_OPTIONAL_GPIOLIB
 345         select ARM_AMBA
 346         select ARM_TIMER_SP804
 347         select ARM_VIC
 348         select CLKDEV_LOOKUP
 349         select GENERIC_CLOCKEVENTS
 350         select HAVE_MACH_CLKDEV
 351         select ICST
 352         select PLAT_VERSATILE
 353         select PLAT_VERSATILE_CLCD
 354         select PLAT_VERSATILE_CLOCK
 355         select VERSATILE_FPGA_IRQ
 356         help
 357           This enables support for ARM Ltd Versatile board.
 358
 359 config ARCH_AT91
 360         bool "Atmel AT91"
 361         select ARCH_REQUIRE_GPIOLIB
 362         select CLKDEV_LOOKUP
 363         select IRQ_DOMAIN
 364         select NEED_MACH_GPIO_H
 365         select NEED_MACH_IO_H if PCCARD
 366         select PINCTRL
 367         select PINCTRL_AT91 if USE_OF
 368         help
 369           This enables support for systems based on Atmel
 370           AT91RM9200 and AT91SAM9* processors.
 371
 372 config ARCH_CLPS711X
 373         bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
 374         select ARCH_REQUIRE_GPIOLIB
 375         select AUTO_ZRELADDR
 376         select CLKSRC_MMIO
 377         select COMMON_CLK
 378         select CPU_ARM720T
 379         select GENERIC_CLOCKEVENTS
 380         select MFD_SYSCON
 381         select MULTI_IRQ_HANDLER
 382         select SPARSE_IRQ
 383         help
 384           Support for Cirrus Logic 711x/721x/731x based boards.
 385
 386 config ARCH_GEMINI
 387         bool "Cortina Systems Gemini"
 388         select ARCH_REQUIRE_GPIOLIB
 389         select CLKSRC_MMIO
 390         select CPU_FA526
 391         select GENERIC_CLOCKEVENTS
 392         help
 393           Support for the Cortina Systems Gemini family SoCs
 394
 395 config ARCH_EBSA110
 396         bool "EBSA-110"
 397         select ARCH_USES_GETTIMEOFFSET
 398         select CPU_SA110
 399         select ISA
 400         select NEED_MACH_IO_H
 401         select NEED_MACH_MEMORY_H
 402         select NO_IOPORT
 403         help
 404           This is an evaluation board for the StrongARM processor available
 405           from Digital. It has limited hardware on-board, including an
 406           Ethernet interface, two PCMCIA sockets, two serial ports and a
 407           parallel port.
 408
 409 config ARCH_EP93XX
 410         bool "EP93xx-based"
 411         select ARCH_HAS_HOLES_MEMORYMODEL
 412         select ARCH_REQUIRE_GPIOLIB
 413         select ARCH_USES_GETTIMEOFFSET
 414         select ARM_AMBA
 415         select ARM_VIC
 416         select CLKDEV_LOOKUP
 417         select CPU_ARM920T
 418         select NEED_MACH_MEMORY_H
 419         help
 420           This enables support for the Cirrus EP93xx series of CPUs.
 421
 422 config ARCH_FOOTBRIDGE
 423         bool "FootBridge"
 424         select CPU_SA110
 425         select FOOTBRIDGE
 426         select GENERIC_CLOCKEVENTS
 427         select HAVE_IDE
 428         select NEED_MACH_IO_H if !MMU
 429         select NEED_MACH_MEMORY_H
 430         help
 431           Support for systems based on the DC21285 companion chip
 432           ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
 433
 434 config ARCH_NETX
 435         bool "Hilscher NetX based"
 436         select ARM_VIC
 437         select CLKSRC_MMIO
 438         select CPU_ARM926T
 439         select GENERIC_CLOCKEVENTS
 440         help
 441           This enables support for systems based on the Hilscher NetX Soc
 442
 443 config ARCH_IOP13XX
 444         bool "IOP13xx-based"
 445         depends on MMU
 446         select CPU_XSC3
 447         select NEED_MACH_MEMORY_H
 448         select NEED_RET_TO_USER
 449         select PCI
 450         select PLAT_IOP
 451         select VMSPLIT_1G
 452         help
 453           Support for Intel's IOP13XX (XScale) family of processors.
 454
 455 config ARCH_IOP32X
 456         bool "IOP32x-based"
 457         depends on MMU
 458         select ARCH_REQUIRE_GPIOLIB
 459         select CPU_XSCALE
 460         select GPIO_IOP
 461         select NEED_RET_TO_USER
 462         select PCI
 463         select PLAT_IOP
 464         help
 465           Support for Intel's 80219 and IOP32X (XScale) family of
 466           processors.
 467
 468 config ARCH_IOP33X
 469         bool "IOP33x-based"
 470         depends on MMU
 471         select ARCH_REQUIRE_GPIOLIB
 472         select CPU_XSCALE
 473         select GPIO_IOP
 474         select NEED_RET_TO_USER
 475         select PCI
 476         select PLAT_IOP
 477         help
 478           Support for Intel's IOP33X (XScale) family of processors.
 479
 480 config ARCH_IXP4XX
 481         bool "IXP4xx-based"
 482         depends on MMU
 483         select ARCH_HAS_DMA_SET_COHERENT_MASK
 484         select ARCH_REQUIRE_GPIOLIB
 485         select CLKSRC_MMIO
 486         select CPU_XSCALE
 487         select DMABOUNCE if PCI
 488         select GENERIC_CLOCKEVENTS
 489         select MIGHT_HAVE_PCI
 490         select NEED_MACH_IO_H
 491         select USB_EHCI_BIG_ENDIAN_DESC
 492         select USB_EHCI_BIG_ENDIAN_MMIO
 493         help
 494           Support for Intel's IXP4XX (XScale) family of processors.
 495
 496 config ARCH_DOVE
 497         bool "Marvell Dove"
 498         select ARCH_REQUIRE_GPIOLIB
 499         select CPU_PJ4
 500         select GENERIC_CLOCKEVENTS
 501         select MIGHT_HAVE_PCI
 502         select MVEBU_MBUS
 503         select PINCTRL
 504         select PINCTRL_DOVE
 505         select PLAT_ORION_LEGACY
 506         select USB_ARCH_HAS_EHCI
 507         help
 508           Support for the Marvell Dove SoC 88AP510
 509
 510 config ARCH_KIRKWOOD
 511         bool "Marvell Kirkwood"
 512         select ARCH_HAS_CPUFREQ
 513         select ARCH_REQUIRE_GPIOLIB
 514         select CPU_FEROCEON
 515         select GENERIC_CLOCKEVENTS
 516         select MVEBU_MBUS
 517         select PCI
 518         select PCI_QUIRKS
 519         select PINCTRL
 520         select PINCTRL_KIRKWOOD
 521         select PLAT_ORION_LEGACY
 522         help
 523           Support for the following Marvell Kirkwood series SoCs:
 524           88F6180, 88F6192 and 88F6281.
 525
 526 config ARCH_MV78XX0
 527         bool "Marvell MV78xx0"
 528         select ARCH_REQUIRE_GPIOLIB
 529         select CPU_FEROCEON
 530         select GENERIC_CLOCKEVENTS
 531         select MVEBU_MBUS
 532         select PCI
 533         select PLAT_ORION_LEGACY
 534         help
 535           Support for the following Marvell MV78xx0 series SoCs:
 536           MV781x0, MV782x0.
 537
 538 config ARCH_ORION5X
 539         bool "Marvell Orion"
 540         depends on MMU
 541         select ARCH_REQUIRE_GPIOLIB
 542         select CPU_FEROCEON
 543         select GENERIC_CLOCKEVENTS
 544         select MVEBU_MBUS
 545         select PCI
 546         select PLAT_ORION_LEGACY
 547         help
 548           Support for the following Marvell Orion 5x series SoCs:
 549           Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
 550           Orion-2 (5281), Orion-1-90 (6183).
 551
 552 config ARCH_MMP
 553         bool "Marvell PXA168/910/MMP2"
 554         depends on MMU
 555         select ARCH_REQUIRE_GPIOLIB
 556         select CLKDEV_LOOKUP
 557         select GENERIC_ALLOCATOR
 558         select GENERIC_CLOCKEVENTS
 559         select GPIO_PXA
 560         select IRQ_DOMAIN
 561         select MULTI_IRQ_HANDLER
 562         select PINCTRL
 563         select PLAT_PXA
 564         select SPARSE_IRQ
 565         help
 566           Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
 567
 568 config ARCH_KS8695
 569         bool "Micrel/Kendin KS8695"
 570         select ARCH_REQUIRE_GPIOLIB
 571         select CLKSRC_MMIO
 572         select CPU_ARM922T
 573         select GENERIC_CLOCKEVENTS
 574         select NEED_MACH_MEMORY_H
 575         help
 576           Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
 577           System-on-Chip devices.
 578
 579 config ARCH_W90X900
 580         bool "Nuvoton W90X900 CPU"
 581         select ARCH_REQUIRE_GPIOLIB
 582         select CLKDEV_LOOKUP
 583         select CLKSRC_MMIO
 584         select CPU_ARM926T
 585         select GENERIC_CLOCKEVENTS
 586         help
 587           Support for Nuvoton (Winbond logic dept.) ARM9 processor,
 588           At present, the w90x900 has been renamed nuc900, regarding
 589           the ARM series product line, you can login the following
 590           link address to know more.
 591
 592           <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
 593                 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
 594
 595 config ARCH_LPC32XX
 596         bool "NXP LPC32XX"
 597         select ARCH_REQUIRE_GPIOLIB
 598         select ARM_AMBA
 599         select CLKDEV_LOOKUP
 600         select CLKSRC_MMIO
 601         select CPU_ARM926T
 602         select GENERIC_CLOCKEVENTS
 603         select HAVE_IDE
 604         select HAVE_PWM
 605         select USB_ARCH_HAS_OHCI
 606         select USE_OF
 607         help
 608           Support for the NXP LPC32XX family of processors
 609
 610 config ARCH_PXA
 611         bool "PXA2xx/PXA3xx-based"
 612         depends on MMU
 613         select ARCH_HAS_CPUFREQ
 614         select ARCH_MTD_XIP
 615         select ARCH_REQUIRE_GPIOLIB
 616         select ARM_CPU_SUSPEND if PM
 617         select AUTO_ZRELADDR
 618         select CLKDEV_LOOKUP
 619         select CLKSRC_MMIO
 620         select GENERIC_CLOCKEVENTS
 621         select GPIO_PXA
 622         select HAVE_IDE
 623         select MULTI_IRQ_HANDLER
 624         select PLAT_PXA
 625         select SPARSE_IRQ
 626         help
 627           Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
 628
 629 config ARCH_MSM
 630         bool "Qualcomm MSM"
 631         select ARCH_REQUIRE_GPIOLIB
 632         select CLKSRC_OF if OF
 633         select COMMON_CLK
 634         select GENERIC_CLOCKEVENTS
 635         help
 636           Support for Qualcomm MSM/QSD based systems.  This runs on the
 637           apps processor of the MSM/QSD and depends on a shared memory
 638           interface to the modem processor which runs the baseband
 639           stack and controls some vital subsystems
 640           (clock and power control, etc).
 641
 642 config ARCH_SHMOBILE
 643         bool "Renesas SH-Mobile / R-Mobile"
 644         select ARM_PATCH_PHYS_VIRT
 645         select CLKDEV_LOOKUP
 646         select GENERIC_CLOCKEVENTS
 647         select HAVE_ARM_SCU if SMP
 648         select HAVE_ARM_TWD if SMP
 649         select HAVE_MACH_CLKDEV
 650         select HAVE_SMP
 651         select MIGHT_HAVE_CACHE_L2X0
 652         select MULTI_IRQ_HANDLER
 653         select NO_IOPORT
 654         select PINCTRL
 655         select PM_GENERIC_DOMAINS if PM
 656         select SPARSE_IRQ
 657         help
 658           Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
 659
 660 config ARCH_RPC
 661         bool "RiscPC"
 662         select ARCH_ACORN
 663         select ARCH_MAY_HAVE_PC_FDC
 664         select ARCH_SPARSEMEM_ENABLE
 665         select ARCH_USES_GETTIMEOFFSET
 666         select FIQ
 667         select HAVE_IDE
 668         select HAVE_PATA_PLATFORM
 669         select ISA_DMA_API
 670         select NEED_MACH_IO_H
 671         select NEED_MACH_MEMORY_H
 672         select NO_IOPORT
 673         select VIRT_TO_BUS
 674         help
 675           On the Acorn Risc-PC, Linux can support the internal IDE disk and
 676           CD-ROM interface, serial and parallel port, and the floppy drive.
 677
 678 config ARCH_SA1100
 679         bool "SA1100-based"
 680         select ARCH_HAS_CPUFREQ
 681         select ARCH_MTD_XIP
 682         select ARCH_REQUIRE_GPIOLIB
 683         select ARCH_SPARSEMEM_ENABLE
 684         select CLKDEV_LOOKUP
 685         select CLKSRC_MMIO
 686         select CPU_FREQ
 687         select CPU_SA1100
 688         select GENERIC_CLOCKEVENTS
 689         select HAVE_IDE
 690         select ISA
 691         select NEED_MACH_GPIO_H
 692         select NEED_MACH_MEMORY_H
 693         select SPARSE_IRQ
 694         help
 695           Support for StrongARM 11x0 based boards.
 696
 697 config ARCH_S3C24XX
 698         bool "Samsung S3C24XX SoCs"
 699         select ARCH_HAS_CPUFREQ
 700         select ARCH_REQUIRE_GPIOLIB
 701         select CLKDEV_LOOKUP
 702         select CLKSRC_SAMSUNG_PWM
 703         select GENERIC_CLOCKEVENTS
 704         select GPIO_SAMSUNG
 705         select HAVE_S3C2410_I2C if I2C
 706         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 707         select HAVE_S3C_RTC if RTC_CLASS
 708         select MULTI_IRQ_HANDLER
 709         select NEED_MACH_GPIO_H
 710         select NEED_MACH_IO_H
 711         select SAMSUNG_ATAGS
 712         help
 713           Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
 714           and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
 715           (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
 716           Samsung SMDK2410 development board (and derivatives).
 717
 718 config ARCH_S3C64XX
 719         bool "Samsung S3C64XX"
 720         select ARCH_HAS_CPUFREQ
 721         select ARCH_REQUIRE_GPIOLIB
 722         select ARM_VIC
 723         select CLKDEV_LOOKUP
 724         select CLKSRC_SAMSUNG_PWM
 725         select COMMON_CLK
 726         select CPU_V6
 727         select GENERIC_CLOCKEVENTS
 728         select GPIO_SAMSUNG
 729         select HAVE_S3C2410_I2C if I2C
 730         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 731         select HAVE_TCM
 732         select NEED_MACH_GPIO_H
 733         select NO_IOPORT
 734         select PLAT_SAMSUNG
 735         select PM_GENERIC_DOMAINS
 736         select S3C_DEV_NAND
 737         select S3C_GPIO_TRACK
 738         select SAMSUNG_ATAGS
 739         select SAMSUNG_GPIOLIB_4BIT
 740         select SAMSUNG_WAKEMASK
 741         select SAMSUNG_WDT_RESET
 742         select USB_ARCH_HAS_OHCI
 743         help
 744           Samsung S3C64XX series based systems
 745
 746 config ARCH_S5P64X0
 747         bool "Samsung S5P6440 S5P6450"
 748         select CLKDEV_LOOKUP
 749         select CLKSRC_SAMSUNG_PWM
 750         select CPU_V6
 751         select GENERIC_CLOCKEVENTS
 752         select GPIO_SAMSUNG
 753         select HAVE_S3C2410_I2C if I2C
 754         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 755         select HAVE_S3C_RTC if RTC_CLASS
 756         select NEED_MACH_GPIO_H
 757         select SAMSUNG_ATAGS
 758         select SAMSUNG_WDT_RESET
 759         help
 760           Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
 761           SMDK6450.
 762
 763 config ARCH_S5PC100
 764         bool "Samsung S5PC100"
 765         select ARCH_REQUIRE_GPIOLIB
 766         select CLKDEV_LOOKUP
 767         select CLKSRC_SAMSUNG_PWM
 768         select CPU_V7
 769         select GENERIC_CLOCKEVENTS
 770         select GPIO_SAMSUNG
 771         select HAVE_S3C2410_I2C if I2C
 772         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 773         select HAVE_S3C_RTC if RTC_CLASS
 774         select NEED_MACH_GPIO_H
 775         select SAMSUNG_ATAGS
 776         select SAMSUNG_WDT_RESET
 777         help
 778           Samsung S5PC100 series based systems
 779
 780 config ARCH_S5PV210
 781         bool "Samsung S5PV210/S5PC110"
 782         select ARCH_HAS_CPUFREQ
 783         select ARCH_HAS_HOLES_MEMORYMODEL
 784         select ARCH_SPARSEMEM_ENABLE
 785         select CLKDEV_LOOKUP
 786         select CLKSRC_SAMSUNG_PWM
 787         select CPU_V7
 788         select GENERIC_CLOCKEVENTS
 789         select GPIO_SAMSUNG
 790         select HAVE_S3C2410_I2C if I2C
 791         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 792         select HAVE_S3C_RTC if RTC_CLASS
 793         select NEED_MACH_GPIO_H
 794         select NEED_MACH_MEMORY_H
 795         select SAMSUNG_ATAGS
 796         help
 797           Samsung S5PV210/S5PC110 series based systems
 798
 799 config ARCH_EXYNOS
 800         bool "Samsung EXYNOS"
 801         select ARCH_HAS_CPUFREQ
 802         select ARCH_HAS_HOLES_MEMORYMODEL
 803         select ARCH_REQUIRE_GPIOLIB
 804         select ARCH_SPARSEMEM_ENABLE
 805         select ARM_GIC
 806         select COMMON_CLK
 807         select CPU_V7
 808         select GENERIC_CLOCKEVENTS
 809         select HAVE_S3C2410_I2C if I2C
 810         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 811         select HAVE_S3C_RTC if RTC_CLASS
 812         select NEED_MACH_MEMORY_H
 813         select SPARSE_IRQ
 814         select USE_OF
 815         help
 816           Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
 817
 818 config ARCH_DAVINCI
 819         bool "TI DaVinci"
 820         select ARCH_HAS_HOLES_MEMORYMODEL
 821         select ARCH_REQUIRE_GPIOLIB
 822         select CLKDEV_LOOKUP
 823         select GENERIC_ALLOCATOR
 824         select GENERIC_CLOCKEVENTS
 825         select GENERIC_IRQ_CHIP
 826         select HAVE_IDE
 827         select TI_PRIV_EDMA
 828         select USE_OF
 829         select ZONE_DMA
 830         help
 831           Support for TI's DaVinci platform.
 832
 833 config ARCH_OMAP1
 834         bool "TI OMAP1"
 835         depends on MMU
 836         select ARCH_HAS_CPUFREQ
 837         select ARCH_HAS_HOLES_MEMORYMODEL
 838         select ARCH_OMAP
 839         select ARCH_REQUIRE_GPIOLIB
 840         select CLKDEV_LOOKUP
 841         select CLKSRC_MMIO
 842         select GENERIC_CLOCKEVENTS
 843         select GENERIC_IRQ_CHIP
 844         select HAVE_IDE
 845         select IRQ_DOMAIN
 846         select NEED_MACH_IO_H if PCCARD
 847         select NEED_MACH_MEMORY_H
 848         help
 849           Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
 850
 851 endchoice
 852
 853 menu "Multiple platform selection"
 854         depends on ARCH_MULTIPLATFORM
 855
 856 comment "CPU Core family selection"
 857
 858 config ARCH_MULTI_V4T
 859         bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
 860         depends on !ARCH_MULTI_V6_V7
 861         select ARCH_MULTI_V4_V5
 862         select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
 863                 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
 864                 CPU_ARM925T || CPU_ARM940T)
 865
 866 config ARCH_MULTI_V5
 867         bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
 868         depends on !ARCH_MULTI_V6_V7
 869         select ARCH_MULTI_V4_V5
 870         select CPU_ARM926T if (!CPU_ARM946E || CPU_ARM1020 || \
 871                 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
 872                 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
 873
 874 config ARCH_MULTI_V4_V5
 875         bool
 876
 877 config ARCH_MULTI_V6
 878         bool "ARMv6 based platforms (ARM11)"
 879         select ARCH_MULTI_V6_V7
 880         select CPU_V6
 881
 882 config ARCH_MULTI_V7
 883         bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
 884         default y
 885         select ARCH_MULTI_V6_V7
 886         select CPU_V7
 887
 888 config ARCH_MULTI_V6_V7
 889         bool
 890
 891 config ARCH_MULTI_CPU_AUTO
 892         def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
 893         select ARCH_MULTI_V5
 894
 895 endmenu
 896
 897 #
 898 # This is sorted alphabetically by mach-* pathname.  However, plat-*
 899 # Kconfigs may be included either alphabetically (according to the
 900 # plat- suffix) or along side the corresponding mach-* source.
 901 #
 902 source "arch/arm/mach-mvebu/Kconfig"
 903
 904 source "arch/arm/mach-at91/Kconfig"
 905
 906 source "arch/arm/mach-bcm/Kconfig"
 907
 908 source "arch/arm/mach-bcm2835/Kconfig"
 909
 910 source "arch/arm/mach-clps711x/Kconfig"
 911
 912 source "arch/arm/mach-cns3xxx/Kconfig"
 913
 914 source "arch/arm/mach-davinci/Kconfig"
 915
 916 source "arch/arm/mach-dove/Kconfig"
 917
 918 source "arch/arm/mach-ep93xx/Kconfig"
 919
 920 source "arch/arm/mach-footbridge/Kconfig"
 921
 922 source "arch/arm/mach-gemini/Kconfig"
 923
 924 source "arch/arm/mach-highbank/Kconfig"
 925
 926 source "arch/arm/mach-integrator/Kconfig"
 927
 928 source "arch/arm/mach-iop32x/Kconfig"
 929
 930 source "arch/arm/mach-iop33x/Kconfig"
 931
 932 source "arch/arm/mach-iop13xx/Kconfig"
 933
 934 source "arch/arm/mach-ixp4xx/Kconfig"
 935
 936 source "arch/arm/mach-keystone/Kconfig"
 937
 938 source "arch/arm/mach-kirkwood/Kconfig"
 939
 940 source "arch/arm/mach-ks8695/Kconfig"
 941
 942 source "arch/arm/mach-msm/Kconfig"
 943
 944 source "arch/arm/mach-mv78xx0/Kconfig"
 945
 946 source "arch/arm/mach-imx/Kconfig"
 947
 948 source "arch/arm/mach-mxs/Kconfig"
 949
 950 source "arch/arm/mach-netx/Kconfig"
 951
 952 source "arch/arm/mach-nomadik/Kconfig"
 953
 954 source "arch/arm/mach-nspire/Kconfig"
 955
 956 source "arch/arm/plat-omap/Kconfig"
 957
 958 source "arch/arm/mach-omap1/Kconfig"
 959
 960 source "arch/arm/mach-omap2/Kconfig"
 961
 962 source "arch/arm/mach-orion5x/Kconfig"
 963
 964 source "arch/arm/mach-picoxcell/Kconfig"
 965
 966 source "arch/arm/mach-pxa/Kconfig"
 967 source "arch/arm/plat-pxa/Kconfig"
 968
 969 source "arch/arm/mach-mmp/Kconfig"
 970
 971 source "arch/arm/mach-realview/Kconfig"
 972
 973 source "arch/arm/mach-rockchip/Kconfig"
 974
 975 source "arch/arm/mach-sa1100/Kconfig"
 976
 977 source "arch/arm/plat-samsung/Kconfig"
 978
 979 source "arch/arm/mach-socfpga/Kconfig"
 980
 981 source "arch/arm/mach-spear/Kconfig"
 982
 983 source "arch/arm/mach-sti/Kconfig"
 984
 985 source "arch/arm/mach-s3c24xx/Kconfig"
 986
 987 source "arch/arm/mach-s3c64xx/Kconfig"
 988
 989 source "arch/arm/mach-s5p64x0/Kconfig"
 990
 991 source "arch/arm/mach-s5pc100/Kconfig"
 992
 993 source "arch/arm/mach-s5pv210/Kconfig"
 994
 995 source "arch/arm/mach-exynos/Kconfig"
 996
 997 source "arch/arm/mach-shmobile/Kconfig"
 998
 999 source "arch/arm/mach-sunxi/Kconfig"
1000
1001 source "arch/arm/mach-prima2/Kconfig"
1002
1003 source "arch/arm/mach-tegra/Kconfig"
1004
1005 source "arch/arm/mach-u300/Kconfig"
1006
1007 source "arch/arm/mach-ux500/Kconfig"
1008
1009 source "arch/arm/mach-versatile/Kconfig"
1010
1011 source "arch/arm/mach-vexpress/Kconfig"
1012 source "arch/arm/plat-versatile/Kconfig"
1013
1014 source "arch/arm/mach-virt/Kconfig"
1015
1016 source "arch/arm/mach-vt8500/Kconfig"
1017
1018 source "arch/arm/mach-w90x900/Kconfig"
1019
1020 source "arch/arm/mach-zynq/Kconfig"
1021
1022 # Definitions to make life easier
1023 config ARCH_ACORN
1024         bool
1025
1026 config PLAT_IOP
1027         bool
1028         select GENERIC_CLOCKEVENTS
1029
1030 config PLAT_ORION
1031         bool
1032         select CLKSRC_MMIO
1033         select COMMON_CLK
1034         select GENERIC_IRQ_CHIP
1035         select IRQ_DOMAIN
1036
1037 config PLAT_ORION_LEGACY
1038         bool
1039         select PLAT_ORION
1040
1041 config PLAT_PXA
1042         bool
1043
1044 config PLAT_VERSATILE
1045         bool
1046
1047 config ARM_TIMER_SP804
1048         bool
1049         select CLKSRC_MMIO
1050         select CLKSRC_OF if OF
1051
1052 source arch/arm/mm/Kconfig
1053
1054 config ARM_NR_BANKS
1055         int
1056         default 16 if ARCH_EP93XX
1057         default 8
1058
1059 config IWMMXT
1060         bool "Enable iWMMXt support" if !CPU_PJ4
1061         depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1062         default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4
1063         help
1064           Enable support for iWMMXt context switching at run time if
1065           running on a CPU that supports it.
1066
1067 config XSCALE_PMU
1068         bool
1069         depends on CPU_XSCALE
1070         default y
1071
1072 config MULTI_IRQ_HANDLER
1073         bool
1074         help
1075           Allow each machine to specify it's own IRQ handler at run time.
1076
1077 if !MMU
1078 source "arch/arm/Kconfig-nommu"
1079 endif
1080
1081 config PJ4B_ERRATA_4742
1082         bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1083         depends on CPU_PJ4B && MACH_ARMADA_370
1084         default y
1085         help
1086           When coming out of either a Wait for Interrupt (WFI) or a Wait for
1087           Event (WFE) IDLE states, a specific timing sensitivity exists between
1088           the retiring WFI/WFE instructions and the newly issued subsequent
1089           instructions.  This sensitivity can result in a CPU hang scenario.
1090           Workaround:
1091           The software must insert either a Data Synchronization Barrier (DSB)
1092           or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1093           instruction
1094
1095 config ARM_ERRATA_326103
1096         bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1097         depends on CPU_V6
1098         help
1099           Executing a SWP instruction to read-only memory does not set bit 11
1100           of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1101           treat the access as a read, preventing a COW from occurring and
1102           causing the faulting task to livelock.
1103
1104 config ARM_ERRATA_411920
1105         bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1106         depends on CPU_V6 || CPU_V6K
1107         help
1108           Invalidation of the Instruction Cache operation can
1109           fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1110           It does not affect the MPCore. This option enables the ARM Ltd.
1111           recommended workaround.
1112
1113 config ARM_ERRATA_430973
1114         bool "ARM errata: Stale prediction on replaced interworking branch"
1115         depends on CPU_V7
1116         help
1117           This option enables the workaround for the 430973 Cortex-A8
1118           (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1119           interworking branch is replaced with another code sequence at the
1120           same virtual address, whether due to self-modifying code or virtual
1121           to physical address re-mapping, Cortex-A8 does not recover from the
1122           stale interworking branch prediction. This results in Cortex-A8
1123           executing the new code sequence in the incorrect ARM or Thumb state.
1124           The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1125           and also flushes the branch target cache at every context switch.
1126           Note that setting specific bits in the ACTLR register may not be
1127           available in non-secure mode.
1128
1129 config ARM_ERRATA_458693
1130         bool "ARM errata: Processor deadlock when a false hazard is created"
1131         depends on CPU_V7
1132         depends on !ARCH_MULTIPLATFORM
1133         help
1134           This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1135           erratum. For very specific sequences of memory operations, it is
1136           possible for a hazard condition intended for a cache line to instead
1137           be incorrectly associated with a different cache line. This false
1138           hazard might then cause a processor deadlock. The workaround enables
1139           the L1 caching of the NEON accesses and disables the PLD instruction
1140           in the ACTLR register. Note that setting specific bits in the ACTLR
1141           register may not be available in non-secure mode.
1142
1143 config ARM_ERRATA_460075
1144         bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1145         depends on CPU_V7
1146         depends on !ARCH_MULTIPLATFORM
1147         help
1148           This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1149           erratum. Any asynchronous access to the L2 cache may encounter a
1150           situation in which recent store transactions to the L2 cache are lost
1151           and overwritten with stale memory contents from external memory. The
1152           workaround disables the write-allocate mode for the L2 cache via the
1153           ACTLR register. Note that setting specific bits in the ACTLR register
1154           may not be available in non-secure mode.
1155
1156 config ARM_ERRATA_742230
1157         bool "ARM errata: DMB operation may be faulty"
1158         depends on CPU_V7 && SMP
1159         depends on !ARCH_MULTIPLATFORM
1160         help
1161           This option enables the workaround for the 742230 Cortex-A9
1162           (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1163           between two write operations may not ensure the correct visibility
1164           ordering of the two writes. This workaround sets a specific bit in
1165           the diagnostic register of the Cortex-A9 which causes the DMB
1166           instruction to behave as a DSB, ensuring the correct behaviour of
1167           the two writes.
1168
1169 config ARM_ERRATA_742231
1170         bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1171         depends on CPU_V7 && SMP
1172         depends on !ARCH_MULTIPLATFORM
1173         help
1174           This option enables the workaround for the 742231 Cortex-A9
1175           (r2p0..r2p2) erratum. Under certain conditions, specific to the
1176           Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1177           accessing some data located in the same cache line, may get corrupted
1178           data due to bad handling of the address hazard when the line gets
1179           replaced from one of the CPUs at the same time as another CPU is
1180           accessing it. This workaround sets specific bits in the diagnostic
1181           register of the Cortex-A9 which reduces the linefill issuing
1182           capabilities of the processor.
1183
1184 config PL310_ERRATA_588369
1185         bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1186         depends on CACHE_L2X0
1187         help
1188            The PL310 L2 cache controller implements three types of Clean &
1189            Invalidate maintenance operations: by Physical Address
1190            (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1191            They are architecturally defined to behave as the execution of a
1192            clean operation followed immediately by an invalidate operation,
1193            both performing to the same memory location. This functionality
1194            is not correctly implemented in PL310 as clean lines are not
1195            invalidated as a result of these operations.
1196
1197 config ARM_ERRATA_643719
1198         bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1199         depends on CPU_V7 && SMP
1200         help
1201           This option enables the workaround for the 643719 Cortex-A9 (prior to
1202           r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1203           register returns zero when it should return one. The workaround
1204           corrects this value, ensuring cache maintenance operations which use
1205           it behave as intended and avoiding data corruption.
1206
1207 config ARM_ERRATA_720789
1208         bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1209         depends on CPU_V7
1210         help
1211           This option enables the workaround for the 720789 Cortex-A9 (prior to
1212           r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1213           broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1214           As a consequence of this erratum, some TLB entries which should be
1215           invalidated are not, resulting in an incoherency in the system page
1216           tables. The workaround changes the TLB flushing routines to invalidate
1217           entries regardless of the ASID.
1218
1219 config PL310_ERRATA_727915
1220         bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1221         depends on CACHE_L2X0
1222         help
1223           PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1224           operation (offset 0x7FC). This operation runs in background so that
1225           PL310 can handle normal accesses while it is in progress. Under very
1226           rare circumstances, due to this erratum, write data can be lost when
1227           PL310 treats a cacheable write transaction during a Clean &
1228           Invalidate by Way operation.
1229
1230 config ARM_ERRATA_743622
1231         bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1232         depends on CPU_V7
1233         depends on !ARCH_MULTIPLATFORM
1234         help
1235           This option enables the workaround for the 743622 Cortex-A9
1236           (r2p*) erratum. Under very rare conditions, a faulty
1237           optimisation in the Cortex-A9 Store Buffer may lead to data
1238           corruption. This workaround sets a specific bit in the diagnostic
1239           register of the Cortex-A9 which disables the Store Buffer
1240           optimisation, preventing the defect from occurring. This has no
1241           visible impact on the overall performance or power consumption of the
1242           processor.
1243
1244 config ARM_ERRATA_751472
1245         bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1246         depends on CPU_V7
1247         depends on !ARCH_MULTIPLATFORM
1248         help
1249           This option enables the workaround for the 751472 Cortex-A9 (prior
1250           to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1251           completion of a following broadcasted operation if the second
1252           operation is received by a CPU before the ICIALLUIS has completed,
1253           potentially leading to corrupted entries in the cache or TLB.
1254
1255 config PL310_ERRATA_753970
1256         bool "PL310 errata: cache sync operation may be faulty"
1257         depends on CACHE_PL310
1258         help
1259           This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1260
1261           Under some condition the effect of cache sync operation on
1262           the store buffer still remains when the operation completes.
1263           This means that the store buffer is always asked to drain and
1264           this prevents it from merging any further writes. The workaround
1265           is to replace the normal offset of cache sync operation (0x730)
1266           by another offset targeting an unmapped PL310 register 0x740.
1267           This has the same effect as the cache sync operation: store buffer
1268           drain and waiting for all buffers empty.
1269
1270 config ARM_ERRATA_754322
1271         bool "ARM errata: possible faulty MMU translations following an ASID switch"
1272         depends on CPU_V7
1273         help
1274           This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1275           r3p*) erratum. A speculative memory access may cause a page table walk
1276           which starts prior to an ASID switch but completes afterwards. This
1277           can populate the micro-TLB with a stale entry which may be hit with
1278           the new ASID. This workaround places two dsb instructions in the mm
1279           switching code so that no page table walks can cross the ASID switch.
1280
1281 config ARM_ERRATA_754327
1282         bool "ARM errata: no automatic Store Buffer drain"
1283         depends on CPU_V7 && SMP
1284         help
1285           This option enables the workaround for the 754327 Cortex-A9 (prior to
1286           r2p0) erratum. The Store Buffer does not have any automatic draining
1287           mechanism and therefore a livelock may occur if an external agent
1288           continuously polls a memory location waiting to observe an update.
1289           This workaround defines cpu_relax() as smp_mb(), preventing correctly
1290           written polling loops from denying visibility of updates to memory.
1291
1292 config ARM_ERRATA_364296
1293         bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1294         depends on CPU_V6
1295         help
1296           This options enables the workaround for the 364296 ARM1136
1297           r0p2 erratum (possible cache data corruption with
1298           hit-under-miss enabled). It sets the undocumented bit 31 in
1299           the auxiliary control register and the FI bit in the control
1300           register, thus disabling hit-under-miss without putting the
1301           processor into full low interrupt latency mode. ARM11MPCore
1302           is not affected.
1303
1304 config ARM_ERRATA_764369
1305         bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1306         depends on CPU_V7 && SMP
1307         help
1308           This option enables the workaround for erratum 764369
1309           affecting Cortex-A9 MPCore with two or more processors (all
1310           current revisions). Under certain timing circumstances, a data
1311           cache line maintenance operation by MVA targeting an Inner
1312           Shareable memory region may fail to proceed up to either the
1313           Point of Coherency or to the Point of Unification of the
1314           system. This workaround adds a DSB instruction before the
1315           relevant cache maintenance functions and sets a specific bit
1316           in the diagnostic control register of the SCU.
1317
1318 config PL310_ERRATA_769419
1319         bool "PL310 errata: no automatic Store Buffer drain"
1320         depends on CACHE_L2X0
1321         help
1322           On revisions of the PL310 prior to r3p2, the Store Buffer does
1323           not automatically drain. This can cause normal, non-cacheable
1324           writes to be retained when the memory system is idle, leading
1325           to suboptimal I/O performance for drivers using coherent DMA.
1326           This option adds a write barrier to the cpu_idle loop so that,
1327           on systems with an outer cache, the store buffer is drained
1328           explicitly.
1329
1330 config ARM_ERRATA_775420
1331        bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1332        depends on CPU_V7
1333        help
1334          This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1335          r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1336          operation aborts with MMU exception, it might cause the processor
1337          to deadlock. This workaround puts DSB before executing ISB if
1338          an abort may occur on cache maintenance.
1339
1340 config ARM_ERRATA_798181
1341         bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1342         depends on CPU_V7 && SMP
1343         help
1344           On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1345           adequately shooting down all use of the old entries. This
1346           option enables the Linux kernel workaround for this erratum
1347           which sends an IPI to the CPUs that are running the same ASID
1348           as the one being invalidated.
1349
1350 config ARM_ERRATA_773022
1351         bool "ARM errata: incorrect instructions may be executed from loop buffer"
1352         depends on CPU_V7
1353         help
1354           This option enables the workaround for the 773022 Cortex-A15
1355           (up to r0p4) erratum. In certain rare sequences of code, the
1356           loop buffer may deliver incorrect instructions. This
1357           workaround disables the loop buffer to avoid the erratum.
1358
1359 endmenu
1360
1361 source "arch/arm/common/Kconfig"
1362
1363 menu "Bus support"
1364
1365 config ARM_AMBA
1366         bool
1367
1368 config ISA
1369         bool
1370         help
1371           Find out whether you have ISA slots on your motherboard.  ISA is the
1372           name of a bus system, i.e. the way the CPU talks to the other stuff
1373           inside your box.  Other bus systems are PCI, EISA, MicroChannel
1374           (MCA) or VESA.  ISA is an older system, now being displaced by PCI;
1375           newer boards don't support it.  If you have ISA, say Y, otherwise N.
1376
1377 # Select ISA DMA controller support
1378 config ISA_DMA
1379         bool
1380         select ISA_DMA_API
1381
1382 # Select ISA DMA interface
1383 config ISA_DMA_API
1384         bool
1385
1386 config PCI
1387         bool "PCI support" if MIGHT_HAVE_PCI
1388         help
1389           Find out whether you have a PCI motherboard. PCI is the name of a
1390           bus system, i.e. the way the CPU talks to the other stuff inside
1391           your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1392           VESA. If you have PCI, say Y, otherwise N.
1393
1394 config PCI_DOMAINS
1395         bool
1396         depends on PCI
1397
1398 config PCI_NANOENGINE
1399         bool "BSE nanoEngine PCI support"
1400         depends on SA1100_NANOENGINE
1401         help
1402           Enable PCI on the BSE nanoEngine board.
1403
1404 config PCI_SYSCALL
1405         def_bool PCI
1406
1407 config PCI_HOST_ITE8152
1408         bool
1409         depends on PCI && MACH_ARMCORE
1410         default y
1411         select DMABOUNCE
1412
1413 source "drivers/pci/Kconfig"
1414 source "drivers/pci/pcie/Kconfig"
1415
1416 source "drivers/pcmcia/Kconfig"
1417
1418 endmenu
1419
1420 menu "Kernel Features"
1421
1422 config HAVE_SMP
1423         bool
1424         help
1425           This option should be selected by machines which have an SMP-
1426           capable CPU.
1427
1428           The only effect of this option is to make the SMP-related
1429           options available to the user for configuration.
1430
1431 config SMP
1432         bool "Symmetric Multi-Processing"
1433         depends on CPU_V6K || CPU_V7
1434         depends on GENERIC_CLOCKEVENTS
1435         depends on HAVE_SMP
1436         depends on MMU || ARM_MPU
1437         select USE_GENERIC_SMP_HELPERS
1438         help
1439           This enables support for systems with more than one CPU. If you have
1440           a system with only one CPU, like most personal computers, say N. If
1441           you have a system with more than one CPU, say Y.
1442
1443           If you say N here, the kernel will run on single and multiprocessor
1444           machines, but will use only one CPU of a multiprocessor machine. If
1445           you say Y here, the kernel will run on many, but not all, single
1446           processor machines. On a single processor machine, the kernel will
1447           run faster if you say N here.
1448
1449           See also <file:Documentation/x86/i386/IO-APIC.txt>,
1450           <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1451           <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1452
1453           If you don't know what to do here, say N.
1454
1455 config SMP_ON_UP
1456         bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1457         depends on SMP && !XIP_KERNEL && MMU
1458         default y
1459         help
1460           SMP kernels contain instructions which fail on non-SMP processors.
1461           Enabling this option allows the kernel to modify itself to make
1462           these instructions safe.  Disabling it allows about 1K of space
1463           savings.
1464
1465           If you don't know what to do here, say Y.
1466
1467 config ARM_CPU_TOPOLOGY
1468         bool "Support cpu topology definition"
1469         depends on SMP && CPU_V7
1470         default y
1471         help
1472           Support ARM cpu topology definition. The MPIDR register defines
1473           affinity between processors which is then used to describe the cpu
1474           topology of an ARM System.
1475
1476 config SCHED_MC
1477         bool "Multi-core scheduler support"
1478         depends on ARM_CPU_TOPOLOGY
1479         help
1480           Multi-core scheduler support improves the CPU scheduler's decision
1481           making when dealing with multi-core CPU chips at a cost of slightly
1482           increased overhead in some places. If unsure say N here.
1483
1484 config SCHED_SMT
1485         bool "SMT scheduler support"
1486         depends on ARM_CPU_TOPOLOGY
1487         help
1488           Improves the CPU scheduler's decision making when dealing with
1489           MultiThreading at a cost of slightly increased overhead in some
1490           places. If unsure say N here.
1491
1492 config HAVE_ARM_SCU
1493         bool
1494         help
1495           This option enables support for the ARM system coherency unit
1496
1497 config HAVE_ARM_ARCH_TIMER
1498         bool "Architected timer support"
1499         depends on CPU_V7
1500         select ARM_ARCH_TIMER
1501         help
1502           This option enables support for the ARM architected timer
1503
1504 config HAVE_ARM_TWD
1505         bool
1506         depends on SMP
1507         select CLKSRC_OF if OF
1508         help
1509           This options enables support for the ARM timer and watchdog unit
1510
1511 config MCPM
1512         bool "Multi-Cluster Power Management"
1513         depends on CPU_V7 && SMP
1514         help
1515           This option provides the common power management infrastructure
1516           for (multi-)cluster based systems, such as big.LITTLE based
1517           systems.
1518
1519 choice
1520         prompt "Memory split"
1521         default VMSPLIT_3G
1522         help
1523           Select the desired split between kernel and user memory.
1524
1525           If you are not absolutely sure what you are doing, leave this
1526           option alone!
1527
1528         config VMSPLIT_3G
1529                 bool "3G/1G user/kernel split"
1530         config VMSPLIT_2G
1531                 bool "2G/2G user/kernel split"
1532         config VMSPLIT_1G
1533                 bool "1G/3G user/kernel split"
1534 endchoice
1535
1536 config PAGE_OFFSET
1537         hex
1538         default 0x40000000 if VMSPLIT_1G
1539         default 0x80000000 if VMSPLIT_2G
1540         default 0xC0000000
1541
1542 config NR_CPUS
1543         int "Maximum number of CPUs (2-32)"
1544         range 2 32
1545         depends on SMP
1546         default "4"
1547
1548 config HOTPLUG_CPU
1549         bool "Support for hot-pluggable CPUs"
1550         depends on SMP
1551         help
1552           Say Y here to experiment with turning CPUs off and on.  CPUs
1553           can be controlled through /sys/devices/system/cpu.
1554
1555 config ARM_PSCI
1556         bool "Support for the ARM Power State Coordination Interface (PSCI)"
1557         depends on CPU_V7
1558         help
1559           Say Y here if you want Linux to communicate with system firmware
1560           implementing the PSCI specification for CPU-centric power
1561           management operations described in ARM document number ARM DEN
1562           0022A ("Power State Coordination Interface System Software on
1563           ARM processors").
1564
1565 # The GPIO number here must be sorted by descending number. In case of
1566 # a multiplatform kernel, we just want the highest value required by the
1567 # selected platforms.
1568 config ARCH_NR_GPIO
1569         int
1570         default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1571         default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX
1572         default 392 if ARCH_U8500
1573         default 352 if ARCH_VT8500
1574         default 288 if ARCH_SUNXI
1575         default 264 if MACH_H4700
1576         default 0
1577         help
1578           Maximum number of GPIOs in the system.
1579
1580           If unsure, leave the default value.
1581
1582 source kernel/Kconfig.preempt
1583
1584 config HZ_FIXED
1585         int
1586         default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1587                 ARCH_S5PV210 || ARCH_EXYNOS4
1588         default AT91_TIMER_HZ if ARCH_AT91
1589         default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1590         default 0
1591
1592 choice
1593         depends on HZ_FIXED = 0
1594         prompt "Timer frequency"
1595
1596 config HZ_100
1597         bool "100 Hz"
1598
1599 config HZ_200
1600         bool "200 Hz"
1601
1602 config HZ_250
1603         bool "250 Hz"
1604
1605 config HZ_300
1606         bool "300 Hz"
1607
1608 config HZ_500
1609         bool "500 Hz"
1610
1611 config HZ_1000
1612         bool "1000 Hz"
1613
1614 endchoice
1615
1616 config HZ
1617         int
1618         default HZ_FIXED if HZ_FIXED != 0
1619         default 100 if HZ_100
1620         default 200 if HZ_200
1621         default 250 if HZ_250
1622         default 300 if HZ_300
1623         default 500 if HZ_500
1624         default 1000
1625
1626 config SCHED_HRTICK
1627         def_bool HIGH_RES_TIMERS
1628
1629 config SCHED_HRTICK
1630         def_bool HIGH_RES_TIMERS
1631
1632 config THUMB2_KERNEL
1633         bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1634         depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1635         default y if CPU_THUMBONLY
1636         select AEABI
1637         select ARM_ASM_UNIFIED
1638         select ARM_UNWIND
1639         help
1640           By enabling this option, the kernel will be compiled in
1641           Thumb-2 mode. A compiler/assembler that understand the unified
1642           ARM-Thumb syntax is needed.
1643
1644           If unsure, say N.
1645
1646 config THUMB2_AVOID_R_ARM_THM_JUMP11
1647         bool "Work around buggy Thumb-2 short branch relocations in gas"
1648         depends on THUMB2_KERNEL && MODULES
1649         default y
1650         help
1651           Various binutils versions can resolve Thumb-2 branches to
1652           locally-defined, preemptible global symbols as short-range "b.n"
1653           branch instructions.
1654
1655           This is a problem, because there's no guarantee the final
1656           destination of the symbol, or any candidate locations for a
1657           trampoline, are within range of the branch.  For this reason, the
1658           kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1659           relocation in modules at all, and it makes little sense to add
1660           support.
1661
1662           The symptom is that the kernel fails with an "unsupported
1663           relocation" error when loading some modules.
1664
1665           Until fixed tools are available, passing
1666           -fno-optimize-sibling-calls to gcc should prevent gcc generating
1667           code which hits this problem, at the cost of a bit of extra runtime
1668           stack usage in some cases.
1669
1670           The problem is described in more detail at:
1671               https://bugs.launchpad.net/binutils-linaro/+bug/725126
1672
1673           Only Thumb-2 kernels are affected.
1674
1675           Unless you are sure your tools don't have this problem, say Y.
1676
1677 config ARM_ASM_UNIFIED
1678         bool
1679
1680 config AEABI
1681         bool "Use the ARM EABI to compile the kernel"
1682         help
1683           This option allows for the kernel to be compiled using the latest
1684           ARM ABI (aka EABI).  This is only useful if you are using a user
1685           space environment that is also compiled with EABI.
1686
1687           Since there are major incompatibilities between the legacy ABI and
1688           EABI, especially with regard to structure member alignment, this
1689           option also changes the kernel syscall calling convention to
1690           disambiguate both ABIs and allow for backward compatibility support
1691           (selected with CONFIG_OABI_COMPAT).
1692
1693           To use this you need GCC version 4.0.0 or later.
1694
1695 config OABI_COMPAT
1696         bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1697         depends on AEABI && !THUMB2_KERNEL
1698         default y
1699         help
1700           This option preserves the old syscall interface along with the
1701           new (ARM EABI) one. It also provides a compatibility layer to
1702           intercept syscalls that have structure arguments which layout
1703           in memory differs between the legacy ABI and the new ARM EABI
1704           (only for non "thumb" binaries). This option adds a tiny
1705           overhead to all syscalls and produces a slightly larger kernel.
1706           If you know you'll be using only pure EABI user space then you
1707           can say N here. If this option is not selected and you attempt
1708           to execute a legacy ABI binary then the result will be
1709           UNPREDICTABLE (in fact it can be predicted that it won't work
1710           at all). If in doubt say Y.
1711
1712 config ARCH_HAS_HOLES_MEMORYMODEL
1713         bool
1714
1715 config ARCH_SPARSEMEM_ENABLE
1716         bool
1717
1718 config ARCH_SPARSEMEM_DEFAULT
1719         def_bool ARCH_SPARSEMEM_ENABLE
1720
1721 config ARCH_SELECT_MEMORY_MODEL
1722         def_bool ARCH_SPARSEMEM_ENABLE
1723
1724 config HAVE_ARCH_PFN_VALID
1725         def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1726
1727 config HIGHMEM
1728         bool "High Memory Support"
1729         depends on MMU
1730         help
1731           The address space of ARM processors is only 4 Gigabytes large
1732           and it has to accommodate user address space, kernel address
1733           space as well as some memory mapped IO. That means that, if you
1734           have a large amount of physical memory and/or IO, not all of the
1735           memory can be "permanently mapped" by the kernel. The physical
1736           memory that is not permanently mapped is called "high memory".
1737
1738           Depending on the selected kernel/user memory split, minimum
1739           vmalloc space and actual amount of RAM, you may not need this
1740           option which should result in a slightly faster kernel.
1741
1742           If unsure, say n.
1743
1744 config HIGHPTE
1745         bool "Allocate 2nd-level pagetables from highmem"
1746         depends on HIGHMEM
1747
1748 config HW_PERF_EVENTS
1749         bool "Enable hardware performance counter support for perf events"
1750         depends on PERF_EVENTS
1751         default y
1752         help
1753           Enable hardware performance counter support for perf events. If
1754           disabled, perf events will use software events only.
1755
1756 config SYS_SUPPORTS_HUGETLBFS
1757        def_bool y
1758        depends on ARM_LPAE
1759
1760 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1761        def_bool y
1762        depends on ARM_LPAE
1763
1764 config ARCH_WANT_GENERAL_HUGETLB
1765         def_bool y
1766
1767 source "mm/Kconfig"
1768
1769 config FORCE_MAX_ZONEORDER
1770         int "Maximum zone order" if ARCH_SHMOBILE
1771         range 11 64 if ARCH_SHMOBILE
1772         default "12" if SOC_AM33XX
1773         default "9" if SA1111
1774         default "11"
1775         help
1776           The kernel memory allocator divides physically contiguous memory
1777           blocks into "zones", where each zone is a power of two number of
1778           pages.  This option selects the largest power of two that the kernel
1779           keeps in the memory allocator.  If you need to allocate very large
1780           blocks of physically contiguous memory, then you may need to
1781           increase this value.
1782
1783           This config option is actually maximum order plus one. For example,
1784           a value of 11 means that the largest free memory block is 2^10 pages.
1785
1786 config ALIGNMENT_TRAP
1787         bool
1788         depends on CPU_CP15_MMU
1789         default y if !ARCH_EBSA110
1790         select HAVE_PROC_CPU if PROC_FS
1791         help
1792           ARM processors cannot fetch/store information which is not
1793           naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1794           address divisible by 4. On 32-bit ARM processors, these non-aligned
1795           fetch/store instructions will be emulated in software if you say
1796           here, which has a severe performance impact. This is necessary for
1797           correct operation of some network protocols. With an IP-only
1798           configuration it is safe to say N, otherwise say Y.
1799
1800 config UACCESS_WITH_MEMCPY
1801         bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1802         depends on MMU
1803         default y if CPU_FEROCEON
1804         help
1805           Implement faster copy_to_user and clear_user methods for CPU
1806           cores where a 8-word STM instruction give significantly higher
1807           memory write throughput than a sequence of individual 32bit stores.
1808
1809           A possible side effect is a slight increase in scheduling latency
1810           between threads sharing the same address space if they invoke
1811           such copy operations with large buffers.
1812
1813           However, if the CPU data cache is using a write-allocate mode,
1814           this option is unlikely to provide any performance gain.
1815
1816 config SECCOMP
1817         bool
1818         prompt "Enable seccomp to safely compute untrusted bytecode"
1819         ---help---
1820           This kernel feature is useful for number crunching applications
1821           that may need to compute untrusted bytecode during their
1822           execution. By using pipes or other transports made available to
1823           the process as file descriptors supporting the read/write
1824           syscalls, it's possible to isolate those applications in
1825           their own address space using seccomp. Once seccomp is
1826           enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1827           and the task is only allowed to execute a few safe syscalls
1828           defined by each seccomp mode.
1829
1830 config CC_STACKPROTECTOR
1831         bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1832         help
1833           This option turns on the -fstack-protector GCC feature. This
1834           feature puts, at the beginning of functions, a canary value on
1835           the stack just before the return address, and validates
1836           the value just before actually returning.  Stack based buffer
1837           overflows (that need to overwrite this return address) now also
1838           overwrite the canary, which gets detected and the attack is then
1839           neutralized via a kernel panic.
1840           This feature requires gcc version 4.2 or above.
1841
1842 config XEN_DOM0
1843         def_bool y
1844         depends on XEN
1845
1846 config XEN
1847         bool "Xen guest support on ARM (EXPERIMENTAL)"
1848         depends on ARM && AEABI && OF
1849         depends on CPU_V7 && !CPU_V6
1850         depends on !GENERIC_ATOMIC64
1851         select ARM_PSCI
1852         help
1853           Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1854
1855 endmenu
1856
1857 menu "Boot options"
1858
1859 config USE_OF
1860         bool "Flattened Device Tree support"
1861         select IRQ_DOMAIN
1862         select OF
1863         select OF_EARLY_FLATTREE
1864         help
1865           Include support for flattened device tree machine descriptions.
1866
1867 config ATAGS
1868         bool "Support for the traditional ATAGS boot data passing" if USE_OF
1869         default y
1870         help
1871           This is the traditional way of passing data to the kernel at boot
1872           time. If you are solely relying on the flattened device tree (or
1873           the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1874           to remove ATAGS support from your kernel binary.  If unsure,
1875           leave this to y.
1876
1877 config DEPRECATED_PARAM_STRUCT
1878         bool "Provide old way to pass kernel parameters"
1879         depends on ATAGS
1880         help
1881           This was deprecated in 2001 and announced to live on for 5 years.
1882           Some old boot loaders still use this way.
1883
1884 # Compressed boot loader in ROM.  Yes, we really want to ask about
1885 # TEXT and BSS so we preserve their values in the config files.
1886 config ZBOOT_ROM_TEXT
1887         hex "Compressed ROM boot loader base address"
1888         default "0"
1889         help
1890           The physical address at which the ROM-able zImage is to be
1891           placed in the target.  Platforms which normally make use of
1892           ROM-able zImage formats normally set this to a suitable
1893           value in their defconfig file.
1894
1895           If ZBOOT_ROM is not enabled, this has no effect.
1896
1897 config ZBOOT_ROM_BSS
1898         hex "Compressed ROM boot loader BSS address"
1899         default "0"
1900         help
1901           The base address of an area of read/write memory in the target
1902           for the ROM-able zImage which must be available while the
1903           decompressor is running. It must be large enough to hold the
1904           entire decompressed kernel plus an additional 128 KiB.
1905           Platforms which normally make use of ROM-able zImage formats
1906           normally set this to a suitable value in their defconfig file.
1907
1908           If ZBOOT_ROM is not enabled, this has no effect.
1909
1910 config ZBOOT_ROM
1911         bool "Compressed boot loader in ROM/flash"
1912         depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1913         help
1914           Say Y here if you intend to execute your compressed kernel image
1915           (zImage) directly from ROM or flash.  If unsure, say N.
1916
1917 choice
1918         prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1919         depends on ZBOOT_ROM && ARCH_SH7372
1920         default ZBOOT_ROM_NONE
1921         help
1922           Include experimental SD/MMC loading code in the ROM-able zImage.
1923           With this enabled it is possible to write the ROM-able zImage
1924           kernel image to an MMC or SD card and boot the kernel straight
1925           from the reset vector. At reset the processor Mask ROM will load
1926           the first part of the ROM-able zImage which in turn loads the
1927           rest the kernel image to RAM.
1928
1929 config ZBOOT_ROM_NONE
1930         bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1931         help
1932           Do not load image from SD or MMC
1933
1934 config ZBOOT_ROM_MMCIF
1935         bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1936         help
1937           Load image from MMCIF hardware block.
1938
1939 config ZBOOT_ROM_SH_MOBILE_SDHI
1940         bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1941         help
1942           Load image from SDHI hardware block
1943
1944 endchoice
1945
1946 config ARM_APPENDED_DTB
1947         bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1948         depends on OF && !ZBOOT_ROM
1949         help
1950           With this option, the boot code will look for a device tree binary
1951           (DTB) appended to zImage
1952           (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1953
1954           This is meant as a backward compatibility convenience for those
1955           systems with a bootloader that can't be upgraded to accommodate
1956           the documented boot protocol using a device tree.
1957
1958           Beware that there is very little in terms of protection against
1959           this option being confused by leftover garbage in memory that might
1960           look like a DTB header after a reboot if no actual DTB is appended
1961           to zImage.  Do not leave this option active in a production kernel
1962           if you don't intend to always append a DTB.  Proper passing of the
1963           location into r2 of a bootloader provided DTB is always preferable
1964           to this option.
1965
1966 config ARM_ATAG_DTB_COMPAT
1967         bool "Supplement the appended DTB with traditional ATAG information"
1968         depends on ARM_APPENDED_DTB
1969         help
1970           Some old bootloaders can't be updated to a DTB capable one, yet
1971           they provide ATAGs with memory configuration, the ramdisk address,
1972           the kernel cmdline string, etc.  Such information is dynamically
1973           provided by the bootloader and can't always be stored in a static
1974           DTB.  To allow a device tree enabled kernel to be used with such
1975           bootloaders, this option allows zImage to extract the information
1976           from the ATAG list and store it at run time into the appended DTB.
1977
1978 choice
1979         prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1980         default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1981
1982 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1983         bool "Use bootloader kernel arguments if available"
1984         help
1985           Uses the command-line options passed by the boot loader instead of
1986           the device tree bootargs property. If the boot loader doesn't provide
1987           any, the device tree bootargs property will be used.
1988
1989 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1990         bool "Extend with bootloader kernel arguments"
1991         help
1992           The command-line arguments provided by the boot loader will be
1993           appended to the the device tree bootargs property.
1994
1995 endchoice
1996
1997 config CMDLINE
1998         string "Default kernel command string"
1999         default ""
2000         help
2001           On some architectures (EBSA110 and CATS), there is currently no way
2002           for the boot loader to pass arguments to the kernel. For these
2003           architectures, you should supply some command-line options at build
2004           time by entering them here. As a minimum, you should specify the
2005           memory size and the root device (e.g., mem=64M root=/dev/nfs).
2006
2007 choice
2008         prompt "Kernel command line type" if CMDLINE != ""
2009         default CMDLINE_FROM_BOOTLOADER
2010         depends on ATAGS
2011
2012 config CMDLINE_FROM_BOOTLOADER
2013         bool "Use bootloader kernel arguments if available"
2014         help
2015           Uses the command-line options passed by the boot loader. If
2016           the boot loader doesn't provide any, the default kernel command
2017           string provided in CMDLINE will be used.
2018
2019 config CMDLINE_EXTEND
2020         bool "Extend bootloader kernel arguments"
2021         help
2022           The command-line arguments provided by the boot loader will be
2023           appended to the default kernel command string.
2024
2025 config CMDLINE_FORCE
2026         bool "Always use the default kernel command string"
2027         help
2028           Always use the default kernel command string, even if the boot
2029           loader passes other arguments to the kernel.
2030           This is useful if you cannot or don't want to change the
2031           command-line options your boot loader passes to the kernel.
2032 endchoice
2033
2034 config XIP_KERNEL
2035         bool "Kernel Execute-In-Place from ROM"
2036         depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2037         help
2038           Execute-In-Place allows the kernel to run from non-volatile storage
2039           directly addressable by the CPU, such as NOR flash. This saves RAM
2040           space since the text section of the kernel is not loaded from flash
2041           to RAM.  Read-write sections, such as the data section and stack,
2042           are still copied to RAM.  The XIP kernel is not compressed since
2043           it has to run directly from flash, so it will take more space to
2044           store it.  The flash address used to link the kernel object files,
2045           and for storing it, is configuration dependent. Therefore, if you
2046           say Y here, you must know the proper physical address where to
2047           store the kernel image depending on your own flash memory usage.
2048
2049           Also note that the make target becomes "make xipImage" rather than
2050           "make zImage" or "make Image".  The final kernel binary to put in
2051           ROM memory will be arch/arm/boot/xipImage.
2052
2053           If unsure, say N.
2054
2055 config XIP_PHYS_ADDR
2056         hex "XIP Kernel Physical Location"
2057         depends on XIP_KERNEL
2058         default "0x00080000"
2059         help
2060           This is the physical address in your flash memory the kernel will
2061           be linked for and stored to.  This address is dependent on your
2062           own flash usage.
2063
2064 config KEXEC
2065         bool "Kexec system call (EXPERIMENTAL)"
2066         depends on (!SMP || PM_SLEEP_SMP)
2067         help
2068           kexec is a system call that implements the ability to shutdown your
2069           current kernel, and to start another kernel.  It is like a reboot
2070           but it is independent of the system firmware.   And like a reboot
2071           you can start any kernel with it, not just Linux.
2072
2073           It is an ongoing process to be certain the hardware in a machine
2074           is properly shutdown, so do not be surprised if this code does not
2075           initially work for you.
2076
2077 config ATAGS_PROC
2078         bool "Export atags in procfs"
2079         depends on ATAGS && KEXEC
2080         default y
2081         help
2082           Should the atags used to boot the kernel be exported in an "atags"
2083           file in procfs. Useful with kexec.
2084
2085 config CRASH_DUMP
2086         bool "Build kdump crash kernel (EXPERIMENTAL)"
2087         help
2088           Generate crash dump after being started by kexec. This should
2089           be normally only set in special crash dump kernels which are
2090           loaded in the main kernel with kexec-tools into a specially
2091           reserved region and then later executed after a crash by
2092           kdump/kexec. The crash dump kernel must be compiled to a
2093           memory address not used by the main kernel
2094
2095           For more details see Documentation/kdump/kdump.txt
2096
2097 config AUTO_ZRELADDR
2098         bool "Auto calculation of the decompressed kernel image address"
2099         depends on !ZBOOT_ROM
2100         help
2101           ZRELADDR is the physical address where the decompressed kernel
2102           image will be placed. If AUTO_ZRELADDR is selected, the address
2103           will be determined at run-time by masking the current IP with
2104           0xf8000000. This assumes the zImage being placed in the first 128MB
2105           from start of memory.
2106
2107 endmenu
2108
2109 menu "CPU Power Management"
2110
2111 if ARCH_HAS_CPUFREQ
2112 source "drivers/cpufreq/Kconfig"
2113 endif
2114
2115 source "drivers/cpuidle/Kconfig"
2116
2117 endmenu
2118
2119 menu "Floating point emulation"
2120
2121 comment "At least one emulation must be selected"
2122
2123 config FPE_NWFPE
2124         bool "NWFPE math emulation"
2125         depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2126         ---help---
2127           Say Y to include the NWFPE floating point emulator in the kernel.
2128           This is necessary to run most binaries. Linux does not currently
2129           support floating point hardware so you need to say Y here even if
2130           your machine has an FPA or floating point co-processor podule.
2131
2132           You may say N here if you are going to load the Acorn FPEmulator
2133           early in the bootup.
2134
2135 config FPE_NWFPE_XP
2136         bool "Support extended precision"
2137         depends on FPE_NWFPE
2138         help
2139           Say Y to include 80-bit support in the kernel floating-point
2140           emulator.  Otherwise, only 32 and 64-bit support is compiled in.
2141           Note that gcc does not generate 80-bit operations by default,
2142           so in most cases this option only enlarges the size of the
2143           floating point emulator without any good reason.
2144
2145           You almost surely want to say N here.
2146
2147 config FPE_FASTFPE
2148         bool "FastFPE math emulation (EXPERIMENTAL)"
2149         depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2150         ---help---
2151           Say Y here to include the FAST floating point emulator in the kernel.
2152           This is an experimental much faster emulator which now also has full
2153           precision for the mantissa.  It does not support any exceptions.
2154           It is very simple, and approximately 3-6 times faster than NWFPE.
2155
2156           It should be sufficient for most programs.  It may be not suitable
2157           for scientific calculations, but you have to check this for yourself.
2158           If you do not feel you need a faster FP emulation you should better
2159           choose NWFPE.
2160
2161 config VFP
2162         bool "VFP-format floating point maths"
2163         depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2164         help
2165           Say Y to include VFP support code in the kernel. This is needed
2166           if your hardware includes a VFP unit.
2167
2168           Please see <file:Documentation/arm/VFP/release-notes.txt> for
2169           release notes and additional status information.
2170
2171           Say N if your target does not have VFP hardware.
2172
2173 config VFPv3
2174         bool
2175         depends on VFP
2176         default y if CPU_V7
2177
2178 config NEON
2179         bool "Advanced SIMD (NEON) Extension support"
2180         depends on VFPv3 && CPU_V7
2181         help
2182           Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2183           Extension.
2184
2185 config KERNEL_MODE_NEON
2186         bool "Support for NEON in kernel mode"
2187         depends on NEON && AEABI
2188         help
2189           Say Y to include support for NEON in kernel mode.
2190
2191 endmenu
2192
2193 menu "Userspace binary formats"
2194
2195 source "fs/Kconfig.binfmt"
2196
2197 config ARTHUR
2198         tristate "RISC OS personality"
2199         depends on !AEABI
2200         help
2201           Say Y here to include the kernel code necessary if you want to run
2202           Acorn RISC OS/Arthur binaries under Linux. This code is still very
2203           experimental; if this sounds frightening, say N and sleep in peace.
2204           You can also say M here to compile this support as a module (which
2205           will be called arthur).
2206
2207 endmenu
2208
2209 menu "Power management options"
2210
2211 source "kernel/power/Kconfig"
2212
2213 config ARCH_SUSPEND_POSSIBLE
2214         depends on !ARCH_S5PC100
2215         depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2216                 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2217         def_bool y
2218
2219 config ARM_CPU_SUSPEND
2220         def_bool PM_SLEEP
2221
2222 endmenu
2223
2224 source "net/Kconfig"
2225
2226 source "drivers/Kconfig"
2227
2228 source "fs/Kconfig"
2229
2230 source "arch/arm/Kconfig.debug"
2231
2232 source "security/Kconfig"
2233
2234 source "crypto/Kconfig"
2235
2236 source "lib/Kconfig"
2237
2238 source "arch/arm/kvm/Kconfig"