arch/arm/Kconfig

   1 config ARM
   2         bool
   3         default y
   4         select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
   5         select ARCH_HAS_DEVMEM_IS_ALLOWED
   6         select ARCH_HAS_ELF_RANDOMIZE
   7         select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
   8         select ARCH_HAVE_CUSTOM_GPIO_H
   9         select ARCH_HAS_GCOV_PROFILE_ALL
  10         select ARCH_MIGHT_HAVE_PC_PARPORT
  11         select ARCH_SUPPORTS_ATOMIC_RMW
  12         select ARCH_USE_BUILTIN_BSWAP
  13         select ARCH_USE_CMPXCHG_LOCKREF
  14         select ARCH_WANT_IPC_PARSE_VERSION
  15         select BUILDTIME_EXTABLE_SORT if MMU
  16         select CLONE_BACKWARDS
  17         select CPU_PM if (SUSPEND || CPU_IDLE)
  18         select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
  19         select EDAC_SUPPORT
  20         select EDAC_ATOMIC_SCRUB
  21         select GENERIC_ALLOCATOR
  22         select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
  23         select GENERIC_CLOCKEVENTS_BROADCAST if SMP
  24         select GENERIC_EARLY_IOREMAP
  25         select GENERIC_IDLE_POLL_SETUP
  26         select GENERIC_IRQ_PROBE
  27         select GENERIC_IRQ_SHOW
  28         select GENERIC_IRQ_SHOW_LEVEL
  29         select GENERIC_PCI_IOMAP
  30         select GENERIC_SCHED_CLOCK
  31         select GENERIC_SMP_IDLE_THREAD
  32         select GENERIC_STRNCPY_FROM_USER
  33         select GENERIC_STRNLEN_USER
  34         select HANDLE_DOMAIN_IRQ
  35         select HARDIRQS_SW_RESEND
  36         select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
  37         select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
  38         select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
  39         select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
  40         select HAVE_ARCH_MMAP_RND_BITS if MMU
  41         select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
  42         select HAVE_ARCH_TRACEHOOK
  43         select HAVE_ARM_SMCCC if CPU_V7
  44         select HAVE_BPF_JIT
  45         select HAVE_CC_STACKPROTECTOR
  46         select HAVE_CONTEXT_TRACKING
  47         select HAVE_C_RECORDMCOUNT
  48         select HAVE_DEBUG_KMEMLEAK
  49         select HAVE_DMA_API_DEBUG
  50         select HAVE_DMA_ATTRS
  51         select HAVE_DMA_CONTIGUOUS if MMU
  52         select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32 && MMU
  53         select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
  54         select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
  55         select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
  56         select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
  57         select HAVE_GENERIC_DMA_COHERENT
  58         select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
  59         select HAVE_IDE if PCI || ISA || PCMCIA
  60         select HAVE_IRQ_TIME_ACCOUNTING
  61         select HAVE_KERNEL_GZIP
  62         select HAVE_KERNEL_LZ4
  63         select HAVE_KERNEL_LZMA
  64         select HAVE_KERNEL_LZO
  65         select HAVE_KERNEL_XZ
  66         select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
  67         select HAVE_KRETPROBES if (HAVE_KPROBES)
  68         select HAVE_MEMBLOCK
  69         select HAVE_MOD_ARCH_SPECIFIC
  70         select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
  71         select HAVE_OPTPROBES if !THUMB2_KERNEL
  72         select HAVE_PERF_EVENTS
  73         select HAVE_PERF_REGS
  74         select HAVE_PERF_USER_STACK_DUMP
  75         select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
  76         select HAVE_REGS_AND_STACK_ACCESS_API
  77         select HAVE_SYSCALL_TRACEPOINTS
  78         select HAVE_UID16
  79         select HAVE_VIRT_CPU_ACCOUNTING_GEN
  80         select IRQ_FORCED_THREADING
  81         select MODULES_USE_ELF_REL
  82         select NO_BOOTMEM
  83         select OF_EARLY_FLATTREE if OF
  84         select OF_RESERVED_MEM if OF
  85         select OLD_SIGACTION
  86         select OLD_SIGSUSPEND3
  87         select PERF_USE_VMALLOC
  88         select RTC_LIB
  89         select SYS_SUPPORTS_APM_EMULATION
  90         # Above selects are sorted alphabetically; please add new ones
  91         # according to that.  Thanks.
  92         help
  93           The ARM series is a line of low-power-consumption RISC chip designs
  94           licensed by ARM Ltd and targeted at embedded applications and
  95           handhelds such as the Compaq IPAQ.  ARM-based PCs are no longer
  96           manufactured, but legacy ARM-based PC hardware remains popular in
  97           Europe.  There is an ARM Linux project with a web page at
  98           <http://www.arm.linux.org.uk/>.
  99
 100 config ARM_HAS_SG_CHAIN
 101         select ARCH_HAS_SG_CHAIN
 102         bool
 103
 104 config NEED_SG_DMA_LENGTH
 105         bool
 106
 107 config ARM_DMA_USE_IOMMU
 108         bool
 109         select ARM_HAS_SG_CHAIN
 110         select NEED_SG_DMA_LENGTH
 111
 112 if ARM_DMA_USE_IOMMU
 113
 114 config ARM_DMA_IOMMU_ALIGNMENT
 115         int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
 116         range 4 9
 117         default 8
 118         help
 119           DMA mapping framework by default aligns all buffers to the smallest
 120           PAGE_SIZE order which is greater than or equal to the requested buffer
 121           size. This works well for buffers up to a few hundreds kilobytes, but
 122           for larger buffers it just a waste of address space. Drivers which has
 123           relatively small addressing window (like 64Mib) might run out of
 124           virtual space with just a few allocations.
 125
 126           With this parameter you can specify the maximum PAGE_SIZE order for
 127           DMA IOMMU buffers. Larger buffers will be aligned only to this
 128           specified order. The order is expressed as a power of two multiplied
 129           by the PAGE_SIZE.
 130
 131 endif
 132
 133 config MIGHT_HAVE_PCI
 134         bool
 135
 136 config SYS_SUPPORTS_APM_EMULATION
 137         bool
 138
 139 config HAVE_TCM
 140         bool
 141         select GENERIC_ALLOCATOR
 142
 143 config HAVE_PROC_CPU
 144         bool
 145
 146 config NO_IOPORT_MAP
 147         bool
 148
 149 config EISA
 150         bool
 151         ---help---
 152           The Extended Industry Standard Architecture (EISA) bus was
 153           developed as an open alternative to the IBM MicroChannel bus.
 154
 155           The EISA bus provided some of the features of the IBM MicroChannel
 156           bus while maintaining backward compatibility with cards made for
 157           the older ISA bus.  The EISA bus saw limited use between 1988 and
 158           1995 when it was made obsolete by the PCI bus.
 159
 160           Say Y here if you are building a kernel for an EISA-based machine.
 161
 162           Otherwise, say N.
 163
 164 config SBUS
 165         bool
 166
 167 config STACKTRACE_SUPPORT
 168         bool
 169         default y
 170
 171 config LOCKDEP_SUPPORT
 172         bool
 173         default y
 174
 175 config TRACE_IRQFLAGS_SUPPORT
 176         bool
 177         default !CPU_V7M
 178
 179 config RWSEM_XCHGADD_ALGORITHM
 180         bool
 181         default y
 182
 183 config ARCH_HAS_ILOG2_U32
 184         bool
 185
 186 config ARCH_HAS_ILOG2_U64
 187         bool
 188
 189 config ARCH_HAS_BANDGAP
 190         bool
 191
 192 config FIX_EARLYCON_MEM
 193         def_bool y if MMU
 194
 195 config GENERIC_HWEIGHT
 196         bool
 197         default y
 198
 199 config GENERIC_CALIBRATE_DELAY
 200         bool
 201         default y
 202
 203 config ARCH_MAY_HAVE_PC_FDC
 204         bool
 205
 206 config ZONE_DMA
 207         bool
 208
 209 config NEED_DMA_MAP_STATE
 210        def_bool y
 211
 212 config ARCH_SUPPORTS_UPROBES
 213         def_bool y
 214
 215 config ARCH_HAS_DMA_SET_COHERENT_MASK
 216         bool
 217
 218 config GENERIC_ISA_DMA
 219         bool
 220
 221 config FIQ
 222         bool
 223
 224 config NEED_RET_TO_USER
 225         bool
 226
 227 config ARCH_MTD_XIP
 228         bool
 229
 230 config VECTORS_BASE
 231         hex
 232         default 0xffff0000 if MMU || CPU_HIGH_VECTOR
 233         default DRAM_BASE if REMAP_VECTORS_TO_RAM
 234         default 0x00000000
 235         help
 236           The base address of exception vectors.  This must be two pages
 237           in size.
 238
 239 config ARM_PATCH_PHYS_VIRT
 240         bool "Patch physical to virtual translations at runtime" if EMBEDDED
 241         default y
 242         depends on !XIP_KERNEL && MMU
 243         depends on !ARCH_REALVIEW || !SPARSEMEM
 244         help
 245           Patch phys-to-virt and virt-to-phys translation functions at
 246           boot and module load time according to the position of the
 247           kernel in system memory.
 248
 249           This can only be used with non-XIP MMU kernels where the base
 250           of physical memory is at a 16MB boundary.
 251
 252           Only disable this option if you know that you do not require
 253           this feature (eg, building a kernel for a single machine) and
 254           you need to shrink the kernel to the minimal size.
 255
 256 config NEED_MACH_IO_H
 257         bool
 258         help
 259           Select this when mach/io.h is required to provide special
 260           definitions for this platform.  The need for mach/io.h should
 261           be avoided when possible.
 262
 263 config NEED_MACH_MEMORY_H
 264         bool
 265         help
 266           Select this when mach/memory.h is required to provide special
 267           definitions for this platform.  The need for mach/memory.h should
 268           be avoided when possible.
 269
 270 config PHYS_OFFSET
 271         hex "Physical address of main memory" if MMU
 272         depends on !ARM_PATCH_PHYS_VIRT
 273         default DRAM_BASE if !MMU
 274         default 0x00000000 if ARCH_EBSA110 || \
 275                         ARCH_FOOTBRIDGE || \
 276                         ARCH_INTEGRATOR || \
 277                         ARCH_IOP13XX || \
 278                         ARCH_KS8695 || \
 279                         (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET)
 280         default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
 281         default 0x20000000 if ARCH_S5PV210
 282         default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET
 283         default 0xc0000000 if ARCH_SA1100
 284         help
 285           Please provide the physical address corresponding to the
 286           location of main memory in your system.
 287
 288 config GENERIC_BUG
 289         def_bool y
 290         depends on BUG
 291
 292 config PGTABLE_LEVELS
 293         int
 294         default 3 if ARM_LPAE
 295         default 2
 296
 297 source "init/Kconfig"
 298
 299 source "kernel/Kconfig.freezer"
 300
 301 menu "System Type"
 302
 303 config MMU
 304         bool "MMU-based Paged Memory Management Support"
 305         default y
 306         help
 307           Select if you want MMU-based virtualised addressing space
 308           support by paged memory management. If unsure, say 'Y'.
 309
 310 config ARCH_MMAP_RND_BITS_MIN
 311         default 8
 312
 313 config ARCH_MMAP_RND_BITS_MAX
 314         default 14 if PAGE_OFFSET=0x40000000
 315         default 15 if PAGE_OFFSET=0x80000000
 316         default 16
 317
 318 #
 319 # The "ARM system type" choice list is ordered alphabetically by option
 320 # text.  Please add new entries in the option alphabetic order.
 321 #
 322 choice
 323         prompt "ARM system type"
 324         default ARCH_VERSATILE if !MMU
 325         default ARCH_MULTIPLATFORM if MMU
 326
 327 config ARCH_MULTIPLATFORM
 328         bool "Allow multiple platforms to be selected"
 329         depends on MMU
 330         select ARCH_WANT_OPTIONAL_GPIOLIB
 331         select ARM_HAS_SG_CHAIN
 332         select ARM_PATCH_PHYS_VIRT
 333         select AUTO_ZRELADDR
 334         select CLKSRC_OF
 335         select COMMON_CLK
 336         select GENERIC_CLOCKEVENTS
 337         select MIGHT_HAVE_PCI
 338         select MULTI_IRQ_HANDLER
 339         select SPARSE_IRQ
 340         select USE_OF
 341
 342 config ARM_SINGLE_ARMV7M
 343         bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
 344         depends on !MMU
 345         select ARCH_WANT_OPTIONAL_GPIOLIB
 346         select ARM_NVIC
 347         select AUTO_ZRELADDR
 348         select CLKSRC_OF
 349         select COMMON_CLK
 350         select CPU_V7M
 351         select GENERIC_CLOCKEVENTS
 352         select NO_IOPORT_MAP
 353         select SPARSE_IRQ
 354         select USE_OF
 355
 356 config ARCH_REALVIEW
 357         bool "ARM Ltd. RealView family"
 358         select ARCH_WANT_OPTIONAL_GPIOLIB
 359         select ARM_AMBA
 360         select ARM_TIMER_SP804
 361         select COMMON_CLK
 362         select COMMON_CLK_VERSATILE
 363         select GENERIC_CLOCKEVENTS
 364         select GPIO_PL061 if GPIOLIB
 365         select ICST
 366         select NEED_MACH_MEMORY_H
 367         select PLAT_VERSATILE
 368         select PLAT_VERSATILE_SCHED_CLOCK
 369         help
 370           This enables support for ARM Ltd RealView boards.
 371
 372 config ARCH_VERSATILE
 373         bool "ARM Ltd. Versatile family"
 374         select ARCH_WANT_OPTIONAL_GPIOLIB
 375         select ARM_AMBA
 376         select ARM_TIMER_SP804
 377         select ARM_VIC
 378         select CLKDEV_LOOKUP
 379         select GENERIC_CLOCKEVENTS
 380         select HAVE_MACH_CLKDEV
 381         select ICST
 382         select PLAT_VERSATILE
 383         select PLAT_VERSATILE_CLOCK
 384         select PLAT_VERSATILE_SCHED_CLOCK
 385         select VERSATILE_FPGA_IRQ
 386         help
 387           This enables support for ARM Ltd Versatile board.
 388
 389 config ARCH_CLPS711X
 390         bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
 391         select ARCH_REQUIRE_GPIOLIB
 392         select AUTO_ZRELADDR
 393         select CLKSRC_MMIO
 394         select COMMON_CLK
 395         select CPU_ARM720T
 396         select GENERIC_CLOCKEVENTS
 397         select MFD_SYSCON
 398         select SOC_BUS
 399         help
 400           Support for Cirrus Logic 711x/721x/731x based boards.
 401
 402 config ARCH_GEMINI
 403         bool "Cortina Systems Gemini"
 404         select ARCH_REQUIRE_GPIOLIB
 405         select CLKSRC_MMIO
 406         select CPU_FA526
 407         select GENERIC_CLOCKEVENTS
 408         help
 409           Support for the Cortina Systems Gemini family SoCs
 410
 411 config ARCH_EBSA110
 412         bool "EBSA-110"
 413         select ARCH_USES_GETTIMEOFFSET
 414         select CPU_SA110
 415         select ISA
 416         select NEED_MACH_IO_H
 417         select NEED_MACH_MEMORY_H
 418         select NO_IOPORT_MAP
 419         help
 420           This is an evaluation board for the StrongARM processor available
 421           from Digital. It has limited hardware on-board, including an
 422           Ethernet interface, two PCMCIA sockets, two serial ports and a
 423           parallel port.
 424
 425 config ARCH_EP93XX
 426         bool "EP93xx-based"
 427         select ARCH_HAS_HOLES_MEMORYMODEL
 428         select ARCH_REQUIRE_GPIOLIB
 429         select ARM_AMBA
 430         select ARM_PATCH_PHYS_VIRT
 431         select ARM_VIC
 432         select AUTO_ZRELADDR
 433         select CLKDEV_LOOKUP
 434         select CLKSRC_MMIO
 435         select CPU_ARM920T
 436         select GENERIC_CLOCKEVENTS
 437         help
 438           This enables support for the Cirrus EP93xx series of CPUs.
 439
 440 config ARCH_FOOTBRIDGE
 441         bool "FootBridge"
 442         select CPU_SA110
 443         select FOOTBRIDGE
 444         select GENERIC_CLOCKEVENTS
 445         select HAVE_IDE
 446         select NEED_MACH_IO_H if !MMU
 447         select NEED_MACH_MEMORY_H
 448         help
 449           Support for systems based on the DC21285 companion chip
 450           ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
 451
 452 config ARCH_NETX
 453         bool "Hilscher NetX based"
 454         select ARM_VIC
 455         select CLKSRC_MMIO
 456         select CPU_ARM926T
 457         select GENERIC_CLOCKEVENTS
 458         help
 459           This enables support for systems based on the Hilscher NetX Soc
 460
 461 config ARCH_IOP13XX
 462         bool "IOP13xx-based"
 463         depends on MMU
 464         select CPU_XSC3
 465         select NEED_MACH_MEMORY_H
 466         select NEED_RET_TO_USER
 467         select PCI
 468         select PLAT_IOP
 469         select VMSPLIT_1G
 470         select SPARSE_IRQ
 471         help
 472           Support for Intel's IOP13XX (XScale) family of processors.
 473
 474 config ARCH_IOP32X
 475         bool "IOP32x-based"
 476         depends on MMU
 477         select ARCH_REQUIRE_GPIOLIB
 478         select CPU_XSCALE
 479         select GPIO_IOP
 480         select NEED_RET_TO_USER
 481         select PCI
 482         select PLAT_IOP
 483         help
 484           Support for Intel's 80219 and IOP32X (XScale) family of
 485           processors.
 486
 487 config ARCH_IOP33X
 488         bool "IOP33x-based"
 489         depends on MMU
 490         select ARCH_REQUIRE_GPIOLIB
 491         select CPU_XSCALE
 492         select GPIO_IOP
 493         select NEED_RET_TO_USER
 494         select PCI
 495         select PLAT_IOP
 496         help
 497           Support for Intel's IOP33X (XScale) family of processors.
 498
 499 config ARCH_IXP4XX
 500         bool "IXP4xx-based"
 501         depends on MMU
 502         select ARCH_HAS_DMA_SET_COHERENT_MASK
 503         select ARCH_REQUIRE_GPIOLIB
 504         select ARCH_SUPPORTS_BIG_ENDIAN
 505         select CLKSRC_MMIO
 506         select CPU_XSCALE
 507         select DMABOUNCE if PCI
 508         select GENERIC_CLOCKEVENTS
 509         select MIGHT_HAVE_PCI
 510         select NEED_MACH_IO_H
 511         select USB_EHCI_BIG_ENDIAN_DESC
 512         select USB_EHCI_BIG_ENDIAN_MMIO
 513         help
 514           Support for Intel's IXP4XX (XScale) family of processors.
 515
 516 config ARCH_DOVE
 517         bool "Marvell Dove"
 518         select ARCH_REQUIRE_GPIOLIB
 519         select CPU_PJ4
 520         select GENERIC_CLOCKEVENTS
 521         select MIGHT_HAVE_PCI
 522         select MVEBU_MBUS
 523         select PINCTRL
 524         select PINCTRL_DOVE
 525         select PLAT_ORION_LEGACY
 526         help
 527           Support for the Marvell Dove SoC 88AP510
 528
 529 config ARCH_MV78XX0
 530         bool "Marvell MV78xx0"
 531         select ARCH_REQUIRE_GPIOLIB
 532         select CPU_FEROCEON
 533         select GENERIC_CLOCKEVENTS
 534         select MVEBU_MBUS
 535         select PCI
 536         select PLAT_ORION_LEGACY
 537         help
 538           Support for the following Marvell MV78xx0 series SoCs:
 539           MV781x0, MV782x0.
 540
 541 config ARCH_ORION5X
 542         bool "Marvell Orion"
 543         depends on MMU
 544         select ARCH_REQUIRE_GPIOLIB
 545         select CPU_FEROCEON
 546         select GENERIC_CLOCKEVENTS
 547         select MVEBU_MBUS
 548         select PCI
 549         select PLAT_ORION_LEGACY
 550         select MULTI_IRQ_HANDLER
 551         help
 552           Support for the following Marvell Orion 5x series SoCs:
 553           Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
 554           Orion-2 (5281), Orion-1-90 (6183).
 555
 556 config ARCH_MMP
 557         bool "Marvell PXA168/910/MMP2"
 558         depends on MMU
 559         select ARCH_REQUIRE_GPIOLIB
 560         select CLKDEV_LOOKUP
 561         select GENERIC_ALLOCATOR
 562         select GENERIC_CLOCKEVENTS
 563         select GPIO_PXA
 564         select IRQ_DOMAIN
 565         select MULTI_IRQ_HANDLER
 566         select PINCTRL
 567         select PLAT_PXA
 568         select SPARSE_IRQ
 569         help
 570           Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
 571
 572 config ARCH_KS8695
 573         bool "Micrel/Kendin KS8695"
 574         select ARCH_REQUIRE_GPIOLIB
 575         select CLKSRC_MMIO
 576         select CPU_ARM922T
 577         select GENERIC_CLOCKEVENTS
 578         select NEED_MACH_MEMORY_H
 579         help
 580           Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
 581           System-on-Chip devices.
 582
 583 config ARCH_W90X900
 584         bool "Nuvoton W90X900 CPU"
 585         select ARCH_REQUIRE_GPIOLIB
 586         select CLKDEV_LOOKUP
 587         select CLKSRC_MMIO
 588         select CPU_ARM926T
 589         select GENERIC_CLOCKEVENTS
 590         help
 591           Support for Nuvoton (Winbond logic dept.) ARM9 processor,
 592           At present, the w90x900 has been renamed nuc900, regarding
 593           the ARM series product line, you can login the following
 594           link address to know more.
 595
 596           <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
 597                 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
 598
 599 config ARCH_LPC32XX
 600         bool "NXP LPC32XX"
 601         select ARCH_REQUIRE_GPIOLIB
 602         select ARM_AMBA
 603         select CLKDEV_LOOKUP
 604         select CLKSRC_MMIO
 605         select CPU_ARM926T
 606         select GENERIC_CLOCKEVENTS
 607         select HAVE_IDE
 608         select USE_OF
 609         help
 610           Support for the NXP LPC32XX family of processors
 611
 612 config ARCH_PXA
 613         bool "PXA2xx/PXA3xx-based"
 614         depends on MMU
 615         select ARCH_MTD_XIP
 616         select ARCH_REQUIRE_GPIOLIB
 617         select ARM_CPU_SUSPEND if PM
 618         select AUTO_ZRELADDR
 619         select COMMON_CLK
 620         select CLKDEV_LOOKUP
 621         select CLKSRC_PXA
 622         select CLKSRC_MMIO
 623         select CLKSRC_OF
 624         select GENERIC_CLOCKEVENTS
 625         select GPIO_PXA
 626         select HAVE_IDE
 627         select IRQ_DOMAIN
 628         select MULTI_IRQ_HANDLER
 629         select PLAT_PXA
 630         select SPARSE_IRQ
 631         help
 632           Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
 633
 634 config ARCH_RPC
 635         bool "RiscPC"
 636         depends on MMU
 637         select ARCH_ACORN
 638         select ARCH_MAY_HAVE_PC_FDC
 639         select ARCH_SPARSEMEM_ENABLE
 640         select ARCH_USES_GETTIMEOFFSET
 641         select CPU_SA110
 642         select FIQ
 643         select HAVE_IDE
 644         select HAVE_PATA_PLATFORM
 645         select ISA_DMA_API
 646         select NEED_MACH_IO_H
 647         select NEED_MACH_MEMORY_H
 648         select NO_IOPORT_MAP
 649         select VIRT_TO_BUS
 650         help
 651           On the Acorn Risc-PC, Linux can support the internal IDE disk and
 652           CD-ROM interface, serial and parallel port, and the floppy drive.
 653
 654 config ARCH_SA1100
 655         bool "SA1100-based"
 656         select ARCH_MTD_XIP
 657         select ARCH_REQUIRE_GPIOLIB
 658         select ARCH_SPARSEMEM_ENABLE
 659         select CLKDEV_LOOKUP
 660         select CLKSRC_MMIO
 661         select CLKSRC_PXA
 662         select CLKSRC_OF if OF
 663         select CPU_FREQ
 664         select CPU_SA1100
 665         select GENERIC_CLOCKEVENTS
 666         select HAVE_IDE
 667         select IRQ_DOMAIN
 668         select ISA
 669         select MULTI_IRQ_HANDLER
 670         select NEED_MACH_MEMORY_H
 671         select SPARSE_IRQ
 672         help
 673           Support for StrongARM 11x0 based boards.
 674
 675 config ARCH_S3C24XX
 676         bool "Samsung S3C24XX SoCs"
 677         select ARCH_REQUIRE_GPIOLIB
 678         select ATAGS
 679         select CLKDEV_LOOKUP
 680         select CLKSRC_SAMSUNG_PWM
 681         select GENERIC_CLOCKEVENTS
 682         select GPIO_SAMSUNG
 683         select HAVE_S3C2410_I2C if I2C
 684         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 685         select HAVE_S3C_RTC if RTC_CLASS
 686         select MULTI_IRQ_HANDLER
 687         select NEED_MACH_IO_H
 688         select SAMSUNG_ATAGS
 689         help
 690           Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
 691           and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
 692           (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
 693           Samsung SMDK2410 development board (and derivatives).
 694
 695 config ARCH_S3C64XX
 696         bool "Samsung S3C64XX"
 697         select ARCH_REQUIRE_GPIOLIB
 698         select ARM_AMBA
 699         select ARM_VIC
 700         select ATAGS
 701         select CLKDEV_LOOKUP
 702         select CLKSRC_SAMSUNG_PWM
 703         select COMMON_CLK_SAMSUNG
 704         select CPU_V6K
 705         select GENERIC_CLOCKEVENTS
 706         select GPIO_SAMSUNG
 707         select HAVE_S3C2410_I2C if I2C
 708         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 709         select HAVE_TCM
 710         select NO_IOPORT_MAP
 711         select PLAT_SAMSUNG
 712         select PM_GENERIC_DOMAINS if PM
 713         select S3C_DEV_NAND
 714         select S3C_GPIO_TRACK
 715         select SAMSUNG_ATAGS
 716         select SAMSUNG_WAKEMASK
 717         select SAMSUNG_WDT_RESET
 718         help
 719           Samsung S3C64XX series based systems
 720
 721 config ARCH_DAVINCI
 722         bool "TI DaVinci"
 723         select ARCH_HAS_HOLES_MEMORYMODEL
 724         select ARCH_REQUIRE_GPIOLIB
 725         select CLKDEV_LOOKUP
 726         select GENERIC_ALLOCATOR
 727         select GENERIC_CLOCKEVENTS
 728         select GENERIC_IRQ_CHIP
 729         select HAVE_IDE
 730         select USE_OF
 731         select ZONE_DMA
 732         help
 733           Support for TI's DaVinci platform.
 734
 735 config ARCH_OMAP1
 736         bool "TI OMAP1"
 737         depends on MMU
 738         select ARCH_HAS_HOLES_MEMORYMODEL
 739         select ARCH_OMAP
 740         select ARCH_REQUIRE_GPIOLIB
 741         select CLKDEV_LOOKUP
 742         select CLKSRC_MMIO
 743         select GENERIC_CLOCKEVENTS
 744         select GENERIC_IRQ_CHIP
 745         select HAVE_IDE
 746         select IRQ_DOMAIN
 747         select MULTI_IRQ_HANDLER
 748         select NEED_MACH_IO_H if PCCARD
 749         select NEED_MACH_MEMORY_H
 750         select SPARSE_IRQ
 751         help
 752           Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
 753
 754 endchoice
 755
 756 menu "Multiple platform selection"
 757         depends on ARCH_MULTIPLATFORM
 758
 759 comment "CPU Core family selection"
 760
 761 config ARCH_MULTI_V4
 762         bool "ARMv4 based platforms (FA526)"
 763         depends on !ARCH_MULTI_V6_V7
 764         select ARCH_MULTI_V4_V5
 765         select CPU_FA526
 766
 767 config ARCH_MULTI_V4T
 768         bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
 769         depends on !ARCH_MULTI_V6_V7
 770         select ARCH_MULTI_V4_V5
 771         select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
 772                 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
 773                 CPU_ARM925T || CPU_ARM940T)
 774
 775 config ARCH_MULTI_V5
 776         bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
 777         depends on !ARCH_MULTI_V6_V7
 778         select ARCH_MULTI_V4_V5
 779         select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
 780                 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
 781                 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
 782
 783 config ARCH_MULTI_V4_V5
 784         bool
 785
 786 config ARCH_MULTI_V6
 787         bool "ARMv6 based platforms (ARM11)"
 788         select ARCH_MULTI_V6_V7
 789         select CPU_V6K
 790
 791 config ARCH_MULTI_V7
 792         bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
 793         default y
 794         select ARCH_MULTI_V6_V7
 795         select CPU_V7
 796         select HAVE_SMP
 797
 798 config ARCH_MULTI_V6_V7
 799         bool
 800         select MIGHT_HAVE_CACHE_L2X0
 801
 802 config ARCH_MULTI_CPU_AUTO
 803         def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
 804         select ARCH_MULTI_V5
 805
 806 endmenu
 807
 808 config ARCH_VIRT
 809         bool "Dummy Virtual Machine" if ARCH_MULTI_V7
 810         select ARM_AMBA
 811         select ARM_GIC
 812         select ARM_GIC_V2M if PCI_MSI
 813         select ARM_GIC_V3
 814         select ARM_PSCI
 815         select HAVE_ARM_ARCH_TIMER
 816
 817 #
 818 # This is sorted alphabetically by mach-* pathname.  However, plat-*
 819 # Kconfigs may be included either alphabetically (according to the
 820 # plat- suffix) or along side the corresponding mach-* source.
 821 #
 822 source "arch/arm/mach-mvebu/Kconfig"
 823
 824 source "arch/arm/mach-alpine/Kconfig"
 825
 826 source "arch/arm/mach-asm9260/Kconfig"
 827
 828 source "arch/arm/mach-at91/Kconfig"
 829
 830 source "arch/arm/mach-axxia/Kconfig"
 831
 832 source "arch/arm/mach-bcm/Kconfig"
 833
 834 source "arch/arm/mach-berlin/Kconfig"
 835
 836 source "arch/arm/mach-clps711x/Kconfig"
 837
 838 source "arch/arm/mach-cns3xxx/Kconfig"
 839
 840 source "arch/arm/mach-davinci/Kconfig"
 841
 842 source "arch/arm/mach-digicolor/Kconfig"
 843
 844 source "arch/arm/mach-dove/Kconfig"
 845
 846 source "arch/arm/mach-ep93xx/Kconfig"
 847
 848 source "arch/arm/mach-footbridge/Kconfig"
 849
 850 source "arch/arm/mach-gemini/Kconfig"
 851
 852 source "arch/arm/mach-highbank/Kconfig"
 853
 854 source "arch/arm/mach-hisi/Kconfig"
 855
 856 source "arch/arm/mach-integrator/Kconfig"
 857
 858 source "arch/arm/mach-iop32x/Kconfig"
 859
 860 source "arch/arm/mach-iop33x/Kconfig"
 861
 862 source "arch/arm/mach-iop13xx/Kconfig"
 863
 864 source "arch/arm/mach-ixp4xx/Kconfig"
 865
 866 source "arch/arm/mach-keystone/Kconfig"
 867
 868 source "arch/arm/mach-ks8695/Kconfig"
 869
 870 source "arch/arm/mach-meson/Kconfig"
 871
 872 source "arch/arm/mach-moxart/Kconfig"
 873
 874 source "arch/arm/mach-mv78xx0/Kconfig"
 875
 876 source "arch/arm/mach-imx/Kconfig"
 877
 878 source "arch/arm/mach-mediatek/Kconfig"
 879
 880 source "arch/arm/mach-mxs/Kconfig"
 881
 882 source "arch/arm/mach-netx/Kconfig"
 883
 884 source "arch/arm/mach-nomadik/Kconfig"
 885
 886 source "arch/arm/mach-nspire/Kconfig"
 887
 888 source "arch/arm/plat-omap/Kconfig"
 889
 890 source "arch/arm/mach-omap1/Kconfig"
 891
 892 source "arch/arm/mach-omap2/Kconfig"
 893
 894 source "arch/arm/mach-orion5x/Kconfig"
 895
 896 source "arch/arm/mach-picoxcell/Kconfig"
 897
 898 source "arch/arm/mach-pxa/Kconfig"
 899 source "arch/arm/plat-pxa/Kconfig"
 900
 901 source "arch/arm/mach-mmp/Kconfig"
 902
 903 source "arch/arm/mach-qcom/Kconfig"
 904
 905 source "arch/arm/mach-realview/Kconfig"
 906
 907 source "arch/arm/mach-rockchip/Kconfig"
 908
 909 source "arch/arm/mach-sa1100/Kconfig"
 910
 911 source "arch/arm/mach-socfpga/Kconfig"
 912
 913 source "arch/arm/mach-spear/Kconfig"
 914
 915 source "arch/arm/mach-sti/Kconfig"
 916
 917 source "arch/arm/mach-s3c24xx/Kconfig"
 918
 919 source "arch/arm/mach-s3c64xx/Kconfig"
 920
 921 source "arch/arm/mach-s5pv210/Kconfig"
 922
 923 source "arch/arm/mach-exynos/Kconfig"
 924 source "arch/arm/plat-samsung/Kconfig"
 925
 926 source "arch/arm/mach-shmobile/Kconfig"
 927
 928 source "arch/arm/mach-sunxi/Kconfig"
 929
 930 source "arch/arm/mach-prima2/Kconfig"
 931
 932 source "arch/arm/mach-tegra/Kconfig"
 933
 934 source "arch/arm/mach-u300/Kconfig"
 935
 936 source "arch/arm/mach-uniphier/Kconfig"
 937
 938 source "arch/arm/mach-ux500/Kconfig"
 939
 940 source "arch/arm/mach-versatile/Kconfig"
 941
 942 source "arch/arm/mach-vexpress/Kconfig"
 943 source "arch/arm/plat-versatile/Kconfig"
 944
 945 source "arch/arm/mach-vt8500/Kconfig"
 946
 947 source "arch/arm/mach-w90x900/Kconfig"
 948
 949 source "arch/arm/mach-zx/Kconfig"
 950
 951 source "arch/arm/mach-zynq/Kconfig"
 952
 953 # ARMv7-M architecture
 954 config ARCH_EFM32
 955         bool "Energy Micro efm32"
 956         depends on ARM_SINGLE_ARMV7M
 957         select ARCH_REQUIRE_GPIOLIB
 958         help
 959           Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
 960           processors.
 961
 962 config ARCH_LPC18XX
 963         bool "NXP LPC18xx/LPC43xx"
 964         depends on ARM_SINGLE_ARMV7M
 965         select ARCH_HAS_RESET_CONTROLLER
 966         select ARM_AMBA
 967         select CLKSRC_LPC32XX
 968         select PINCTRL
 969         help
 970           Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
 971           high performance microcontrollers.
 972
 973 config ARCH_STM32
 974         bool "STMicrolectronics STM32"
 975         depends on ARM_SINGLE_ARMV7M
 976         select ARCH_HAS_RESET_CONTROLLER
 977         select ARMV7M_SYSTICK
 978         select CLKSRC_STM32
 979         select RESET_CONTROLLER
 980         help
 981           Support for STMicroelectronics STM32 processors.
 982
 983 # Definitions to make life easier
 984 config ARCH_ACORN
 985         bool
 986
 987 config PLAT_IOP
 988         bool
 989         select GENERIC_CLOCKEVENTS
 990
 991 config PLAT_ORION
 992         bool
 993         select CLKSRC_MMIO
 994         select COMMON_CLK
 995         select GENERIC_IRQ_CHIP
 996         select IRQ_DOMAIN
 997
 998 config PLAT_ORION_LEGACY
 999         bool
1000         select PLAT_ORION
1001
1002 config PLAT_PXA
1003         bool
1004
1005 config PLAT_VERSATILE
1006         bool
1007
1008 source "arch/arm/firmware/Kconfig"
1009
1010 source arch/arm/mm/Kconfig
1011
1012 config IWMMXT
1013         bool "Enable iWMMXt support"
1014         depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
1015         default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
1016         help
1017           Enable support for iWMMXt context switching at run time if
1018           running on a CPU that supports it.
1019
1020 config MULTI_IRQ_HANDLER
1021         bool
1022         help
1023           Allow each machine to specify it's own IRQ handler at run time.
1024
1025 if !MMU
1026 source "arch/arm/Kconfig-nommu"
1027 endif
1028
1029 config PJ4B_ERRATA_4742
1030         bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1031         depends on CPU_PJ4B && MACH_ARMADA_370
1032         default y
1033         help
1034           When coming out of either a Wait for Interrupt (WFI) or a Wait for
1035           Event (WFE) IDLE states, a specific timing sensitivity exists between
1036           the retiring WFI/WFE instructions and the newly issued subsequent
1037           instructions.  This sensitivity can result in a CPU hang scenario.
1038           Workaround:
1039           The software must insert either a Data Synchronization Barrier (DSB)
1040           or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1041           instruction
1042
1043 config ARM_ERRATA_326103
1044         bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1045         depends on CPU_V6
1046         help
1047           Executing a SWP instruction to read-only memory does not set bit 11
1048           of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1049           treat the access as a read, preventing a COW from occurring and
1050           causing the faulting task to livelock.
1051
1052 config ARM_ERRATA_411920
1053         bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1054         depends on CPU_V6 || CPU_V6K
1055         help
1056           Invalidation of the Instruction Cache operation can
1057           fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1058           It does not affect the MPCore. This option enables the ARM Ltd.
1059           recommended workaround.
1060
1061 config ARM_ERRATA_430973
1062         bool "ARM errata: Stale prediction on replaced interworking branch"
1063         depends on CPU_V7
1064         help
1065           This option enables the workaround for the 430973 Cortex-A8
1066           r1p* erratum. If a code sequence containing an ARM/Thumb
1067           interworking branch is replaced with another code sequence at the
1068           same virtual address, whether due to self-modifying code or virtual
1069           to physical address re-mapping, Cortex-A8 does not recover from the
1070           stale interworking branch prediction. This results in Cortex-A8
1071           executing the new code sequence in the incorrect ARM or Thumb state.
1072           The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1073           and also flushes the branch target cache at every context switch.
1074           Note that setting specific bits in the ACTLR register may not be
1075           available in non-secure mode.
1076
1077 config ARM_ERRATA_458693
1078         bool "ARM errata: Processor deadlock when a false hazard is created"
1079         depends on CPU_V7
1080         depends on !ARCH_MULTIPLATFORM
1081         help
1082           This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1083           erratum. For very specific sequences of memory operations, it is
1084           possible for a hazard condition intended for a cache line to instead
1085           be incorrectly associated with a different cache line. This false
1086           hazard might then cause a processor deadlock. The workaround enables
1087           the L1 caching of the NEON accesses and disables the PLD instruction
1088           in the ACTLR register. Note that setting specific bits in the ACTLR
1089           register may not be available in non-secure mode.
1090
1091 config ARM_ERRATA_460075
1092         bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1093         depends on CPU_V7
1094         depends on !ARCH_MULTIPLATFORM
1095         help
1096           This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1097           erratum. Any asynchronous access to the L2 cache may encounter a
1098           situation in which recent store transactions to the L2 cache are lost
1099           and overwritten with stale memory contents from external memory. The
1100           workaround disables the write-allocate mode for the L2 cache via the
1101           ACTLR register. Note that setting specific bits in the ACTLR register
1102           may not be available in non-secure mode.
1103
1104 config ARM_ERRATA_742230
1105         bool "ARM errata: DMB operation may be faulty"
1106         depends on CPU_V7 && SMP
1107         depends on !ARCH_MULTIPLATFORM
1108         help
1109           This option enables the workaround for the 742230 Cortex-A9
1110           (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1111           between two write operations may not ensure the correct visibility
1112           ordering of the two writes. This workaround sets a specific bit in
1113           the diagnostic register of the Cortex-A9 which causes the DMB
1114           instruction to behave as a DSB, ensuring the correct behaviour of
1115           the two writes.
1116
1117 config ARM_ERRATA_742231
1118         bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1119         depends on CPU_V7 && SMP
1120         depends on !ARCH_MULTIPLATFORM
1121         help
1122           This option enables the workaround for the 742231 Cortex-A9
1123           (r2p0..r2p2) erratum. Under certain conditions, specific to the
1124           Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1125           accessing some data located in the same cache line, may get corrupted
1126           data due to bad handling of the address hazard when the line gets
1127           replaced from one of the CPUs at the same time as another CPU is
1128           accessing it. This workaround sets specific bits in the diagnostic
1129           register of the Cortex-A9 which reduces the linefill issuing
1130           capabilities of the processor.
1131
1132 config ARM_ERRATA_643719
1133         bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1134         depends on CPU_V7 && SMP
1135         default y
1136         help
1137           This option enables the workaround for the 643719 Cortex-A9 (prior to
1138           r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1139           register returns zero when it should return one. The workaround
1140           corrects this value, ensuring cache maintenance operations which use
1141           it behave as intended and avoiding data corruption.
1142
1143 config ARM_ERRATA_720789
1144         bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1145         depends on CPU_V7
1146         help
1147           This option enables the workaround for the 720789 Cortex-A9 (prior to
1148           r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1149           broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1150           As a consequence of this erratum, some TLB entries which should be
1151           invalidated are not, resulting in an incoherency in the system page
1152           tables. The workaround changes the TLB flushing routines to invalidate
1153           entries regardless of the ASID.
1154
1155 config ARM_ERRATA_743622
1156         bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1157         depends on CPU_V7
1158         depends on !ARCH_MULTIPLATFORM
1159         help
1160           This option enables the workaround for the 743622 Cortex-A9
1161           (r2p*) erratum. Under very rare conditions, a faulty
1162           optimisation in the Cortex-A9 Store Buffer may lead to data
1163           corruption. This workaround sets a specific bit in the diagnostic
1164           register of the Cortex-A9 which disables the Store Buffer
1165           optimisation, preventing the defect from occurring. This has no
1166           visible impact on the overall performance or power consumption of the
1167           processor.
1168
1169 config ARM_ERRATA_751472
1170         bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1171         depends on CPU_V7
1172         depends on !ARCH_MULTIPLATFORM
1173         help
1174           This option enables the workaround for the 751472 Cortex-A9 (prior
1175           to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1176           completion of a following broadcasted operation if the second
1177           operation is received by a CPU before the ICIALLUIS has completed,
1178           potentially leading to corrupted entries in the cache or TLB.
1179
1180 config ARM_ERRATA_754322
1181         bool "ARM errata: possible faulty MMU translations following an ASID switch"
1182         depends on CPU_V7
1183         help
1184           This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1185           r3p*) erratum. A speculative memory access may cause a page table walk
1186           which starts prior to an ASID switch but completes afterwards. This
1187           can populate the micro-TLB with a stale entry which may be hit with
1188           the new ASID. This workaround places two dsb instructions in the mm
1189           switching code so that no page table walks can cross the ASID switch.
1190
1191 config ARM_ERRATA_754327
1192         bool "ARM errata: no automatic Store Buffer drain"
1193         depends on CPU_V7 && SMP
1194         help
1195           This option enables the workaround for the 754327 Cortex-A9 (prior to
1196           r2p0) erratum. The Store Buffer does not have any automatic draining
1197           mechanism and therefore a livelock may occur if an external agent
1198           continuously polls a memory location waiting to observe an update.
1199           This workaround defines cpu_relax() as smp_mb(), preventing correctly
1200           written polling loops from denying visibility of updates to memory.
1201
1202 config ARM_ERRATA_364296
1203         bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1204         depends on CPU_V6
1205         help
1206           This options enables the workaround for the 364296 ARM1136
1207           r0p2 erratum (possible cache data corruption with
1208           hit-under-miss enabled). It sets the undocumented bit 31 in
1209           the auxiliary control register and the FI bit in the control
1210           register, thus disabling hit-under-miss without putting the
1211           processor into full low interrupt latency mode. ARM11MPCore
1212           is not affected.
1213
1214 config ARM_ERRATA_764369
1215         bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1216         depends on CPU_V7 && SMP
1217         help
1218           This option enables the workaround for erratum 764369
1219           affecting Cortex-A9 MPCore with two or more processors (all
1220           current revisions). Under certain timing circumstances, a data
1221           cache line maintenance operation by MVA targeting an Inner
1222           Shareable memory region may fail to proceed up to either the
1223           Point of Coherency or to the Point of Unification of the
1224           system. This workaround adds a DSB instruction before the
1225           relevant cache maintenance functions and sets a specific bit
1226           in the diagnostic control register of the SCU.
1227
1228 config ARM_ERRATA_775420
1229        bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1230        depends on CPU_V7
1231        help
1232          This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1233          r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1234          operation aborts with MMU exception, it might cause the processor
1235          to deadlock. This workaround puts DSB before executing ISB if
1236          an abort may occur on cache maintenance.
1237
1238 config ARM_ERRATA_798181
1239         bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1240         depends on CPU_V7 && SMP
1241         help
1242           On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1243           adequately shooting down all use of the old entries. This
1244           option enables the Linux kernel workaround for this erratum
1245           which sends an IPI to the CPUs that are running the same ASID
1246           as the one being invalidated.
1247
1248 config ARM_ERRATA_773022
1249         bool "ARM errata: incorrect instructions may be executed from loop buffer"
1250         depends on CPU_V7
1251         help
1252           This option enables the workaround for the 773022 Cortex-A15
1253           (up to r0p4) erratum. In certain rare sequences of code, the
1254           loop buffer may deliver incorrect instructions. This
1255           workaround disables the loop buffer to avoid the erratum.
1256
1257 endmenu
1258
1259 source "arch/arm/common/Kconfig"
1260
1261 menu "Bus support"
1262
1263 config ISA
1264         bool
1265         help
1266           Find out whether you have ISA slots on your motherboard.  ISA is the
1267           name of a bus system, i.e. the way the CPU talks to the other stuff
1268           inside your box.  Other bus systems are PCI, EISA, MicroChannel
1269           (MCA) or VESA.  ISA is an older system, now being displaced by PCI;
1270           newer boards don't support it.  If you have ISA, say Y, otherwise N.
1271
1272 # Select ISA DMA controller support
1273 config ISA_DMA
1274         bool
1275         select ISA_DMA_API
1276
1277 # Select ISA DMA interface
1278 config ISA_DMA_API
1279         bool
1280
1281 config PCI
1282         bool "PCI support" if MIGHT_HAVE_PCI
1283         help
1284           Find out whether you have a PCI motherboard. PCI is the name of a
1285           bus system, i.e. the way the CPU talks to the other stuff inside
1286           your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1287           VESA. If you have PCI, say Y, otherwise N.
1288
1289 config PCI_DOMAINS
1290         bool
1291         depends on PCI
1292
1293 config PCI_DOMAINS_GENERIC
1294         def_bool PCI_DOMAINS
1295
1296 config PCI_NANOENGINE
1297         bool "BSE nanoEngine PCI support"
1298         depends on SA1100_NANOENGINE
1299         help
1300           Enable PCI on the BSE nanoEngine board.
1301
1302 config PCI_SYSCALL
1303         def_bool PCI
1304
1305 config PCI_HOST_ITE8152
1306         bool
1307         depends on PCI && MACH_ARMCORE
1308         default y
1309         select DMABOUNCE
1310
1311 source "drivers/pci/Kconfig"
1312 source "drivers/pci/pcie/Kconfig"
1313
1314 source "drivers/pcmcia/Kconfig"
1315
1316 endmenu
1317
1318 menu "Kernel Features"
1319
1320 config HAVE_SMP
1321         bool
1322         help
1323           This option should be selected by machines which have an SMP-
1324           capable CPU.
1325
1326           The only effect of this option is to make the SMP-related
1327           options available to the user for configuration.
1328
1329 config SMP
1330         bool "Symmetric Multi-Processing"
1331         depends on CPU_V6K || CPU_V7
1332         depends on GENERIC_CLOCKEVENTS
1333         depends on HAVE_SMP
1334         depends on MMU || ARM_MPU
1335         select IRQ_WORK
1336         help
1337           This enables support for systems with more than one CPU. If you have
1338           a system with only one CPU, say N. If you have a system with more
1339           than one CPU, say Y.
1340
1341           If you say N here, the kernel will run on uni- and multiprocessor
1342           machines, but will use only one CPU of a multiprocessor machine. If
1343           you say Y here, the kernel will run on many, but not all,
1344           uniprocessor machines. On a uniprocessor machine, the kernel
1345           will run faster if you say N here.
1346
1347           See also <file:Documentation/x86/i386/IO-APIC.txt>,
1348           <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1349           <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1350
1351           If you don't know what to do here, say N.
1352
1353 config SMP_ON_UP
1354         bool "Allow booting SMP kernel on uniprocessor systems"
1355         depends on SMP && !XIP_KERNEL && MMU
1356         default y
1357         help
1358           SMP kernels contain instructions which fail on non-SMP processors.
1359           Enabling this option allows the kernel to modify itself to make
1360           these instructions safe.  Disabling it allows about 1K of space
1361           savings.
1362
1363           If you don't know what to do here, say Y.
1364
1365 config ARM_CPU_TOPOLOGY
1366         bool "Support cpu topology definition"
1367         depends on SMP && CPU_V7
1368         default y
1369         help
1370           Support ARM cpu topology definition. The MPIDR register defines
1371           affinity between processors which is then used to describe the cpu
1372           topology of an ARM System.
1373
1374 config SCHED_MC
1375         bool "Multi-core scheduler support"
1376         depends on ARM_CPU_TOPOLOGY
1377         help
1378           Multi-core scheduler support improves the CPU scheduler's decision
1379           making when dealing with multi-core CPU chips at a cost of slightly
1380           increased overhead in some places. If unsure say N here.
1381
1382 config SCHED_SMT
1383         bool "SMT scheduler support"
1384         depends on ARM_CPU_TOPOLOGY
1385         help
1386           Improves the CPU scheduler's decision making when dealing with
1387           MultiThreading at a cost of slightly increased overhead in some
1388           places. If unsure say N here.
1389
1390 config HAVE_ARM_SCU
1391         bool
1392         help
1393           This option enables support for the ARM system coherency unit
1394
1395 config HAVE_ARM_ARCH_TIMER
1396         bool "Architected timer support"
1397         depends on CPU_V7
1398         select ARM_ARCH_TIMER
1399         select GENERIC_CLOCKEVENTS
1400         help
1401           This option enables support for the ARM architected timer
1402
1403 config HAVE_ARM_TWD
1404         bool
1405         select CLKSRC_OF if OF
1406         help
1407           This options enables support for the ARM timer and watchdog unit
1408
1409 config MCPM
1410         bool "Multi-Cluster Power Management"
1411         depends on CPU_V7 && SMP
1412         help
1413           This option provides the common power management infrastructure
1414           for (multi-)cluster based systems, such as big.LITTLE based
1415           systems.
1416
1417 config MCPM_QUAD_CLUSTER
1418         bool
1419         depends on MCPM
1420         help
1421           To avoid wasting resources unnecessarily, MCPM only supports up
1422           to 2 clusters by default.
1423           Platforms with 3 or 4 clusters that use MCPM must select this
1424           option to allow the additional clusters to be managed.
1425
1426 config BIG_LITTLE
1427         bool "big.LITTLE support (Experimental)"
1428         depends on CPU_V7 && SMP
1429         select MCPM
1430         help
1431           This option enables support selections for the big.LITTLE
1432           system architecture.
1433
1434 config BL_SWITCHER
1435         bool "big.LITTLE switcher support"
1436         depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1437         select ARM_CPU_SUSPEND
1438         select CPU_PM
1439         help
1440           The big.LITTLE "switcher" provides the core functionality to
1441           transparently handle transition between a cluster of A15's
1442           and a cluster of A7's in a big.LITTLE system.
1443
1444 config BL_SWITCHER_DUMMY_IF
1445         tristate "Simple big.LITTLE switcher user interface"
1446         depends on BL_SWITCHER && DEBUG_KERNEL
1447         help
1448           This is a simple and dummy char dev interface to control
1449           the big.LITTLE switcher core code.  It is meant for
1450           debugging purposes only.
1451
1452 choice
1453         prompt "Memory split"
1454         depends on MMU
1455         default VMSPLIT_3G
1456         help
1457           Select the desired split between kernel and user memory.
1458
1459           If you are not absolutely sure what you are doing, leave this
1460           option alone!
1461
1462         config VMSPLIT_3G
1463                 bool "3G/1G user/kernel split"
1464         config VMSPLIT_3G_OPT
1465                 bool "3G/1G user/kernel split (for full 1G low memory)"
1466         config VMSPLIT_2G
1467                 bool "2G/2G user/kernel split"
1468         config VMSPLIT_1G
1469                 bool "1G/3G user/kernel split"
1470 endchoice
1471
1472 config PAGE_OFFSET
1473         hex
1474         default PHYS_OFFSET if !MMU
1475         default 0x40000000 if VMSPLIT_1G
1476         default 0x80000000 if VMSPLIT_2G
1477         default 0xB0000000 if VMSPLIT_3G_OPT
1478         default 0xC0000000
1479
1480 config NR_CPUS
1481         int "Maximum number of CPUs (2-32)"
1482         range 2 32
1483         depends on SMP
1484         default "4"
1485
1486 config HOTPLUG_CPU
1487         bool "Support for hot-pluggable CPUs"
1488         depends on SMP
1489         help
1490           Say Y here to experiment with turning CPUs off and on.  CPUs
1491           can be controlled through /sys/devices/system/cpu.
1492
1493 config ARM_PSCI
1494         bool "Support for the ARM Power State Coordination Interface (PSCI)"
1495         depends on HAVE_ARM_SMCCC
1496         select ARM_PSCI_FW
1497         help
1498           Say Y here if you want Linux to communicate with system firmware
1499           implementing the PSCI specification for CPU-centric power
1500           management operations described in ARM document number ARM DEN
1501           0022A ("Power State Coordination Interface System Software on
1502           ARM processors").
1503
1504 # The GPIO number here must be sorted by descending number. In case of
1505 # a multiplatform kernel, we just want the highest value required by the
1506 # selected platforms.
1507 config ARCH_NR_GPIO
1508         int
1509         default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \
1510                 ARCH_ZYNQ
1511         default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1512                 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1513         default 416 if ARCH_SUNXI
1514         default 392 if ARCH_U8500
1515         default 352 if ARCH_VT8500
1516         default 288 if ARCH_ROCKCHIP
1517         default 264 if MACH_H4700
1518         default 0
1519         help
1520           Maximum number of GPIOs in the system.
1521
1522           If unsure, leave the default value.
1523
1524 source kernel/Kconfig.preempt
1525
1526 config HZ_FIXED
1527         int
1528         default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1529                 ARCH_S5PV210 || ARCH_EXYNOS4
1530         default 128 if SOC_AT91RM9200
1531         default 0
1532
1533 choice
1534         depends on HZ_FIXED = 0
1535         prompt "Timer frequency"
1536
1537 config HZ_100
1538         bool "100 Hz"
1539
1540 config HZ_200
1541         bool "200 Hz"
1542
1543 config HZ_250
1544         bool "250 Hz"
1545
1546 config HZ_300
1547         bool "300 Hz"
1548
1549 config HZ_500
1550         bool "500 Hz"
1551
1552 config HZ_1000
1553         bool "1000 Hz"
1554
1555 endchoice
1556
1557 config HZ
1558         int
1559         default HZ_FIXED if HZ_FIXED != 0
1560         default 100 if HZ_100
1561         default 200 if HZ_200
1562         default 250 if HZ_250
1563         default 300 if HZ_300
1564         default 500 if HZ_500
1565         default 1000
1566
1567 config SCHED_HRTICK
1568         def_bool HIGH_RES_TIMERS
1569
1570 config THUMB2_KERNEL
1571         bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1572         depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1573         default y if CPU_THUMBONLY
1574         select AEABI
1575         select ARM_ASM_UNIFIED
1576         select ARM_UNWIND
1577         help
1578           By enabling this option, the kernel will be compiled in
1579           Thumb-2 mode. A compiler/assembler that understand the unified
1580           ARM-Thumb syntax is needed.
1581
1582           If unsure, say N.
1583
1584 config THUMB2_AVOID_R_ARM_THM_JUMP11
1585         bool "Work around buggy Thumb-2 short branch relocations in gas"
1586         depends on THUMB2_KERNEL && MODULES
1587         default y
1588         help
1589           Various binutils versions can resolve Thumb-2 branches to
1590           locally-defined, preemptible global symbols as short-range "b.n"
1591           branch instructions.
1592
1593           This is a problem, because there's no guarantee the final
1594           destination of the symbol, or any candidate locations for a
1595           trampoline, are within range of the branch.  For this reason, the
1596           kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1597           relocation in modules at all, and it makes little sense to add
1598           support.
1599
1600           The symptom is that the kernel fails with an "unsupported
1601           relocation" error when loading some modules.
1602
1603           Until fixed tools are available, passing
1604           -fno-optimize-sibling-calls to gcc should prevent gcc generating
1605           code which hits this problem, at the cost of a bit of extra runtime
1606           stack usage in some cases.
1607
1608           The problem is described in more detail at:
1609               https://bugs.launchpad.net/binutils-linaro/+bug/725126
1610
1611           Only Thumb-2 kernels are affected.
1612
1613           Unless you are sure your tools don't have this problem, say Y.
1614
1615 config ARM_ASM_UNIFIED
1616         bool
1617
1618 config ARM_PATCH_IDIV
1619         bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1620         depends on CPU_32v7 && !XIP_KERNEL
1621         default y
1622         help
1623           The ARM compiler inserts calls to __aeabi_idiv() and
1624           __aeabi_uidiv() when it needs to perform division on signed
1625           and unsigned integers. Some v7 CPUs have support for the sdiv
1626           and udiv instructions that can be used to implement those
1627           functions.
1628
1629           Enabling this option allows the kernel to modify itself to
1630           replace the first two instructions of these library functions
1631           with the sdiv or udiv plus "bx lr" instructions when the CPU
1632           it is running on supports them. Typically this will be faster
1633           and less power intensive than running the original library
1634           code to do integer division.
1635
1636 config AEABI
1637         bool "Use the ARM EABI to compile the kernel"
1638         help
1639           This option allows for the kernel to be compiled using the latest
1640           ARM ABI (aka EABI).  This is only useful if you are using a user
1641           space environment that is also compiled with EABI.
1642
1643           Since there are major incompatibilities between the legacy ABI and
1644           EABI, especially with regard to structure member alignment, this
1645           option also changes the kernel syscall calling convention to
1646           disambiguate both ABIs and allow for backward compatibility support
1647           (selected with CONFIG_OABI_COMPAT).
1648
1649           To use this you need GCC version 4.0.0 or later.
1650
1651 config OABI_COMPAT
1652         bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1653         depends on AEABI && !THUMB2_KERNEL
1654         help
1655           This option preserves the old syscall interface along with the
1656           new (ARM EABI) one. It also provides a compatibility layer to
1657           intercept syscalls that have structure arguments which layout
1658           in memory differs between the legacy ABI and the new ARM EABI
1659           (only for non "thumb" binaries). This option adds a tiny
1660           overhead to all syscalls and produces a slightly larger kernel.
1661
1662           The seccomp filter system will not be available when this is
1663           selected, since there is no way yet to sensibly distinguish
1664           between calling conventions during filtering.
1665
1666           If you know you'll be using only pure EABI user space then you
1667           can say N here. If this option is not selected and you attempt
1668           to execute a legacy ABI binary then the result will be
1669           UNPREDICTABLE (in fact it can be predicted that it won't work
1670           at all). If in doubt say N.
1671
1672 config ARCH_HAS_HOLES_MEMORYMODEL
1673         bool
1674
1675 config ARCH_SPARSEMEM_ENABLE
1676         bool
1677
1678 config ARCH_SPARSEMEM_DEFAULT
1679         def_bool ARCH_SPARSEMEM_ENABLE
1680
1681 config ARCH_SELECT_MEMORY_MODEL
1682         def_bool ARCH_SPARSEMEM_ENABLE
1683
1684 config HAVE_ARCH_PFN_VALID
1685         def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1686
1687 config HAVE_GENERIC_RCU_GUP
1688         def_bool y
1689         depends on ARM_LPAE
1690
1691 config HIGHMEM
1692         bool "High Memory Support"
1693         depends on MMU
1694         help
1695           The address space of ARM processors is only 4 Gigabytes large
1696           and it has to accommodate user address space, kernel address
1697           space as well as some memory mapped IO. That means that, if you
1698           have a large amount of physical memory and/or IO, not all of the
1699           memory can be "permanently mapped" by the kernel. The physical
1700           memory that is not permanently mapped is called "high memory".
1701
1702           Depending on the selected kernel/user memory split, minimum
1703           vmalloc space and actual amount of RAM, you may not need this
1704           option which should result in a slightly faster kernel.
1705
1706           If unsure, say n.
1707
1708 config HIGHPTE
1709         bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1710         depends on HIGHMEM
1711         default y
1712         help
1713           The VM uses one page of physical memory for each page table.
1714           For systems with a lot of processes, this can use a lot of
1715           precious low memory, eventually leading to low memory being
1716           consumed by page tables.  Setting this option will allow
1717           user-space 2nd level page tables to reside in high memory.
1718
1719 config CPU_SW_DOMAIN_PAN
1720         bool "Enable use of CPU domains to implement privileged no-access"
1721         depends on MMU && !ARM_LPAE
1722         default y
1723         help
1724           Increase kernel security by ensuring that normal kernel accesses
1725           are unable to access userspace addresses.  This can help prevent
1726           use-after-free bugs becoming an exploitable privilege escalation
1727           by ensuring that magic values (such as LIST_POISON) will always
1728           fault when dereferenced.
1729
1730           CPUs with low-vector mappings use a best-efforts implementation.
1731           Their lower 1MB needs to remain accessible for the vectors, but
1732           the remainder of userspace will become appropriately inaccessible.
1733
1734 config HW_PERF_EVENTS
1735         def_bool y
1736         depends on ARM_PMU
1737
1738 config SYS_SUPPORTS_HUGETLBFS
1739        def_bool y
1740        depends on ARM_LPAE
1741
1742 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1743        def_bool y
1744        depends on ARM_LPAE
1745
1746 config ARCH_WANT_GENERAL_HUGETLB
1747         def_bool y
1748
1749 config ARM_MODULE_PLTS
1750         bool "Use PLTs to allow module memory to spill over into vmalloc area"
1751         depends on MODULES
1752         help
1753           Allocate PLTs when loading modules so that jumps and calls whose
1754           targets are too far away for their relative offsets to be encoded
1755           in the instructions themselves can be bounced via veneers in the
1756           module's PLT. This allows modules to be allocated in the generic
1757           vmalloc area after the dedicated module memory area has been
1758           exhausted. The modules will use slightly more memory, but after
1759           rounding up to page size, the actual memory footprint is usually
1760           the same.
1761
1762           Say y if you are getting out of memory errors while loading modules
1763
1764 source "mm/Kconfig"
1765
1766 config FORCE_MAX_ZONEORDER
1767         int "Maximum zone order"
1768         default "12" if SOC_AM33XX
1769         default "9" if SA1111 || ARCH_EFM32
1770         default "11"
1771         help
1772           The kernel memory allocator divides physically contiguous memory
1773           blocks into "zones", where each zone is a power of two number of
1774           pages.  This option selects the largest power of two that the kernel
1775           keeps in the memory allocator.  If you need to allocate very large
1776           blocks of physically contiguous memory, then you may need to
1777           increase this value.
1778
1779           This config option is actually maximum order plus one. For example,
1780           a value of 11 means that the largest free memory block is 2^10 pages.
1781
1782 config ALIGNMENT_TRAP
1783         bool
1784         depends on CPU_CP15_MMU
1785         default y if !ARCH_EBSA110
1786         select HAVE_PROC_CPU if PROC_FS
1787         help
1788           ARM processors cannot fetch/store information which is not
1789           naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1790           address divisible by 4. On 32-bit ARM processors, these non-aligned
1791           fetch/store instructions will be emulated in software if you say
1792           here, which has a severe performance impact. This is necessary for
1793           correct operation of some network protocols. With an IP-only
1794           configuration it is safe to say N, otherwise say Y.
1795
1796 config UACCESS_WITH_MEMCPY
1797         bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1798         depends on MMU
1799         default y if CPU_FEROCEON
1800         help
1801           Implement faster copy_to_user and clear_user methods for CPU
1802           cores where a 8-word STM instruction give significantly higher
1803           memory write throughput than a sequence of individual 32bit stores.
1804
1805           A possible side effect is a slight increase in scheduling latency
1806           between threads sharing the same address space if they invoke
1807           such copy operations with large buffers.
1808
1809           However, if the CPU data cache is using a write-allocate mode,
1810           this option is unlikely to provide any performance gain.
1811
1812 config SECCOMP
1813         bool
1814         prompt "Enable seccomp to safely compute untrusted bytecode"
1815         ---help---
1816           This kernel feature is useful for number crunching applications
1817           that may need to compute untrusted bytecode during their
1818           execution. By using pipes or other transports made available to
1819           the process as file descriptors supporting the read/write
1820           syscalls, it's possible to isolate those applications in
1821           their own address space using seccomp. Once seccomp is
1822           enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1823           and the task is only allowed to execute a few safe syscalls
1824           defined by each seccomp mode.
1825
1826 config SWIOTLB
1827         def_bool y
1828
1829 config IOMMU_HELPER
1830         def_bool SWIOTLB
1831
1832 config PARAVIRT
1833         bool "Enable paravirtualization code"
1834         help
1835           This changes the kernel so it can modify itself when it is run
1836           under a hypervisor, potentially improving performance significantly
1837           over full virtualization.
1838
1839 config PARAVIRT_TIME_ACCOUNTING
1840         bool "Paravirtual steal time accounting"
1841         select PARAVIRT
1842         default n
1843         help
1844           Select this option to enable fine granularity task steal time
1845           accounting. Time spent executing other tasks in parallel with
1846           the current vCPU is discounted from the vCPU power. To account for
1847           that, there can be a small performance impact.
1848
1849           If in doubt, say N here.
1850
1851 config XEN_DOM0
1852         def_bool y
1853         depends on XEN
1854
1855 config XEN
1856         bool "Xen guest support on ARM"
1857         depends on ARM && AEABI && OF
1858         depends on CPU_V7 && !CPU_V6
1859         depends on !GENERIC_ATOMIC64
1860         depends on MMU
1861         select ARCH_DMA_ADDR_T_64BIT
1862         select ARM_PSCI
1863         select SWIOTLB_XEN
1864         select PARAVIRT
1865         help
1866           Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1867
1868 endmenu
1869
1870 menu "Boot options"
1871
1872 config USE_OF
1873         bool "Flattened Device Tree support"
1874         select IRQ_DOMAIN
1875         select OF
1876         help
1877           Include support for flattened device tree machine descriptions.
1878
1879 config ATAGS
1880         bool "Support for the traditional ATAGS boot data passing" if USE_OF
1881         default y
1882         help
1883           This is the traditional way of passing data to the kernel at boot
1884           time. If you are solely relying on the flattened device tree (or
1885           the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1886           to remove ATAGS support from your kernel binary.  If unsure,
1887           leave this to y.
1888
1889 config DEPRECATED_PARAM_STRUCT
1890         bool "Provide old way to pass kernel parameters"
1891         depends on ATAGS
1892         help
1893           This was deprecated in 2001 and announced to live on for 5 years.
1894           Some old boot loaders still use this way.
1895
1896 # Compressed boot loader in ROM.  Yes, we really want to ask about
1897 # TEXT and BSS so we preserve their values in the config files.
1898 config ZBOOT_ROM_TEXT
1899         hex "Compressed ROM boot loader base address"
1900         default "0"
1901         help
1902           The physical address at which the ROM-able zImage is to be
1903           placed in the target.  Platforms which normally make use of
1904           ROM-able zImage formats normally set this to a suitable
1905           value in their defconfig file.
1906
1907           If ZBOOT_ROM is not enabled, this has no effect.
1908
1909 config ZBOOT_ROM_BSS
1910         hex "Compressed ROM boot loader BSS address"
1911         default "0"
1912         help
1913           The base address of an area of read/write memory in the target
1914           for the ROM-able zImage which must be available while the
1915           decompressor is running. It must be large enough to hold the
1916           entire decompressed kernel plus an additional 128 KiB.
1917           Platforms which normally make use of ROM-able zImage formats
1918           normally set this to a suitable value in their defconfig file.
1919
1920           If ZBOOT_ROM is not enabled, this has no effect.
1921
1922 config ZBOOT_ROM
1923         bool "Compressed boot loader in ROM/flash"
1924         depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1925         depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1926         help
1927           Say Y here if you intend to execute your compressed kernel image
1928           (zImage) directly from ROM or flash.  If unsure, say N.
1929
1930 config ARM_APPENDED_DTB
1931         bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1932         depends on OF
1933         help
1934           With this option, the boot code will look for a device tree binary
1935           (DTB) appended to zImage
1936           (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1937
1938           This is meant as a backward compatibility convenience for those
1939           systems with a bootloader that can't be upgraded to accommodate
1940           the documented boot protocol using a device tree.
1941
1942           Beware that there is very little in terms of protection against
1943           this option being confused by leftover garbage in memory that might
1944           look like a DTB header after a reboot if no actual DTB is appended
1945           to zImage.  Do not leave this option active in a production kernel
1946           if you don't intend to always append a DTB.  Proper passing of the
1947           location into r2 of a bootloader provided DTB is always preferable
1948           to this option.
1949
1950 config ARM_ATAG_DTB_COMPAT
1951         bool "Supplement the appended DTB with traditional ATAG information"
1952         depends on ARM_APPENDED_DTB
1953         help
1954           Some old bootloaders can't be updated to a DTB capable one, yet
1955           they provide ATAGs with memory configuration, the ramdisk address,
1956           the kernel cmdline string, etc.  Such information is dynamically
1957           provided by the bootloader and can't always be stored in a static
1958           DTB.  To allow a device tree enabled kernel to be used with such
1959           bootloaders, this option allows zImage to extract the information
1960           from the ATAG list and store it at run time into the appended DTB.
1961
1962 choice
1963         prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1964         default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1965
1966 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1967         bool "Use bootloader kernel arguments if available"
1968         help
1969           Uses the command-line options passed by the boot loader instead of
1970           the device tree bootargs property. If the boot loader doesn't provide
1971           any, the device tree bootargs property will be used.
1972
1973 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1974         bool "Extend with bootloader kernel arguments"
1975         help
1976           The command-line arguments provided by the boot loader will be
1977           appended to the the device tree bootargs property.
1978
1979 endchoice
1980
1981 config CMDLINE
1982         string "Default kernel command string"
1983         default ""
1984         help
1985           On some architectures (EBSA110 and CATS), there is currently no way
1986           for the boot loader to pass arguments to the kernel. For these
1987           architectures, you should supply some command-line options at build
1988           time by entering them here. As a minimum, you should specify the
1989           memory size and the root device (e.g., mem=64M root=/dev/nfs).
1990
1991 choice
1992         prompt "Kernel command line type" if CMDLINE != ""
1993         default CMDLINE_FROM_BOOTLOADER
1994         depends on ATAGS
1995
1996 config CMDLINE_FROM_BOOTLOADER
1997         bool "Use bootloader kernel arguments if available"
1998         help
1999           Uses the command-line options passed by the boot loader. If
2000           the boot loader doesn't provide any, the default kernel command
2001           string provided in CMDLINE will be used.
2002
2003 config CMDLINE_EXTEND
2004         bool "Extend bootloader kernel arguments"
2005         help
2006           The command-line arguments provided by the boot loader will be
2007           appended to the default kernel command string.
2008
2009 config CMDLINE_FORCE
2010         bool "Always use the default kernel command string"
2011         help
2012           Always use the default kernel command string, even if the boot
2013           loader passes other arguments to the kernel.
2014           This is useful if you cannot or don't want to change the
2015           command-line options your boot loader passes to the kernel.
2016 endchoice
2017
2018 config XIP_KERNEL
2019         bool "Kernel Execute-In-Place from ROM"
2020         depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
2021         help
2022           Execute-In-Place allows the kernel to run from non-volatile storage
2023           directly addressable by the CPU, such as NOR flash. This saves RAM
2024           space since the text section of the kernel is not loaded from flash
2025           to RAM.  Read-write sections, such as the data section and stack,
2026           are still copied to RAM.  The XIP kernel is not compressed since
2027           it has to run directly from flash, so it will take more space to
2028           store it.  The flash address used to link the kernel object files,
2029           and for storing it, is configuration dependent. Therefore, if you
2030           say Y here, you must know the proper physical address where to
2031           store the kernel image depending on your own flash memory usage.
2032
2033           Also note that the make target becomes "make xipImage" rather than
2034           "make zImage" or "make Image".  The final kernel binary to put in
2035           ROM memory will be arch/arm/boot/xipImage.
2036
2037           If unsure, say N.
2038
2039 config XIP_PHYS_ADDR
2040         hex "XIP Kernel Physical Location"
2041         depends on XIP_KERNEL
2042         default "0x00080000"
2043         help
2044           This is the physical address in your flash memory the kernel will
2045           be linked for and stored to.  This address is dependent on your
2046           own flash usage.
2047
2048 config KEXEC
2049         bool "Kexec system call (EXPERIMENTAL)"
2050         depends on (!SMP || PM_SLEEP_SMP)
2051         depends on !CPU_V7M
2052         select KEXEC_CORE
2053         help
2054           kexec is a system call that implements the ability to shutdown your
2055           current kernel, and to start another kernel.  It is like a reboot
2056           but it is independent of the system firmware.   And like a reboot
2057           you can start any kernel with it, not just Linux.
2058
2059           It is an ongoing process to be certain the hardware in a machine
2060           is properly shutdown, so do not be surprised if this code does not
2061           initially work for you.
2062
2063 config ATAGS_PROC
2064         bool "Export atags in procfs"
2065         depends on ATAGS && KEXEC
2066         default y
2067         help
2068           Should the atags used to boot the kernel be exported in an "atags"
2069           file in procfs. Useful with kexec.
2070
2071 config CRASH_DUMP
2072         bool "Build kdump crash kernel (EXPERIMENTAL)"
2073         help
2074           Generate crash dump after being started by kexec. This should
2075           be normally only set in special crash dump kernels which are
2076           loaded in the main kernel with kexec-tools into a specially
2077           reserved region and then later executed after a crash by
2078           kdump/kexec. The crash dump kernel must be compiled to a
2079           memory address not used by the main kernel
2080
2081           For more details see Documentation/kdump/kdump.txt
2082
2083 config AUTO_ZRELADDR
2084         bool "Auto calculation of the decompressed kernel image address"
2085         help
2086           ZRELADDR is the physical address where the decompressed kernel
2087           image will be placed. If AUTO_ZRELADDR is selected, the address
2088           will be determined at run-time by masking the current IP with
2089           0xf8000000. This assumes the zImage being placed in the first 128MB
2090           from start of memory.
2091
2092 config EFI_STUB
2093         bool
2094
2095 config EFI
2096         bool "UEFI runtime support"
2097         depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
2098         select UCS2_STRING
2099         select EFI_PARAMS_FROM_FDT
2100         select EFI_STUB
2101         select EFI_ARMSTUB
2102         select EFI_RUNTIME_WRAPPERS
2103         ---help---
2104           This option provides support for runtime services provided
2105           by UEFI firmware (such as non-volatile variables, realtime
2106           clock, and platform reset). A UEFI stub is also provided to
2107           allow the kernel to be booted as an EFI application. This
2108           is only useful for kernels that may run on systems that have
2109           UEFI firmware.
2110
2111 endmenu
2112
2113 menu "CPU Power Management"
2114
2115 source "drivers/cpufreq/Kconfig"
2116
2117 source "drivers/cpuidle/Kconfig"
2118
2119 endmenu
2120
2121 menu "Floating point emulation"
2122
2123 comment "At least one emulation must be selected"
2124
2125 config FPE_NWFPE
2126         bool "NWFPE math emulation"
2127         depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2128         ---help---
2129           Say Y to include the NWFPE floating point emulator in the kernel.
2130           This is necessary to run most binaries. Linux does not currently
2131           support floating point hardware so you need to say Y here even if
2132           your machine has an FPA or floating point co-processor podule.
2133
2134           You may say N here if you are going to load the Acorn FPEmulator
2135           early in the bootup.
2136
2137 config FPE_NWFPE_XP
2138         bool "Support extended precision"
2139         depends on FPE_NWFPE
2140         help
2141           Say Y to include 80-bit support in the kernel floating-point
2142           emulator.  Otherwise, only 32 and 64-bit support is compiled in.
2143           Note that gcc does not generate 80-bit operations by default,
2144           so in most cases this option only enlarges the size of the
2145           floating point emulator without any good reason.
2146
2147           You almost surely want to say N here.
2148
2149 config FPE_FASTFPE
2150         bool "FastFPE math emulation (EXPERIMENTAL)"
2151         depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2152         ---help---
2153           Say Y here to include the FAST floating point emulator in the kernel.
2154           This is an experimental much faster emulator which now also has full
2155           precision for the mantissa.  It does not support any exceptions.
2156           It is very simple, and approximately 3-6 times faster than NWFPE.
2157
2158           It should be sufficient for most programs.  It may be not suitable
2159           for scientific calculations, but you have to check this for yourself.
2160           If you do not feel you need a faster FP emulation you should better
2161           choose NWFPE.
2162
2163 config VFP
2164         bool "VFP-format floating point maths"
2165         depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2166         help
2167           Say Y to include VFP support code in the kernel. This is needed
2168           if your hardware includes a VFP unit.
2169
2170           Please see <file:Documentation/arm/VFP/release-notes.txt> for
2171           release notes and additional status information.
2172
2173           Say N if your target does not have VFP hardware.
2174
2175 config VFPv3
2176         bool
2177         depends on VFP
2178         default y if CPU_V7
2179
2180 config NEON
2181         bool "Advanced SIMD (NEON) Extension support"
2182         depends on VFPv3 && CPU_V7
2183         help
2184           Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2185           Extension.
2186
2187 config KERNEL_MODE_NEON
2188         bool "Support for NEON in kernel mode"
2189         depends on NEON && AEABI
2190         help
2191           Say Y to include support for NEON in kernel mode.
2192
2193 endmenu
2194
2195 menu "Userspace binary formats"
2196
2197 source "fs/Kconfig.binfmt"
2198
2199 endmenu
2200
2201 menu "Power management options"
2202
2203 source "kernel/power/Kconfig"
2204
2205 config ARCH_SUSPEND_POSSIBLE
2206         depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2207                 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2208         def_bool y
2209
2210 config ARM_CPU_SUSPEND
2211         def_bool PM_SLEEP
2212
2213 config ARCH_HIBERNATION_POSSIBLE
2214         bool
2215         depends on MMU
2216         default y if ARCH_SUSPEND_POSSIBLE
2217
2218 endmenu
2219
2220 source "net/Kconfig"
2221
2222 source "drivers/Kconfig"
2223
2224 source "drivers/firmware/Kconfig"
2225
2226 source "fs/Kconfig"
2227
2228 source "arch/arm/Kconfig.debug"
2229
2230 source "security/Kconfig"
2231
2232 source "crypto/Kconfig"
2233 if CRYPTO
2234 source "arch/arm/crypto/Kconfig"
2235 endif
2236
2237 source "lib/Kconfig"
2238
2239 source "arch/arm/kvm/Kconfig"