arch/arm/Kconfig

   1 config ARM
   2         bool
   3         default y
   4         select ARCH_BINFMT_ELF_RANDOMIZE_PIE
   5         select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
   6         select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
   7         select ARCH_HAVE_CUSTOM_GPIO_H
   8         select ARCH_HAS_GCOV_PROFILE_ALL
   9         select ARCH_MIGHT_HAVE_PC_PARPORT
  10         select ARCH_SUPPORTS_ATOMIC_RMW
  11         select ARCH_USE_BUILTIN_BSWAP
  12         select ARCH_USE_CMPXCHG_LOCKREF
  13         select ARCH_WANT_IPC_PARSE_VERSION
  14         select BUILDTIME_EXTABLE_SORT if MMU
  15         select CLONE_BACKWARDS
  16         select CPU_PM if (SUSPEND || CPU_IDLE)
  17         select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
  18         select GENERIC_ALLOCATOR
  19         select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
  20         select GENERIC_CLOCKEVENTS_BROADCAST if SMP
  21         select GENERIC_IDLE_POLL_SETUP
  22         select GENERIC_IRQ_PROBE
  23         select GENERIC_IRQ_SHOW
  24         select GENERIC_PCI_IOMAP
  25         select GENERIC_SCHED_CLOCK
  26         select GENERIC_SMP_IDLE_THREAD
  27         select GENERIC_STRNCPY_FROM_USER
  28         select GENERIC_STRNLEN_USER
  29         select HANDLE_DOMAIN_IRQ
  30         select HARDIRQS_SW_RESEND
  31         select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
  32         select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
  33         select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
  34         select HAVE_ARCH_KGDB
  35         select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
  36         select HAVE_ARCH_TRACEHOOK
  37         select HAVE_BPF_JIT
  38         select HAVE_CC_STACKPROTECTOR
  39         select HAVE_CONTEXT_TRACKING
  40         select HAVE_C_RECORDMCOUNT
  41         select HAVE_DEBUG_KMEMLEAK
  42         select HAVE_DMA_API_DEBUG
  43         select HAVE_DMA_ATTRS
  44         select HAVE_DMA_CONTIGUOUS if MMU
  45         select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
  46         select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
  47         select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
  48         select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
  49         select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
  50         select HAVE_GENERIC_DMA_COHERENT
  51         select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
  52         select HAVE_IDE if PCI || ISA || PCMCIA
  53         select HAVE_IRQ_TIME_ACCOUNTING
  54         select HAVE_KERNEL_GZIP
  55         select HAVE_KERNEL_LZ4
  56         select HAVE_KERNEL_LZMA
  57         select HAVE_KERNEL_LZO
  58         select HAVE_KERNEL_XZ
  59         select HAVE_KPROBES if !XIP_KERNEL
  60         select HAVE_KRETPROBES if (HAVE_KPROBES)
  61         select HAVE_MEMBLOCK
  62         select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
  63         select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
  64         select HAVE_OPTPROBES if !THUMB2_KERNEL
  65         select HAVE_PERF_EVENTS
  66         select HAVE_PERF_REGS
  67         select HAVE_PERF_USER_STACK_DUMP
  68         select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
  69         select HAVE_REGS_AND_STACK_ACCESS_API
  70         select HAVE_SYSCALL_TRACEPOINTS
  71         select HAVE_UID16
  72         select HAVE_VIRT_CPU_ACCOUNTING_GEN
  73         select IRQ_FORCED_THREADING
  74         select MODULES_USE_ELF_REL
  75         select NO_BOOTMEM
  76         select OLD_SIGACTION
  77         select OLD_SIGSUSPEND3
  78         select PERF_USE_VMALLOC
  79         select RTC_LIB
  80         select SYS_SUPPORTS_APM_EMULATION
  81         # Above selects are sorted alphabetically; please add new ones
  82         # according to that.  Thanks.
  83         help
  84           The ARM series is a line of low-power-consumption RISC chip designs
  85           licensed by ARM Ltd and targeted at embedded applications and
  86           handhelds such as the Compaq IPAQ.  ARM-based PCs are no longer
  87           manufactured, but legacy ARM-based PC hardware remains popular in
  88           Europe.  There is an ARM Linux project with a web page at
  89           <http://www.arm.linux.org.uk/>.
  90
  91 config ARM_HAS_SG_CHAIN
  92         select ARCH_HAS_SG_CHAIN
  93         bool
  94
  95 config NEED_SG_DMA_LENGTH
  96         bool
  97
  98 config ARM_DMA_USE_IOMMU
  99         bool
 100         select ARM_HAS_SG_CHAIN
 101         select NEED_SG_DMA_LENGTH
 102
 103 if ARM_DMA_USE_IOMMU
 104
 105 config ARM_DMA_IOMMU_ALIGNMENT
 106         int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
 107         range 4 9
 108         default 8
 109         help
 110           DMA mapping framework by default aligns all buffers to the smallest
 111           PAGE_SIZE order which is greater than or equal to the requested buffer
 112           size. This works well for buffers up to a few hundreds kilobytes, but
 113           for larger buffers it just a waste of address space. Drivers which has
 114           relatively small addressing window (like 64Mib) might run out of
 115           virtual space with just a few allocations.
 116
 117           With this parameter you can specify the maximum PAGE_SIZE order for
 118           DMA IOMMU buffers. Larger buffers will be aligned only to this
 119           specified order. The order is expressed as a power of two multiplied
 120           by the PAGE_SIZE.
 121
 122 endif
 123
 124 config MIGHT_HAVE_PCI
 125         bool
 126
 127 config SYS_SUPPORTS_APM_EMULATION
 128         bool
 129
 130 config HAVE_TCM
 131         bool
 132         select GENERIC_ALLOCATOR
 133
 134 config HAVE_PROC_CPU
 135         bool
 136
 137 config NO_IOPORT_MAP
 138         bool
 139
 140 config EISA
 141         bool
 142         ---help---
 143           The Extended Industry Standard Architecture (EISA) bus was
 144           developed as an open alternative to the IBM MicroChannel bus.
 145
 146           The EISA bus provided some of the features of the IBM MicroChannel
 147           bus while maintaining backward compatibility with cards made for
 148           the older ISA bus.  The EISA bus saw limited use between 1988 and
 149           1995 when it was made obsolete by the PCI bus.
 150
 151           Say Y here if you are building a kernel for an EISA-based machine.
 152
 153           Otherwise, say N.
 154
 155 config SBUS
 156         bool
 157
 158 config STACKTRACE_SUPPORT
 159         bool
 160         default y
 161
 162 config HAVE_LATENCYTOP_SUPPORT
 163         bool
 164         depends on !SMP
 165         default y
 166
 167 config LOCKDEP_SUPPORT
 168         bool
 169         default y
 170
 171 config TRACE_IRQFLAGS_SUPPORT
 172         bool
 173         default y
 174
 175 config RWSEM_XCHGADD_ALGORITHM
 176         bool
 177         default y
 178
 179 config ARCH_HAS_ILOG2_U32
 180         bool
 181
 182 config ARCH_HAS_ILOG2_U64
 183         bool
 184
 185 config ARCH_HAS_BANDGAP
 186         bool
 187
 188 config GENERIC_HWEIGHT
 189         bool
 190         default y
 191
 192 config GENERIC_CALIBRATE_DELAY
 193         bool
 194         default y
 195
 196 config ARCH_MAY_HAVE_PC_FDC
 197         bool
 198
 199 config ZONE_DMA
 200         bool
 201
 202 config NEED_DMA_MAP_STATE
 203        def_bool y
 204
 205 config ARCH_SUPPORTS_UPROBES
 206         def_bool y
 207
 208 config ARCH_HAS_DMA_SET_COHERENT_MASK
 209         bool
 210
 211 config GENERIC_ISA_DMA
 212         bool
 213
 214 config FIQ
 215         bool
 216
 217 config NEED_RET_TO_USER
 218         bool
 219
 220 config ARCH_MTD_XIP
 221         bool
 222
 223 config VECTORS_BASE
 224         hex
 225         default 0xffff0000 if MMU || CPU_HIGH_VECTOR
 226         default DRAM_BASE if REMAP_VECTORS_TO_RAM
 227         default 0x00000000
 228         help
 229           The base address of exception vectors.  This must be two pages
 230           in size.
 231
 232 config ARM_PATCH_PHYS_VIRT
 233         bool "Patch physical to virtual translations at runtime" if EMBEDDED
 234         default y
 235         depends on !XIP_KERNEL && MMU
 236         depends on !ARCH_REALVIEW || !SPARSEMEM
 237         help
 238           Patch phys-to-virt and virt-to-phys translation functions at
 239           boot and module load time according to the position of the
 240           kernel in system memory.
 241
 242           This can only be used with non-XIP MMU kernels where the base
 243           of physical memory is at a 16MB boundary.
 244
 245           Only disable this option if you know that you do not require
 246           this feature (eg, building a kernel for a single machine) and
 247           you need to shrink the kernel to the minimal size.
 248
 249 config NEED_MACH_IO_H
 250         bool
 251         help
 252           Select this when mach/io.h is required to provide special
 253           definitions for this platform.  The need for mach/io.h should
 254           be avoided when possible.
 255
 256 config NEED_MACH_MEMORY_H
 257         bool
 258         help
 259           Select this when mach/memory.h is required to provide special
 260           definitions for this platform.  The need for mach/memory.h should
 261           be avoided when possible.
 262
 263 config PHYS_OFFSET
 264         hex "Physical address of main memory" if MMU
 265         depends on !ARM_PATCH_PHYS_VIRT
 266         default DRAM_BASE if !MMU
 267         default 0x00000000 if ARCH_EBSA110 || \
 268                         EP93XX_SDCE3_SYNC_PHYS_OFFSET || \
 269                         ARCH_FOOTBRIDGE || \
 270                         ARCH_INTEGRATOR || \
 271                         ARCH_IOP13XX || \
 272                         ARCH_KS8695 || \
 273                         (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET)
 274         default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
 275         default 0x20000000 if ARCH_S5PV210
 276         default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET
 277         default 0xc0000000 if EP93XX_SDCE0_PHYS_OFFSET || ARCH_SA1100
 278         default 0xd0000000 if EP93XX_SDCE1_PHYS_OFFSET
 279         default 0xe0000000 if EP93XX_SDCE2_PHYS_OFFSET
 280         default 0xf0000000 if EP93XX_SDCE3_ASYNC_PHYS_OFFSET
 281         help
 282           Please provide the physical address corresponding to the
 283           location of main memory in your system.
 284
 285 config GENERIC_BUG
 286         def_bool y
 287         depends on BUG
 288
 289 source "init/Kconfig"
 290
 291 source "kernel/Kconfig.freezer"
 292
 293 menu "System Type"
 294
 295 config MMU
 296         bool "MMU-based Paged Memory Management Support"
 297         default y
 298         help
 299           Select if you want MMU-based virtualised addressing space
 300           support by paged memory management. If unsure, say 'Y'.
 301
 302 #
 303 # The "ARM system type" choice list is ordered alphabetically by option
 304 # text.  Please add new entries in the option alphabetic order.
 305 #
 306 choice
 307         prompt "ARM system type"
 308         default ARCH_VERSATILE if !MMU
 309         default ARCH_MULTIPLATFORM if MMU
 310
 311 config ARCH_MULTIPLATFORM
 312         bool "Allow multiple platforms to be selected"
 313         depends on MMU
 314         select ARCH_WANT_OPTIONAL_GPIOLIB
 315         select ARM_HAS_SG_CHAIN
 316         select ARM_PATCH_PHYS_VIRT
 317         select AUTO_ZRELADDR
 318         select CLKSRC_OF
 319         select COMMON_CLK
 320         select GENERIC_CLOCKEVENTS
 321         select MIGHT_HAVE_PCI
 322         select MULTI_IRQ_HANDLER
 323         select SPARSE_IRQ
 324         select USE_OF
 325
 326 config ARCH_REALVIEW
 327         bool "ARM Ltd. RealView family"
 328         select ARCH_WANT_OPTIONAL_GPIOLIB
 329         select ARM_AMBA
 330         select ARM_TIMER_SP804
 331         select COMMON_CLK
 332         select COMMON_CLK_VERSATILE
 333         select GENERIC_CLOCKEVENTS
 334         select GPIO_PL061 if GPIOLIB
 335         select ICST
 336         select NEED_MACH_MEMORY_H
 337         select PLAT_VERSATILE
 338         select PLAT_VERSATILE_SCHED_CLOCK
 339         help
 340           This enables support for ARM Ltd RealView boards.
 341
 342 config ARCH_VERSATILE
 343         bool "ARM Ltd. Versatile family"
 344         select ARCH_WANT_OPTIONAL_GPIOLIB
 345         select ARM_AMBA
 346         select ARM_TIMER_SP804
 347         select ARM_VIC
 348         select CLKDEV_LOOKUP
 349         select GENERIC_CLOCKEVENTS
 350         select HAVE_MACH_CLKDEV
 351         select ICST
 352         select PLAT_VERSATILE
 353         select PLAT_VERSATILE_CLOCK
 354         select PLAT_VERSATILE_SCHED_CLOCK
 355         select VERSATILE_FPGA_IRQ
 356         help
 357           This enables support for ARM Ltd Versatile board.
 358
 359 config ARCH_AT91
 360         bool "Atmel AT91"
 361         select ARCH_REQUIRE_GPIOLIB
 362         select CLKDEV_LOOKUP
 363         select IRQ_DOMAIN
 364         select NEED_MACH_IO_H if PCCARD
 365         select PINCTRL
 366         select PINCTRL_AT91
 367         select USE_OF
 368         help
 369           This enables support for systems based on Atmel
 370           AT91RM9200, AT91SAM9 and SAMA5 processors.
 371
 372 config ARCH_CLPS711X
 373         bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
 374         select ARCH_REQUIRE_GPIOLIB
 375         select AUTO_ZRELADDR
 376         select CLKSRC_MMIO
 377         select COMMON_CLK
 378         select CPU_ARM720T
 379         select GENERIC_CLOCKEVENTS
 380         select MFD_SYSCON
 381         select SOC_BUS
 382         help
 383           Support for Cirrus Logic 711x/721x/731x based boards.
 384
 385 config ARCH_GEMINI
 386         bool "Cortina Systems Gemini"
 387         select ARCH_REQUIRE_GPIOLIB
 388         select CLKSRC_MMIO
 389         select CPU_FA526
 390         select GENERIC_CLOCKEVENTS
 391         help
 392           Support for the Cortina Systems Gemini family SoCs
 393
 394 config ARCH_EBSA110
 395         bool "EBSA-110"
 396         select ARCH_USES_GETTIMEOFFSET
 397         select CPU_SA110
 398         select ISA
 399         select NEED_MACH_IO_H
 400         select NEED_MACH_MEMORY_H
 401         select NO_IOPORT_MAP
 402         help
 403           This is an evaluation board for the StrongARM processor available
 404           from Digital. It has limited hardware on-board, including an
 405           Ethernet interface, two PCMCIA sockets, two serial ports and a
 406           parallel port.
 407
 408 config ARCH_EFM32
 409         bool "Energy Micro efm32"
 410         depends on !MMU
 411         select ARCH_REQUIRE_GPIOLIB
 412         select ARM_NVIC
 413         select AUTO_ZRELADDR
 414         select CLKSRC_OF
 415         select COMMON_CLK
 416         select CPU_V7M
 417         select GENERIC_CLOCKEVENTS
 418         select NO_DMA
 419         select NO_IOPORT_MAP
 420         select SPARSE_IRQ
 421         select USE_OF
 422         help
 423           Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
 424           processors.
 425
 426 config ARCH_EP93XX
 427         bool "EP93xx-based"
 428         select ARCH_HAS_HOLES_MEMORYMODEL
 429         select ARCH_REQUIRE_GPIOLIB
 430         select ARCH_USES_GETTIMEOFFSET
 431         select ARM_AMBA
 432         select ARM_VIC
 433         select CLKDEV_LOOKUP
 434         select CPU_ARM920T
 435         help
 436           This enables support for the Cirrus EP93xx series of CPUs.
 437
 438 config ARCH_FOOTBRIDGE
 439         bool "FootBridge"
 440         select CPU_SA110
 441         select FOOTBRIDGE
 442         select GENERIC_CLOCKEVENTS
 443         select HAVE_IDE
 444         select NEED_MACH_IO_H if !MMU
 445         select NEED_MACH_MEMORY_H
 446         help
 447           Support for systems based on the DC21285 companion chip
 448           ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
 449
 450 config ARCH_NETX
 451         bool "Hilscher NetX based"
 452         select ARM_VIC
 453         select CLKSRC_MMIO
 454         select CPU_ARM926T
 455         select GENERIC_CLOCKEVENTS
 456         help
 457           This enables support for systems based on the Hilscher NetX Soc
 458
 459 config ARCH_IOP13XX
 460         bool "IOP13xx-based"
 461         depends on MMU
 462         select CPU_XSC3
 463         select NEED_MACH_MEMORY_H
 464         select NEED_RET_TO_USER
 465         select PCI
 466         select PLAT_IOP
 467         select VMSPLIT_1G
 468         select SPARSE_IRQ
 469         help
 470           Support for Intel's IOP13XX (XScale) family of processors.
 471
 472 config ARCH_IOP32X
 473         bool "IOP32x-based"
 474         depends on MMU
 475         select ARCH_REQUIRE_GPIOLIB
 476         select CPU_XSCALE
 477         select GPIO_IOP
 478         select NEED_RET_TO_USER
 479         select PCI
 480         select PLAT_IOP
 481         help
 482           Support for Intel's 80219 and IOP32X (XScale) family of
 483           processors.
 484
 485 config ARCH_IOP33X
 486         bool "IOP33x-based"
 487         depends on MMU
 488         select ARCH_REQUIRE_GPIOLIB
 489         select CPU_XSCALE
 490         select GPIO_IOP
 491         select NEED_RET_TO_USER
 492         select PCI
 493         select PLAT_IOP
 494         help
 495           Support for Intel's IOP33X (XScale) family of processors.
 496
 497 config ARCH_IXP4XX
 498         bool "IXP4xx-based"
 499         depends on MMU
 500         select ARCH_HAS_DMA_SET_COHERENT_MASK
 501         select ARCH_REQUIRE_GPIOLIB
 502         select ARCH_SUPPORTS_BIG_ENDIAN
 503         select CLKSRC_MMIO
 504         select CPU_XSCALE
 505         select DMABOUNCE if PCI
 506         select GENERIC_CLOCKEVENTS
 507         select MIGHT_HAVE_PCI
 508         select NEED_MACH_IO_H
 509         select USB_EHCI_BIG_ENDIAN_DESC
 510         select USB_EHCI_BIG_ENDIAN_MMIO
 511         help
 512           Support for Intel's IXP4XX (XScale) family of processors.
 513
 514 config ARCH_DOVE
 515         bool "Marvell Dove"
 516         select ARCH_REQUIRE_GPIOLIB
 517         select CPU_PJ4
 518         select GENERIC_CLOCKEVENTS
 519         select MIGHT_HAVE_PCI
 520         select MVEBU_MBUS
 521         select PINCTRL
 522         select PINCTRL_DOVE
 523         select PLAT_ORION_LEGACY
 524         help
 525           Support for the Marvell Dove SoC 88AP510
 526
 527 config ARCH_MV78XX0
 528         bool "Marvell MV78xx0"
 529         select ARCH_REQUIRE_GPIOLIB
 530         select CPU_FEROCEON
 531         select GENERIC_CLOCKEVENTS
 532         select MVEBU_MBUS
 533         select PCI
 534         select PLAT_ORION_LEGACY
 535         help
 536           Support for the following Marvell MV78xx0 series SoCs:
 537           MV781x0, MV782x0.
 538
 539 config ARCH_ORION5X
 540         bool "Marvell Orion"
 541         depends on MMU
 542         select ARCH_REQUIRE_GPIOLIB
 543         select CPU_FEROCEON
 544         select GENERIC_CLOCKEVENTS
 545         select MVEBU_MBUS
 546         select PCI
 547         select PLAT_ORION_LEGACY
 548         help
 549           Support for the following Marvell Orion 5x series SoCs:
 550           Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
 551           Orion-2 (5281), Orion-1-90 (6183).
 552
 553 config ARCH_MMP
 554         bool "Marvell PXA168/910/MMP2"
 555         depends on MMU
 556         select ARCH_REQUIRE_GPIOLIB
 557         select CLKDEV_LOOKUP
 558         select GENERIC_ALLOCATOR
 559         select GENERIC_CLOCKEVENTS
 560         select GPIO_PXA
 561         select IRQ_DOMAIN
 562         select MULTI_IRQ_HANDLER
 563         select PINCTRL
 564         select PLAT_PXA
 565         select SPARSE_IRQ
 566         help
 567           Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
 568
 569 config ARCH_KS8695
 570         bool "Micrel/Kendin KS8695"
 571         select ARCH_REQUIRE_GPIOLIB
 572         select CLKSRC_MMIO
 573         select CPU_ARM922T
 574         select GENERIC_CLOCKEVENTS
 575         select NEED_MACH_MEMORY_H
 576         help
 577           Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
 578           System-on-Chip devices.
 579
 580 config ARCH_W90X900
 581         bool "Nuvoton W90X900 CPU"
 582         select ARCH_REQUIRE_GPIOLIB
 583         select CLKDEV_LOOKUP
 584         select CLKSRC_MMIO
 585         select CPU_ARM926T
 586         select GENERIC_CLOCKEVENTS
 587         help
 588           Support for Nuvoton (Winbond logic dept.) ARM9 processor,
 589           At present, the w90x900 has been renamed nuc900, regarding
 590           the ARM series product line, you can login the following
 591           link address to know more.
 592
 593           <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
 594                 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
 595
 596 config ARCH_LPC32XX
 597         bool "NXP LPC32XX"
 598         select ARCH_REQUIRE_GPIOLIB
 599         select ARM_AMBA
 600         select CLKDEV_LOOKUP
 601         select CLKSRC_MMIO
 602         select CPU_ARM926T
 603         select GENERIC_CLOCKEVENTS
 604         select HAVE_IDE
 605         select USE_OF
 606         help
 607           Support for the NXP LPC32XX family of processors
 608
 609 config ARCH_PXA
 610         bool "PXA2xx/PXA3xx-based"
 611         depends on MMU
 612         select ARCH_MTD_XIP
 613         select ARCH_REQUIRE_GPIOLIB
 614         select ARM_CPU_SUSPEND if PM
 615         select AUTO_ZRELADDR
 616         select CLKDEV_LOOKUP
 617         select CLKSRC_MMIO
 618         select CLKSRC_OF
 619         select GENERIC_CLOCKEVENTS
 620         select GPIO_PXA
 621         select HAVE_IDE
 622         select MULTI_IRQ_HANDLER
 623         select PLAT_PXA
 624         select SPARSE_IRQ
 625         help
 626           Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
 627
 628 config ARCH_MSM
 629         bool "Qualcomm MSM (non-multiplatform)"
 630         select ARCH_REQUIRE_GPIOLIB
 631         select COMMON_CLK
 632         select GENERIC_CLOCKEVENTS
 633         help
 634           Support for Qualcomm MSM/QSD based systems.  This runs on the
 635           apps processor of the MSM/QSD and depends on a shared memory
 636           interface to the modem processor which runs the baseband
 637           stack and controls some vital subsystems
 638           (clock and power control, etc).
 639
 640 config ARCH_SHMOBILE_LEGACY
 641         bool "Renesas ARM SoCs (non-multiplatform)"
 642         select ARCH_SHMOBILE
 643         select ARM_PATCH_PHYS_VIRT if MMU
 644         select CLKDEV_LOOKUP
 645         select CPU_V7
 646         select GENERIC_CLOCKEVENTS
 647         select HAVE_ARM_SCU if SMP
 648         select HAVE_ARM_TWD if SMP
 649         select HAVE_MACH_CLKDEV
 650         select HAVE_SMP
 651         select MIGHT_HAVE_CACHE_L2X0
 652         select MULTI_IRQ_HANDLER
 653         select NO_IOPORT_MAP
 654         select PINCTRL
 655         select PM_GENERIC_DOMAINS if PM
 656         select SH_CLK_CPG
 657         select SPARSE_IRQ
 658         help
 659           Support for Renesas ARM SoC platforms using a non-multiplatform
 660           kernel. This includes the SH-Mobile, R-Mobile, EMMA-Mobile, R-Car
 661           and RZ families.
 662
 663 config ARCH_RPC
 664         bool "RiscPC"
 665         select ARCH_ACORN
 666         select ARCH_MAY_HAVE_PC_FDC
 667         select ARCH_SPARSEMEM_ENABLE
 668         select ARCH_USES_GETTIMEOFFSET
 669         select CPU_SA110
 670         select FIQ
 671         select HAVE_IDE
 672         select HAVE_PATA_PLATFORM
 673         select ISA_DMA_API
 674         select NEED_MACH_IO_H
 675         select NEED_MACH_MEMORY_H
 676         select NO_IOPORT_MAP
 677         select VIRT_TO_BUS
 678         help
 679           On the Acorn Risc-PC, Linux can support the internal IDE disk and
 680           CD-ROM interface, serial and parallel port, and the floppy drive.
 681
 682 config ARCH_SA1100
 683         bool "SA1100-based"
 684         select ARCH_MTD_XIP
 685         select ARCH_REQUIRE_GPIOLIB
 686         select ARCH_SPARSEMEM_ENABLE
 687         select CLKDEV_LOOKUP
 688         select CLKSRC_MMIO
 689         select CPU_FREQ
 690         select CPU_SA1100
 691         select GENERIC_CLOCKEVENTS
 692         select HAVE_IDE
 693         select IRQ_DOMAIN
 694         select ISA
 695         select MULTI_IRQ_HANDLER
 696         select NEED_MACH_MEMORY_H
 697         select SPARSE_IRQ
 698         help
 699           Support for StrongARM 11x0 based boards.
 700
 701 config ARCH_S3C24XX
 702         bool "Samsung S3C24XX SoCs"
 703         select ARCH_REQUIRE_GPIOLIB
 704         select ATAGS
 705         select CLKDEV_LOOKUP
 706         select CLKSRC_SAMSUNG_PWM
 707         select GENERIC_CLOCKEVENTS
 708         select GPIO_SAMSUNG
 709         select HAVE_S3C2410_I2C if I2C
 710         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 711         select HAVE_S3C_RTC if RTC_CLASS
 712         select MULTI_IRQ_HANDLER
 713         select NEED_MACH_IO_H
 714         select SAMSUNG_ATAGS
 715         help
 716           Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
 717           and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
 718           (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
 719           Samsung SMDK2410 development board (and derivatives).
 720
 721 config ARCH_S3C64XX
 722         bool "Samsung S3C64XX"
 723         select ARCH_REQUIRE_GPIOLIB
 724         select ARM_AMBA
 725         select ARM_VIC
 726         select ATAGS
 727         select CLKDEV_LOOKUP
 728         select CLKSRC_SAMSUNG_PWM
 729         select COMMON_CLK_SAMSUNG
 730         select CPU_V6K
 731         select GENERIC_CLOCKEVENTS
 732         select GPIO_SAMSUNG
 733         select HAVE_S3C2410_I2C if I2C
 734         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 735         select HAVE_TCM
 736         select NO_IOPORT_MAP
 737         select PLAT_SAMSUNG
 738         select PM_GENERIC_DOMAINS if PM
 739         select S3C_DEV_NAND
 740         select S3C_GPIO_TRACK
 741         select SAMSUNG_ATAGS
 742         select SAMSUNG_WAKEMASK
 743         select SAMSUNG_WDT_RESET
 744         help
 745           Samsung S3C64XX series based systems
 746
 747 config ARCH_DAVINCI
 748         bool "TI DaVinci"
 749         select ARCH_HAS_HOLES_MEMORYMODEL
 750         select ARCH_REQUIRE_GPIOLIB
 751         select CLKDEV_LOOKUP
 752         select GENERIC_ALLOCATOR
 753         select GENERIC_CLOCKEVENTS
 754         select GENERIC_IRQ_CHIP
 755         select HAVE_IDE
 756         select TI_PRIV_EDMA
 757         select USE_OF
 758         select ZONE_DMA
 759         help
 760           Support for TI's DaVinci platform.
 761
 762 config ARCH_OMAP1
 763         bool "TI OMAP1"
 764         depends on MMU
 765         select ARCH_HAS_HOLES_MEMORYMODEL
 766         select ARCH_OMAP
 767         select ARCH_REQUIRE_GPIOLIB
 768         select CLKDEV_LOOKUP
 769         select CLKSRC_MMIO
 770         select GENERIC_CLOCKEVENTS
 771         select GENERIC_IRQ_CHIP
 772         select HAVE_IDE
 773         select IRQ_DOMAIN
 774         select NEED_MACH_IO_H if PCCARD
 775         select NEED_MACH_MEMORY_H
 776         help
 777           Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
 778
 779 endchoice
 780
 781 menu "Multiple platform selection"
 782         depends on ARCH_MULTIPLATFORM
 783
 784 comment "CPU Core family selection"
 785
 786 config ARCH_MULTI_V4
 787         bool "ARMv4 based platforms (FA526)"
 788         depends on !ARCH_MULTI_V6_V7
 789         select ARCH_MULTI_V4_V5
 790         select CPU_FA526
 791
 792 config ARCH_MULTI_V4T
 793         bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
 794         depends on !ARCH_MULTI_V6_V7
 795         select ARCH_MULTI_V4_V5
 796         select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
 797                 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
 798                 CPU_ARM925T || CPU_ARM940T)
 799
 800 config ARCH_MULTI_V5
 801         bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
 802         depends on !ARCH_MULTI_V6_V7
 803         select ARCH_MULTI_V4_V5
 804         select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
 805                 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
 806                 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
 807
 808 config ARCH_MULTI_V4_V5
 809         bool
 810
 811 config ARCH_MULTI_V6
 812         bool "ARMv6 based platforms (ARM11)"
 813         select ARCH_MULTI_V6_V7
 814         select CPU_V6K
 815
 816 config ARCH_MULTI_V7
 817         bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
 818         default y
 819         select ARCH_MULTI_V6_V7
 820         select CPU_V7
 821         select HAVE_SMP
 822
 823 config ARCH_MULTI_V6_V7
 824         bool
 825         select MIGHT_HAVE_CACHE_L2X0
 826
 827 config ARCH_MULTI_CPU_AUTO
 828         def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
 829         select ARCH_MULTI_V5
 830
 831 endmenu
 832
 833 config ARCH_VIRT
 834         bool "Dummy Virtual Machine" if ARCH_MULTI_V7
 835         select ARM_AMBA
 836         select ARM_GIC
 837         select ARM_PSCI
 838         select HAVE_ARM_ARCH_TIMER
 839
 840 #
 841 # This is sorted alphabetically by mach-* pathname.  However, plat-*
 842 # Kconfigs may be included either alphabetically (according to the
 843 # plat- suffix) or along side the corresponding mach-* source.
 844 #
 845 source "arch/arm/mach-mvebu/Kconfig"
 846
 847 source "arch/arm/mach-asm9260/Kconfig"
 848
 849 source "arch/arm/mach-at91/Kconfig"
 850
 851 source "arch/arm/mach-axxia/Kconfig"
 852
 853 source "arch/arm/mach-bcm/Kconfig"
 854
 855 source "arch/arm/mach-berlin/Kconfig"
 856
 857 source "arch/arm/mach-clps711x/Kconfig"
 858
 859 source "arch/arm/mach-cns3xxx/Kconfig"
 860
 861 source "arch/arm/mach-davinci/Kconfig"
 862
 863 source "arch/arm/mach-digicolor/Kconfig"
 864
 865 source "arch/arm/mach-dove/Kconfig"
 866
 867 source "arch/arm/mach-ep93xx/Kconfig"
 868
 869 source "arch/arm/mach-footbridge/Kconfig"
 870
 871 source "arch/arm/mach-gemini/Kconfig"
 872
 873 source "arch/arm/mach-highbank/Kconfig"
 874
 875 source "arch/arm/mach-hisi/Kconfig"
 876
 877 source "arch/arm/mach-integrator/Kconfig"
 878
 879 source "arch/arm/mach-iop32x/Kconfig"
 880
 881 source "arch/arm/mach-iop33x/Kconfig"
 882
 883 source "arch/arm/mach-iop13xx/Kconfig"
 884
 885 source "arch/arm/mach-ixp4xx/Kconfig"
 886
 887 source "arch/arm/mach-keystone/Kconfig"
 888
 889 source "arch/arm/mach-ks8695/Kconfig"
 890
 891 source "arch/arm/mach-meson/Kconfig"
 892
 893 source "arch/arm/mach-msm/Kconfig"
 894
 895 source "arch/arm/mach-moxart/Kconfig"
 896
 897 source "arch/arm/mach-mv78xx0/Kconfig"
 898
 899 source "arch/arm/mach-imx/Kconfig"
 900
 901 source "arch/arm/mach-mediatek/Kconfig"
 902
 903 source "arch/arm/mach-mxs/Kconfig"
 904
 905 source "arch/arm/mach-netx/Kconfig"
 906
 907 source "arch/arm/mach-nomadik/Kconfig"
 908
 909 source "arch/arm/mach-nspire/Kconfig"
 910
 911 source "arch/arm/plat-omap/Kconfig"
 912
 913 source "arch/arm/mach-omap1/Kconfig"
 914
 915 source "arch/arm/mach-omap2/Kconfig"
 916
 917 source "arch/arm/mach-orion5x/Kconfig"
 918
 919 source "arch/arm/mach-picoxcell/Kconfig"
 920
 921 source "arch/arm/mach-pxa/Kconfig"
 922 source "arch/arm/plat-pxa/Kconfig"
 923
 924 source "arch/arm/mach-mmp/Kconfig"
 925
 926 source "arch/arm/mach-qcom/Kconfig"
 927
 928 source "arch/arm/mach-realview/Kconfig"
 929
 930 source "arch/arm/mach-rockchip/Kconfig"
 931
 932 source "arch/arm/mach-sa1100/Kconfig"
 933
 934 source "arch/arm/mach-socfpga/Kconfig"
 935
 936 source "arch/arm/mach-spear/Kconfig"
 937
 938 source "arch/arm/mach-sti/Kconfig"
 939
 940 source "arch/arm/mach-s3c24xx/Kconfig"
 941
 942 source "arch/arm/mach-s3c64xx/Kconfig"
 943
 944 source "arch/arm/mach-s5pv210/Kconfig"
 945
 946 source "arch/arm/mach-exynos/Kconfig"
 947 source "arch/arm/plat-samsung/Kconfig"
 948
 949 source "arch/arm/mach-shmobile/Kconfig"
 950
 951 source "arch/arm/mach-sunxi/Kconfig"
 952
 953 source "arch/arm/mach-prima2/Kconfig"
 954
 955 source "arch/arm/mach-tegra/Kconfig"
 956
 957 source "arch/arm/mach-u300/Kconfig"
 958
 959 source "arch/arm/mach-ux500/Kconfig"
 960
 961 source "arch/arm/mach-versatile/Kconfig"
 962
 963 source "arch/arm/mach-vexpress/Kconfig"
 964 source "arch/arm/plat-versatile/Kconfig"
 965
 966 source "arch/arm/mach-vt8500/Kconfig"
 967
 968 source "arch/arm/mach-w90x900/Kconfig"
 969
 970 source "arch/arm/mach-zynq/Kconfig"
 971
 972 # Definitions to make life easier
 973 config ARCH_ACORN
 974         bool
 975
 976 config PLAT_IOP
 977         bool
 978         select GENERIC_CLOCKEVENTS
 979
 980 config PLAT_ORION
 981         bool
 982         select CLKSRC_MMIO
 983         select COMMON_CLK
 984         select GENERIC_IRQ_CHIP
 985         select IRQ_DOMAIN
 986
 987 config PLAT_ORION_LEGACY
 988         bool
 989         select PLAT_ORION
 990
 991 config PLAT_PXA
 992         bool
 993
 994 config PLAT_VERSATILE
 995         bool
 996
 997 config ARM_TIMER_SP804
 998         bool
 999         select CLKSRC_MMIO
1000         select CLKSRC_OF if OF
1001
1002 source "arch/arm/firmware/Kconfig"
1003
1004 source arch/arm/mm/Kconfig
1005
1006 config IWMMXT
1007         bool "Enable iWMMXt support"
1008         depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
1009         default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
1010         help
1011           Enable support for iWMMXt context switching at run time if
1012           running on a CPU that supports it.
1013
1014 config MULTI_IRQ_HANDLER
1015         bool
1016         help
1017           Allow each machine to specify it's own IRQ handler at run time.
1018
1019 if !MMU
1020 source "arch/arm/Kconfig-nommu"
1021 endif
1022
1023 config PJ4B_ERRATA_4742
1024         bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1025         depends on CPU_PJ4B && MACH_ARMADA_370
1026         default y
1027         help
1028           When coming out of either a Wait for Interrupt (WFI) or a Wait for
1029           Event (WFE) IDLE states, a specific timing sensitivity exists between
1030           the retiring WFI/WFE instructions and the newly issued subsequent
1031           instructions.  This sensitivity can result in a CPU hang scenario.
1032           Workaround:
1033           The software must insert either a Data Synchronization Barrier (DSB)
1034           or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1035           instruction
1036
1037 config ARM_ERRATA_326103
1038         bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1039         depends on CPU_V6
1040         help
1041           Executing a SWP instruction to read-only memory does not set bit 11
1042           of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1043           treat the access as a read, preventing a COW from occurring and
1044           causing the faulting task to livelock.
1045
1046 config ARM_ERRATA_411920
1047         bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1048         depends on CPU_V6 || CPU_V6K
1049         help
1050           Invalidation of the Instruction Cache operation can
1051           fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1052           It does not affect the MPCore. This option enables the ARM Ltd.
1053           recommended workaround.
1054
1055 config ARM_ERRATA_430973
1056         bool "ARM errata: Stale prediction on replaced interworking branch"
1057         depends on CPU_V7
1058         help
1059           This option enables the workaround for the 430973 Cortex-A8
1060           (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1061           interworking branch is replaced with another code sequence at the
1062           same virtual address, whether due to self-modifying code or virtual
1063           to physical address re-mapping, Cortex-A8 does not recover from the
1064           stale interworking branch prediction. This results in Cortex-A8
1065           executing the new code sequence in the incorrect ARM or Thumb state.
1066           The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1067           and also flushes the branch target cache at every context switch.
1068           Note that setting specific bits in the ACTLR register may not be
1069           available in non-secure mode.
1070
1071 config ARM_ERRATA_458693
1072         bool "ARM errata: Processor deadlock when a false hazard is created"
1073         depends on CPU_V7
1074         depends on !ARCH_MULTIPLATFORM
1075         help
1076           This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1077           erratum. For very specific sequences of memory operations, it is
1078           possible for a hazard condition intended for a cache line to instead
1079           be incorrectly associated with a different cache line. This false
1080           hazard might then cause a processor deadlock. The workaround enables
1081           the L1 caching of the NEON accesses and disables the PLD instruction
1082           in the ACTLR register. Note that setting specific bits in the ACTLR
1083           register may not be available in non-secure mode.
1084
1085 config ARM_ERRATA_460075
1086         bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1087         depends on CPU_V7
1088         depends on !ARCH_MULTIPLATFORM
1089         help
1090           This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1091           erratum. Any asynchronous access to the L2 cache may encounter a
1092           situation in which recent store transactions to the L2 cache are lost
1093           and overwritten with stale memory contents from external memory. The
1094           workaround disables the write-allocate mode for the L2 cache via the
1095           ACTLR register. Note that setting specific bits in the ACTLR register
1096           may not be available in non-secure mode.
1097
1098 config ARM_ERRATA_742230
1099         bool "ARM errata: DMB operation may be faulty"
1100         depends on CPU_V7 && SMP
1101         depends on !ARCH_MULTIPLATFORM
1102         help
1103           This option enables the workaround for the 742230 Cortex-A9
1104           (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1105           between two write operations may not ensure the correct visibility
1106           ordering of the two writes. This workaround sets a specific bit in
1107           the diagnostic register of the Cortex-A9 which causes the DMB
1108           instruction to behave as a DSB, ensuring the correct behaviour of
1109           the two writes.
1110
1111 config ARM_ERRATA_742231
1112         bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1113         depends on CPU_V7 && SMP
1114         depends on !ARCH_MULTIPLATFORM
1115         help
1116           This option enables the workaround for the 742231 Cortex-A9
1117           (r2p0..r2p2) erratum. Under certain conditions, specific to the
1118           Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1119           accessing some data located in the same cache line, may get corrupted
1120           data due to bad handling of the address hazard when the line gets
1121           replaced from one of the CPUs at the same time as another CPU is
1122           accessing it. This workaround sets specific bits in the diagnostic
1123           register of the Cortex-A9 which reduces the linefill issuing
1124           capabilities of the processor.
1125
1126 config ARM_ERRATA_643719
1127         bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1128         depends on CPU_V7 && SMP
1129         help
1130           This option enables the workaround for the 643719 Cortex-A9 (prior to
1131           r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1132           register returns zero when it should return one. The workaround
1133           corrects this value, ensuring cache maintenance operations which use
1134           it behave as intended and avoiding data corruption.
1135
1136 config ARM_ERRATA_720789
1137         bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1138         depends on CPU_V7
1139         help
1140           This option enables the workaround for the 720789 Cortex-A9 (prior to
1141           r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1142           broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1143           As a consequence of this erratum, some TLB entries which should be
1144           invalidated are not, resulting in an incoherency in the system page
1145           tables. The workaround changes the TLB flushing routines to invalidate
1146           entries regardless of the ASID.
1147
1148 config ARM_ERRATA_743622
1149         bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1150         depends on CPU_V7
1151         depends on !ARCH_MULTIPLATFORM
1152         help
1153           This option enables the workaround for the 743622 Cortex-A9
1154           (r2p*) erratum. Under very rare conditions, a faulty
1155           optimisation in the Cortex-A9 Store Buffer may lead to data
1156           corruption. This workaround sets a specific bit in the diagnostic
1157           register of the Cortex-A9 which disables the Store Buffer
1158           optimisation, preventing the defect from occurring. This has no
1159           visible impact on the overall performance or power consumption of the
1160           processor.
1161
1162 config ARM_ERRATA_751472
1163         bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1164         depends on CPU_V7
1165         depends on !ARCH_MULTIPLATFORM
1166         help
1167           This option enables the workaround for the 751472 Cortex-A9 (prior
1168           to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1169           completion of a following broadcasted operation if the second
1170           operation is received by a CPU before the ICIALLUIS has completed,
1171           potentially leading to corrupted entries in the cache or TLB.
1172
1173 config ARM_ERRATA_754322
1174         bool "ARM errata: possible faulty MMU translations following an ASID switch"
1175         depends on CPU_V7
1176         help
1177           This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1178           r3p*) erratum. A speculative memory access may cause a page table walk
1179           which starts prior to an ASID switch but completes afterwards. This
1180           can populate the micro-TLB with a stale entry which may be hit with
1181           the new ASID. This workaround places two dsb instructions in the mm
1182           switching code so that no page table walks can cross the ASID switch.
1183
1184 config ARM_ERRATA_754327
1185         bool "ARM errata: no automatic Store Buffer drain"
1186         depends on CPU_V7 && SMP
1187         help
1188           This option enables the workaround for the 754327 Cortex-A9 (prior to
1189           r2p0) erratum. The Store Buffer does not have any automatic draining
1190           mechanism and therefore a livelock may occur if an external agent
1191           continuously polls a memory location waiting to observe an update.
1192           This workaround defines cpu_relax() as smp_mb(), preventing correctly
1193           written polling loops from denying visibility of updates to memory.
1194
1195 config ARM_ERRATA_364296
1196         bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1197         depends on CPU_V6
1198         help
1199           This options enables the workaround for the 364296 ARM1136
1200           r0p2 erratum (possible cache data corruption with
1201           hit-under-miss enabled). It sets the undocumented bit 31 in
1202           the auxiliary control register and the FI bit in the control
1203           register, thus disabling hit-under-miss without putting the
1204           processor into full low interrupt latency mode. ARM11MPCore
1205           is not affected.
1206
1207 config ARM_ERRATA_764369
1208         bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1209         depends on CPU_V7 && SMP
1210         help
1211           This option enables the workaround for erratum 764369
1212           affecting Cortex-A9 MPCore with two or more processors (all
1213           current revisions). Under certain timing circumstances, a data
1214           cache line maintenance operation by MVA targeting an Inner
1215           Shareable memory region may fail to proceed up to either the
1216           Point of Coherency or to the Point of Unification of the
1217           system. This workaround adds a DSB instruction before the
1218           relevant cache maintenance functions and sets a specific bit
1219           in the diagnostic control register of the SCU.
1220
1221 config ARM_ERRATA_775420
1222        bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1223        depends on CPU_V7
1224        help
1225          This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1226          r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1227          operation aborts with MMU exception, it might cause the processor
1228          to deadlock. This workaround puts DSB before executing ISB if
1229          an abort may occur on cache maintenance.
1230
1231 config ARM_ERRATA_798181
1232         bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1233         depends on CPU_V7 && SMP
1234         help
1235           On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1236           adequately shooting down all use of the old entries. This
1237           option enables the Linux kernel workaround for this erratum
1238           which sends an IPI to the CPUs that are running the same ASID
1239           as the one being invalidated.
1240
1241 config ARM_ERRATA_773022
1242         bool "ARM errata: incorrect instructions may be executed from loop buffer"
1243         depends on CPU_V7
1244         help
1245           This option enables the workaround for the 773022 Cortex-A15
1246           (up to r0p4) erratum. In certain rare sequences of code, the
1247           loop buffer may deliver incorrect instructions. This
1248           workaround disables the loop buffer to avoid the erratum.
1249
1250 endmenu
1251
1252 source "arch/arm/common/Kconfig"
1253
1254 menu "Bus support"
1255
1256 config ISA
1257         bool
1258         help
1259           Find out whether you have ISA slots on your motherboard.  ISA is the
1260           name of a bus system, i.e. the way the CPU talks to the other stuff
1261           inside your box.  Other bus systems are PCI, EISA, MicroChannel
1262           (MCA) or VESA.  ISA is an older system, now being displaced by PCI;
1263           newer boards don't support it.  If you have ISA, say Y, otherwise N.
1264
1265 # Select ISA DMA controller support
1266 config ISA_DMA
1267         bool
1268         select ISA_DMA_API
1269
1270 # Select ISA DMA interface
1271 config ISA_DMA_API
1272         bool
1273
1274 config PCI
1275         bool "PCI support" if MIGHT_HAVE_PCI
1276         help
1277           Find out whether you have a PCI motherboard. PCI is the name of a
1278           bus system, i.e. the way the CPU talks to the other stuff inside
1279           your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1280           VESA. If you have PCI, say Y, otherwise N.
1281
1282 config PCI_DOMAINS
1283         bool
1284         depends on PCI
1285
1286 config PCI_DOMAINS_GENERIC
1287         def_bool PCI_DOMAINS
1288
1289 config PCI_NANOENGINE
1290         bool "BSE nanoEngine PCI support"
1291         depends on SA1100_NANOENGINE
1292         help
1293           Enable PCI on the BSE nanoEngine board.
1294
1295 config PCI_SYSCALL
1296         def_bool PCI
1297
1298 config PCI_HOST_ITE8152
1299         bool
1300         depends on PCI && MACH_ARMCORE
1301         default y
1302         select DMABOUNCE
1303
1304 source "drivers/pci/Kconfig"
1305 source "drivers/pci/pcie/Kconfig"
1306
1307 source "drivers/pcmcia/Kconfig"
1308
1309 endmenu
1310
1311 menu "Kernel Features"
1312
1313 config HAVE_SMP
1314         bool
1315         help
1316           This option should be selected by machines which have an SMP-
1317           capable CPU.
1318
1319           The only effect of this option is to make the SMP-related
1320           options available to the user for configuration.
1321
1322 config SMP
1323         bool "Symmetric Multi-Processing"
1324         depends on CPU_V6K || CPU_V7
1325         depends on GENERIC_CLOCKEVENTS
1326         depends on HAVE_SMP
1327         depends on MMU || ARM_MPU
1328         help
1329           This enables support for systems with more than one CPU. If you have
1330           a system with only one CPU, say N. If you have a system with more
1331           than one CPU, say Y.
1332
1333           If you say N here, the kernel will run on uni- and multiprocessor
1334           machines, but will use only one CPU of a multiprocessor machine. If
1335           you say Y here, the kernel will run on many, but not all,
1336           uniprocessor machines. On a uniprocessor machine, the kernel
1337           will run faster if you say N here.
1338
1339           See also <file:Documentation/x86/i386/IO-APIC.txt>,
1340           <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1341           <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1342
1343           If you don't know what to do here, say N.
1344
1345 config SMP_ON_UP
1346         bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1347         depends on SMP && !XIP_KERNEL && MMU
1348         default y
1349         help
1350           SMP kernels contain instructions which fail on non-SMP processors.
1351           Enabling this option allows the kernel to modify itself to make
1352           these instructions safe.  Disabling it allows about 1K of space
1353           savings.
1354
1355           If you don't know what to do here, say Y.
1356
1357 config ARM_CPU_TOPOLOGY
1358         bool "Support cpu topology definition"
1359         depends on SMP && CPU_V7
1360         default y
1361         help
1362           Support ARM cpu topology definition. The MPIDR register defines
1363           affinity between processors which is then used to describe the cpu
1364           topology of an ARM System.
1365
1366 config SCHED_MC
1367         bool "Multi-core scheduler support"
1368         depends on ARM_CPU_TOPOLOGY
1369         help
1370           Multi-core scheduler support improves the CPU scheduler's decision
1371           making when dealing with multi-core CPU chips at a cost of slightly
1372           increased overhead in some places. If unsure say N here.
1373
1374 config SCHED_SMT
1375         bool "SMT scheduler support"
1376         depends on ARM_CPU_TOPOLOGY
1377         help
1378           Improves the CPU scheduler's decision making when dealing with
1379           MultiThreading at a cost of slightly increased overhead in some
1380           places. If unsure say N here.
1381
1382 config HAVE_ARM_SCU
1383         bool
1384         help
1385           This option enables support for the ARM system coherency unit
1386
1387 config HAVE_ARM_ARCH_TIMER
1388         bool "Architected timer support"
1389         depends on CPU_V7
1390         select ARM_ARCH_TIMER
1391         select GENERIC_CLOCKEVENTS
1392         help
1393           This option enables support for the ARM architected timer
1394
1395 config HAVE_ARM_TWD
1396         bool
1397         depends on SMP
1398         select CLKSRC_OF if OF
1399         help
1400           This options enables support for the ARM timer and watchdog unit
1401
1402 config MCPM
1403         bool "Multi-Cluster Power Management"
1404         depends on CPU_V7 && SMP
1405         help
1406           This option provides the common power management infrastructure
1407           for (multi-)cluster based systems, such as big.LITTLE based
1408           systems.
1409
1410 config MCPM_QUAD_CLUSTER
1411         bool
1412         depends on MCPM
1413         help
1414           To avoid wasting resources unnecessarily, MCPM only supports up
1415           to 2 clusters by default.
1416           Platforms with 3 or 4 clusters that use MCPM must select this
1417           option to allow the additional clusters to be managed.
1418
1419 config BIG_LITTLE
1420         bool "big.LITTLE support (Experimental)"
1421         depends on CPU_V7 && SMP
1422         select MCPM
1423         help
1424           This option enables support selections for the big.LITTLE
1425           system architecture.
1426
1427 config BL_SWITCHER
1428         bool "big.LITTLE switcher support"
1429         depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1430         select ARM_CPU_SUSPEND
1431         select CPU_PM
1432         help
1433           The big.LITTLE "switcher" provides the core functionality to
1434           transparently handle transition between a cluster of A15's
1435           and a cluster of A7's in a big.LITTLE system.
1436
1437 config BL_SWITCHER_DUMMY_IF
1438         tristate "Simple big.LITTLE switcher user interface"
1439         depends on BL_SWITCHER && DEBUG_KERNEL
1440         help
1441           This is a simple and dummy char dev interface to control
1442           the big.LITTLE switcher core code.  It is meant for
1443           debugging purposes only.
1444
1445 choice
1446         prompt "Memory split"
1447         depends on MMU
1448         default VMSPLIT_3G
1449         help
1450           Select the desired split between kernel and user memory.
1451
1452           If you are not absolutely sure what you are doing, leave this
1453           option alone!
1454
1455         config VMSPLIT_3G
1456                 bool "3G/1G user/kernel split"
1457         config VMSPLIT_2G
1458                 bool "2G/2G user/kernel split"
1459         config VMSPLIT_1G
1460                 bool "1G/3G user/kernel split"
1461 endchoice
1462
1463 config PAGE_OFFSET
1464         hex
1465         default PHYS_OFFSET if !MMU
1466         default 0x40000000 if VMSPLIT_1G
1467         default 0x80000000 if VMSPLIT_2G
1468         default 0xC0000000
1469
1470 config NR_CPUS
1471         int "Maximum number of CPUs (2-32)"
1472         range 2 32
1473         depends on SMP
1474         default "4"
1475
1476 config HOTPLUG_CPU
1477         bool "Support for hot-pluggable CPUs"
1478         depends on SMP
1479         help
1480           Say Y here to experiment with turning CPUs off and on.  CPUs
1481           can be controlled through /sys/devices/system/cpu.
1482
1483 config ARM_PSCI
1484         bool "Support for the ARM Power State Coordination Interface (PSCI)"
1485         depends on CPU_V7
1486         help
1487           Say Y here if you want Linux to communicate with system firmware
1488           implementing the PSCI specification for CPU-centric power
1489           management operations described in ARM document number ARM DEN
1490           0022A ("Power State Coordination Interface System Software on
1491           ARM processors").
1492
1493 # The GPIO number here must be sorted by descending number. In case of
1494 # a multiplatform kernel, we just want the highest value required by the
1495 # selected platforms.
1496 config ARCH_NR_GPIO
1497         int
1498         default 1024 if ARCH_SHMOBILE || ARCH_TEGRA || ARCH_ZYNQ
1499         default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1500                 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1501         default 416 if ARCH_SUNXI
1502         default 392 if ARCH_U8500
1503         default 352 if ARCH_VT8500
1504         default 288 if ARCH_ROCKCHIP
1505         default 264 if MACH_H4700
1506         default 0
1507         help
1508           Maximum number of GPIOs in the system.
1509
1510           If unsure, leave the default value.
1511
1512 source kernel/Kconfig.preempt
1513
1514 config HZ_FIXED
1515         int
1516         default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1517                 ARCH_S5PV210 || ARCH_EXYNOS4
1518         default AT91_TIMER_HZ if ARCH_AT91
1519         default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
1520         default 0
1521
1522 choice
1523         depends on HZ_FIXED = 0
1524         prompt "Timer frequency"
1525
1526 config HZ_100
1527         bool "100 Hz"
1528
1529 config HZ_200
1530         bool "200 Hz"
1531
1532 config HZ_250
1533         bool "250 Hz"
1534
1535 config HZ_300
1536         bool "300 Hz"
1537
1538 config HZ_500
1539         bool "500 Hz"
1540
1541 config HZ_1000
1542         bool "1000 Hz"
1543
1544 endchoice
1545
1546 config HZ
1547         int
1548         default HZ_FIXED if HZ_FIXED != 0
1549         default 100 if HZ_100
1550         default 200 if HZ_200
1551         default 250 if HZ_250
1552         default 300 if HZ_300
1553         default 500 if HZ_500
1554         default 1000
1555
1556 config SCHED_HRTICK
1557         def_bool HIGH_RES_TIMERS
1558
1559 config THUMB2_KERNEL
1560         bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1561         depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1562         default y if CPU_THUMBONLY
1563         select AEABI
1564         select ARM_ASM_UNIFIED
1565         select ARM_UNWIND
1566         help
1567           By enabling this option, the kernel will be compiled in
1568           Thumb-2 mode. A compiler/assembler that understand the unified
1569           ARM-Thumb syntax is needed.
1570
1571           If unsure, say N.
1572
1573 config THUMB2_AVOID_R_ARM_THM_JUMP11
1574         bool "Work around buggy Thumb-2 short branch relocations in gas"
1575         depends on THUMB2_KERNEL && MODULES
1576         default y
1577         help
1578           Various binutils versions can resolve Thumb-2 branches to
1579           locally-defined, preemptible global symbols as short-range "b.n"
1580           branch instructions.
1581
1582           This is a problem, because there's no guarantee the final
1583           destination of the symbol, or any candidate locations for a
1584           trampoline, are within range of the branch.  For this reason, the
1585           kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1586           relocation in modules at all, and it makes little sense to add
1587           support.
1588
1589           The symptom is that the kernel fails with an "unsupported
1590           relocation" error when loading some modules.
1591
1592           Until fixed tools are available, passing
1593           -fno-optimize-sibling-calls to gcc should prevent gcc generating
1594           code which hits this problem, at the cost of a bit of extra runtime
1595           stack usage in some cases.
1596
1597           The problem is described in more detail at:
1598               https://bugs.launchpad.net/binutils-linaro/+bug/725126
1599
1600           Only Thumb-2 kernels are affected.
1601
1602           Unless you are sure your tools don't have this problem, say Y.
1603
1604 config ARM_ASM_UNIFIED
1605         bool
1606
1607 config AEABI
1608         bool "Use the ARM EABI to compile the kernel"
1609         help
1610           This option allows for the kernel to be compiled using the latest
1611           ARM ABI (aka EABI).  This is only useful if you are using a user
1612           space environment that is also compiled with EABI.
1613
1614           Since there are major incompatibilities between the legacy ABI and
1615           EABI, especially with regard to structure member alignment, this
1616           option also changes the kernel syscall calling convention to
1617           disambiguate both ABIs and allow for backward compatibility support
1618           (selected with CONFIG_OABI_COMPAT).
1619
1620           To use this you need GCC version 4.0.0 or later.
1621
1622 config OABI_COMPAT
1623         bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1624         depends on AEABI && !THUMB2_KERNEL
1625         help
1626           This option preserves the old syscall interface along with the
1627           new (ARM EABI) one. It also provides a compatibility layer to
1628           intercept syscalls that have structure arguments which layout
1629           in memory differs between the legacy ABI and the new ARM EABI
1630           (only for non "thumb" binaries). This option adds a tiny
1631           overhead to all syscalls and produces a slightly larger kernel.
1632
1633           The seccomp filter system will not be available when this is
1634           selected, since there is no way yet to sensibly distinguish
1635           between calling conventions during filtering.
1636
1637           If you know you'll be using only pure EABI user space then you
1638           can say N here. If this option is not selected and you attempt
1639           to execute a legacy ABI binary then the result will be
1640           UNPREDICTABLE (in fact it can be predicted that it won't work
1641           at all). If in doubt say N.
1642
1643 config ARCH_HAS_HOLES_MEMORYMODEL
1644         bool
1645
1646 config ARCH_SPARSEMEM_ENABLE
1647         bool
1648
1649 config ARCH_SPARSEMEM_DEFAULT
1650         def_bool ARCH_SPARSEMEM_ENABLE
1651
1652 config ARCH_SELECT_MEMORY_MODEL
1653         def_bool ARCH_SPARSEMEM_ENABLE
1654
1655 config HAVE_ARCH_PFN_VALID
1656         def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1657
1658 config HAVE_GENERIC_RCU_GUP
1659         def_bool y
1660         depends on ARM_LPAE
1661
1662 config HIGHMEM
1663         bool "High Memory Support"
1664         depends on MMU
1665         help
1666           The address space of ARM processors is only 4 Gigabytes large
1667           and it has to accommodate user address space, kernel address
1668           space as well as some memory mapped IO. That means that, if you
1669           have a large amount of physical memory and/or IO, not all of the
1670           memory can be "permanently mapped" by the kernel. The physical
1671           memory that is not permanently mapped is called "high memory".
1672
1673           Depending on the selected kernel/user memory split, minimum
1674           vmalloc space and actual amount of RAM, you may not need this
1675           option which should result in a slightly faster kernel.
1676
1677           If unsure, say n.
1678
1679 config HIGHPTE
1680         bool "Allocate 2nd-level pagetables from highmem"
1681         depends on HIGHMEM
1682
1683 config HW_PERF_EVENTS
1684         bool "Enable hardware performance counter support for perf events"
1685         depends on PERF_EVENTS
1686         default y
1687         help
1688           Enable hardware performance counter support for perf events. If
1689           disabled, perf events will use software events only.
1690
1691 config SYS_SUPPORTS_HUGETLBFS
1692        def_bool y
1693        depends on ARM_LPAE
1694
1695 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1696        def_bool y
1697        depends on ARM_LPAE
1698
1699 config ARCH_WANT_GENERAL_HUGETLB
1700         def_bool y
1701
1702 source "mm/Kconfig"
1703
1704 config FORCE_MAX_ZONEORDER
1705         int "Maximum zone order" if ARCH_SHMOBILE_LEGACY
1706         range 11 64 if ARCH_SHMOBILE_LEGACY
1707         default "12" if SOC_AM33XX
1708         default "9" if SA1111 || ARCH_EFM32
1709         default "11"
1710         help
1711           The kernel memory allocator divides physically contiguous memory
1712           blocks into "zones", where each zone is a power of two number of
1713           pages.  This option selects the largest power of two that the kernel
1714           keeps in the memory allocator.  If you need to allocate very large
1715           blocks of physically contiguous memory, then you may need to
1716           increase this value.
1717
1718           This config option is actually maximum order plus one. For example,
1719           a value of 11 means that the largest free memory block is 2^10 pages.
1720
1721 config ALIGNMENT_TRAP
1722         bool
1723         depends on CPU_CP15_MMU
1724         default y if !ARCH_EBSA110
1725         select HAVE_PROC_CPU if PROC_FS
1726         help
1727           ARM processors cannot fetch/store information which is not
1728           naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1729           address divisible by 4. On 32-bit ARM processors, these non-aligned
1730           fetch/store instructions will be emulated in software if you say
1731           here, which has a severe performance impact. This is necessary for
1732           correct operation of some network protocols. With an IP-only
1733           configuration it is safe to say N, otherwise say Y.
1734
1735 config UACCESS_WITH_MEMCPY
1736         bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1737         depends on MMU
1738         default y if CPU_FEROCEON
1739         help
1740           Implement faster copy_to_user and clear_user methods for CPU
1741           cores where a 8-word STM instruction give significantly higher
1742           memory write throughput than a sequence of individual 32bit stores.
1743
1744           A possible side effect is a slight increase in scheduling latency
1745           between threads sharing the same address space if they invoke
1746           such copy operations with large buffers.
1747
1748           However, if the CPU data cache is using a write-allocate mode,
1749           this option is unlikely to provide any performance gain.
1750
1751 config SECCOMP
1752         bool
1753         prompt "Enable seccomp to safely compute untrusted bytecode"
1754         ---help---
1755           This kernel feature is useful for number crunching applications
1756           that may need to compute untrusted bytecode during their
1757           execution. By using pipes or other transports made available to
1758           the process as file descriptors supporting the read/write
1759           syscalls, it's possible to isolate those applications in
1760           their own address space using seccomp. Once seccomp is
1761           enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1762           and the task is only allowed to execute a few safe syscalls
1763           defined by each seccomp mode.
1764
1765 config SWIOTLB
1766         def_bool y
1767
1768 config IOMMU_HELPER
1769         def_bool SWIOTLB
1770
1771 config XEN_DOM0
1772         def_bool y
1773         depends on XEN
1774
1775 config XEN
1776         bool "Xen guest support on ARM"
1777         depends on ARM && AEABI && OF
1778         depends on CPU_V7 && !CPU_V6
1779         depends on !GENERIC_ATOMIC64
1780         depends on MMU
1781         select ARCH_DMA_ADDR_T_64BIT
1782         select ARM_PSCI
1783         select SWIOTLB_XEN
1784         help
1785           Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1786
1787 endmenu
1788
1789 menu "Boot options"
1790
1791 config USE_OF
1792         bool "Flattened Device Tree support"
1793         select IRQ_DOMAIN
1794         select OF
1795         select OF_EARLY_FLATTREE
1796         select OF_RESERVED_MEM
1797         help
1798           Include support for flattened device tree machine descriptions.
1799
1800 config ATAGS
1801         bool "Support for the traditional ATAGS boot data passing" if USE_OF
1802         default y
1803         help
1804           This is the traditional way of passing data to the kernel at boot
1805           time. If you are solely relying on the flattened device tree (or
1806           the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1807           to remove ATAGS support from your kernel binary.  If unsure,
1808           leave this to y.
1809
1810 config DEPRECATED_PARAM_STRUCT
1811         bool "Provide old way to pass kernel parameters"
1812         depends on ATAGS
1813         help
1814           This was deprecated in 2001 and announced to live on for 5 years.
1815           Some old boot loaders still use this way.
1816
1817 # Compressed boot loader in ROM.  Yes, we really want to ask about
1818 # TEXT and BSS so we preserve their values in the config files.
1819 config ZBOOT_ROM_TEXT
1820         hex "Compressed ROM boot loader base address"
1821         default "0"
1822         help
1823           The physical address at which the ROM-able zImage is to be
1824           placed in the target.  Platforms which normally make use of
1825           ROM-able zImage formats normally set this to a suitable
1826           value in their defconfig file.
1827
1828           If ZBOOT_ROM is not enabled, this has no effect.
1829
1830 config ZBOOT_ROM_BSS
1831         hex "Compressed ROM boot loader BSS address"
1832         default "0"
1833         help
1834           The base address of an area of read/write memory in the target
1835           for the ROM-able zImage which must be available while the
1836           decompressor is running. It must be large enough to hold the
1837           entire decompressed kernel plus an additional 128 KiB.
1838           Platforms which normally make use of ROM-able zImage formats
1839           normally set this to a suitable value in their defconfig file.
1840
1841           If ZBOOT_ROM is not enabled, this has no effect.
1842
1843 config ZBOOT_ROM
1844         bool "Compressed boot loader in ROM/flash"
1845         depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1846         depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1847         help
1848           Say Y here if you intend to execute your compressed kernel image
1849           (zImage) directly from ROM or flash.  If unsure, say N.
1850
1851 choice
1852         prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1853         depends on ZBOOT_ROM && ARCH_SH7372
1854         default ZBOOT_ROM_NONE
1855         help
1856           Include experimental SD/MMC loading code in the ROM-able zImage.
1857           With this enabled it is possible to write the ROM-able zImage
1858           kernel image to an MMC or SD card and boot the kernel straight
1859           from the reset vector. At reset the processor Mask ROM will load
1860           the first part of the ROM-able zImage which in turn loads the
1861           rest the kernel image to RAM.
1862
1863 config ZBOOT_ROM_NONE
1864         bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1865         help
1866           Do not load image from SD or MMC
1867
1868 config ZBOOT_ROM_MMCIF
1869         bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1870         help
1871           Load image from MMCIF hardware block.
1872
1873 config ZBOOT_ROM_SH_MOBILE_SDHI
1874         bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1875         help
1876           Load image from SDHI hardware block
1877
1878 endchoice
1879
1880 config ARM_APPENDED_DTB
1881         bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1882         depends on OF
1883         help
1884           With this option, the boot code will look for a device tree binary
1885           (DTB) appended to zImage
1886           (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1887
1888           This is meant as a backward compatibility convenience for those
1889           systems with a bootloader that can't be upgraded to accommodate
1890           the documented boot protocol using a device tree.
1891
1892           Beware that there is very little in terms of protection against
1893           this option being confused by leftover garbage in memory that might
1894           look like a DTB header after a reboot if no actual DTB is appended
1895           to zImage.  Do not leave this option active in a production kernel
1896           if you don't intend to always append a DTB.  Proper passing of the
1897           location into r2 of a bootloader provided DTB is always preferable
1898           to this option.
1899
1900 config ARM_ATAG_DTB_COMPAT
1901         bool "Supplement the appended DTB with traditional ATAG information"
1902         depends on ARM_APPENDED_DTB
1903         help
1904           Some old bootloaders can't be updated to a DTB capable one, yet
1905           they provide ATAGs with memory configuration, the ramdisk address,
1906           the kernel cmdline string, etc.  Such information is dynamically
1907           provided by the bootloader and can't always be stored in a static
1908           DTB.  To allow a device tree enabled kernel to be used with such
1909           bootloaders, this option allows zImage to extract the information
1910           from the ATAG list and store it at run time into the appended DTB.
1911
1912 choice
1913         prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1914         default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1915
1916 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1917         bool "Use bootloader kernel arguments if available"
1918         help
1919           Uses the command-line options passed by the boot loader instead of
1920           the device tree bootargs property. If the boot loader doesn't provide
1921           any, the device tree bootargs property will be used.
1922
1923 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1924         bool "Extend with bootloader kernel arguments"
1925         help
1926           The command-line arguments provided by the boot loader will be
1927           appended to the the device tree bootargs property.
1928
1929 endchoice
1930
1931 config CMDLINE
1932         string "Default kernel command string"
1933         default ""
1934         help
1935           On some architectures (EBSA110 and CATS), there is currently no way
1936           for the boot loader to pass arguments to the kernel. For these
1937           architectures, you should supply some command-line options at build
1938           time by entering them here. As a minimum, you should specify the
1939           memory size and the root device (e.g., mem=64M root=/dev/nfs).
1940
1941 choice
1942         prompt "Kernel command line type" if CMDLINE != ""
1943         default CMDLINE_FROM_BOOTLOADER
1944         depends on ATAGS
1945
1946 config CMDLINE_FROM_BOOTLOADER
1947         bool "Use bootloader kernel arguments if available"
1948         help
1949           Uses the command-line options passed by the boot loader. If
1950           the boot loader doesn't provide any, the default kernel command
1951           string provided in CMDLINE will be used.
1952
1953 config CMDLINE_EXTEND
1954         bool "Extend bootloader kernel arguments"
1955         help
1956           The command-line arguments provided by the boot loader will be
1957           appended to the default kernel command string.
1958
1959 config CMDLINE_FORCE
1960         bool "Always use the default kernel command string"
1961         help
1962           Always use the default kernel command string, even if the boot
1963           loader passes other arguments to the kernel.
1964           This is useful if you cannot or don't want to change the
1965           command-line options your boot loader passes to the kernel.
1966 endchoice
1967
1968 config XIP_KERNEL
1969         bool "Kernel Execute-In-Place from ROM"
1970         depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1971         help
1972           Execute-In-Place allows the kernel to run from non-volatile storage
1973           directly addressable by the CPU, such as NOR flash. This saves RAM
1974           space since the text section of the kernel is not loaded from flash
1975           to RAM.  Read-write sections, such as the data section and stack,
1976           are still copied to RAM.  The XIP kernel is not compressed since
1977           it has to run directly from flash, so it will take more space to
1978           store it.  The flash address used to link the kernel object files,
1979           and for storing it, is configuration dependent. Therefore, if you
1980           say Y here, you must know the proper physical address where to
1981           store the kernel image depending on your own flash memory usage.
1982
1983           Also note that the make target becomes "make xipImage" rather than
1984           "make zImage" or "make Image".  The final kernel binary to put in
1985           ROM memory will be arch/arm/boot/xipImage.
1986
1987           If unsure, say N.
1988
1989 config XIP_PHYS_ADDR
1990         hex "XIP Kernel Physical Location"
1991         depends on XIP_KERNEL
1992         default "0x00080000"
1993         help
1994           This is the physical address in your flash memory the kernel will
1995           be linked for and stored to.  This address is dependent on your
1996           own flash usage.
1997
1998 config KEXEC
1999         bool "Kexec system call (EXPERIMENTAL)"
2000         depends on (!SMP || PM_SLEEP_SMP)
2001         help
2002           kexec is a system call that implements the ability to shutdown your
2003           current kernel, and to start another kernel.  It is like a reboot
2004           but it is independent of the system firmware.   And like a reboot
2005           you can start any kernel with it, not just Linux.
2006
2007           It is an ongoing process to be certain the hardware in a machine
2008           is properly shutdown, so do not be surprised if this code does not
2009           initially work for you.
2010
2011 config ATAGS_PROC
2012         bool "Export atags in procfs"
2013         depends on ATAGS && KEXEC
2014         default y
2015         help
2016           Should the atags used to boot the kernel be exported in an "atags"
2017           file in procfs. Useful with kexec.
2018
2019 config CRASH_DUMP
2020         bool "Build kdump crash kernel (EXPERIMENTAL)"
2021         help
2022           Generate crash dump after being started by kexec. This should
2023           be normally only set in special crash dump kernels which are
2024           loaded in the main kernel with kexec-tools into a specially
2025           reserved region and then later executed after a crash by
2026           kdump/kexec. The crash dump kernel must be compiled to a
2027           memory address not used by the main kernel
2028
2029           For more details see Documentation/kdump/kdump.txt
2030
2031 config AUTO_ZRELADDR
2032         bool "Auto calculation of the decompressed kernel image address"
2033         help
2034           ZRELADDR is the physical address where the decompressed kernel
2035           image will be placed. If AUTO_ZRELADDR is selected, the address
2036           will be determined at run-time by masking the current IP with
2037           0xf8000000. This assumes the zImage being placed in the first 128MB
2038           from start of memory.
2039
2040 endmenu
2041
2042 menu "CPU Power Management"
2043
2044 source "drivers/cpufreq/Kconfig"
2045
2046 source "drivers/cpuidle/Kconfig"
2047
2048 endmenu
2049
2050 menu "Floating point emulation"
2051
2052 comment "At least one emulation must be selected"
2053
2054 config FPE_NWFPE
2055         bool "NWFPE math emulation"
2056         depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2057         ---help---
2058           Say Y to include the NWFPE floating point emulator in the kernel.
2059           This is necessary to run most binaries. Linux does not currently
2060           support floating point hardware so you need to say Y here even if
2061           your machine has an FPA or floating point co-processor podule.
2062
2063           You may say N here if you are going to load the Acorn FPEmulator
2064           early in the bootup.
2065
2066 config FPE_NWFPE_XP
2067         bool "Support extended precision"
2068         depends on FPE_NWFPE
2069         help
2070           Say Y to include 80-bit support in the kernel floating-point
2071           emulator.  Otherwise, only 32 and 64-bit support is compiled in.
2072           Note that gcc does not generate 80-bit operations by default,
2073           so in most cases this option only enlarges the size of the
2074           floating point emulator without any good reason.
2075
2076           You almost surely want to say N here.
2077
2078 config FPE_FASTFPE
2079         bool "FastFPE math emulation (EXPERIMENTAL)"
2080         depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2081         ---help---
2082           Say Y here to include the FAST floating point emulator in the kernel.
2083           This is an experimental much faster emulator which now also has full
2084           precision for the mantissa.  It does not support any exceptions.
2085           It is very simple, and approximately 3-6 times faster than NWFPE.
2086
2087           It should be sufficient for most programs.  It may be not suitable
2088           for scientific calculations, but you have to check this for yourself.
2089           If you do not feel you need a faster FP emulation you should better
2090           choose NWFPE.
2091
2092 config VFP
2093         bool "VFP-format floating point maths"
2094         depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2095         help
2096           Say Y to include VFP support code in the kernel. This is needed
2097           if your hardware includes a VFP unit.
2098
2099           Please see <file:Documentation/arm/VFP/release-notes.txt> for
2100           release notes and additional status information.
2101
2102           Say N if your target does not have VFP hardware.
2103
2104 config VFPv3
2105         bool
2106         depends on VFP
2107         default y if CPU_V7
2108
2109 config NEON
2110         bool "Advanced SIMD (NEON) Extension support"
2111         depends on VFPv3 && CPU_V7
2112         help
2113           Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2114           Extension.
2115
2116 config KERNEL_MODE_NEON
2117         bool "Support for NEON in kernel mode"
2118         depends on NEON && AEABI
2119         help
2120           Say Y to include support for NEON in kernel mode.
2121
2122 endmenu
2123
2124 menu "Userspace binary formats"
2125
2126 source "fs/Kconfig.binfmt"
2127
2128 config ARTHUR
2129         tristate "RISC OS personality"
2130         depends on !AEABI
2131         help
2132           Say Y here to include the kernel code necessary if you want to run
2133           Acorn RISC OS/Arthur binaries under Linux. This code is still very
2134           experimental; if this sounds frightening, say N and sleep in peace.
2135           You can also say M here to compile this support as a module (which
2136           will be called arthur).
2137
2138 endmenu
2139
2140 menu "Power management options"
2141
2142 source "kernel/power/Kconfig"
2143
2144 config ARCH_SUSPEND_POSSIBLE
2145         depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2146                 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2147         def_bool y
2148
2149 config ARM_CPU_SUSPEND
2150         def_bool PM_SLEEP
2151
2152 config ARCH_HIBERNATION_POSSIBLE
2153         bool
2154         depends on MMU
2155         default y if ARCH_SUSPEND_POSSIBLE
2156
2157 endmenu
2158
2159 source "net/Kconfig"
2160
2161 source "drivers/Kconfig"
2162
2163 source "fs/Kconfig"
2164
2165 source "arch/arm/Kconfig.debug"
2166
2167 source "security/Kconfig"
2168
2169 source "crypto/Kconfig"
2170
2171 source "lib/Kconfig"
2172
2173 source "arch/arm/kvm/Kconfig"