arch/arm/Kconfig

   1 config ARM
   2         bool
   3         default y
   4         select ARCH_BINFMT_ELF_RANDOMIZE_PIE
   5         select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
   6         select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
   7         select ARCH_HAVE_CUSTOM_GPIO_H
   8         select ARCH_HAS_GCOV_PROFILE_ALL
   9         select ARCH_MIGHT_HAVE_PC_PARPORT
  10         select ARCH_SUPPORTS_ATOMIC_RMW
  11         select ARCH_USE_BUILTIN_BSWAP
  12         select ARCH_USE_CMPXCHG_LOCKREF
  13         select ARCH_WANT_IPC_PARSE_VERSION
  14         select BUILDTIME_EXTABLE_SORT if MMU
  15         select CLONE_BACKWARDS
  16         select CPU_PM if (SUSPEND || CPU_IDLE)
  17         select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
  18         select GENERIC_ALLOCATOR
  19         select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
  20         select GENERIC_CLOCKEVENTS_BROADCAST if SMP
  21         select GENERIC_IDLE_POLL_SETUP
  22         select GENERIC_IRQ_PROBE
  23         select GENERIC_IRQ_SHOW
  24         select GENERIC_PCI_IOMAP
  25         select GENERIC_SCHED_CLOCK
  26         select GENERIC_SMP_IDLE_THREAD
  27         select GENERIC_STRNCPY_FROM_USER
  28         select GENERIC_STRNLEN_USER
  29         select HANDLE_DOMAIN_IRQ
  30         select HARDIRQS_SW_RESEND
  31         select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
  32         select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
  33         select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
  34         select HAVE_ARCH_KGDB
  35         select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
  36         select HAVE_ARCH_TRACEHOOK
  37         select HAVE_BPF_JIT
  38         select HAVE_CC_STACKPROTECTOR
  39         select HAVE_CONTEXT_TRACKING
  40         select HAVE_C_RECORDMCOUNT
  41         select HAVE_DEBUG_KMEMLEAK
  42         select HAVE_DMA_API_DEBUG
  43         select HAVE_DMA_ATTRS
  44         select HAVE_DMA_CONTIGUOUS if MMU
  45         select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
  46         select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
  47         select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
  48         select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
  49         select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
  50         select HAVE_GENERIC_DMA_COHERENT
  51         select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
  52         select HAVE_IDE if PCI || ISA || PCMCIA
  53         select HAVE_IRQ_TIME_ACCOUNTING
  54         select HAVE_KERNEL_GZIP
  55         select HAVE_KERNEL_LZ4
  56         select HAVE_KERNEL_LZMA
  57         select HAVE_KERNEL_LZO
  58         select HAVE_KERNEL_XZ
  59         select HAVE_KPROBES if !XIP_KERNEL
  60         select HAVE_KRETPROBES if (HAVE_KPROBES)
  61         select HAVE_MEMBLOCK
  62         select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
  63         select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
  64         select HAVE_OPTPROBES if !THUMB2_KERNEL
  65         select HAVE_PERF_EVENTS
  66         select HAVE_PERF_REGS
  67         select HAVE_PERF_USER_STACK_DUMP
  68         select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
  69         select HAVE_REGS_AND_STACK_ACCESS_API
  70         select HAVE_SYSCALL_TRACEPOINTS
  71         select HAVE_UID16
  72         select HAVE_VIRT_CPU_ACCOUNTING_GEN
  73         select IRQ_FORCED_THREADING
  74         select MODULES_USE_ELF_REL
  75         select NO_BOOTMEM
  76         select OLD_SIGACTION
  77         select OLD_SIGSUSPEND3
  78         select PERF_USE_VMALLOC
  79         select RTC_LIB
  80         select SYS_SUPPORTS_APM_EMULATION
  81         # Above selects are sorted alphabetically; please add new ones
  82         # according to that.  Thanks.
  83         help
  84           The ARM series is a line of low-power-consumption RISC chip designs
  85           licensed by ARM Ltd and targeted at embedded applications and
  86           handhelds such as the Compaq IPAQ.  ARM-based PCs are no longer
  87           manufactured, but legacy ARM-based PC hardware remains popular in
  88           Europe.  There is an ARM Linux project with a web page at
  89           <http://www.arm.linux.org.uk/>.
  90
  91 config ARM_HAS_SG_CHAIN
  92         select ARCH_HAS_SG_CHAIN
  93         bool
  94
  95 config NEED_SG_DMA_LENGTH
  96         bool
  97
  98 config ARM_DMA_USE_IOMMU
  99         bool
 100         select ARM_HAS_SG_CHAIN
 101         select NEED_SG_DMA_LENGTH
 102
 103 if ARM_DMA_USE_IOMMU
 104
 105 config ARM_DMA_IOMMU_ALIGNMENT
 106         int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
 107         range 4 9
 108         default 8
 109         help
 110           DMA mapping framework by default aligns all buffers to the smallest
 111           PAGE_SIZE order which is greater than or equal to the requested buffer
 112           size. This works well for buffers up to a few hundreds kilobytes, but
 113           for larger buffers it just a waste of address space. Drivers which has
 114           relatively small addressing window (like 64Mib) might run out of
 115           virtual space with just a few allocations.
 116
 117           With this parameter you can specify the maximum PAGE_SIZE order for
 118           DMA IOMMU buffers. Larger buffers will be aligned only to this
 119           specified order. The order is expressed as a power of two multiplied
 120           by the PAGE_SIZE.
 121
 122 endif
 123
 124 config MIGHT_HAVE_PCI
 125         bool
 126
 127 config SYS_SUPPORTS_APM_EMULATION
 128         bool
 129
 130 config HAVE_TCM
 131         bool
 132         select GENERIC_ALLOCATOR
 133
 134 config HAVE_PROC_CPU
 135         bool
 136
 137 config NO_IOPORT_MAP
 138         bool
 139
 140 config EISA
 141         bool
 142         ---help---
 143           The Extended Industry Standard Architecture (EISA) bus was
 144           developed as an open alternative to the IBM MicroChannel bus.
 145
 146           The EISA bus provided some of the features of the IBM MicroChannel
 147           bus while maintaining backward compatibility with cards made for
 148           the older ISA bus.  The EISA bus saw limited use between 1988 and
 149           1995 when it was made obsolete by the PCI bus.
 150
 151           Say Y here if you are building a kernel for an EISA-based machine.
 152
 153           Otherwise, say N.
 154
 155 config SBUS
 156         bool
 157
 158 config STACKTRACE_SUPPORT
 159         bool
 160         default y
 161
 162 config HAVE_LATENCYTOP_SUPPORT
 163         bool
 164         depends on !SMP
 165         default y
 166
 167 config LOCKDEP_SUPPORT
 168         bool
 169         default y
 170
 171 config TRACE_IRQFLAGS_SUPPORT
 172         bool
 173         default y
 174
 175 config RWSEM_XCHGADD_ALGORITHM
 176         bool
 177         default y
 178
 179 config ARCH_HAS_ILOG2_U32
 180         bool
 181
 182 config ARCH_HAS_ILOG2_U64
 183         bool
 184
 185 config ARCH_HAS_BANDGAP
 186         bool
 187
 188 config GENERIC_HWEIGHT
 189         bool
 190         default y
 191
 192 config GENERIC_CALIBRATE_DELAY
 193         bool
 194         default y
 195
 196 config ARCH_MAY_HAVE_PC_FDC
 197         bool
 198
 199 config ZONE_DMA
 200         bool
 201
 202 config NEED_DMA_MAP_STATE
 203        def_bool y
 204
 205 config ARCH_SUPPORTS_UPROBES
 206         def_bool y
 207
 208 config ARCH_HAS_DMA_SET_COHERENT_MASK
 209         bool
 210
 211 config GENERIC_ISA_DMA
 212         bool
 213
 214 config FIQ
 215         bool
 216
 217 config NEED_RET_TO_USER
 218         bool
 219
 220 config ARCH_MTD_XIP
 221         bool
 222
 223 config VECTORS_BASE
 224         hex
 225         default 0xffff0000 if MMU || CPU_HIGH_VECTOR
 226         default DRAM_BASE if REMAP_VECTORS_TO_RAM
 227         default 0x00000000
 228         help
 229           The base address of exception vectors.  This must be two pages
 230           in size.
 231
 232 config ARM_PATCH_PHYS_VIRT
 233         bool "Patch physical to virtual translations at runtime" if EMBEDDED
 234         default y
 235         depends on !XIP_KERNEL && MMU
 236         depends on !ARCH_REALVIEW || !SPARSEMEM
 237         help
 238           Patch phys-to-virt and virt-to-phys translation functions at
 239           boot and module load time according to the position of the
 240           kernel in system memory.
 241
 242           This can only be used with non-XIP MMU kernels where the base
 243           of physical memory is at a 16MB boundary.
 244
 245           Only disable this option if you know that you do not require
 246           this feature (eg, building a kernel for a single machine) and
 247           you need to shrink the kernel to the minimal size.
 248
 249 config NEED_MACH_IO_H
 250         bool
 251         help
 252           Select this when mach/io.h is required to provide special
 253           definitions for this platform.  The need for mach/io.h should
 254           be avoided when possible.
 255
 256 config NEED_MACH_MEMORY_H
 257         bool
 258         help
 259           Select this when mach/memory.h is required to provide special
 260           definitions for this platform.  The need for mach/memory.h should
 261           be avoided when possible.
 262
 263 config PHYS_OFFSET
 264         hex "Physical address of main memory" if MMU
 265         depends on !ARM_PATCH_PHYS_VIRT
 266         default DRAM_BASE if !MMU
 267         default 0x00000000 if ARCH_EBSA110 || \
 268                         EP93XX_SDCE3_SYNC_PHYS_OFFSET || \
 269                         ARCH_FOOTBRIDGE || \
 270                         ARCH_INTEGRATOR || \
 271                         ARCH_IOP13XX || \
 272                         ARCH_KS8695 || \
 273                         (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET)
 274         default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
 275         default 0x20000000 if ARCH_S5PV210
 276         default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET
 277         default 0xc0000000 if EP93XX_SDCE0_PHYS_OFFSET || ARCH_SA1100
 278         default 0xd0000000 if EP93XX_SDCE1_PHYS_OFFSET
 279         default 0xe0000000 if EP93XX_SDCE2_PHYS_OFFSET
 280         default 0xf0000000 if EP93XX_SDCE3_ASYNC_PHYS_OFFSET
 281         help
 282           Please provide the physical address corresponding to the
 283           location of main memory in your system.
 284
 285 config GENERIC_BUG
 286         def_bool y
 287         depends on BUG
 288
 289 source "init/Kconfig"
 290
 291 source "kernel/Kconfig.freezer"
 292
 293 menu "System Type"
 294
 295 config MMU
 296         bool "MMU-based Paged Memory Management Support"
 297         default y
 298         help
 299           Select if you want MMU-based virtualised addressing space
 300           support by paged memory management. If unsure, say 'Y'.
 301
 302 #
 303 # The "ARM system type" choice list is ordered alphabetically by option
 304 # text.  Please add new entries in the option alphabetic order.
 305 #
 306 choice
 307         prompt "ARM system type"
 308         default ARCH_VERSATILE if !MMU
 309         default ARCH_MULTIPLATFORM if MMU
 310
 311 config ARCH_MULTIPLATFORM
 312         bool "Allow multiple platforms to be selected"
 313         depends on MMU
 314         select ARCH_WANT_OPTIONAL_GPIOLIB
 315         select ARM_HAS_SG_CHAIN
 316         select ARM_PATCH_PHYS_VIRT
 317         select AUTO_ZRELADDR
 318         select CLKSRC_OF
 319         select COMMON_CLK
 320         select GENERIC_CLOCKEVENTS
 321         select MIGHT_HAVE_PCI
 322         select MULTI_IRQ_HANDLER
 323         select SPARSE_IRQ
 324         select USE_OF
 325
 326 config ARCH_REALVIEW
 327         bool "ARM Ltd. RealView family"
 328         select ARCH_WANT_OPTIONAL_GPIOLIB
 329         select ARM_AMBA
 330         select ARM_TIMER_SP804
 331         select COMMON_CLK
 332         select COMMON_CLK_VERSATILE
 333         select GENERIC_CLOCKEVENTS
 334         select GPIO_PL061 if GPIOLIB
 335         select ICST
 336         select NEED_MACH_MEMORY_H
 337         select PLAT_VERSATILE
 338         select PLAT_VERSATILE_SCHED_CLOCK
 339         help
 340           This enables support for ARM Ltd RealView boards.
 341
 342 config ARCH_VERSATILE
 343         bool "ARM Ltd. Versatile family"
 344         select ARCH_WANT_OPTIONAL_GPIOLIB
 345         select ARM_AMBA
 346         select ARM_TIMER_SP804
 347         select ARM_VIC
 348         select CLKDEV_LOOKUP
 349         select GENERIC_CLOCKEVENTS
 350         select HAVE_MACH_CLKDEV
 351         select ICST
 352         select PLAT_VERSATILE
 353         select PLAT_VERSATILE_CLOCK
 354         select PLAT_VERSATILE_SCHED_CLOCK
 355         select VERSATILE_FPGA_IRQ
 356         help
 357           This enables support for ARM Ltd Versatile board.
 358
 359 config ARCH_AT91
 360         bool "Atmel AT91"
 361         select ARCH_REQUIRE_GPIOLIB
 362         select CLKDEV_LOOKUP
 363         select IRQ_DOMAIN
 364         select NEED_MACH_IO_H if PCCARD
 365         select PINCTRL
 366         select PINCTRL_AT91
 367         select USE_OF
 368         help
 369           This enables support for systems based on Atmel
 370           AT91RM9200, AT91SAM9 and SAMA5 processors.
 371
 372 config ARCH_CLPS711X
 373         bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
 374         select ARCH_REQUIRE_GPIOLIB
 375         select AUTO_ZRELADDR
 376         select CLKSRC_MMIO
 377         select COMMON_CLK
 378         select CPU_ARM720T
 379         select GENERIC_CLOCKEVENTS
 380         select MFD_SYSCON
 381         select SOC_BUS
 382         help
 383           Support for Cirrus Logic 711x/721x/731x based boards.
 384
 385 config ARCH_GEMINI
 386         bool "Cortina Systems Gemini"
 387         select ARCH_REQUIRE_GPIOLIB
 388         select CLKSRC_MMIO
 389         select CPU_FA526
 390         select GENERIC_CLOCKEVENTS
 391         help
 392           Support for the Cortina Systems Gemini family SoCs
 393
 394 config ARCH_EBSA110
 395         bool "EBSA-110"
 396         select ARCH_USES_GETTIMEOFFSET
 397         select CPU_SA110
 398         select ISA
 399         select NEED_MACH_IO_H
 400         select NEED_MACH_MEMORY_H
 401         select NO_IOPORT_MAP
 402         help
 403           This is an evaluation board for the StrongARM processor available
 404           from Digital. It has limited hardware on-board, including an
 405           Ethernet interface, two PCMCIA sockets, two serial ports and a
 406           parallel port.
 407
 408 config ARCH_EFM32
 409         bool "Energy Micro efm32"
 410         depends on !MMU
 411         select ARCH_REQUIRE_GPIOLIB
 412         select ARM_NVIC
 413         select AUTO_ZRELADDR
 414         select CLKSRC_OF
 415         select COMMON_CLK
 416         select CPU_V7M
 417         select GENERIC_CLOCKEVENTS
 418         select NO_DMA
 419         select NO_IOPORT_MAP
 420         select SPARSE_IRQ
 421         select USE_OF
 422         help
 423           Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
 424           processors.
 425
 426 config ARCH_EP93XX
 427         bool "EP93xx-based"
 428         select ARCH_HAS_HOLES_MEMORYMODEL
 429         select ARCH_REQUIRE_GPIOLIB
 430         select ARCH_USES_GETTIMEOFFSET
 431         select ARM_AMBA
 432         select ARM_VIC
 433         select CLKDEV_LOOKUP
 434         select CPU_ARM920T
 435         help
 436           This enables support for the Cirrus EP93xx series of CPUs.
 437
 438 config ARCH_FOOTBRIDGE
 439         bool "FootBridge"
 440         select CPU_SA110
 441         select FOOTBRIDGE
 442         select GENERIC_CLOCKEVENTS
 443         select HAVE_IDE
 444         select NEED_MACH_IO_H if !MMU
 445         select NEED_MACH_MEMORY_H
 446         help
 447           Support for systems based on the DC21285 companion chip
 448           ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
 449
 450 config ARCH_NETX
 451         bool "Hilscher NetX based"
 452         select ARM_VIC
 453         select CLKSRC_MMIO
 454         select CPU_ARM926T
 455         select GENERIC_CLOCKEVENTS
 456         help
 457           This enables support for systems based on the Hilscher NetX Soc
 458
 459 config ARCH_IOP13XX
 460         bool "IOP13xx-based"
 461         depends on MMU
 462         select CPU_XSC3
 463         select NEED_MACH_MEMORY_H
 464         select NEED_RET_TO_USER
 465         select PCI
 466         select PLAT_IOP
 467         select VMSPLIT_1G
 468         select SPARSE_IRQ
 469         help
 470           Support for Intel's IOP13XX (XScale) family of processors.
 471
 472 config ARCH_IOP32X
 473         bool "IOP32x-based"
 474         depends on MMU
 475         select ARCH_REQUIRE_GPIOLIB
 476         select CPU_XSCALE
 477         select GPIO_IOP
 478         select NEED_RET_TO_USER
 479         select PCI
 480         select PLAT_IOP
 481         help
 482           Support for Intel's 80219 and IOP32X (XScale) family of
 483           processors.
 484
 485 config ARCH_IOP33X
 486         bool "IOP33x-based"
 487         depends on MMU
 488         select ARCH_REQUIRE_GPIOLIB
 489         select CPU_XSCALE
 490         select GPIO_IOP
 491         select NEED_RET_TO_USER
 492         select PCI
 493         select PLAT_IOP
 494         help
 495           Support for Intel's IOP33X (XScale) family of processors.
 496
 497 config ARCH_IXP4XX
 498         bool "IXP4xx-based"
 499         depends on MMU
 500         select ARCH_HAS_DMA_SET_COHERENT_MASK
 501         select ARCH_REQUIRE_GPIOLIB
 502         select ARCH_SUPPORTS_BIG_ENDIAN
 503         select CLKSRC_MMIO
 504         select CPU_XSCALE
 505         select DMABOUNCE if PCI
 506         select GENERIC_CLOCKEVENTS
 507         select MIGHT_HAVE_PCI
 508         select NEED_MACH_IO_H
 509         select USB_EHCI_BIG_ENDIAN_DESC
 510         select USB_EHCI_BIG_ENDIAN_MMIO
 511         help
 512           Support for Intel's IXP4XX (XScale) family of processors.
 513
 514 config ARCH_DOVE
 515         bool "Marvell Dove"
 516         select ARCH_REQUIRE_GPIOLIB
 517         select CPU_PJ4
 518         select GENERIC_CLOCKEVENTS
 519         select MIGHT_HAVE_PCI
 520         select MVEBU_MBUS
 521         select PINCTRL
 522         select PINCTRL_DOVE
 523         select PLAT_ORION_LEGACY
 524         help
 525           Support for the Marvell Dove SoC 88AP510
 526
 527 config ARCH_MV78XX0
 528         bool "Marvell MV78xx0"
 529         select ARCH_REQUIRE_GPIOLIB
 530         select CPU_FEROCEON
 531         select GENERIC_CLOCKEVENTS
 532         select MVEBU_MBUS
 533         select PCI
 534         select PLAT_ORION_LEGACY
 535         help
 536           Support for the following Marvell MV78xx0 series SoCs:
 537           MV781x0, MV782x0.
 538
 539 config ARCH_ORION5X
 540         bool "Marvell Orion"
 541         depends on MMU
 542         select ARCH_REQUIRE_GPIOLIB
 543         select CPU_FEROCEON
 544         select GENERIC_CLOCKEVENTS
 545         select MVEBU_MBUS
 546         select PCI
 547         select PLAT_ORION_LEGACY
 548         help
 549           Support for the following Marvell Orion 5x series SoCs:
 550           Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
 551           Orion-2 (5281), Orion-1-90 (6183).
 552
 553 config ARCH_MMP
 554         bool "Marvell PXA168/910/MMP2"
 555         depends on MMU
 556         select ARCH_REQUIRE_GPIOLIB
 557         select CLKDEV_LOOKUP
 558         select GENERIC_ALLOCATOR
 559         select GENERIC_CLOCKEVENTS
 560         select GPIO_PXA
 561         select IRQ_DOMAIN
 562         select MULTI_IRQ_HANDLER
 563         select PINCTRL
 564         select PLAT_PXA
 565         select SPARSE_IRQ
 566         help
 567           Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
 568
 569 config ARCH_KS8695
 570         bool "Micrel/Kendin KS8695"
 571         select ARCH_REQUIRE_GPIOLIB
 572         select CLKSRC_MMIO
 573         select CPU_ARM922T
 574         select GENERIC_CLOCKEVENTS
 575         select NEED_MACH_MEMORY_H
 576         help
 577           Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
 578           System-on-Chip devices.
 579
 580 config ARCH_W90X900
 581         bool "Nuvoton W90X900 CPU"
 582         select ARCH_REQUIRE_GPIOLIB
 583         select CLKDEV_LOOKUP
 584         select CLKSRC_MMIO
 585         select CPU_ARM926T
 586         select GENERIC_CLOCKEVENTS
 587         help
 588           Support for Nuvoton (Winbond logic dept.) ARM9 processor,
 589           At present, the w90x900 has been renamed nuc900, regarding
 590           the ARM series product line, you can login the following
 591           link address to know more.
 592
 593           <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
 594                 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
 595
 596 config ARCH_LPC32XX
 597         bool "NXP LPC32XX"
 598         select ARCH_REQUIRE_GPIOLIB
 599         select ARM_AMBA
 600         select CLKDEV_LOOKUP
 601         select CLKSRC_MMIO
 602         select CPU_ARM926T
 603         select GENERIC_CLOCKEVENTS
 604         select HAVE_IDE
 605         select USE_OF
 606         help
 607           Support for the NXP LPC32XX family of processors
 608
 609 config ARCH_PXA
 610         bool "PXA2xx/PXA3xx-based"
 611         depends on MMU
 612         select ARCH_MTD_XIP
 613         select ARCH_REQUIRE_GPIOLIB
 614         select ARM_CPU_SUSPEND if PM
 615         select AUTO_ZRELADDR
 616         select CLKDEV_LOOKUP
 617         select CLKSRC_MMIO
 618         select CLKSRC_OF
 619         select GENERIC_CLOCKEVENTS
 620         select GPIO_PXA
 621         select HAVE_IDE
 622         select MULTI_IRQ_HANDLER
 623         select PLAT_PXA
 624         select SPARSE_IRQ
 625         help
 626           Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
 627
 628 config ARCH_MSM
 629         bool "Qualcomm MSM (non-multiplatform)"
 630         select ARCH_REQUIRE_GPIOLIB
 631         select COMMON_CLK
 632         select GENERIC_CLOCKEVENTS
 633         help
 634           Support for Qualcomm MSM/QSD based systems.  This runs on the
 635           apps processor of the MSM/QSD and depends on a shared memory
 636           interface to the modem processor which runs the baseband
 637           stack and controls some vital subsystems
 638           (clock and power control, etc).
 639
 640 config ARCH_SHMOBILE_LEGACY
 641         bool "Renesas ARM SoCs (non-multiplatform)"
 642         select ARCH_SHMOBILE
 643         select ARM_PATCH_PHYS_VIRT if MMU
 644         select CLKDEV_LOOKUP
 645         select CPU_V7
 646         select GENERIC_CLOCKEVENTS
 647         select HAVE_ARM_SCU if SMP
 648         select HAVE_ARM_TWD if SMP
 649         select HAVE_MACH_CLKDEV
 650         select HAVE_SMP
 651         select MIGHT_HAVE_CACHE_L2X0
 652         select MULTI_IRQ_HANDLER
 653         select NO_IOPORT_MAP
 654         select PINCTRL
 655         select PM_GENERIC_DOMAINS if PM
 656         select SH_CLK_CPG
 657         select SPARSE_IRQ
 658         help
 659           Support for Renesas ARM SoC platforms using a non-multiplatform
 660           kernel. This includes the SH-Mobile, R-Mobile, EMMA-Mobile, R-Car
 661           and RZ families.
 662
 663 config ARCH_RPC
 664         bool "RiscPC"
 665         select ARCH_ACORN
 666         select ARCH_MAY_HAVE_PC_FDC
 667         select ARCH_SPARSEMEM_ENABLE
 668         select ARCH_USES_GETTIMEOFFSET
 669         select CPU_SA110
 670         select FIQ
 671         select HAVE_IDE
 672         select HAVE_PATA_PLATFORM
 673         select ISA_DMA_API
 674         select NEED_MACH_IO_H
 675         select NEED_MACH_MEMORY_H
 676         select NO_IOPORT_MAP
 677         select VIRT_TO_BUS
 678         help
 679           On the Acorn Risc-PC, Linux can support the internal IDE disk and
 680           CD-ROM interface, serial and parallel port, and the floppy drive.
 681
 682 config ARCH_SA1100
 683         bool "SA1100-based"
 684         select ARCH_MTD_XIP
 685         select ARCH_REQUIRE_GPIOLIB
 686         select ARCH_SPARSEMEM_ENABLE
 687         select CLKDEV_LOOKUP
 688         select CLKSRC_MMIO
 689         select CPU_FREQ
 690         select CPU_SA1100
 691         select GENERIC_CLOCKEVENTS
 692         select HAVE_IDE
 693         select IRQ_DOMAIN
 694         select ISA
 695         select MULTI_IRQ_HANDLER
 696         select NEED_MACH_MEMORY_H
 697         select SPARSE_IRQ
 698         help
 699           Support for StrongARM 11x0 based boards.
 700
 701 config ARCH_S3C24XX
 702         bool "Samsung S3C24XX SoCs"
 703         select ARCH_REQUIRE_GPIOLIB
 704         select ATAGS
 705         select CLKDEV_LOOKUP
 706         select CLKSRC_SAMSUNG_PWM
 707         select GENERIC_CLOCKEVENTS
 708         select GPIO_SAMSUNG
 709         select HAVE_S3C2410_I2C if I2C
 710         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 711         select HAVE_S3C_RTC if RTC_CLASS
 712         select MULTI_IRQ_HANDLER
 713         select NEED_MACH_IO_H
 714         select SAMSUNG_ATAGS
 715         help
 716           Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
 717           and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
 718           (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
 719           Samsung SMDK2410 development board (and derivatives).
 720
 721 config ARCH_S3C64XX
 722         bool "Samsung S3C64XX"
 723         select ARCH_REQUIRE_GPIOLIB
 724         select ARM_AMBA
 725         select ARM_VIC
 726         select ATAGS
 727         select CLKDEV_LOOKUP
 728         select CLKSRC_SAMSUNG_PWM
 729         select COMMON_CLK_SAMSUNG
 730         select CPU_V6K
 731         select GENERIC_CLOCKEVENTS
 732         select GPIO_SAMSUNG
 733         select HAVE_S3C2410_I2C if I2C
 734         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 735         select HAVE_TCM
 736         select NO_IOPORT_MAP
 737         select PLAT_SAMSUNG
 738         select PM_GENERIC_DOMAINS if PM
 739         select S3C_DEV_NAND
 740         select S3C_GPIO_TRACK
 741         select SAMSUNG_ATAGS
 742         select SAMSUNG_WAKEMASK
 743         select SAMSUNG_WDT_RESET
 744         help
 745           Samsung S3C64XX series based systems
 746
 747 config ARCH_DAVINCI
 748         bool "TI DaVinci"
 749         select ARCH_HAS_HOLES_MEMORYMODEL
 750         select ARCH_REQUIRE_GPIOLIB
 751         select CLKDEV_LOOKUP
 752         select GENERIC_ALLOCATOR
 753         select GENERIC_CLOCKEVENTS
 754         select GENERIC_IRQ_CHIP
 755         select HAVE_IDE
 756         select TI_PRIV_EDMA
 757         select USE_OF
 758         select ZONE_DMA
 759         help
 760           Support for TI's DaVinci platform.
 761
 762 config ARCH_OMAP1
 763         bool "TI OMAP1"
 764         depends on MMU
 765         select ARCH_HAS_HOLES_MEMORYMODEL
 766         select ARCH_OMAP
 767         select ARCH_REQUIRE_GPIOLIB
 768         select CLKDEV_LOOKUP
 769         select CLKSRC_MMIO
 770         select GENERIC_CLOCKEVENTS
 771         select GENERIC_IRQ_CHIP
 772         select HAVE_IDE
 773         select IRQ_DOMAIN
 774         select NEED_MACH_IO_H if PCCARD
 775         select NEED_MACH_MEMORY_H
 776         help
 777           Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
 778
 779 endchoice
 780
 781 menu "Multiple platform selection"
 782         depends on ARCH_MULTIPLATFORM
 783
 784 comment "CPU Core family selection"
 785
 786 config ARCH_MULTI_V4
 787         bool "ARMv4 based platforms (FA526)"
 788         depends on !ARCH_MULTI_V6_V7
 789         select ARCH_MULTI_V4_V5
 790         select CPU_FA526
 791
 792 config ARCH_MULTI_V4T
 793         bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
 794         depends on !ARCH_MULTI_V6_V7
 795         select ARCH_MULTI_V4_V5
 796         select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
 797                 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
 798                 CPU_ARM925T || CPU_ARM940T)
 799
 800 config ARCH_MULTI_V5
 801         bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
 802         depends on !ARCH_MULTI_V6_V7
 803         select ARCH_MULTI_V4_V5
 804         select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
 805                 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
 806                 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
 807
 808 config ARCH_MULTI_V4_V5
 809         bool
 810
 811 config ARCH_MULTI_V6
 812         bool "ARMv6 based platforms (ARM11)"
 813         select ARCH_MULTI_V6_V7
 814         select CPU_V6K
 815
 816 config ARCH_MULTI_V7
 817         bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
 818         default y
 819         select ARCH_MULTI_V6_V7
 820         select CPU_V7
 821         select HAVE_SMP
 822
 823 config ARCH_MULTI_V6_V7
 824         bool
 825         select MIGHT_HAVE_CACHE_L2X0
 826
 827 config ARCH_MULTI_CPU_AUTO
 828         def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
 829         select ARCH_MULTI_V5
 830
 831 endmenu
 832
 833 config ARCH_VIRT
 834         bool "Dummy Virtual Machine" if ARCH_MULTI_V7
 835         select ARM_AMBA
 836         select ARM_GIC
 837         select ARM_PSCI
 838         select HAVE_ARM_ARCH_TIMER
 839
 840 #
 841 # This is sorted alphabetically by mach-* pathname.  However, plat-*
 842 # Kconfigs may be included either alphabetically (according to the
 843 # plat- suffix) or along side the corresponding mach-* source.
 844 #
 845 source "arch/arm/mach-mvebu/Kconfig"
 846
 847 source "arch/arm/mach-asm9260/Kconfig"
 848
 849 source "arch/arm/mach-at91/Kconfig"
 850
 851 source "arch/arm/mach-axxia/Kconfig"
 852
 853 source "arch/arm/mach-bcm/Kconfig"
 854
 855 source "arch/arm/mach-berlin/Kconfig"
 856
 857 source "arch/arm/mach-clps711x/Kconfig"
 858
 859 source "arch/arm/mach-cns3xxx/Kconfig"
 860
 861 source "arch/arm/mach-davinci/Kconfig"
 862
 863 source "arch/arm/mach-dove/Kconfig"
 864
 865 source "arch/arm/mach-ep93xx/Kconfig"
 866
 867 source "arch/arm/mach-footbridge/Kconfig"
 868
 869 source "arch/arm/mach-gemini/Kconfig"
 870
 871 source "arch/arm/mach-highbank/Kconfig"
 872
 873 source "arch/arm/mach-hisi/Kconfig"
 874
 875 source "arch/arm/mach-integrator/Kconfig"
 876
 877 source "arch/arm/mach-iop32x/Kconfig"
 878
 879 source "arch/arm/mach-iop33x/Kconfig"
 880
 881 source "arch/arm/mach-iop13xx/Kconfig"
 882
 883 source "arch/arm/mach-ixp4xx/Kconfig"
 884
 885 source "arch/arm/mach-keystone/Kconfig"
 886
 887 source "arch/arm/mach-ks8695/Kconfig"
 888
 889 source "arch/arm/mach-meson/Kconfig"
 890
 891 source "arch/arm/mach-msm/Kconfig"
 892
 893 source "arch/arm/mach-moxart/Kconfig"
 894
 895 source "arch/arm/mach-mv78xx0/Kconfig"
 896
 897 source "arch/arm/mach-imx/Kconfig"
 898
 899 source "arch/arm/mach-mediatek/Kconfig"
 900
 901 source "arch/arm/mach-mxs/Kconfig"
 902
 903 source "arch/arm/mach-netx/Kconfig"
 904
 905 source "arch/arm/mach-nomadik/Kconfig"
 906
 907 source "arch/arm/mach-nspire/Kconfig"
 908
 909 source "arch/arm/plat-omap/Kconfig"
 910
 911 source "arch/arm/mach-omap1/Kconfig"
 912
 913 source "arch/arm/mach-omap2/Kconfig"
 914
 915 source "arch/arm/mach-orion5x/Kconfig"
 916
 917 source "arch/arm/mach-picoxcell/Kconfig"
 918
 919 source "arch/arm/mach-pxa/Kconfig"
 920 source "arch/arm/plat-pxa/Kconfig"
 921
 922 source "arch/arm/mach-mmp/Kconfig"
 923
 924 source "arch/arm/mach-qcom/Kconfig"
 925
 926 source "arch/arm/mach-realview/Kconfig"
 927
 928 source "arch/arm/mach-rockchip/Kconfig"
 929
 930 source "arch/arm/mach-sa1100/Kconfig"
 931
 932 source "arch/arm/mach-socfpga/Kconfig"
 933
 934 source "arch/arm/mach-spear/Kconfig"
 935
 936 source "arch/arm/mach-sti/Kconfig"
 937
 938 source "arch/arm/mach-s3c24xx/Kconfig"
 939
 940 source "arch/arm/mach-s3c64xx/Kconfig"
 941
 942 source "arch/arm/mach-s5pv210/Kconfig"
 943
 944 source "arch/arm/mach-exynos/Kconfig"
 945 source "arch/arm/plat-samsung/Kconfig"
 946
 947 source "arch/arm/mach-shmobile/Kconfig"
 948
 949 source "arch/arm/mach-sunxi/Kconfig"
 950
 951 source "arch/arm/mach-prima2/Kconfig"
 952
 953 source "arch/arm/mach-tegra/Kconfig"
 954
 955 source "arch/arm/mach-u300/Kconfig"
 956
 957 source "arch/arm/mach-ux500/Kconfig"
 958
 959 source "arch/arm/mach-versatile/Kconfig"
 960
 961 source "arch/arm/mach-vexpress/Kconfig"
 962 source "arch/arm/plat-versatile/Kconfig"
 963
 964 source "arch/arm/mach-vt8500/Kconfig"
 965
 966 source "arch/arm/mach-w90x900/Kconfig"
 967
 968 source "arch/arm/mach-zynq/Kconfig"
 969
 970 # Definitions to make life easier
 971 config ARCH_ACORN
 972         bool
 973
 974 config PLAT_IOP
 975         bool
 976         select GENERIC_CLOCKEVENTS
 977
 978 config PLAT_ORION
 979         bool
 980         select CLKSRC_MMIO
 981         select COMMON_CLK
 982         select GENERIC_IRQ_CHIP
 983         select IRQ_DOMAIN
 984
 985 config PLAT_ORION_LEGACY
 986         bool
 987         select PLAT_ORION
 988
 989 config PLAT_PXA
 990         bool
 991
 992 config PLAT_VERSATILE
 993         bool
 994
 995 config ARM_TIMER_SP804
 996         bool
 997         select CLKSRC_MMIO
 998         select CLKSRC_OF if OF
 999
1000 source "arch/arm/firmware/Kconfig"
1001
1002 source arch/arm/mm/Kconfig
1003
1004 config IWMMXT
1005         bool "Enable iWMMXt support"
1006         depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
1007         default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
1008         help
1009           Enable support for iWMMXt context switching at run time if
1010           running on a CPU that supports it.
1011
1012 config MULTI_IRQ_HANDLER
1013         bool
1014         help
1015           Allow each machine to specify it's own IRQ handler at run time.
1016
1017 if !MMU
1018 source "arch/arm/Kconfig-nommu"
1019 endif
1020
1021 config PJ4B_ERRATA_4742
1022         bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1023         depends on CPU_PJ4B && MACH_ARMADA_370
1024         default y
1025         help
1026           When coming out of either a Wait for Interrupt (WFI) or a Wait for
1027           Event (WFE) IDLE states, a specific timing sensitivity exists between
1028           the retiring WFI/WFE instructions and the newly issued subsequent
1029           instructions.  This sensitivity can result in a CPU hang scenario.
1030           Workaround:
1031           The software must insert either a Data Synchronization Barrier (DSB)
1032           or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1033           instruction
1034
1035 config ARM_ERRATA_326103
1036         bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1037         depends on CPU_V6
1038         help
1039           Executing a SWP instruction to read-only memory does not set bit 11
1040           of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1041           treat the access as a read, preventing a COW from occurring and
1042           causing the faulting task to livelock.
1043
1044 config ARM_ERRATA_411920
1045         bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1046         depends on CPU_V6 || CPU_V6K
1047         help
1048           Invalidation of the Instruction Cache operation can
1049           fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1050           It does not affect the MPCore. This option enables the ARM Ltd.
1051           recommended workaround.
1052
1053 config ARM_ERRATA_430973
1054         bool "ARM errata: Stale prediction on replaced interworking branch"
1055         depends on CPU_V7
1056         help
1057           This option enables the workaround for the 430973 Cortex-A8
1058           (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1059           interworking branch is replaced with another code sequence at the
1060           same virtual address, whether due to self-modifying code or virtual
1061           to physical address re-mapping, Cortex-A8 does not recover from the
1062           stale interworking branch prediction. This results in Cortex-A8
1063           executing the new code sequence in the incorrect ARM or Thumb state.
1064           The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1065           and also flushes the branch target cache at every context switch.
1066           Note that setting specific bits in the ACTLR register may not be
1067           available in non-secure mode.
1068
1069 config ARM_ERRATA_458693
1070         bool "ARM errata: Processor deadlock when a false hazard is created"
1071         depends on CPU_V7
1072         depends on !ARCH_MULTIPLATFORM
1073         help
1074           This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1075           erratum. For very specific sequences of memory operations, it is
1076           possible for a hazard condition intended for a cache line to instead
1077           be incorrectly associated with a different cache line. This false
1078           hazard might then cause a processor deadlock. The workaround enables
1079           the L1 caching of the NEON accesses and disables the PLD instruction
1080           in the ACTLR register. Note that setting specific bits in the ACTLR
1081           register may not be available in non-secure mode.
1082
1083 config ARM_ERRATA_460075
1084         bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1085         depends on CPU_V7
1086         depends on !ARCH_MULTIPLATFORM
1087         help
1088           This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1089           erratum. Any asynchronous access to the L2 cache may encounter a
1090           situation in which recent store transactions to the L2 cache are lost
1091           and overwritten with stale memory contents from external memory. The
1092           workaround disables the write-allocate mode for the L2 cache via the
1093           ACTLR register. Note that setting specific bits in the ACTLR register
1094           may not be available in non-secure mode.
1095
1096 config ARM_ERRATA_742230
1097         bool "ARM errata: DMB operation may be faulty"
1098         depends on CPU_V7 && SMP
1099         depends on !ARCH_MULTIPLATFORM
1100         help
1101           This option enables the workaround for the 742230 Cortex-A9
1102           (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1103           between two write operations may not ensure the correct visibility
1104           ordering of the two writes. This workaround sets a specific bit in
1105           the diagnostic register of the Cortex-A9 which causes the DMB
1106           instruction to behave as a DSB, ensuring the correct behaviour of
1107           the two writes.
1108
1109 config ARM_ERRATA_742231
1110         bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1111         depends on CPU_V7 && SMP
1112         depends on !ARCH_MULTIPLATFORM
1113         help
1114           This option enables the workaround for the 742231 Cortex-A9
1115           (r2p0..r2p2) erratum. Under certain conditions, specific to the
1116           Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1117           accessing some data located in the same cache line, may get corrupted
1118           data due to bad handling of the address hazard when the line gets
1119           replaced from one of the CPUs at the same time as another CPU is
1120           accessing it. This workaround sets specific bits in the diagnostic
1121           register of the Cortex-A9 which reduces the linefill issuing
1122           capabilities of the processor.
1123
1124 config ARM_ERRATA_643719
1125         bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1126         depends on CPU_V7 && SMP
1127         help
1128           This option enables the workaround for the 643719 Cortex-A9 (prior to
1129           r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1130           register returns zero when it should return one. The workaround
1131           corrects this value, ensuring cache maintenance operations which use
1132           it behave as intended and avoiding data corruption.
1133
1134 config ARM_ERRATA_720789
1135         bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1136         depends on CPU_V7
1137         help
1138           This option enables the workaround for the 720789 Cortex-A9 (prior to
1139           r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1140           broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1141           As a consequence of this erratum, some TLB entries which should be
1142           invalidated are not, resulting in an incoherency in the system page
1143           tables. The workaround changes the TLB flushing routines to invalidate
1144           entries regardless of the ASID.
1145
1146 config ARM_ERRATA_743622
1147         bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1148         depends on CPU_V7
1149         depends on !ARCH_MULTIPLATFORM
1150         help
1151           This option enables the workaround for the 743622 Cortex-A9
1152           (r2p*) erratum. Under very rare conditions, a faulty
1153           optimisation in the Cortex-A9 Store Buffer may lead to data
1154           corruption. This workaround sets a specific bit in the diagnostic
1155           register of the Cortex-A9 which disables the Store Buffer
1156           optimisation, preventing the defect from occurring. This has no
1157           visible impact on the overall performance or power consumption of the
1158           processor.
1159
1160 config ARM_ERRATA_751472
1161         bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1162         depends on CPU_V7
1163         depends on !ARCH_MULTIPLATFORM
1164         help
1165           This option enables the workaround for the 751472 Cortex-A9 (prior
1166           to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1167           completion of a following broadcasted operation if the second
1168           operation is received by a CPU before the ICIALLUIS has completed,
1169           potentially leading to corrupted entries in the cache or TLB.
1170
1171 config ARM_ERRATA_754322
1172         bool "ARM errata: possible faulty MMU translations following an ASID switch"
1173         depends on CPU_V7
1174         help
1175           This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1176           r3p*) erratum. A speculative memory access may cause a page table walk
1177           which starts prior to an ASID switch but completes afterwards. This
1178           can populate the micro-TLB with a stale entry which may be hit with
1179           the new ASID. This workaround places two dsb instructions in the mm
1180           switching code so that no page table walks can cross the ASID switch.
1181
1182 config ARM_ERRATA_754327
1183         bool "ARM errata: no automatic Store Buffer drain"
1184         depends on CPU_V7 && SMP
1185         help
1186           This option enables the workaround for the 754327 Cortex-A9 (prior to
1187           r2p0) erratum. The Store Buffer does not have any automatic draining
1188           mechanism and therefore a livelock may occur if an external agent
1189           continuously polls a memory location waiting to observe an update.
1190           This workaround defines cpu_relax() as smp_mb(), preventing correctly
1191           written polling loops from denying visibility of updates to memory.
1192
1193 config ARM_ERRATA_364296
1194         bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1195         depends on CPU_V6
1196         help
1197           This options enables the workaround for the 364296 ARM1136
1198           r0p2 erratum (possible cache data corruption with
1199           hit-under-miss enabled). It sets the undocumented bit 31 in
1200           the auxiliary control register and the FI bit in the control
1201           register, thus disabling hit-under-miss without putting the
1202           processor into full low interrupt latency mode. ARM11MPCore
1203           is not affected.
1204
1205 config ARM_ERRATA_764369
1206         bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1207         depends on CPU_V7 && SMP
1208         help
1209           This option enables the workaround for erratum 764369
1210           affecting Cortex-A9 MPCore with two or more processors (all
1211           current revisions). Under certain timing circumstances, a data
1212           cache line maintenance operation by MVA targeting an Inner
1213           Shareable memory region may fail to proceed up to either the
1214           Point of Coherency or to the Point of Unification of the
1215           system. This workaround adds a DSB instruction before the
1216           relevant cache maintenance functions and sets a specific bit
1217           in the diagnostic control register of the SCU.
1218
1219 config ARM_ERRATA_775420
1220        bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1221        depends on CPU_V7
1222        help
1223          This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1224          r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1225          operation aborts with MMU exception, it might cause the processor
1226          to deadlock. This workaround puts DSB before executing ISB if
1227          an abort may occur on cache maintenance.
1228
1229 config ARM_ERRATA_798181
1230         bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1231         depends on CPU_V7 && SMP
1232         help
1233           On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1234           adequately shooting down all use of the old entries. This
1235           option enables the Linux kernel workaround for this erratum
1236           which sends an IPI to the CPUs that are running the same ASID
1237           as the one being invalidated.
1238
1239 config ARM_ERRATA_773022
1240         bool "ARM errata: incorrect instructions may be executed from loop buffer"
1241         depends on CPU_V7
1242         help
1243           This option enables the workaround for the 773022 Cortex-A15
1244           (up to r0p4) erratum. In certain rare sequences of code, the
1245           loop buffer may deliver incorrect instructions. This
1246           workaround disables the loop buffer to avoid the erratum.
1247
1248 endmenu
1249
1250 source "arch/arm/common/Kconfig"
1251
1252 menu "Bus support"
1253
1254 config ISA
1255         bool
1256         help
1257           Find out whether you have ISA slots on your motherboard.  ISA is the
1258           name of a bus system, i.e. the way the CPU talks to the other stuff
1259           inside your box.  Other bus systems are PCI, EISA, MicroChannel
1260           (MCA) or VESA.  ISA is an older system, now being displaced by PCI;
1261           newer boards don't support it.  If you have ISA, say Y, otherwise N.
1262
1263 # Select ISA DMA controller support
1264 config ISA_DMA
1265         bool
1266         select ISA_DMA_API
1267
1268 # Select ISA DMA interface
1269 config ISA_DMA_API
1270         bool
1271
1272 config PCI
1273         bool "PCI support" if MIGHT_HAVE_PCI
1274         help
1275           Find out whether you have a PCI motherboard. PCI is the name of a
1276           bus system, i.e. the way the CPU talks to the other stuff inside
1277           your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1278           VESA. If you have PCI, say Y, otherwise N.
1279
1280 config PCI_DOMAINS
1281         bool
1282         depends on PCI
1283
1284 config PCI_DOMAINS_GENERIC
1285         def_bool PCI_DOMAINS
1286
1287 config PCI_NANOENGINE
1288         bool "BSE nanoEngine PCI support"
1289         depends on SA1100_NANOENGINE
1290         help
1291           Enable PCI on the BSE nanoEngine board.
1292
1293 config PCI_SYSCALL
1294         def_bool PCI
1295
1296 config PCI_HOST_ITE8152
1297         bool
1298         depends on PCI && MACH_ARMCORE
1299         default y
1300         select DMABOUNCE
1301
1302 source "drivers/pci/Kconfig"
1303 source "drivers/pci/pcie/Kconfig"
1304
1305 source "drivers/pcmcia/Kconfig"
1306
1307 endmenu
1308
1309 menu "Kernel Features"
1310
1311 config HAVE_SMP
1312         bool
1313         help
1314           This option should be selected by machines which have an SMP-
1315           capable CPU.
1316
1317           The only effect of this option is to make the SMP-related
1318           options available to the user for configuration.
1319
1320 config SMP
1321         bool "Symmetric Multi-Processing"
1322         depends on CPU_V6K || CPU_V7
1323         depends on GENERIC_CLOCKEVENTS
1324         depends on HAVE_SMP
1325         depends on MMU || ARM_MPU
1326         help
1327           This enables support for systems with more than one CPU. If you have
1328           a system with only one CPU, say N. If you have a system with more
1329           than one CPU, say Y.
1330
1331           If you say N here, the kernel will run on uni- and multiprocessor
1332           machines, but will use only one CPU of a multiprocessor machine. If
1333           you say Y here, the kernel will run on many, but not all,
1334           uniprocessor machines. On a uniprocessor machine, the kernel
1335           will run faster if you say N here.
1336
1337           See also <file:Documentation/x86/i386/IO-APIC.txt>,
1338           <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1339           <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1340
1341           If you don't know what to do here, say N.
1342
1343 config SMP_ON_UP
1344         bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1345         depends on SMP && !XIP_KERNEL && MMU
1346         default y
1347         help
1348           SMP kernels contain instructions which fail on non-SMP processors.
1349           Enabling this option allows the kernel to modify itself to make
1350           these instructions safe.  Disabling it allows about 1K of space
1351           savings.
1352
1353           If you don't know what to do here, say Y.
1354
1355 config ARM_CPU_TOPOLOGY
1356         bool "Support cpu topology definition"
1357         depends on SMP && CPU_V7
1358         default y
1359         help
1360           Support ARM cpu topology definition. The MPIDR register defines
1361           affinity between processors which is then used to describe the cpu
1362           topology of an ARM System.
1363
1364 config SCHED_MC
1365         bool "Multi-core scheduler support"
1366         depends on ARM_CPU_TOPOLOGY
1367         help
1368           Multi-core scheduler support improves the CPU scheduler's decision
1369           making when dealing with multi-core CPU chips at a cost of slightly
1370           increased overhead in some places. If unsure say N here.
1371
1372 config SCHED_SMT
1373         bool "SMT scheduler support"
1374         depends on ARM_CPU_TOPOLOGY
1375         help
1376           Improves the CPU scheduler's decision making when dealing with
1377           MultiThreading at a cost of slightly increased overhead in some
1378           places. If unsure say N here.
1379
1380 config HAVE_ARM_SCU
1381         bool
1382         help
1383           This option enables support for the ARM system coherency unit
1384
1385 config HAVE_ARM_ARCH_TIMER
1386         bool "Architected timer support"
1387         depends on CPU_V7
1388         select ARM_ARCH_TIMER
1389         select GENERIC_CLOCKEVENTS
1390         help
1391           This option enables support for the ARM architected timer
1392
1393 config HAVE_ARM_TWD
1394         bool
1395         depends on SMP
1396         select CLKSRC_OF if OF
1397         help
1398           This options enables support for the ARM timer and watchdog unit
1399
1400 config MCPM
1401         bool "Multi-Cluster Power Management"
1402         depends on CPU_V7 && SMP
1403         help
1404           This option provides the common power management infrastructure
1405           for (multi-)cluster based systems, such as big.LITTLE based
1406           systems.
1407
1408 config MCPM_QUAD_CLUSTER
1409         bool
1410         depends on MCPM
1411         help
1412           To avoid wasting resources unnecessarily, MCPM only supports up
1413           to 2 clusters by default.
1414           Platforms with 3 or 4 clusters that use MCPM must select this
1415           option to allow the additional clusters to be managed.
1416
1417 config BIG_LITTLE
1418         bool "big.LITTLE support (Experimental)"
1419         depends on CPU_V7 && SMP
1420         select MCPM
1421         help
1422           This option enables support selections for the big.LITTLE
1423           system architecture.
1424
1425 config BL_SWITCHER
1426         bool "big.LITTLE switcher support"
1427         depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1428         select ARM_CPU_SUSPEND
1429         select CPU_PM
1430         help
1431           The big.LITTLE "switcher" provides the core functionality to
1432           transparently handle transition between a cluster of A15's
1433           and a cluster of A7's in a big.LITTLE system.
1434
1435 config BL_SWITCHER_DUMMY_IF
1436         tristate "Simple big.LITTLE switcher user interface"
1437         depends on BL_SWITCHER && DEBUG_KERNEL
1438         help
1439           This is a simple and dummy char dev interface to control
1440           the big.LITTLE switcher core code.  It is meant for
1441           debugging purposes only.
1442
1443 choice
1444         prompt "Memory split"
1445         depends on MMU
1446         default VMSPLIT_3G
1447         help
1448           Select the desired split between kernel and user memory.
1449
1450           If you are not absolutely sure what you are doing, leave this
1451           option alone!
1452
1453         config VMSPLIT_3G
1454                 bool "3G/1G user/kernel split"
1455         config VMSPLIT_2G
1456                 bool "2G/2G user/kernel split"
1457         config VMSPLIT_1G
1458                 bool "1G/3G user/kernel split"
1459 endchoice
1460
1461 config PAGE_OFFSET
1462         hex
1463         default PHYS_OFFSET if !MMU
1464         default 0x40000000 if VMSPLIT_1G
1465         default 0x80000000 if VMSPLIT_2G
1466         default 0xC0000000
1467
1468 config NR_CPUS
1469         int "Maximum number of CPUs (2-32)"
1470         range 2 32
1471         depends on SMP
1472         default "4"
1473
1474 config HOTPLUG_CPU
1475         bool "Support for hot-pluggable CPUs"
1476         depends on SMP
1477         help
1478           Say Y here to experiment with turning CPUs off and on.  CPUs
1479           can be controlled through /sys/devices/system/cpu.
1480
1481 config ARM_PSCI
1482         bool "Support for the ARM Power State Coordination Interface (PSCI)"
1483         depends on CPU_V7
1484         help
1485           Say Y here if you want Linux to communicate with system firmware
1486           implementing the PSCI specification for CPU-centric power
1487           management operations described in ARM document number ARM DEN
1488           0022A ("Power State Coordination Interface System Software on
1489           ARM processors").
1490
1491 # The GPIO number here must be sorted by descending number. In case of
1492 # a multiplatform kernel, we just want the highest value required by the
1493 # selected platforms.
1494 config ARCH_NR_GPIO
1495         int
1496         default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1497         default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1498                 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1499         default 416 if ARCH_SUNXI
1500         default 392 if ARCH_U8500
1501         default 352 if ARCH_VT8500
1502         default 288 if ARCH_ROCKCHIP
1503         default 264 if MACH_H4700
1504         default 0
1505         help
1506           Maximum number of GPIOs in the system.
1507
1508           If unsure, leave the default value.
1509
1510 source kernel/Kconfig.preempt
1511
1512 config HZ_FIXED
1513         int
1514         default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1515                 ARCH_S5PV210 || ARCH_EXYNOS4
1516         default AT91_TIMER_HZ if ARCH_AT91
1517         default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
1518         default 0
1519
1520 choice
1521         depends on HZ_FIXED = 0
1522         prompt "Timer frequency"
1523
1524 config HZ_100
1525         bool "100 Hz"
1526
1527 config HZ_200
1528         bool "200 Hz"
1529
1530 config HZ_250
1531         bool "250 Hz"
1532
1533 config HZ_300
1534         bool "300 Hz"
1535
1536 config HZ_500
1537         bool "500 Hz"
1538
1539 config HZ_1000
1540         bool "1000 Hz"
1541
1542 endchoice
1543
1544 config HZ
1545         int
1546         default HZ_FIXED if HZ_FIXED != 0
1547         default 100 if HZ_100
1548         default 200 if HZ_200
1549         default 250 if HZ_250
1550         default 300 if HZ_300
1551         default 500 if HZ_500
1552         default 1000
1553
1554 config SCHED_HRTICK
1555         def_bool HIGH_RES_TIMERS
1556
1557 config THUMB2_KERNEL
1558         bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1559         depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1560         default y if CPU_THUMBONLY
1561         select AEABI
1562         select ARM_ASM_UNIFIED
1563         select ARM_UNWIND
1564         help
1565           By enabling this option, the kernel will be compiled in
1566           Thumb-2 mode. A compiler/assembler that understand the unified
1567           ARM-Thumb syntax is needed.
1568
1569           If unsure, say N.
1570
1571 config THUMB2_AVOID_R_ARM_THM_JUMP11
1572         bool "Work around buggy Thumb-2 short branch relocations in gas"
1573         depends on THUMB2_KERNEL && MODULES
1574         default y
1575         help
1576           Various binutils versions can resolve Thumb-2 branches to
1577           locally-defined, preemptible global symbols as short-range "b.n"
1578           branch instructions.
1579
1580           This is a problem, because there's no guarantee the final
1581           destination of the symbol, or any candidate locations for a
1582           trampoline, are within range of the branch.  For this reason, the
1583           kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1584           relocation in modules at all, and it makes little sense to add
1585           support.
1586
1587           The symptom is that the kernel fails with an "unsupported
1588           relocation" error when loading some modules.
1589
1590           Until fixed tools are available, passing
1591           -fno-optimize-sibling-calls to gcc should prevent gcc generating
1592           code which hits this problem, at the cost of a bit of extra runtime
1593           stack usage in some cases.
1594
1595           The problem is described in more detail at:
1596               https://bugs.launchpad.net/binutils-linaro/+bug/725126
1597
1598           Only Thumb-2 kernels are affected.
1599
1600           Unless you are sure your tools don't have this problem, say Y.
1601
1602 config ARM_ASM_UNIFIED
1603         bool
1604
1605 config AEABI
1606         bool "Use the ARM EABI to compile the kernel"
1607         help
1608           This option allows for the kernel to be compiled using the latest
1609           ARM ABI (aka EABI).  This is only useful if you are using a user
1610           space environment that is also compiled with EABI.
1611
1612           Since there are major incompatibilities between the legacy ABI and
1613           EABI, especially with regard to structure member alignment, this
1614           option also changes the kernel syscall calling convention to
1615           disambiguate both ABIs and allow for backward compatibility support
1616           (selected with CONFIG_OABI_COMPAT).
1617
1618           To use this you need GCC version 4.0.0 or later.
1619
1620 config OABI_COMPAT
1621         bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1622         depends on AEABI && !THUMB2_KERNEL
1623         help
1624           This option preserves the old syscall interface along with the
1625           new (ARM EABI) one. It also provides a compatibility layer to
1626           intercept syscalls that have structure arguments which layout
1627           in memory differs between the legacy ABI and the new ARM EABI
1628           (only for non "thumb" binaries). This option adds a tiny
1629           overhead to all syscalls and produces a slightly larger kernel.
1630
1631           The seccomp filter system will not be available when this is
1632           selected, since there is no way yet to sensibly distinguish
1633           between calling conventions during filtering.
1634
1635           If you know you'll be using only pure EABI user space then you
1636           can say N here. If this option is not selected and you attempt
1637           to execute a legacy ABI binary then the result will be
1638           UNPREDICTABLE (in fact it can be predicted that it won't work
1639           at all). If in doubt say N.
1640
1641 config ARCH_HAS_HOLES_MEMORYMODEL
1642         bool
1643
1644 config ARCH_SPARSEMEM_ENABLE
1645         bool
1646
1647 config ARCH_SPARSEMEM_DEFAULT
1648         def_bool ARCH_SPARSEMEM_ENABLE
1649
1650 config ARCH_SELECT_MEMORY_MODEL
1651         def_bool ARCH_SPARSEMEM_ENABLE
1652
1653 config HAVE_ARCH_PFN_VALID
1654         def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1655
1656 config HAVE_GENERIC_RCU_GUP
1657         def_bool y
1658         depends on ARM_LPAE
1659
1660 config HIGHMEM
1661         bool "High Memory Support"
1662         depends on MMU
1663         help
1664           The address space of ARM processors is only 4 Gigabytes large
1665           and it has to accommodate user address space, kernel address
1666           space as well as some memory mapped IO. That means that, if you
1667           have a large amount of physical memory and/or IO, not all of the
1668           memory can be "permanently mapped" by the kernel. The physical
1669           memory that is not permanently mapped is called "high memory".
1670
1671           Depending on the selected kernel/user memory split, minimum
1672           vmalloc space and actual amount of RAM, you may not need this
1673           option which should result in a slightly faster kernel.
1674
1675           If unsure, say n.
1676
1677 config HIGHPTE
1678         bool "Allocate 2nd-level pagetables from highmem"
1679         depends on HIGHMEM
1680
1681 config HW_PERF_EVENTS
1682         bool "Enable hardware performance counter support for perf events"
1683         depends on PERF_EVENTS
1684         default y
1685         help
1686           Enable hardware performance counter support for perf events. If
1687           disabled, perf events will use software events only.
1688
1689 config SYS_SUPPORTS_HUGETLBFS
1690        def_bool y
1691        depends on ARM_LPAE
1692
1693 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1694        def_bool y
1695        depends on ARM_LPAE
1696
1697 config ARCH_WANT_GENERAL_HUGETLB
1698         def_bool y
1699
1700 source "mm/Kconfig"
1701
1702 config FORCE_MAX_ZONEORDER
1703         int "Maximum zone order" if ARCH_SHMOBILE_LEGACY
1704         range 11 64 if ARCH_SHMOBILE_LEGACY
1705         default "12" if SOC_AM33XX
1706         default "9" if SA1111 || ARCH_EFM32
1707         default "11"
1708         help
1709           The kernel memory allocator divides physically contiguous memory
1710           blocks into "zones", where each zone is a power of two number of
1711           pages.  This option selects the largest power of two that the kernel
1712           keeps in the memory allocator.  If you need to allocate very large
1713           blocks of physically contiguous memory, then you may need to
1714           increase this value.
1715
1716           This config option is actually maximum order plus one. For example,
1717           a value of 11 means that the largest free memory block is 2^10 pages.
1718
1719 config ALIGNMENT_TRAP
1720         bool
1721         depends on CPU_CP15_MMU
1722         default y if !ARCH_EBSA110
1723         select HAVE_PROC_CPU if PROC_FS
1724         help
1725           ARM processors cannot fetch/store information which is not
1726           naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1727           address divisible by 4. On 32-bit ARM processors, these non-aligned
1728           fetch/store instructions will be emulated in software if you say
1729           here, which has a severe performance impact. This is necessary for
1730           correct operation of some network protocols. With an IP-only
1731           configuration it is safe to say N, otherwise say Y.
1732
1733 config UACCESS_WITH_MEMCPY
1734         bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1735         depends on MMU
1736         default y if CPU_FEROCEON
1737         help
1738           Implement faster copy_to_user and clear_user methods for CPU
1739           cores where a 8-word STM instruction give significantly higher
1740           memory write throughput than a sequence of individual 32bit stores.
1741
1742           A possible side effect is a slight increase in scheduling latency
1743           between threads sharing the same address space if they invoke
1744           such copy operations with large buffers.
1745
1746           However, if the CPU data cache is using a write-allocate mode,
1747           this option is unlikely to provide any performance gain.
1748
1749 config SECCOMP
1750         bool
1751         prompt "Enable seccomp to safely compute untrusted bytecode"
1752         ---help---
1753           This kernel feature is useful for number crunching applications
1754           that may need to compute untrusted bytecode during their
1755           execution. By using pipes or other transports made available to
1756           the process as file descriptors supporting the read/write
1757           syscalls, it's possible to isolate those applications in
1758           their own address space using seccomp. Once seccomp is
1759           enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1760           and the task is only allowed to execute a few safe syscalls
1761           defined by each seccomp mode.
1762
1763 config SWIOTLB
1764         def_bool y
1765
1766 config IOMMU_HELPER
1767         def_bool SWIOTLB
1768
1769 config XEN_DOM0
1770         def_bool y
1771         depends on XEN
1772
1773 config XEN
1774         bool "Xen guest support on ARM"
1775         depends on ARM && AEABI && OF
1776         depends on CPU_V7 && !CPU_V6
1777         depends on !GENERIC_ATOMIC64
1778         depends on MMU
1779         select ARCH_DMA_ADDR_T_64BIT
1780         select ARM_PSCI
1781         select SWIOTLB_XEN
1782         help
1783           Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1784
1785 endmenu
1786
1787 menu "Boot options"
1788
1789 config USE_OF
1790         bool "Flattened Device Tree support"
1791         select IRQ_DOMAIN
1792         select OF
1793         select OF_EARLY_FLATTREE
1794         select OF_RESERVED_MEM
1795         help
1796           Include support for flattened device tree machine descriptions.
1797
1798 config ATAGS
1799         bool "Support for the traditional ATAGS boot data passing" if USE_OF
1800         default y
1801         help
1802           This is the traditional way of passing data to the kernel at boot
1803           time. If you are solely relying on the flattened device tree (or
1804           the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1805           to remove ATAGS support from your kernel binary.  If unsure,
1806           leave this to y.
1807
1808 config DEPRECATED_PARAM_STRUCT
1809         bool "Provide old way to pass kernel parameters"
1810         depends on ATAGS
1811         help
1812           This was deprecated in 2001 and announced to live on for 5 years.
1813           Some old boot loaders still use this way.
1814
1815 # Compressed boot loader in ROM.  Yes, we really want to ask about
1816 # TEXT and BSS so we preserve their values in the config files.
1817 config ZBOOT_ROM_TEXT
1818         hex "Compressed ROM boot loader base address"
1819         default "0"
1820         help
1821           The physical address at which the ROM-able zImage is to be
1822           placed in the target.  Platforms which normally make use of
1823           ROM-able zImage formats normally set this to a suitable
1824           value in their defconfig file.
1825
1826           If ZBOOT_ROM is not enabled, this has no effect.
1827
1828 config ZBOOT_ROM_BSS
1829         hex "Compressed ROM boot loader BSS address"
1830         default "0"
1831         help
1832           The base address of an area of read/write memory in the target
1833           for the ROM-able zImage which must be available while the
1834           decompressor is running. It must be large enough to hold the
1835           entire decompressed kernel plus an additional 128 KiB.
1836           Platforms which normally make use of ROM-able zImage formats
1837           normally set this to a suitable value in their defconfig file.
1838
1839           If ZBOOT_ROM is not enabled, this has no effect.
1840
1841 config ZBOOT_ROM
1842         bool "Compressed boot loader in ROM/flash"
1843         depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1844         depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1845         help
1846           Say Y here if you intend to execute your compressed kernel image
1847           (zImage) directly from ROM or flash.  If unsure, say N.
1848
1849 choice
1850         prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1851         depends on ZBOOT_ROM && ARCH_SH7372
1852         default ZBOOT_ROM_NONE
1853         help
1854           Include experimental SD/MMC loading code in the ROM-able zImage.
1855           With this enabled it is possible to write the ROM-able zImage
1856           kernel image to an MMC or SD card and boot the kernel straight
1857           from the reset vector. At reset the processor Mask ROM will load
1858           the first part of the ROM-able zImage which in turn loads the
1859           rest the kernel image to RAM.
1860
1861 config ZBOOT_ROM_NONE
1862         bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1863         help
1864           Do not load image from SD or MMC
1865
1866 config ZBOOT_ROM_MMCIF
1867         bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1868         help
1869           Load image from MMCIF hardware block.
1870
1871 config ZBOOT_ROM_SH_MOBILE_SDHI
1872         bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1873         help
1874           Load image from SDHI hardware block
1875
1876 endchoice
1877
1878 config ARM_APPENDED_DTB
1879         bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1880         depends on OF
1881         help
1882           With this option, the boot code will look for a device tree binary
1883           (DTB) appended to zImage
1884           (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1885
1886           This is meant as a backward compatibility convenience for those
1887           systems with a bootloader that can't be upgraded to accommodate
1888           the documented boot protocol using a device tree.
1889
1890           Beware that there is very little in terms of protection against
1891           this option being confused by leftover garbage in memory that might
1892           look like a DTB header after a reboot if no actual DTB is appended
1893           to zImage.  Do not leave this option active in a production kernel
1894           if you don't intend to always append a DTB.  Proper passing of the
1895           location into r2 of a bootloader provided DTB is always preferable
1896           to this option.
1897
1898 config ARM_ATAG_DTB_COMPAT
1899         bool "Supplement the appended DTB with traditional ATAG information"
1900         depends on ARM_APPENDED_DTB
1901         help
1902           Some old bootloaders can't be updated to a DTB capable one, yet
1903           they provide ATAGs with memory configuration, the ramdisk address,
1904           the kernel cmdline string, etc.  Such information is dynamically
1905           provided by the bootloader and can't always be stored in a static
1906           DTB.  To allow a device tree enabled kernel to be used with such
1907           bootloaders, this option allows zImage to extract the information
1908           from the ATAG list and store it at run time into the appended DTB.
1909
1910 choice
1911         prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1912         default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1913
1914 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1915         bool "Use bootloader kernel arguments if available"
1916         help
1917           Uses the command-line options passed by the boot loader instead of
1918           the device tree bootargs property. If the boot loader doesn't provide
1919           any, the device tree bootargs property will be used.
1920
1921 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1922         bool "Extend with bootloader kernel arguments"
1923         help
1924           The command-line arguments provided by the boot loader will be
1925           appended to the the device tree bootargs property.
1926
1927 endchoice
1928
1929 config CMDLINE
1930         string "Default kernel command string"
1931         default ""
1932         help
1933           On some architectures (EBSA110 and CATS), there is currently no way
1934           for the boot loader to pass arguments to the kernel. For these
1935           architectures, you should supply some command-line options at build
1936           time by entering them here. As a minimum, you should specify the
1937           memory size and the root device (e.g., mem=64M root=/dev/nfs).
1938
1939 choice
1940         prompt "Kernel command line type" if CMDLINE != ""
1941         default CMDLINE_FROM_BOOTLOADER
1942         depends on ATAGS
1943
1944 config CMDLINE_FROM_BOOTLOADER
1945         bool "Use bootloader kernel arguments if available"
1946         help
1947           Uses the command-line options passed by the boot loader. If
1948           the boot loader doesn't provide any, the default kernel command
1949           string provided in CMDLINE will be used.
1950
1951 config CMDLINE_EXTEND
1952         bool "Extend bootloader kernel arguments"
1953         help
1954           The command-line arguments provided by the boot loader will be
1955           appended to the default kernel command string.
1956
1957 config CMDLINE_FORCE
1958         bool "Always use the default kernel command string"
1959         help
1960           Always use the default kernel command string, even if the boot
1961           loader passes other arguments to the kernel.
1962           This is useful if you cannot or don't want to change the
1963           command-line options your boot loader passes to the kernel.
1964 endchoice
1965
1966 config XIP_KERNEL
1967         bool "Kernel Execute-In-Place from ROM"
1968         depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1969         help
1970           Execute-In-Place allows the kernel to run from non-volatile storage
1971           directly addressable by the CPU, such as NOR flash. This saves RAM
1972           space since the text section of the kernel is not loaded from flash
1973           to RAM.  Read-write sections, such as the data section and stack,
1974           are still copied to RAM.  The XIP kernel is not compressed since
1975           it has to run directly from flash, so it will take more space to
1976           store it.  The flash address used to link the kernel object files,
1977           and for storing it, is configuration dependent. Therefore, if you
1978           say Y here, you must know the proper physical address where to
1979           store the kernel image depending on your own flash memory usage.
1980
1981           Also note that the make target becomes "make xipImage" rather than
1982           "make zImage" or "make Image".  The final kernel binary to put in
1983           ROM memory will be arch/arm/boot/xipImage.
1984
1985           If unsure, say N.
1986
1987 config XIP_PHYS_ADDR
1988         hex "XIP Kernel Physical Location"
1989         depends on XIP_KERNEL
1990         default "0x00080000"
1991         help
1992           This is the physical address in your flash memory the kernel will
1993           be linked for and stored to.  This address is dependent on your
1994           own flash usage.
1995
1996 config KEXEC
1997         bool "Kexec system call (EXPERIMENTAL)"
1998         depends on (!SMP || PM_SLEEP_SMP)
1999         help
2000           kexec is a system call that implements the ability to shutdown your
2001           current kernel, and to start another kernel.  It is like a reboot
2002           but it is independent of the system firmware.   And like a reboot
2003           you can start any kernel with it, not just Linux.
2004
2005           It is an ongoing process to be certain the hardware in a machine
2006           is properly shutdown, so do not be surprised if this code does not
2007           initially work for you.
2008
2009 config ATAGS_PROC
2010         bool "Export atags in procfs"
2011         depends on ATAGS && KEXEC
2012         default y
2013         help
2014           Should the atags used to boot the kernel be exported in an "atags"
2015           file in procfs. Useful with kexec.
2016
2017 config CRASH_DUMP
2018         bool "Build kdump crash kernel (EXPERIMENTAL)"
2019         help
2020           Generate crash dump after being started by kexec. This should
2021           be normally only set in special crash dump kernels which are
2022           loaded in the main kernel with kexec-tools into a specially
2023           reserved region and then later executed after a crash by
2024           kdump/kexec. The crash dump kernel must be compiled to a
2025           memory address not used by the main kernel
2026
2027           For more details see Documentation/kdump/kdump.txt
2028
2029 config AUTO_ZRELADDR
2030         bool "Auto calculation of the decompressed kernel image address"
2031         help
2032           ZRELADDR is the physical address where the decompressed kernel
2033           image will be placed. If AUTO_ZRELADDR is selected, the address
2034           will be determined at run-time by masking the current IP with
2035           0xf8000000. This assumes the zImage being placed in the first 128MB
2036           from start of memory.
2037
2038 endmenu
2039
2040 menu "CPU Power Management"
2041
2042 source "drivers/cpufreq/Kconfig"
2043
2044 source "drivers/cpuidle/Kconfig"
2045
2046 endmenu
2047
2048 menu "Floating point emulation"
2049
2050 comment "At least one emulation must be selected"
2051
2052 config FPE_NWFPE
2053         bool "NWFPE math emulation"
2054         depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2055         ---help---
2056           Say Y to include the NWFPE floating point emulator in the kernel.
2057           This is necessary to run most binaries. Linux does not currently
2058           support floating point hardware so you need to say Y here even if
2059           your machine has an FPA or floating point co-processor podule.
2060
2061           You may say N here if you are going to load the Acorn FPEmulator
2062           early in the bootup.
2063
2064 config FPE_NWFPE_XP
2065         bool "Support extended precision"
2066         depends on FPE_NWFPE
2067         help
2068           Say Y to include 80-bit support in the kernel floating-point
2069           emulator.  Otherwise, only 32 and 64-bit support is compiled in.
2070           Note that gcc does not generate 80-bit operations by default,
2071           so in most cases this option only enlarges the size of the
2072           floating point emulator without any good reason.
2073
2074           You almost surely want to say N here.
2075
2076 config FPE_FASTFPE
2077         bool "FastFPE math emulation (EXPERIMENTAL)"
2078         depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2079         ---help---
2080           Say Y here to include the FAST floating point emulator in the kernel.
2081           This is an experimental much faster emulator which now also has full
2082           precision for the mantissa.  It does not support any exceptions.
2083           It is very simple, and approximately 3-6 times faster than NWFPE.
2084
2085           It should be sufficient for most programs.  It may be not suitable
2086           for scientific calculations, but you have to check this for yourself.
2087           If you do not feel you need a faster FP emulation you should better
2088           choose NWFPE.
2089
2090 config VFP
2091         bool "VFP-format floating point maths"
2092         depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2093         help
2094           Say Y to include VFP support code in the kernel. This is needed
2095           if your hardware includes a VFP unit.
2096
2097           Please see <file:Documentation/arm/VFP/release-notes.txt> for
2098           release notes and additional status information.
2099
2100           Say N if your target does not have VFP hardware.
2101
2102 config VFPv3
2103         bool
2104         depends on VFP
2105         default y if CPU_V7
2106
2107 config NEON
2108         bool "Advanced SIMD (NEON) Extension support"
2109         depends on VFPv3 && CPU_V7
2110         help
2111           Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2112           Extension.
2113
2114 config KERNEL_MODE_NEON
2115         bool "Support for NEON in kernel mode"
2116         depends on NEON && AEABI
2117         help
2118           Say Y to include support for NEON in kernel mode.
2119
2120 endmenu
2121
2122 menu "Userspace binary formats"
2123
2124 source "fs/Kconfig.binfmt"
2125
2126 config ARTHUR
2127         tristate "RISC OS personality"
2128         depends on !AEABI
2129         help
2130           Say Y here to include the kernel code necessary if you want to run
2131           Acorn RISC OS/Arthur binaries under Linux. This code is still very
2132           experimental; if this sounds frightening, say N and sleep in peace.
2133           You can also say M here to compile this support as a module (which
2134           will be called arthur).
2135
2136 endmenu
2137
2138 menu "Power management options"
2139
2140 source "kernel/power/Kconfig"
2141
2142 config ARCH_SUSPEND_POSSIBLE
2143         depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2144                 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2145         def_bool y
2146
2147 config ARM_CPU_SUSPEND
2148         def_bool PM_SLEEP
2149
2150 config ARCH_HIBERNATION_POSSIBLE
2151         bool
2152         depends on MMU
2153         default y if ARCH_SUSPEND_POSSIBLE
2154
2155 endmenu
2156
2157 source "net/Kconfig"
2158
2159 source "drivers/Kconfig"
2160
2161 source "fs/Kconfig"
2162
2163 source "arch/arm/Kconfig.debug"
2164
2165 source "security/Kconfig"
2166
2167 source "crypto/Kconfig"
2168
2169 source "lib/Kconfig"
2170
2171 source "arch/arm/kvm/Kconfig"