4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_MIGHT_HAVE_PC_PARPORT
9 select ARCH_SUPPORTS_ATOMIC_RMW
10 select ARCH_USE_BUILTIN_BSWAP
11 select ARCH_USE_CMPXCHG_LOCKREF
12 select ARCH_WANT_IPC_PARSE_VERSION
13 select BUILDTIME_EXTABLE_SORT if MMU
14 select CLONE_BACKWARDS
15 select CPU_PM if (SUSPEND || CPU_IDLE)
16 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
17 select GENERIC_ALLOCATOR
18 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
19 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
20 select GENERIC_IDLE_POLL_SETUP
21 select GENERIC_IRQ_PROBE
22 select GENERIC_IRQ_SHOW
23 select GENERIC_PCI_IOMAP
24 select GENERIC_SCHED_CLOCK
25 select GENERIC_SMP_IDLE_THREAD
26 select GENERIC_STRNCPY_FROM_USER
27 select GENERIC_STRNLEN_USER
28 select HANDLE_DOMAIN_IRQ
29 select HARDIRQS_SW_RESEND
30 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
31 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
33 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
34 select HAVE_ARCH_TRACEHOOK
36 select HAVE_CC_STACKPROTECTOR
37 select HAVE_CONTEXT_TRACKING
38 select HAVE_C_RECORDMCOUNT
39 select HAVE_DEBUG_KMEMLEAK
40 select HAVE_DMA_API_DEBUG
42 select HAVE_DMA_CONTIGUOUS if MMU
43 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
44 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
45 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
46 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
47 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
48 select HAVE_GENERIC_DMA_COHERENT
49 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
50 select HAVE_IDE if PCI || ISA || PCMCIA
51 select HAVE_IRQ_TIME_ACCOUNTING
52 select HAVE_KERNEL_GZIP
53 select HAVE_KERNEL_LZ4
54 select HAVE_KERNEL_LZMA
55 select HAVE_KERNEL_LZO
57 select HAVE_KPROBES if !XIP_KERNEL
58 select HAVE_KRETPROBES if (HAVE_KPROBES)
60 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
61 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
62 select HAVE_PERF_EVENTS
64 select HAVE_PERF_USER_STACK_DUMP
65 select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
66 select HAVE_REGS_AND_STACK_ACCESS_API
67 select HAVE_SYSCALL_TRACEPOINTS
69 select HAVE_VIRT_CPU_ACCOUNTING_GEN
70 select IRQ_FORCED_THREADING
71 select MODULES_USE_ELF_REL
74 select OLD_SIGSUSPEND3
75 select PERF_USE_VMALLOC
77 select SYS_SUPPORTS_APM_EMULATION
78 # Above selects are sorted alphabetically; please add new ones
79 # according to that. Thanks.
81 The ARM series is a line of low-power-consumption RISC chip designs
82 licensed by ARM Ltd and targeted at embedded applications and
83 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
84 manufactured, but legacy ARM-based PC hardware remains popular in
85 Europe. There is an ARM Linux project with a web page at
86 <http://www.arm.linux.org.uk/>.
88 config ARM_HAS_SG_CHAIN
89 select ARCH_HAS_SG_CHAIN
92 config NEED_SG_DMA_LENGTH
95 config ARM_DMA_USE_IOMMU
97 select ARM_HAS_SG_CHAIN
98 select NEED_SG_DMA_LENGTH
102 config ARM_DMA_IOMMU_ALIGNMENT
103 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
107 DMA mapping framework by default aligns all buffers to the smallest
108 PAGE_SIZE order which is greater than or equal to the requested buffer
109 size. This works well for buffers up to a few hundreds kilobytes, but
110 for larger buffers it just a waste of address space. Drivers which has
111 relatively small addressing window (like 64Mib) might run out of
112 virtual space with just a few allocations.
114 With this parameter you can specify the maximum PAGE_SIZE order for
115 DMA IOMMU buffers. Larger buffers will be aligned only to this
116 specified order. The order is expressed as a power of two multiplied
121 config MIGHT_HAVE_PCI
124 config SYS_SUPPORTS_APM_EMULATION
129 select GENERIC_ALLOCATOR
140 The Extended Industry Standard Architecture (EISA) bus was
141 developed as an open alternative to the IBM MicroChannel bus.
143 The EISA bus provided some of the features of the IBM MicroChannel
144 bus while maintaining backward compatibility with cards made for
145 the older ISA bus. The EISA bus saw limited use between 1988 and
146 1995 when it was made obsolete by the PCI bus.
148 Say Y here if you are building a kernel for an EISA-based machine.
155 config STACKTRACE_SUPPORT
159 config HAVE_LATENCYTOP_SUPPORT
164 config LOCKDEP_SUPPORT
168 config TRACE_IRQFLAGS_SUPPORT
172 config RWSEM_XCHGADD_ALGORITHM
176 config ARCH_HAS_ILOG2_U32
179 config ARCH_HAS_ILOG2_U64
182 config ARCH_HAS_BANDGAP
185 config GENERIC_HWEIGHT
189 config GENERIC_CALIBRATE_DELAY
193 config ARCH_MAY_HAVE_PC_FDC
199 config NEED_DMA_MAP_STATE
202 config ARCH_SUPPORTS_UPROBES
205 config ARCH_HAS_DMA_SET_COHERENT_MASK
208 config GENERIC_ISA_DMA
214 config NEED_RET_TO_USER
222 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
223 default DRAM_BASE if REMAP_VECTORS_TO_RAM
226 The base address of exception vectors. This must be two pages
229 config ARM_PATCH_PHYS_VIRT
230 bool "Patch physical to virtual translations at runtime" if EMBEDDED
232 depends on !XIP_KERNEL && MMU
233 depends on !ARCH_REALVIEW || !SPARSEMEM
235 Patch phys-to-virt and virt-to-phys translation functions at
236 boot and module load time according to the position of the
237 kernel in system memory.
239 This can only be used with non-XIP MMU kernels where the base
240 of physical memory is at a 16MB boundary.
242 Only disable this option if you know that you do not require
243 this feature (eg, building a kernel for a single machine) and
244 you need to shrink the kernel to the minimal size.
246 config NEED_MACH_IO_H
249 Select this when mach/io.h is required to provide special
250 definitions for this platform. The need for mach/io.h should
251 be avoided when possible.
253 config NEED_MACH_MEMORY_H
256 Select this when mach/memory.h is required to provide special
257 definitions for this platform. The need for mach/memory.h should
258 be avoided when possible.
261 hex "Physical address of main memory" if MMU
262 depends on !ARM_PATCH_PHYS_VIRT
263 default DRAM_BASE if !MMU
264 default 0x00000000 if ARCH_EBSA110 || \
265 EP93XX_SDCE3_SYNC_PHYS_OFFSET || \
270 (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET)
271 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
272 default 0x20000000 if ARCH_S5PV210
273 default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET
274 default 0xc0000000 if EP93XX_SDCE0_PHYS_OFFSET || ARCH_SA1100
275 default 0xd0000000 if EP93XX_SDCE1_PHYS_OFFSET
276 default 0xe0000000 if EP93XX_SDCE2_PHYS_OFFSET
277 default 0xf0000000 if EP93XX_SDCE3_ASYNC_PHYS_OFFSET
279 Please provide the physical address corresponding to the
280 location of main memory in your system.
286 source "init/Kconfig"
288 source "kernel/Kconfig.freezer"
293 bool "MMU-based Paged Memory Management Support"
296 Select if you want MMU-based virtualised addressing space
297 support by paged memory management. If unsure, say 'Y'.
300 # The "ARM system type" choice list is ordered alphabetically by option
301 # text. Please add new entries in the option alphabetic order.
304 prompt "ARM system type"
305 default ARCH_VERSATILE if !MMU
306 default ARCH_MULTIPLATFORM if MMU
308 config ARCH_MULTIPLATFORM
309 bool "Allow multiple platforms to be selected"
311 select ARCH_WANT_OPTIONAL_GPIOLIB
312 select ARM_HAS_SG_CHAIN
313 select ARM_PATCH_PHYS_VIRT
317 select GENERIC_CLOCKEVENTS
318 select MIGHT_HAVE_PCI
319 select MULTI_IRQ_HANDLER
324 bool "ARM Ltd. RealView family"
325 select ARCH_WANT_OPTIONAL_GPIOLIB
327 select ARM_TIMER_SP804
329 select COMMON_CLK_VERSATILE
330 select GENERIC_CLOCKEVENTS
331 select GPIO_PL061 if GPIOLIB
333 select NEED_MACH_MEMORY_H
334 select PLAT_VERSATILE
335 select PLAT_VERSATILE_SCHED_CLOCK
337 This enables support for ARM Ltd RealView boards.
339 config ARCH_VERSATILE
340 bool "ARM Ltd. Versatile family"
341 select ARCH_WANT_OPTIONAL_GPIOLIB
343 select ARM_TIMER_SP804
346 select GENERIC_CLOCKEVENTS
347 select HAVE_MACH_CLKDEV
349 select PLAT_VERSATILE
350 select PLAT_VERSATILE_CLOCK
351 select PLAT_VERSATILE_SCHED_CLOCK
352 select VERSATILE_FPGA_IRQ
354 This enables support for ARM Ltd Versatile board.
358 select ARCH_REQUIRE_GPIOLIB
361 select NEED_MACH_IO_H if PCCARD
366 This enables support for systems based on Atmel
367 AT91RM9200, AT91SAM9 and SAMA5 processors.
370 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
371 select ARCH_REQUIRE_GPIOLIB
376 select GENERIC_CLOCKEVENTS
380 Support for Cirrus Logic 711x/721x/731x based boards.
383 bool "Cortina Systems Gemini"
384 select ARCH_REQUIRE_GPIOLIB
387 select GENERIC_CLOCKEVENTS
389 Support for the Cortina Systems Gemini family SoCs
393 select ARCH_USES_GETTIMEOFFSET
396 select NEED_MACH_IO_H
397 select NEED_MACH_MEMORY_H
400 This is an evaluation board for the StrongARM processor available
401 from Digital. It has limited hardware on-board, including an
402 Ethernet interface, two PCMCIA sockets, two serial ports and a
406 bool "Energy Micro efm32"
408 select ARCH_REQUIRE_GPIOLIB
414 select GENERIC_CLOCKEVENTS
420 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
425 select ARCH_HAS_HOLES_MEMORYMODEL
426 select ARCH_REQUIRE_GPIOLIB
427 select ARCH_USES_GETTIMEOFFSET
433 This enables support for the Cirrus EP93xx series of CPUs.
435 config ARCH_FOOTBRIDGE
439 select GENERIC_CLOCKEVENTS
441 select NEED_MACH_IO_H if !MMU
442 select NEED_MACH_MEMORY_H
444 Support for systems based on the DC21285 companion chip
445 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
448 bool "Hilscher NetX based"
452 select GENERIC_CLOCKEVENTS
454 This enables support for systems based on the Hilscher NetX Soc
460 select NEED_MACH_MEMORY_H
461 select NEED_RET_TO_USER
467 Support for Intel's IOP13XX (XScale) family of processors.
472 select ARCH_REQUIRE_GPIOLIB
475 select NEED_RET_TO_USER
479 Support for Intel's 80219 and IOP32X (XScale) family of
485 select ARCH_REQUIRE_GPIOLIB
488 select NEED_RET_TO_USER
492 Support for Intel's IOP33X (XScale) family of processors.
497 select ARCH_HAS_DMA_SET_COHERENT_MASK
498 select ARCH_REQUIRE_GPIOLIB
499 select ARCH_SUPPORTS_BIG_ENDIAN
502 select DMABOUNCE if PCI
503 select GENERIC_CLOCKEVENTS
504 select MIGHT_HAVE_PCI
505 select NEED_MACH_IO_H
506 select USB_EHCI_BIG_ENDIAN_DESC
507 select USB_EHCI_BIG_ENDIAN_MMIO
509 Support for Intel's IXP4XX (XScale) family of processors.
513 select ARCH_REQUIRE_GPIOLIB
515 select GENERIC_CLOCKEVENTS
516 select MIGHT_HAVE_PCI
520 select PLAT_ORION_LEGACY
522 Support for the Marvell Dove SoC 88AP510
525 bool "Marvell MV78xx0"
526 select ARCH_REQUIRE_GPIOLIB
528 select GENERIC_CLOCKEVENTS
531 select PLAT_ORION_LEGACY
533 Support for the following Marvell MV78xx0 series SoCs:
539 select ARCH_REQUIRE_GPIOLIB
541 select GENERIC_CLOCKEVENTS
544 select PLAT_ORION_LEGACY
546 Support for the following Marvell Orion 5x series SoCs:
547 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
548 Orion-2 (5281), Orion-1-90 (6183).
551 bool "Marvell PXA168/910/MMP2"
553 select ARCH_REQUIRE_GPIOLIB
555 select GENERIC_ALLOCATOR
556 select GENERIC_CLOCKEVENTS
559 select MULTI_IRQ_HANDLER
564 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
567 bool "Micrel/Kendin KS8695"
568 select ARCH_REQUIRE_GPIOLIB
571 select GENERIC_CLOCKEVENTS
572 select NEED_MACH_MEMORY_H
574 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
575 System-on-Chip devices.
578 bool "Nuvoton W90X900 CPU"
579 select ARCH_REQUIRE_GPIOLIB
583 select GENERIC_CLOCKEVENTS
585 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
586 At present, the w90x900 has been renamed nuc900, regarding
587 the ARM series product line, you can login the following
588 link address to know more.
590 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
591 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
595 select ARCH_REQUIRE_GPIOLIB
600 select GENERIC_CLOCKEVENTS
604 Support for the NXP LPC32XX family of processors
607 bool "PXA2xx/PXA3xx-based"
610 select ARCH_REQUIRE_GPIOLIB
611 select ARM_CPU_SUSPEND if PM
616 select GENERIC_CLOCKEVENTS
619 select MULTI_IRQ_HANDLER
623 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
626 bool "Qualcomm MSM (non-multiplatform)"
627 select ARCH_REQUIRE_GPIOLIB
629 select GENERIC_CLOCKEVENTS
631 Support for Qualcomm MSM/QSD based systems. This runs on the
632 apps processor of the MSM/QSD and depends on a shared memory
633 interface to the modem processor which runs the baseband
634 stack and controls some vital subsystems
635 (clock and power control, etc).
637 config ARCH_SHMOBILE_LEGACY
638 bool "Renesas ARM SoCs (non-multiplatform)"
640 select ARM_PATCH_PHYS_VIRT if MMU
643 select GENERIC_CLOCKEVENTS
644 select HAVE_ARM_SCU if SMP
645 select HAVE_ARM_TWD if SMP
646 select HAVE_MACH_CLKDEV
648 select MIGHT_HAVE_CACHE_L2X0
649 select MULTI_IRQ_HANDLER
652 select PM_GENERIC_DOMAINS if PM
656 Support for Renesas ARM SoC platforms using a non-multiplatform
657 kernel. This includes the SH-Mobile, R-Mobile, EMMA-Mobile, R-Car
663 select ARCH_MAY_HAVE_PC_FDC
664 select ARCH_SPARSEMEM_ENABLE
665 select ARCH_USES_GETTIMEOFFSET
669 select HAVE_PATA_PLATFORM
671 select NEED_MACH_IO_H
672 select NEED_MACH_MEMORY_H
676 On the Acorn Risc-PC, Linux can support the internal IDE disk and
677 CD-ROM interface, serial and parallel port, and the floppy drive.
682 select ARCH_REQUIRE_GPIOLIB
683 select ARCH_SPARSEMEM_ENABLE
688 select GENERIC_CLOCKEVENTS
691 select NEED_MACH_MEMORY_H
694 Support for StrongARM 11x0 based boards.
697 bool "Samsung S3C24XX SoCs"
698 select ARCH_REQUIRE_GPIOLIB
701 select CLKSRC_SAMSUNG_PWM
702 select GENERIC_CLOCKEVENTS
704 select HAVE_S3C2410_I2C if I2C
705 select HAVE_S3C2410_WATCHDOG if WATCHDOG
706 select HAVE_S3C_RTC if RTC_CLASS
707 select MULTI_IRQ_HANDLER
708 select NEED_MACH_IO_H
711 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
712 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
713 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
714 Samsung SMDK2410 development board (and derivatives).
717 bool "Samsung S3C64XX"
718 select ARCH_REQUIRE_GPIOLIB
723 select CLKSRC_SAMSUNG_PWM
724 select COMMON_CLK_SAMSUNG
726 select GENERIC_CLOCKEVENTS
728 select HAVE_S3C2410_I2C if I2C
729 select HAVE_S3C2410_WATCHDOG if WATCHDOG
733 select PM_GENERIC_DOMAINS if PM
735 select S3C_GPIO_TRACK
737 select SAMSUNG_WAKEMASK
738 select SAMSUNG_WDT_RESET
740 Samsung S3C64XX series based systems
744 select ARCH_HAS_HOLES_MEMORYMODEL
745 select ARCH_REQUIRE_GPIOLIB
747 select GENERIC_ALLOCATOR
748 select GENERIC_CLOCKEVENTS
749 select GENERIC_IRQ_CHIP
755 Support for TI's DaVinci platform.
760 select ARCH_HAS_HOLES_MEMORYMODEL
762 select ARCH_REQUIRE_GPIOLIB
765 select GENERIC_CLOCKEVENTS
766 select GENERIC_IRQ_CHIP
769 select NEED_MACH_IO_H if PCCARD
770 select NEED_MACH_MEMORY_H
772 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
776 menu "Multiple platform selection"
777 depends on ARCH_MULTIPLATFORM
779 comment "CPU Core family selection"
782 bool "ARMv4 based platforms (FA526)"
783 depends on !ARCH_MULTI_V6_V7
784 select ARCH_MULTI_V4_V5
787 config ARCH_MULTI_V4T
788 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
789 depends on !ARCH_MULTI_V6_V7
790 select ARCH_MULTI_V4_V5
791 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
792 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
793 CPU_ARM925T || CPU_ARM940T)
796 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
797 depends on !ARCH_MULTI_V6_V7
798 select ARCH_MULTI_V4_V5
799 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
800 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
801 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
803 config ARCH_MULTI_V4_V5
807 bool "ARMv6 based platforms (ARM11)"
808 select ARCH_MULTI_V6_V7
812 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
814 select ARCH_MULTI_V6_V7
818 config ARCH_MULTI_V6_V7
820 select MIGHT_HAVE_CACHE_L2X0
822 config ARCH_MULTI_CPU_AUTO
823 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
829 bool "Dummy Virtual Machine" if ARCH_MULTI_V7
833 select HAVE_ARM_ARCH_TIMER
836 # This is sorted alphabetically by mach-* pathname. However, plat-*
837 # Kconfigs may be included either alphabetically (according to the
838 # plat- suffix) or along side the corresponding mach-* source.
840 source "arch/arm/mach-mvebu/Kconfig"
842 source "arch/arm/mach-asm9260/Kconfig"
844 source "arch/arm/mach-at91/Kconfig"
846 source "arch/arm/mach-axxia/Kconfig"
848 source "arch/arm/mach-bcm/Kconfig"
850 source "arch/arm/mach-berlin/Kconfig"
852 source "arch/arm/mach-clps711x/Kconfig"
854 source "arch/arm/mach-cns3xxx/Kconfig"
856 source "arch/arm/mach-davinci/Kconfig"
858 source "arch/arm/mach-dove/Kconfig"
860 source "arch/arm/mach-ep93xx/Kconfig"
862 source "arch/arm/mach-footbridge/Kconfig"
864 source "arch/arm/mach-gemini/Kconfig"
866 source "arch/arm/mach-highbank/Kconfig"
868 source "arch/arm/mach-hisi/Kconfig"
870 source "arch/arm/mach-integrator/Kconfig"
872 source "arch/arm/mach-iop32x/Kconfig"
874 source "arch/arm/mach-iop33x/Kconfig"
876 source "arch/arm/mach-iop13xx/Kconfig"
878 source "arch/arm/mach-ixp4xx/Kconfig"
880 source "arch/arm/mach-keystone/Kconfig"
882 source "arch/arm/mach-ks8695/Kconfig"
884 source "arch/arm/mach-meson/Kconfig"
886 source "arch/arm/mach-msm/Kconfig"
888 source "arch/arm/mach-moxart/Kconfig"
890 source "arch/arm/mach-mv78xx0/Kconfig"
892 source "arch/arm/mach-imx/Kconfig"
894 source "arch/arm/mach-mediatek/Kconfig"
896 source "arch/arm/mach-mxs/Kconfig"
898 source "arch/arm/mach-netx/Kconfig"
900 source "arch/arm/mach-nomadik/Kconfig"
902 source "arch/arm/mach-nspire/Kconfig"
904 source "arch/arm/plat-omap/Kconfig"
906 source "arch/arm/mach-omap1/Kconfig"
908 source "arch/arm/mach-omap2/Kconfig"
910 source "arch/arm/mach-orion5x/Kconfig"
912 source "arch/arm/mach-picoxcell/Kconfig"
914 source "arch/arm/mach-pxa/Kconfig"
915 source "arch/arm/plat-pxa/Kconfig"
917 source "arch/arm/mach-mmp/Kconfig"
919 source "arch/arm/mach-qcom/Kconfig"
921 source "arch/arm/mach-realview/Kconfig"
923 source "arch/arm/mach-rockchip/Kconfig"
925 source "arch/arm/mach-sa1100/Kconfig"
927 source "arch/arm/mach-socfpga/Kconfig"
929 source "arch/arm/mach-spear/Kconfig"
931 source "arch/arm/mach-sti/Kconfig"
933 source "arch/arm/mach-s3c24xx/Kconfig"
935 source "arch/arm/mach-s3c64xx/Kconfig"
937 source "arch/arm/mach-s5pv210/Kconfig"
939 source "arch/arm/mach-exynos/Kconfig"
940 source "arch/arm/plat-samsung/Kconfig"
942 source "arch/arm/mach-shmobile/Kconfig"
944 source "arch/arm/mach-sunxi/Kconfig"
946 source "arch/arm/mach-prima2/Kconfig"
948 source "arch/arm/mach-tegra/Kconfig"
950 source "arch/arm/mach-u300/Kconfig"
952 source "arch/arm/mach-ux500/Kconfig"
954 source "arch/arm/mach-versatile/Kconfig"
956 source "arch/arm/mach-vexpress/Kconfig"
957 source "arch/arm/plat-versatile/Kconfig"
959 source "arch/arm/mach-vt8500/Kconfig"
961 source "arch/arm/mach-w90x900/Kconfig"
963 source "arch/arm/mach-zynq/Kconfig"
965 # Definitions to make life easier
971 select GENERIC_CLOCKEVENTS
977 select GENERIC_IRQ_CHIP
980 config PLAT_ORION_LEGACY
987 config PLAT_VERSATILE
990 config ARM_TIMER_SP804
993 select CLKSRC_OF if OF
995 source "arch/arm/firmware/Kconfig"
997 source arch/arm/mm/Kconfig
1000 bool "Enable iWMMXt support"
1001 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
1002 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
1004 Enable support for iWMMXt context switching at run time if
1005 running on a CPU that supports it.
1007 config MULTI_IRQ_HANDLER
1010 Allow each machine to specify it's own IRQ handler at run time.
1013 source "arch/arm/Kconfig-nommu"
1016 config PJ4B_ERRATA_4742
1017 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1018 depends on CPU_PJ4B && MACH_ARMADA_370
1021 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1022 Event (WFE) IDLE states, a specific timing sensitivity exists between
1023 the retiring WFI/WFE instructions and the newly issued subsequent
1024 instructions. This sensitivity can result in a CPU hang scenario.
1026 The software must insert either a Data Synchronization Barrier (DSB)
1027 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1030 config ARM_ERRATA_326103
1031 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1034 Executing a SWP instruction to read-only memory does not set bit 11
1035 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1036 treat the access as a read, preventing a COW from occurring and
1037 causing the faulting task to livelock.
1039 config ARM_ERRATA_411920
1040 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1041 depends on CPU_V6 || CPU_V6K
1043 Invalidation of the Instruction Cache operation can
1044 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1045 It does not affect the MPCore. This option enables the ARM Ltd.
1046 recommended workaround.
1048 config ARM_ERRATA_430973
1049 bool "ARM errata: Stale prediction on replaced interworking branch"
1052 This option enables the workaround for the 430973 Cortex-A8
1053 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1054 interworking branch is replaced with another code sequence at the
1055 same virtual address, whether due to self-modifying code or virtual
1056 to physical address re-mapping, Cortex-A8 does not recover from the
1057 stale interworking branch prediction. This results in Cortex-A8
1058 executing the new code sequence in the incorrect ARM or Thumb state.
1059 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1060 and also flushes the branch target cache at every context switch.
1061 Note that setting specific bits in the ACTLR register may not be
1062 available in non-secure mode.
1064 config ARM_ERRATA_458693
1065 bool "ARM errata: Processor deadlock when a false hazard is created"
1067 depends on !ARCH_MULTIPLATFORM
1069 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1070 erratum. For very specific sequences of memory operations, it is
1071 possible for a hazard condition intended for a cache line to instead
1072 be incorrectly associated with a different cache line. This false
1073 hazard might then cause a processor deadlock. The workaround enables
1074 the L1 caching of the NEON accesses and disables the PLD instruction
1075 in the ACTLR register. Note that setting specific bits in the ACTLR
1076 register may not be available in non-secure mode.
1078 config ARM_ERRATA_460075
1079 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1081 depends on !ARCH_MULTIPLATFORM
1083 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1084 erratum. Any asynchronous access to the L2 cache may encounter a
1085 situation in which recent store transactions to the L2 cache are lost
1086 and overwritten with stale memory contents from external memory. The
1087 workaround disables the write-allocate mode for the L2 cache via the
1088 ACTLR register. Note that setting specific bits in the ACTLR register
1089 may not be available in non-secure mode.
1091 config ARM_ERRATA_742230
1092 bool "ARM errata: DMB operation may be faulty"
1093 depends on CPU_V7 && SMP
1094 depends on !ARCH_MULTIPLATFORM
1096 This option enables the workaround for the 742230 Cortex-A9
1097 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1098 between two write operations may not ensure the correct visibility
1099 ordering of the two writes. This workaround sets a specific bit in
1100 the diagnostic register of the Cortex-A9 which causes the DMB
1101 instruction to behave as a DSB, ensuring the correct behaviour of
1104 config ARM_ERRATA_742231
1105 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1106 depends on CPU_V7 && SMP
1107 depends on !ARCH_MULTIPLATFORM
1109 This option enables the workaround for the 742231 Cortex-A9
1110 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1111 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1112 accessing some data located in the same cache line, may get corrupted
1113 data due to bad handling of the address hazard when the line gets
1114 replaced from one of the CPUs at the same time as another CPU is
1115 accessing it. This workaround sets specific bits in the diagnostic
1116 register of the Cortex-A9 which reduces the linefill issuing
1117 capabilities of the processor.
1119 config ARM_ERRATA_643719
1120 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1121 depends on CPU_V7 && SMP
1123 This option enables the workaround for the 643719 Cortex-A9 (prior to
1124 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1125 register returns zero when it should return one. The workaround
1126 corrects this value, ensuring cache maintenance operations which use
1127 it behave as intended and avoiding data corruption.
1129 config ARM_ERRATA_720789
1130 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1133 This option enables the workaround for the 720789 Cortex-A9 (prior to
1134 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1135 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1136 As a consequence of this erratum, some TLB entries which should be
1137 invalidated are not, resulting in an incoherency in the system page
1138 tables. The workaround changes the TLB flushing routines to invalidate
1139 entries regardless of the ASID.
1141 config ARM_ERRATA_743622
1142 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1144 depends on !ARCH_MULTIPLATFORM
1146 This option enables the workaround for the 743622 Cortex-A9
1147 (r2p*) erratum. Under very rare conditions, a faulty
1148 optimisation in the Cortex-A9 Store Buffer may lead to data
1149 corruption. This workaround sets a specific bit in the diagnostic
1150 register of the Cortex-A9 which disables the Store Buffer
1151 optimisation, preventing the defect from occurring. This has no
1152 visible impact on the overall performance or power consumption of the
1155 config ARM_ERRATA_751472
1156 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1158 depends on !ARCH_MULTIPLATFORM
1160 This option enables the workaround for the 751472 Cortex-A9 (prior
1161 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1162 completion of a following broadcasted operation if the second
1163 operation is received by a CPU before the ICIALLUIS has completed,
1164 potentially leading to corrupted entries in the cache or TLB.
1166 config ARM_ERRATA_754322
1167 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1170 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1171 r3p*) erratum. A speculative memory access may cause a page table walk
1172 which starts prior to an ASID switch but completes afterwards. This
1173 can populate the micro-TLB with a stale entry which may be hit with
1174 the new ASID. This workaround places two dsb instructions in the mm
1175 switching code so that no page table walks can cross the ASID switch.
1177 config ARM_ERRATA_754327
1178 bool "ARM errata: no automatic Store Buffer drain"
1179 depends on CPU_V7 && SMP
1181 This option enables the workaround for the 754327 Cortex-A9 (prior to
1182 r2p0) erratum. The Store Buffer does not have any automatic draining
1183 mechanism and therefore a livelock may occur if an external agent
1184 continuously polls a memory location waiting to observe an update.
1185 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1186 written polling loops from denying visibility of updates to memory.
1188 config ARM_ERRATA_364296
1189 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1192 This options enables the workaround for the 364296 ARM1136
1193 r0p2 erratum (possible cache data corruption with
1194 hit-under-miss enabled). It sets the undocumented bit 31 in
1195 the auxiliary control register and the FI bit in the control
1196 register, thus disabling hit-under-miss without putting the
1197 processor into full low interrupt latency mode. ARM11MPCore
1200 config ARM_ERRATA_764369
1201 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1202 depends on CPU_V7 && SMP
1204 This option enables the workaround for erratum 764369
1205 affecting Cortex-A9 MPCore with two or more processors (all
1206 current revisions). Under certain timing circumstances, a data
1207 cache line maintenance operation by MVA targeting an Inner
1208 Shareable memory region may fail to proceed up to either the
1209 Point of Coherency or to the Point of Unification of the
1210 system. This workaround adds a DSB instruction before the
1211 relevant cache maintenance functions and sets a specific bit
1212 in the diagnostic control register of the SCU.
1214 config ARM_ERRATA_775420
1215 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1218 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1219 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1220 operation aborts with MMU exception, it might cause the processor
1221 to deadlock. This workaround puts DSB before executing ISB if
1222 an abort may occur on cache maintenance.
1224 config ARM_ERRATA_798181
1225 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1226 depends on CPU_V7 && SMP
1228 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1229 adequately shooting down all use of the old entries. This
1230 option enables the Linux kernel workaround for this erratum
1231 which sends an IPI to the CPUs that are running the same ASID
1232 as the one being invalidated.
1234 config ARM_ERRATA_773022
1235 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1238 This option enables the workaround for the 773022 Cortex-A15
1239 (up to r0p4) erratum. In certain rare sequences of code, the
1240 loop buffer may deliver incorrect instructions. This
1241 workaround disables the loop buffer to avoid the erratum.
1245 source "arch/arm/common/Kconfig"
1252 Find out whether you have ISA slots on your motherboard. ISA is the
1253 name of a bus system, i.e. the way the CPU talks to the other stuff
1254 inside your box. Other bus systems are PCI, EISA, MicroChannel
1255 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1256 newer boards don't support it. If you have ISA, say Y, otherwise N.
1258 # Select ISA DMA controller support
1263 # Select ISA DMA interface
1268 bool "PCI support" if MIGHT_HAVE_PCI
1270 Find out whether you have a PCI motherboard. PCI is the name of a
1271 bus system, i.e. the way the CPU talks to the other stuff inside
1272 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1273 VESA. If you have PCI, say Y, otherwise N.
1279 config PCI_NANOENGINE
1280 bool "BSE nanoEngine PCI support"
1281 depends on SA1100_NANOENGINE
1283 Enable PCI on the BSE nanoEngine board.
1288 config PCI_HOST_ITE8152
1290 depends on PCI && MACH_ARMCORE
1294 source "drivers/pci/Kconfig"
1295 source "drivers/pci/pcie/Kconfig"
1297 source "drivers/pcmcia/Kconfig"
1301 menu "Kernel Features"
1306 This option should be selected by machines which have an SMP-
1309 The only effect of this option is to make the SMP-related
1310 options available to the user for configuration.
1313 bool "Symmetric Multi-Processing"
1314 depends on CPU_V6K || CPU_V7
1315 depends on GENERIC_CLOCKEVENTS
1317 depends on MMU || ARM_MPU
1319 This enables support for systems with more than one CPU. If you have
1320 a system with only one CPU, say N. If you have a system with more
1321 than one CPU, say Y.
1323 If you say N here, the kernel will run on uni- and multiprocessor
1324 machines, but will use only one CPU of a multiprocessor machine. If
1325 you say Y here, the kernel will run on many, but not all,
1326 uniprocessor machines. On a uniprocessor machine, the kernel
1327 will run faster if you say N here.
1329 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1330 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1331 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1333 If you don't know what to do here, say N.
1336 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1337 depends on SMP && !XIP_KERNEL && MMU
1340 SMP kernels contain instructions which fail on non-SMP processors.
1341 Enabling this option allows the kernel to modify itself to make
1342 these instructions safe. Disabling it allows about 1K of space
1345 If you don't know what to do here, say Y.
1347 config ARM_CPU_TOPOLOGY
1348 bool "Support cpu topology definition"
1349 depends on SMP && CPU_V7
1352 Support ARM cpu topology definition. The MPIDR register defines
1353 affinity between processors which is then used to describe the cpu
1354 topology of an ARM System.
1357 bool "Multi-core scheduler support"
1358 depends on ARM_CPU_TOPOLOGY
1360 Multi-core scheduler support improves the CPU scheduler's decision
1361 making when dealing with multi-core CPU chips at a cost of slightly
1362 increased overhead in some places. If unsure say N here.
1365 bool "SMT scheduler support"
1366 depends on ARM_CPU_TOPOLOGY
1368 Improves the CPU scheduler's decision making when dealing with
1369 MultiThreading at a cost of slightly increased overhead in some
1370 places. If unsure say N here.
1375 This option enables support for the ARM system coherency unit
1377 config HAVE_ARM_ARCH_TIMER
1378 bool "Architected timer support"
1380 select ARM_ARCH_TIMER
1381 select GENERIC_CLOCKEVENTS
1383 This option enables support for the ARM architected timer
1388 select CLKSRC_OF if OF
1390 This options enables support for the ARM timer and watchdog unit
1393 bool "Multi-Cluster Power Management"
1394 depends on CPU_V7 && SMP
1396 This option provides the common power management infrastructure
1397 for (multi-)cluster based systems, such as big.LITTLE based
1400 config MCPM_QUAD_CLUSTER
1404 To avoid wasting resources unnecessarily, MCPM only supports up
1405 to 2 clusters by default.
1406 Platforms with 3 or 4 clusters that use MCPM must select this
1407 option to allow the additional clusters to be managed.
1410 bool "big.LITTLE support (Experimental)"
1411 depends on CPU_V7 && SMP
1414 This option enables support selections for the big.LITTLE
1415 system architecture.
1418 bool "big.LITTLE switcher support"
1419 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1420 select ARM_CPU_SUSPEND
1423 The big.LITTLE "switcher" provides the core functionality to
1424 transparently handle transition between a cluster of A15's
1425 and a cluster of A7's in a big.LITTLE system.
1427 config BL_SWITCHER_DUMMY_IF
1428 tristate "Simple big.LITTLE switcher user interface"
1429 depends on BL_SWITCHER && DEBUG_KERNEL
1431 This is a simple and dummy char dev interface to control
1432 the big.LITTLE switcher core code. It is meant for
1433 debugging purposes only.
1436 prompt "Memory split"
1440 Select the desired split between kernel and user memory.
1442 If you are not absolutely sure what you are doing, leave this
1446 bool "3G/1G user/kernel split"
1448 bool "2G/2G user/kernel split"
1450 bool "1G/3G user/kernel split"
1455 default PHYS_OFFSET if !MMU
1456 default 0x40000000 if VMSPLIT_1G
1457 default 0x80000000 if VMSPLIT_2G
1461 int "Maximum number of CPUs (2-32)"
1467 bool "Support for hot-pluggable CPUs"
1470 Say Y here to experiment with turning CPUs off and on. CPUs
1471 can be controlled through /sys/devices/system/cpu.
1474 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1477 Say Y here if you want Linux to communicate with system firmware
1478 implementing the PSCI specification for CPU-centric power
1479 management operations described in ARM document number ARM DEN
1480 0022A ("Power State Coordination Interface System Software on
1483 # The GPIO number here must be sorted by descending number. In case of
1484 # a multiplatform kernel, we just want the highest value required by the
1485 # selected platforms.
1488 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1489 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1490 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1491 default 416 if ARCH_SUNXI
1492 default 392 if ARCH_U8500
1493 default 352 if ARCH_VT8500
1494 default 288 if ARCH_ROCKCHIP
1495 default 264 if MACH_H4700
1498 Maximum number of GPIOs in the system.
1500 If unsure, leave the default value.
1502 source kernel/Kconfig.preempt
1506 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1507 ARCH_S5PV210 || ARCH_EXYNOS4
1508 default AT91_TIMER_HZ if ARCH_AT91
1509 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
1513 depends on HZ_FIXED = 0
1514 prompt "Timer frequency"
1538 default HZ_FIXED if HZ_FIXED != 0
1539 default 100 if HZ_100
1540 default 200 if HZ_200
1541 default 250 if HZ_250
1542 default 300 if HZ_300
1543 default 500 if HZ_500
1547 def_bool HIGH_RES_TIMERS
1549 config THUMB2_KERNEL
1550 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1551 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1552 default y if CPU_THUMBONLY
1554 select ARM_ASM_UNIFIED
1557 By enabling this option, the kernel will be compiled in
1558 Thumb-2 mode. A compiler/assembler that understand the unified
1559 ARM-Thumb syntax is needed.
1563 config THUMB2_AVOID_R_ARM_THM_JUMP11
1564 bool "Work around buggy Thumb-2 short branch relocations in gas"
1565 depends on THUMB2_KERNEL && MODULES
1568 Various binutils versions can resolve Thumb-2 branches to
1569 locally-defined, preemptible global symbols as short-range "b.n"
1570 branch instructions.
1572 This is a problem, because there's no guarantee the final
1573 destination of the symbol, or any candidate locations for a
1574 trampoline, are within range of the branch. For this reason, the
1575 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1576 relocation in modules at all, and it makes little sense to add
1579 The symptom is that the kernel fails with an "unsupported
1580 relocation" error when loading some modules.
1582 Until fixed tools are available, passing
1583 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1584 code which hits this problem, at the cost of a bit of extra runtime
1585 stack usage in some cases.
1587 The problem is described in more detail at:
1588 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1590 Only Thumb-2 kernels are affected.
1592 Unless you are sure your tools don't have this problem, say Y.
1594 config ARM_ASM_UNIFIED
1598 bool "Use the ARM EABI to compile the kernel"
1600 This option allows for the kernel to be compiled using the latest
1601 ARM ABI (aka EABI). This is only useful if you are using a user
1602 space environment that is also compiled with EABI.
1604 Since there are major incompatibilities between the legacy ABI and
1605 EABI, especially with regard to structure member alignment, this
1606 option also changes the kernel syscall calling convention to
1607 disambiguate both ABIs and allow for backward compatibility support
1608 (selected with CONFIG_OABI_COMPAT).
1610 To use this you need GCC version 4.0.0 or later.
1613 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1614 depends on AEABI && !THUMB2_KERNEL
1616 This option preserves the old syscall interface along with the
1617 new (ARM EABI) one. It also provides a compatibility layer to
1618 intercept syscalls that have structure arguments which layout
1619 in memory differs between the legacy ABI and the new ARM EABI
1620 (only for non "thumb" binaries). This option adds a tiny
1621 overhead to all syscalls and produces a slightly larger kernel.
1623 The seccomp filter system will not be available when this is
1624 selected, since there is no way yet to sensibly distinguish
1625 between calling conventions during filtering.
1627 If you know you'll be using only pure EABI user space then you
1628 can say N here. If this option is not selected and you attempt
1629 to execute a legacy ABI binary then the result will be
1630 UNPREDICTABLE (in fact it can be predicted that it won't work
1631 at all). If in doubt say N.
1633 config ARCH_HAS_HOLES_MEMORYMODEL
1636 config ARCH_SPARSEMEM_ENABLE
1639 config ARCH_SPARSEMEM_DEFAULT
1640 def_bool ARCH_SPARSEMEM_ENABLE
1642 config ARCH_SELECT_MEMORY_MODEL
1643 def_bool ARCH_SPARSEMEM_ENABLE
1645 config HAVE_ARCH_PFN_VALID
1646 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1648 config HAVE_GENERIC_RCU_GUP
1653 bool "High Memory Support"
1656 The address space of ARM processors is only 4 Gigabytes large
1657 and it has to accommodate user address space, kernel address
1658 space as well as some memory mapped IO. That means that, if you
1659 have a large amount of physical memory and/or IO, not all of the
1660 memory can be "permanently mapped" by the kernel. The physical
1661 memory that is not permanently mapped is called "high memory".
1663 Depending on the selected kernel/user memory split, minimum
1664 vmalloc space and actual amount of RAM, you may not need this
1665 option which should result in a slightly faster kernel.
1670 bool "Allocate 2nd-level pagetables from highmem"
1673 config HW_PERF_EVENTS
1674 bool "Enable hardware performance counter support for perf events"
1675 depends on PERF_EVENTS
1678 Enable hardware performance counter support for perf events. If
1679 disabled, perf events will use software events only.
1681 config SYS_SUPPORTS_HUGETLBFS
1685 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1689 config ARCH_WANT_GENERAL_HUGETLB
1694 config FORCE_MAX_ZONEORDER
1695 int "Maximum zone order" if ARCH_SHMOBILE_LEGACY
1696 range 11 64 if ARCH_SHMOBILE_LEGACY
1697 default "12" if SOC_AM33XX
1698 default "9" if SA1111 || ARCH_EFM32
1701 The kernel memory allocator divides physically contiguous memory
1702 blocks into "zones", where each zone is a power of two number of
1703 pages. This option selects the largest power of two that the kernel
1704 keeps in the memory allocator. If you need to allocate very large
1705 blocks of physically contiguous memory, then you may need to
1706 increase this value.
1708 This config option is actually maximum order plus one. For example,
1709 a value of 11 means that the largest free memory block is 2^10 pages.
1711 config ALIGNMENT_TRAP
1713 depends on CPU_CP15_MMU
1714 default y if !ARCH_EBSA110
1715 select HAVE_PROC_CPU if PROC_FS
1717 ARM processors cannot fetch/store information which is not
1718 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1719 address divisible by 4. On 32-bit ARM processors, these non-aligned
1720 fetch/store instructions will be emulated in software if you say
1721 here, which has a severe performance impact. This is necessary for
1722 correct operation of some network protocols. With an IP-only
1723 configuration it is safe to say N, otherwise say Y.
1725 config UACCESS_WITH_MEMCPY
1726 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1728 default y if CPU_FEROCEON
1730 Implement faster copy_to_user and clear_user methods for CPU
1731 cores where a 8-word STM instruction give significantly higher
1732 memory write throughput than a sequence of individual 32bit stores.
1734 A possible side effect is a slight increase in scheduling latency
1735 between threads sharing the same address space if they invoke
1736 such copy operations with large buffers.
1738 However, if the CPU data cache is using a write-allocate mode,
1739 this option is unlikely to provide any performance gain.
1743 prompt "Enable seccomp to safely compute untrusted bytecode"
1745 This kernel feature is useful for number crunching applications
1746 that may need to compute untrusted bytecode during their
1747 execution. By using pipes or other transports made available to
1748 the process as file descriptors supporting the read/write
1749 syscalls, it's possible to isolate those applications in
1750 their own address space using seccomp. Once seccomp is
1751 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1752 and the task is only allowed to execute a few safe syscalls
1753 defined by each seccomp mode.
1766 bool "Xen guest support on ARM"
1767 depends on ARM && AEABI && OF
1768 depends on CPU_V7 && !CPU_V6
1769 depends on !GENERIC_ATOMIC64
1771 select ARCH_DMA_ADDR_T_64BIT
1775 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1782 bool "Flattened Device Tree support"
1785 select OF_EARLY_FLATTREE
1786 select OF_RESERVED_MEM
1788 Include support for flattened device tree machine descriptions.
1791 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1794 This is the traditional way of passing data to the kernel at boot
1795 time. If you are solely relying on the flattened device tree (or
1796 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1797 to remove ATAGS support from your kernel binary. If unsure,
1800 config DEPRECATED_PARAM_STRUCT
1801 bool "Provide old way to pass kernel parameters"
1804 This was deprecated in 2001 and announced to live on for 5 years.
1805 Some old boot loaders still use this way.
1807 # Compressed boot loader in ROM. Yes, we really want to ask about
1808 # TEXT and BSS so we preserve their values in the config files.
1809 config ZBOOT_ROM_TEXT
1810 hex "Compressed ROM boot loader base address"
1813 The physical address at which the ROM-able zImage is to be
1814 placed in the target. Platforms which normally make use of
1815 ROM-able zImage formats normally set this to a suitable
1816 value in their defconfig file.
1818 If ZBOOT_ROM is not enabled, this has no effect.
1820 config ZBOOT_ROM_BSS
1821 hex "Compressed ROM boot loader BSS address"
1824 The base address of an area of read/write memory in the target
1825 for the ROM-able zImage which must be available while the
1826 decompressor is running. It must be large enough to hold the
1827 entire decompressed kernel plus an additional 128 KiB.
1828 Platforms which normally make use of ROM-able zImage formats
1829 normally set this to a suitable value in their defconfig file.
1831 If ZBOOT_ROM is not enabled, this has no effect.
1834 bool "Compressed boot loader in ROM/flash"
1835 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1836 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1838 Say Y here if you intend to execute your compressed kernel image
1839 (zImage) directly from ROM or flash. If unsure, say N.
1842 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1843 depends on ZBOOT_ROM && ARCH_SH7372
1844 default ZBOOT_ROM_NONE
1846 Include experimental SD/MMC loading code in the ROM-able zImage.
1847 With this enabled it is possible to write the ROM-able zImage
1848 kernel image to an MMC or SD card and boot the kernel straight
1849 from the reset vector. At reset the processor Mask ROM will load
1850 the first part of the ROM-able zImage which in turn loads the
1851 rest the kernel image to RAM.
1853 config ZBOOT_ROM_NONE
1854 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1856 Do not load image from SD or MMC
1858 config ZBOOT_ROM_MMCIF
1859 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1861 Load image from MMCIF hardware block.
1863 config ZBOOT_ROM_SH_MOBILE_SDHI
1864 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1866 Load image from SDHI hardware block
1870 config ARM_APPENDED_DTB
1871 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1874 With this option, the boot code will look for a device tree binary
1875 (DTB) appended to zImage
1876 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1878 This is meant as a backward compatibility convenience for those
1879 systems with a bootloader that can't be upgraded to accommodate
1880 the documented boot protocol using a device tree.
1882 Beware that there is very little in terms of protection against
1883 this option being confused by leftover garbage in memory that might
1884 look like a DTB header after a reboot if no actual DTB is appended
1885 to zImage. Do not leave this option active in a production kernel
1886 if you don't intend to always append a DTB. Proper passing of the
1887 location into r2 of a bootloader provided DTB is always preferable
1890 config ARM_ATAG_DTB_COMPAT
1891 bool "Supplement the appended DTB with traditional ATAG information"
1892 depends on ARM_APPENDED_DTB
1894 Some old bootloaders can't be updated to a DTB capable one, yet
1895 they provide ATAGs with memory configuration, the ramdisk address,
1896 the kernel cmdline string, etc. Such information is dynamically
1897 provided by the bootloader and can't always be stored in a static
1898 DTB. To allow a device tree enabled kernel to be used with such
1899 bootloaders, this option allows zImage to extract the information
1900 from the ATAG list and store it at run time into the appended DTB.
1903 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1904 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1906 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1907 bool "Use bootloader kernel arguments if available"
1909 Uses the command-line options passed by the boot loader instead of
1910 the device tree bootargs property. If the boot loader doesn't provide
1911 any, the device tree bootargs property will be used.
1913 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1914 bool "Extend with bootloader kernel arguments"
1916 The command-line arguments provided by the boot loader will be
1917 appended to the the device tree bootargs property.
1922 string "Default kernel command string"
1925 On some architectures (EBSA110 and CATS), there is currently no way
1926 for the boot loader to pass arguments to the kernel. For these
1927 architectures, you should supply some command-line options at build
1928 time by entering them here. As a minimum, you should specify the
1929 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1932 prompt "Kernel command line type" if CMDLINE != ""
1933 default CMDLINE_FROM_BOOTLOADER
1936 config CMDLINE_FROM_BOOTLOADER
1937 bool "Use bootloader kernel arguments if available"
1939 Uses the command-line options passed by the boot loader. If
1940 the boot loader doesn't provide any, the default kernel command
1941 string provided in CMDLINE will be used.
1943 config CMDLINE_EXTEND
1944 bool "Extend bootloader kernel arguments"
1946 The command-line arguments provided by the boot loader will be
1947 appended to the default kernel command string.
1949 config CMDLINE_FORCE
1950 bool "Always use the default kernel command string"
1952 Always use the default kernel command string, even if the boot
1953 loader passes other arguments to the kernel.
1954 This is useful if you cannot or don't want to change the
1955 command-line options your boot loader passes to the kernel.
1959 bool "Kernel Execute-In-Place from ROM"
1960 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1962 Execute-In-Place allows the kernel to run from non-volatile storage
1963 directly addressable by the CPU, such as NOR flash. This saves RAM
1964 space since the text section of the kernel is not loaded from flash
1965 to RAM. Read-write sections, such as the data section and stack,
1966 are still copied to RAM. The XIP kernel is not compressed since
1967 it has to run directly from flash, so it will take more space to
1968 store it. The flash address used to link the kernel object files,
1969 and for storing it, is configuration dependent. Therefore, if you
1970 say Y here, you must know the proper physical address where to
1971 store the kernel image depending on your own flash memory usage.
1973 Also note that the make target becomes "make xipImage" rather than
1974 "make zImage" or "make Image". The final kernel binary to put in
1975 ROM memory will be arch/arm/boot/xipImage.
1979 config XIP_PHYS_ADDR
1980 hex "XIP Kernel Physical Location"
1981 depends on XIP_KERNEL
1982 default "0x00080000"
1984 This is the physical address in your flash memory the kernel will
1985 be linked for and stored to. This address is dependent on your
1989 bool "Kexec system call (EXPERIMENTAL)"
1990 depends on (!SMP || PM_SLEEP_SMP)
1992 kexec is a system call that implements the ability to shutdown your
1993 current kernel, and to start another kernel. It is like a reboot
1994 but it is independent of the system firmware. And like a reboot
1995 you can start any kernel with it, not just Linux.
1997 It is an ongoing process to be certain the hardware in a machine
1998 is properly shutdown, so do not be surprised if this code does not
1999 initially work for you.
2002 bool "Export atags in procfs"
2003 depends on ATAGS && KEXEC
2006 Should the atags used to boot the kernel be exported in an "atags"
2007 file in procfs. Useful with kexec.
2010 bool "Build kdump crash kernel (EXPERIMENTAL)"
2012 Generate crash dump after being started by kexec. This should
2013 be normally only set in special crash dump kernels which are
2014 loaded in the main kernel with kexec-tools into a specially
2015 reserved region and then later executed after a crash by
2016 kdump/kexec. The crash dump kernel must be compiled to a
2017 memory address not used by the main kernel
2019 For more details see Documentation/kdump/kdump.txt
2021 config AUTO_ZRELADDR
2022 bool "Auto calculation of the decompressed kernel image address"
2024 ZRELADDR is the physical address where the decompressed kernel
2025 image will be placed. If AUTO_ZRELADDR is selected, the address
2026 will be determined at run-time by masking the current IP with
2027 0xf8000000. This assumes the zImage being placed in the first 128MB
2028 from start of memory.
2032 menu "CPU Power Management"
2034 source "drivers/cpufreq/Kconfig"
2036 source "drivers/cpuidle/Kconfig"
2040 menu "Floating point emulation"
2042 comment "At least one emulation must be selected"
2045 bool "NWFPE math emulation"
2046 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2048 Say Y to include the NWFPE floating point emulator in the kernel.
2049 This is necessary to run most binaries. Linux does not currently
2050 support floating point hardware so you need to say Y here even if
2051 your machine has an FPA or floating point co-processor podule.
2053 You may say N here if you are going to load the Acorn FPEmulator
2054 early in the bootup.
2057 bool "Support extended precision"
2058 depends on FPE_NWFPE
2060 Say Y to include 80-bit support in the kernel floating-point
2061 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2062 Note that gcc does not generate 80-bit operations by default,
2063 so in most cases this option only enlarges the size of the
2064 floating point emulator without any good reason.
2066 You almost surely want to say N here.
2069 bool "FastFPE math emulation (EXPERIMENTAL)"
2070 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2072 Say Y here to include the FAST floating point emulator in the kernel.
2073 This is an experimental much faster emulator which now also has full
2074 precision for the mantissa. It does not support any exceptions.
2075 It is very simple, and approximately 3-6 times faster than NWFPE.
2077 It should be sufficient for most programs. It may be not suitable
2078 for scientific calculations, but you have to check this for yourself.
2079 If you do not feel you need a faster FP emulation you should better
2083 bool "VFP-format floating point maths"
2084 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2086 Say Y to include VFP support code in the kernel. This is needed
2087 if your hardware includes a VFP unit.
2089 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2090 release notes and additional status information.
2092 Say N if your target does not have VFP hardware.
2100 bool "Advanced SIMD (NEON) Extension support"
2101 depends on VFPv3 && CPU_V7
2103 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2106 config KERNEL_MODE_NEON
2107 bool "Support for NEON in kernel mode"
2108 depends on NEON && AEABI
2110 Say Y to include support for NEON in kernel mode.
2114 menu "Userspace binary formats"
2116 source "fs/Kconfig.binfmt"
2119 tristate "RISC OS personality"
2122 Say Y here to include the kernel code necessary if you want to run
2123 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2124 experimental; if this sounds frightening, say N and sleep in peace.
2125 You can also say M here to compile this support as a module (which
2126 will be called arthur).
2130 menu "Power management options"
2132 source "kernel/power/Kconfig"
2134 config ARCH_SUSPEND_POSSIBLE
2135 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2136 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2139 config ARM_CPU_SUSPEND
2142 config ARCH_HIBERNATION_POSSIBLE
2145 default y if ARCH_SUSPEND_POSSIBLE
2149 source "net/Kconfig"
2151 source "drivers/Kconfig"
2155 source "arch/arm/Kconfig.debug"
2157 source "security/Kconfig"
2159 source "crypto/Kconfig"
2161 source "lib/Kconfig"
2163 source "arch/arm/kvm/Kconfig"