arch/arm/Kconfig

   1 config ARM
   2         bool
   3         default y
   4         select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
   5         select ARCH_HAS_ELF_RANDOMIZE
   6         select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
   7         select ARCH_HAVE_CUSTOM_GPIO_H
   8         select ARCH_HAS_GCOV_PROFILE_ALL
   9         select ARCH_MIGHT_HAVE_PC_PARPORT
  10         select ARCH_SUPPORTS_ATOMIC_RMW
  11         select ARCH_USE_BUILTIN_BSWAP
  12         select ARCH_USE_CMPXCHG_LOCKREF
  13         select ARCH_WANT_IPC_PARSE_VERSION
  14         select BUILDTIME_EXTABLE_SORT if MMU
  15         select CLONE_BACKWARDS
  16         select CPU_PM if (SUSPEND || CPU_IDLE)
  17         select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
  18         select EDAC_SUPPORT
  19         select EDAC_ATOMIC_SCRUB
  20         select GENERIC_ALLOCATOR
  21         select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
  22         select GENERIC_CLOCKEVENTS_BROADCAST if SMP
  23         select GENERIC_EARLY_IOREMAP
  24         select GENERIC_IDLE_POLL_SETUP
  25         select GENERIC_IRQ_PROBE
  26         select GENERIC_IRQ_SHOW
  27         select GENERIC_IRQ_SHOW_LEVEL
  28         select GENERIC_PCI_IOMAP
  29         select GENERIC_SCHED_CLOCK
  30         select GENERIC_SMP_IDLE_THREAD
  31         select GENERIC_STRNCPY_FROM_USER
  32         select GENERIC_STRNLEN_USER
  33         select HANDLE_DOMAIN_IRQ
  34         select HARDIRQS_SW_RESEND
  35         select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
  36         select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
  37         select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
  38         select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
  39         select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
  40         select HAVE_ARCH_TRACEHOOK
  41         select HAVE_ARM_SMCCC if CPU_V7
  42         select HAVE_BPF_JIT
  43         select HAVE_CC_STACKPROTECTOR
  44         select HAVE_CONTEXT_TRACKING
  45         select HAVE_C_RECORDMCOUNT
  46         select HAVE_DEBUG_KMEMLEAK
  47         select HAVE_DMA_API_DEBUG
  48         select HAVE_DMA_ATTRS
  49         select HAVE_DMA_CONTIGUOUS if MMU
  50         select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32 && MMU
  51         select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
  52         select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
  53         select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
  54         select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
  55         select HAVE_GENERIC_DMA_COHERENT
  56         select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
  57         select HAVE_IDE if PCI || ISA || PCMCIA
  58         select HAVE_IRQ_TIME_ACCOUNTING
  59         select HAVE_KERNEL_GZIP
  60         select HAVE_KERNEL_LZ4
  61         select HAVE_KERNEL_LZMA
  62         select HAVE_KERNEL_LZO
  63         select HAVE_KERNEL_XZ
  64         select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
  65         select HAVE_KRETPROBES if (HAVE_KPROBES)
  66         select HAVE_MEMBLOCK
  67         select HAVE_MOD_ARCH_SPECIFIC
  68         select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
  69         select HAVE_OPTPROBES if !THUMB2_KERNEL
  70         select HAVE_PERF_EVENTS
  71         select HAVE_PERF_REGS
  72         select HAVE_PERF_USER_STACK_DUMP
  73         select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
  74         select HAVE_REGS_AND_STACK_ACCESS_API
  75         select HAVE_SYSCALL_TRACEPOINTS
  76         select HAVE_UID16
  77         select HAVE_VIRT_CPU_ACCOUNTING_GEN
  78         select IRQ_FORCED_THREADING
  79         select MODULES_USE_ELF_REL
  80         select NO_BOOTMEM
  81         select OF_EARLY_FLATTREE if OF
  82         select OF_RESERVED_MEM if OF
  83         select OLD_SIGACTION
  84         select OLD_SIGSUSPEND3
  85         select PERF_USE_VMALLOC
  86         select RTC_LIB
  87         select SYS_SUPPORTS_APM_EMULATION
  88         # Above selects are sorted alphabetically; please add new ones
  89         # according to that.  Thanks.
  90         help
  91           The ARM series is a line of low-power-consumption RISC chip designs
  92           licensed by ARM Ltd and targeted at embedded applications and
  93           handhelds such as the Compaq IPAQ.  ARM-based PCs are no longer
  94           manufactured, but legacy ARM-based PC hardware remains popular in
  95           Europe.  There is an ARM Linux project with a web page at
  96           <http://www.arm.linux.org.uk/>.
  97
  98 config ARM_HAS_SG_CHAIN
  99         select ARCH_HAS_SG_CHAIN
 100         bool
 101
 102 config NEED_SG_DMA_LENGTH
 103         bool
 104
 105 config ARM_DMA_USE_IOMMU
 106         bool
 107         select ARM_HAS_SG_CHAIN
 108         select NEED_SG_DMA_LENGTH
 109
 110 if ARM_DMA_USE_IOMMU
 111
 112 config ARM_DMA_IOMMU_ALIGNMENT
 113         int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
 114         range 4 9
 115         default 8
 116         help
 117           DMA mapping framework by default aligns all buffers to the smallest
 118           PAGE_SIZE order which is greater than or equal to the requested buffer
 119           size. This works well for buffers up to a few hundreds kilobytes, but
 120           for larger buffers it just a waste of address space. Drivers which has
 121           relatively small addressing window (like 64Mib) might run out of
 122           virtual space with just a few allocations.
 123
 124           With this parameter you can specify the maximum PAGE_SIZE order for
 125           DMA IOMMU buffers. Larger buffers will be aligned only to this
 126           specified order. The order is expressed as a power of two multiplied
 127           by the PAGE_SIZE.
 128
 129 endif
 130
 131 config MIGHT_HAVE_PCI
 132         bool
 133
 134 config SYS_SUPPORTS_APM_EMULATION
 135         bool
 136
 137 config HAVE_TCM
 138         bool
 139         select GENERIC_ALLOCATOR
 140
 141 config HAVE_PROC_CPU
 142         bool
 143
 144 config NO_IOPORT_MAP
 145         bool
 146
 147 config EISA
 148         bool
 149         ---help---
 150           The Extended Industry Standard Architecture (EISA) bus was
 151           developed as an open alternative to the IBM MicroChannel bus.
 152
 153           The EISA bus provided some of the features of the IBM MicroChannel
 154           bus while maintaining backward compatibility with cards made for
 155           the older ISA bus.  The EISA bus saw limited use between 1988 and
 156           1995 when it was made obsolete by the PCI bus.
 157
 158           Say Y here if you are building a kernel for an EISA-based machine.
 159
 160           Otherwise, say N.
 161
 162 config SBUS
 163         bool
 164
 165 config STACKTRACE_SUPPORT
 166         bool
 167         default y
 168
 169 config HAVE_LATENCYTOP_SUPPORT
 170         bool
 171         depends on !SMP
 172         default y
 173
 174 config LOCKDEP_SUPPORT
 175         bool
 176         default y
 177
 178 config TRACE_IRQFLAGS_SUPPORT
 179         bool
 180         default !CPU_V7M
 181
 182 config RWSEM_XCHGADD_ALGORITHM
 183         bool
 184         default y
 185
 186 config ARCH_HAS_ILOG2_U32
 187         bool
 188
 189 config ARCH_HAS_ILOG2_U64
 190         bool
 191
 192 config ARCH_HAS_BANDGAP
 193         bool
 194
 195 config FIX_EARLYCON_MEM
 196         def_bool y if MMU
 197
 198 config GENERIC_HWEIGHT
 199         bool
 200         default y
 201
 202 config GENERIC_CALIBRATE_DELAY
 203         bool
 204         default y
 205
 206 config ARCH_MAY_HAVE_PC_FDC
 207         bool
 208
 209 config ZONE_DMA
 210         bool
 211
 212 config NEED_DMA_MAP_STATE
 213        def_bool y
 214
 215 config ARCH_SUPPORTS_UPROBES
 216         def_bool y
 217
 218 config ARCH_HAS_DMA_SET_COHERENT_MASK
 219         bool
 220
 221 config GENERIC_ISA_DMA
 222         bool
 223
 224 config FIQ
 225         bool
 226
 227 config NEED_RET_TO_USER
 228         bool
 229
 230 config ARCH_MTD_XIP
 231         bool
 232
 233 config VECTORS_BASE
 234         hex
 235         default 0xffff0000 if MMU || CPU_HIGH_VECTOR
 236         default DRAM_BASE if REMAP_VECTORS_TO_RAM
 237         default 0x00000000
 238         help
 239           The base address of exception vectors.  This must be two pages
 240           in size.
 241
 242 config ARM_PATCH_PHYS_VIRT
 243         bool "Patch physical to virtual translations at runtime" if EMBEDDED
 244         default y
 245         depends on !XIP_KERNEL && MMU
 246         depends on !ARCH_REALVIEW || !SPARSEMEM
 247         help
 248           Patch phys-to-virt and virt-to-phys translation functions at
 249           boot and module load time according to the position of the
 250           kernel in system memory.
 251
 252           This can only be used with non-XIP MMU kernels where the base
 253           of physical memory is at a 16MB boundary.
 254
 255           Only disable this option if you know that you do not require
 256           this feature (eg, building a kernel for a single machine) and
 257           you need to shrink the kernel to the minimal size.
 258
 259 config NEED_MACH_IO_H
 260         bool
 261         help
 262           Select this when mach/io.h is required to provide special
 263           definitions for this platform.  The need for mach/io.h should
 264           be avoided when possible.
 265
 266 config NEED_MACH_MEMORY_H
 267         bool
 268         help
 269           Select this when mach/memory.h is required to provide special
 270           definitions for this platform.  The need for mach/memory.h should
 271           be avoided when possible.
 272
 273 config PHYS_OFFSET
 274         hex "Physical address of main memory" if MMU
 275         depends on !ARM_PATCH_PHYS_VIRT
 276         default DRAM_BASE if !MMU
 277         default 0x00000000 if ARCH_EBSA110 || \
 278                         ARCH_FOOTBRIDGE || \
 279                         ARCH_INTEGRATOR || \
 280                         ARCH_IOP13XX || \
 281                         ARCH_KS8695 || \
 282                         (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET)
 283         default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
 284         default 0x20000000 if ARCH_S5PV210
 285         default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET
 286         default 0xc0000000 if ARCH_SA1100
 287         help
 288           Please provide the physical address corresponding to the
 289           location of main memory in your system.
 290
 291 config GENERIC_BUG
 292         def_bool y
 293         depends on BUG
 294
 295 config PGTABLE_LEVELS
 296         int
 297         default 3 if ARM_LPAE
 298         default 2
 299
 300 source "init/Kconfig"
 301
 302 source "kernel/Kconfig.freezer"
 303
 304 menu "System Type"
 305
 306 config MMU
 307         bool "MMU-based Paged Memory Management Support"
 308         default y
 309         help
 310           Select if you want MMU-based virtualised addressing space
 311           support by paged memory management. If unsure, say 'Y'.
 312
 313 #
 314 # The "ARM system type" choice list is ordered alphabetically by option
 315 # text.  Please add new entries in the option alphabetic order.
 316 #
 317 choice
 318         prompt "ARM system type"
 319         default ARCH_VERSATILE if !MMU
 320         default ARCH_MULTIPLATFORM if MMU
 321
 322 config ARCH_MULTIPLATFORM
 323         bool "Allow multiple platforms to be selected"
 324         depends on MMU
 325         select ARCH_WANT_OPTIONAL_GPIOLIB
 326         select ARM_HAS_SG_CHAIN
 327         select ARM_PATCH_PHYS_VIRT
 328         select AUTO_ZRELADDR
 329         select CLKSRC_OF
 330         select COMMON_CLK
 331         select GENERIC_CLOCKEVENTS
 332         select MIGHT_HAVE_PCI
 333         select MULTI_IRQ_HANDLER
 334         select SPARSE_IRQ
 335         select USE_OF
 336
 337 config ARM_SINGLE_ARMV7M
 338         bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
 339         depends on !MMU
 340         select ARCH_WANT_OPTIONAL_GPIOLIB
 341         select ARM_NVIC
 342         select AUTO_ZRELADDR
 343         select CLKSRC_OF
 344         select COMMON_CLK
 345         select CPU_V7M
 346         select GENERIC_CLOCKEVENTS
 347         select NO_IOPORT_MAP
 348         select SPARSE_IRQ
 349         select USE_OF
 350
 351 config ARCH_REALVIEW
 352         bool "ARM Ltd. RealView family"
 353         select ARCH_WANT_OPTIONAL_GPIOLIB
 354         select ARM_AMBA
 355         select ARM_TIMER_SP804
 356         select COMMON_CLK
 357         select COMMON_CLK_VERSATILE
 358         select GENERIC_CLOCKEVENTS
 359         select GPIO_PL061 if GPIOLIB
 360         select ICST
 361         select NEED_MACH_MEMORY_H
 362         select PLAT_VERSATILE
 363         select PLAT_VERSATILE_SCHED_CLOCK
 364         help
 365           This enables support for ARM Ltd RealView boards.
 366
 367 config ARCH_VERSATILE
 368         bool "ARM Ltd. Versatile family"
 369         select ARCH_WANT_OPTIONAL_GPIOLIB
 370         select ARM_AMBA
 371         select ARM_TIMER_SP804
 372         select ARM_VIC
 373         select CLKDEV_LOOKUP
 374         select GENERIC_CLOCKEVENTS
 375         select HAVE_MACH_CLKDEV
 376         select ICST
 377         select PLAT_VERSATILE
 378         select PLAT_VERSATILE_CLOCK
 379         select PLAT_VERSATILE_SCHED_CLOCK
 380         select VERSATILE_FPGA_IRQ
 381         help
 382           This enables support for ARM Ltd Versatile board.
 383
 384 config ARCH_CLPS711X
 385         bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
 386         select ARCH_REQUIRE_GPIOLIB
 387         select AUTO_ZRELADDR
 388         select CLKSRC_MMIO
 389         select COMMON_CLK
 390         select CPU_ARM720T
 391         select GENERIC_CLOCKEVENTS
 392         select MFD_SYSCON
 393         select SOC_BUS
 394         help
 395           Support for Cirrus Logic 711x/721x/731x based boards.
 396
 397 config ARCH_GEMINI
 398         bool "Cortina Systems Gemini"
 399         select ARCH_REQUIRE_GPIOLIB
 400         select CLKSRC_MMIO
 401         select CPU_FA526
 402         select GENERIC_CLOCKEVENTS
 403         help
 404           Support for the Cortina Systems Gemini family SoCs
 405
 406 config ARCH_EBSA110
 407         bool "EBSA-110"
 408         select ARCH_USES_GETTIMEOFFSET
 409         select CPU_SA110
 410         select ISA
 411         select NEED_MACH_IO_H
 412         select NEED_MACH_MEMORY_H
 413         select NO_IOPORT_MAP
 414         help
 415           This is an evaluation board for the StrongARM processor available
 416           from Digital. It has limited hardware on-board, including an
 417           Ethernet interface, two PCMCIA sockets, two serial ports and a
 418           parallel port.
 419
 420 config ARCH_EP93XX
 421         bool "EP93xx-based"
 422         select ARCH_HAS_HOLES_MEMORYMODEL
 423         select ARCH_REQUIRE_GPIOLIB
 424         select ARM_AMBA
 425         select ARM_PATCH_PHYS_VIRT
 426         select ARM_VIC
 427         select AUTO_ZRELADDR
 428         select CLKDEV_LOOKUP
 429         select CLKSRC_MMIO
 430         select CPU_ARM920T
 431         select GENERIC_CLOCKEVENTS
 432         help
 433           This enables support for the Cirrus EP93xx series of CPUs.
 434
 435 config ARCH_FOOTBRIDGE
 436         bool "FootBridge"
 437         select CPU_SA110
 438         select FOOTBRIDGE
 439         select GENERIC_CLOCKEVENTS
 440         select HAVE_IDE
 441         select NEED_MACH_IO_H if !MMU
 442         select NEED_MACH_MEMORY_H
 443         help
 444           Support for systems based on the DC21285 companion chip
 445           ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
 446
 447 config ARCH_NETX
 448         bool "Hilscher NetX based"
 449         select ARM_VIC
 450         select CLKSRC_MMIO
 451         select CPU_ARM926T
 452         select GENERIC_CLOCKEVENTS
 453         help
 454           This enables support for systems based on the Hilscher NetX Soc
 455
 456 config ARCH_IOP13XX
 457         bool "IOP13xx-based"
 458         depends on MMU
 459         select CPU_XSC3
 460         select NEED_MACH_MEMORY_H
 461         select NEED_RET_TO_USER
 462         select PCI
 463         select PLAT_IOP
 464         select VMSPLIT_1G
 465         select SPARSE_IRQ
 466         help
 467           Support for Intel's IOP13XX (XScale) family of processors.
 468
 469 config ARCH_IOP32X
 470         bool "IOP32x-based"
 471         depends on MMU
 472         select ARCH_REQUIRE_GPIOLIB
 473         select CPU_XSCALE
 474         select GPIO_IOP
 475         select NEED_RET_TO_USER
 476         select PCI
 477         select PLAT_IOP
 478         help
 479           Support for Intel's 80219 and IOP32X (XScale) family of
 480           processors.
 481
 482 config ARCH_IOP33X
 483         bool "IOP33x-based"
 484         depends on MMU
 485         select ARCH_REQUIRE_GPIOLIB
 486         select CPU_XSCALE
 487         select GPIO_IOP
 488         select NEED_RET_TO_USER
 489         select PCI
 490         select PLAT_IOP
 491         help
 492           Support for Intel's IOP33X (XScale) family of processors.
 493
 494 config ARCH_IXP4XX
 495         bool "IXP4xx-based"
 496         depends on MMU
 497         select ARCH_HAS_DMA_SET_COHERENT_MASK
 498         select ARCH_REQUIRE_GPIOLIB
 499         select ARCH_SUPPORTS_BIG_ENDIAN
 500         select CLKSRC_MMIO
 501         select CPU_XSCALE
 502         select DMABOUNCE if PCI
 503         select GENERIC_CLOCKEVENTS
 504         select MIGHT_HAVE_PCI
 505         select NEED_MACH_IO_H
 506         select USB_EHCI_BIG_ENDIAN_DESC
 507         select USB_EHCI_BIG_ENDIAN_MMIO
 508         help
 509           Support for Intel's IXP4XX (XScale) family of processors.
 510
 511 config ARCH_DOVE
 512         bool "Marvell Dove"
 513         select ARCH_REQUIRE_GPIOLIB
 514         select CPU_PJ4
 515         select GENERIC_CLOCKEVENTS
 516         select MIGHT_HAVE_PCI
 517         select MVEBU_MBUS
 518         select PINCTRL
 519         select PINCTRL_DOVE
 520         select PLAT_ORION_LEGACY
 521         help
 522           Support for the Marvell Dove SoC 88AP510
 523
 524 config ARCH_MV78XX0
 525         bool "Marvell MV78xx0"
 526         select ARCH_REQUIRE_GPIOLIB
 527         select CPU_FEROCEON
 528         select GENERIC_CLOCKEVENTS
 529         select MVEBU_MBUS
 530         select PCI
 531         select PLAT_ORION_LEGACY
 532         help
 533           Support for the following Marvell MV78xx0 series SoCs:
 534           MV781x0, MV782x0.
 535
 536 config ARCH_ORION5X
 537         bool "Marvell Orion"
 538         depends on MMU
 539         select ARCH_REQUIRE_GPIOLIB
 540         select CPU_FEROCEON
 541         select GENERIC_CLOCKEVENTS
 542         select MVEBU_MBUS
 543         select PCI
 544         select PLAT_ORION_LEGACY
 545         select MULTI_IRQ_HANDLER
 546         help
 547           Support for the following Marvell Orion 5x series SoCs:
 548           Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
 549           Orion-2 (5281), Orion-1-90 (6183).
 550
 551 config ARCH_MMP
 552         bool "Marvell PXA168/910/MMP2"
 553         depends on MMU
 554         select ARCH_REQUIRE_GPIOLIB
 555         select CLKDEV_LOOKUP
 556         select GENERIC_ALLOCATOR
 557         select GENERIC_CLOCKEVENTS
 558         select GPIO_PXA
 559         select IRQ_DOMAIN
 560         select MULTI_IRQ_HANDLER
 561         select PINCTRL
 562         select PLAT_PXA
 563         select SPARSE_IRQ
 564         help
 565           Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
 566
 567 config ARCH_KS8695
 568         bool "Micrel/Kendin KS8695"
 569         select ARCH_REQUIRE_GPIOLIB
 570         select CLKSRC_MMIO
 571         select CPU_ARM922T
 572         select GENERIC_CLOCKEVENTS
 573         select NEED_MACH_MEMORY_H
 574         help
 575           Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
 576           System-on-Chip devices.
 577
 578 config ARCH_W90X900
 579         bool "Nuvoton W90X900 CPU"
 580         select ARCH_REQUIRE_GPIOLIB
 581         select CLKDEV_LOOKUP
 582         select CLKSRC_MMIO
 583         select CPU_ARM926T
 584         select GENERIC_CLOCKEVENTS
 585         help
 586           Support for Nuvoton (Winbond logic dept.) ARM9 processor,
 587           At present, the w90x900 has been renamed nuc900, regarding
 588           the ARM series product line, you can login the following
 589           link address to know more.
 590
 591           <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
 592                 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
 593
 594 config ARCH_LPC32XX
 595         bool "NXP LPC32XX"
 596         select ARCH_REQUIRE_GPIOLIB
 597         select ARM_AMBA
 598         select CLKDEV_LOOKUP
 599         select CLKSRC_MMIO
 600         select CPU_ARM926T
 601         select GENERIC_CLOCKEVENTS
 602         select HAVE_IDE
 603         select USE_OF
 604         help
 605           Support for the NXP LPC32XX family of processors
 606
 607 config ARCH_PXA
 608         bool "PXA2xx/PXA3xx-based"
 609         depends on MMU
 610         select ARCH_MTD_XIP
 611         select ARCH_REQUIRE_GPIOLIB
 612         select ARM_CPU_SUSPEND if PM
 613         select AUTO_ZRELADDR
 614         select COMMON_CLK
 615         select CLKDEV_LOOKUP
 616         select CLKSRC_PXA
 617         select CLKSRC_MMIO
 618         select CLKSRC_OF
 619         select GENERIC_CLOCKEVENTS
 620         select GPIO_PXA
 621         select HAVE_IDE
 622         select IRQ_DOMAIN
 623         select MULTI_IRQ_HANDLER
 624         select PLAT_PXA
 625         select SPARSE_IRQ
 626         help
 627           Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
 628
 629 config ARCH_RPC
 630         bool "RiscPC"
 631         depends on MMU
 632         select ARCH_ACORN
 633         select ARCH_MAY_HAVE_PC_FDC
 634         select ARCH_SPARSEMEM_ENABLE
 635         select ARCH_USES_GETTIMEOFFSET
 636         select CPU_SA110
 637         select FIQ
 638         select HAVE_IDE
 639         select HAVE_PATA_PLATFORM
 640         select ISA_DMA_API
 641         select NEED_MACH_IO_H
 642         select NEED_MACH_MEMORY_H
 643         select NO_IOPORT_MAP
 644         select VIRT_TO_BUS
 645         help
 646           On the Acorn Risc-PC, Linux can support the internal IDE disk and
 647           CD-ROM interface, serial and parallel port, and the floppy drive.
 648
 649 config ARCH_SA1100
 650         bool "SA1100-based"
 651         select ARCH_MTD_XIP
 652         select ARCH_REQUIRE_GPIOLIB
 653         select ARCH_SPARSEMEM_ENABLE
 654         select CLKDEV_LOOKUP
 655         select CLKSRC_MMIO
 656         select CLKSRC_PXA
 657         select CLKSRC_OF if OF
 658         select CPU_FREQ
 659         select CPU_SA1100
 660         select GENERIC_CLOCKEVENTS
 661         select HAVE_IDE
 662         select IRQ_DOMAIN
 663         select ISA
 664         select MULTI_IRQ_HANDLER
 665         select NEED_MACH_MEMORY_H
 666         select SPARSE_IRQ
 667         help
 668           Support for StrongARM 11x0 based boards.
 669
 670 config ARCH_S3C24XX
 671         bool "Samsung S3C24XX SoCs"
 672         select ARCH_REQUIRE_GPIOLIB
 673         select ATAGS
 674         select CLKDEV_LOOKUP
 675         select CLKSRC_SAMSUNG_PWM
 676         select GENERIC_CLOCKEVENTS
 677         select GPIO_SAMSUNG
 678         select HAVE_S3C2410_I2C if I2C
 679         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 680         select HAVE_S3C_RTC if RTC_CLASS
 681         select MULTI_IRQ_HANDLER
 682         select NEED_MACH_IO_H
 683         select SAMSUNG_ATAGS
 684         help
 685           Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
 686           and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
 687           (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
 688           Samsung SMDK2410 development board (and derivatives).
 689
 690 config ARCH_S3C64XX
 691         bool "Samsung S3C64XX"
 692         select ARCH_REQUIRE_GPIOLIB
 693         select ARM_AMBA
 694         select ARM_VIC
 695         select ATAGS
 696         select CLKDEV_LOOKUP
 697         select CLKSRC_SAMSUNG_PWM
 698         select COMMON_CLK_SAMSUNG
 699         select CPU_V6K
 700         select GENERIC_CLOCKEVENTS
 701         select GPIO_SAMSUNG
 702         select HAVE_S3C2410_I2C if I2C
 703         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 704         select HAVE_TCM
 705         select NO_IOPORT_MAP
 706         select PLAT_SAMSUNG
 707         select PM_GENERIC_DOMAINS if PM
 708         select S3C_DEV_NAND
 709         select S3C_GPIO_TRACK
 710         select SAMSUNG_ATAGS
 711         select SAMSUNG_WAKEMASK
 712         select SAMSUNG_WDT_RESET
 713         help
 714           Samsung S3C64XX series based systems
 715
 716 config ARCH_DAVINCI
 717         bool "TI DaVinci"
 718         select ARCH_HAS_HOLES_MEMORYMODEL
 719         select ARCH_REQUIRE_GPIOLIB
 720         select CLKDEV_LOOKUP
 721         select GENERIC_ALLOCATOR
 722         select GENERIC_CLOCKEVENTS
 723         select GENERIC_IRQ_CHIP
 724         select HAVE_IDE
 725         select USE_OF
 726         select ZONE_DMA
 727         help
 728           Support for TI's DaVinci platform.
 729
 730 config ARCH_OMAP1
 731         bool "TI OMAP1"
 732         depends on MMU
 733         select ARCH_HAS_HOLES_MEMORYMODEL
 734         select ARCH_OMAP
 735         select ARCH_REQUIRE_GPIOLIB
 736         select CLKDEV_LOOKUP
 737         select CLKSRC_MMIO
 738         select GENERIC_CLOCKEVENTS
 739         select GENERIC_IRQ_CHIP
 740         select HAVE_IDE
 741         select IRQ_DOMAIN
 742         select MULTI_IRQ_HANDLER
 743         select NEED_MACH_IO_H if PCCARD
 744         select NEED_MACH_MEMORY_H
 745         select SPARSE_IRQ
 746         help
 747           Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
 748
 749 endchoice
 750
 751 menu "Multiple platform selection"
 752         depends on ARCH_MULTIPLATFORM
 753
 754 comment "CPU Core family selection"
 755
 756 config ARCH_MULTI_V4
 757         bool "ARMv4 based platforms (FA526)"
 758         depends on !ARCH_MULTI_V6_V7
 759         select ARCH_MULTI_V4_V5
 760         select CPU_FA526
 761
 762 config ARCH_MULTI_V4T
 763         bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
 764         depends on !ARCH_MULTI_V6_V7
 765         select ARCH_MULTI_V4_V5
 766         select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
 767                 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
 768                 CPU_ARM925T || CPU_ARM940T)
 769
 770 config ARCH_MULTI_V5
 771         bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
 772         depends on !ARCH_MULTI_V6_V7
 773         select ARCH_MULTI_V4_V5
 774         select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
 775                 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
 776                 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
 777
 778 config ARCH_MULTI_V4_V5
 779         bool
 780
 781 config ARCH_MULTI_V6
 782         bool "ARMv6 based platforms (ARM11)"
 783         select ARCH_MULTI_V6_V7
 784         select CPU_V6K
 785
 786 config ARCH_MULTI_V7
 787         bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
 788         default y
 789         select ARCH_MULTI_V6_V7
 790         select CPU_V7
 791         select HAVE_SMP
 792
 793 config ARCH_MULTI_V6_V7
 794         bool
 795         select MIGHT_HAVE_CACHE_L2X0
 796
 797 config ARCH_MULTI_CPU_AUTO
 798         def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
 799         select ARCH_MULTI_V5
 800
 801 endmenu
 802
 803 config ARCH_VIRT
 804         bool "Dummy Virtual Machine" if ARCH_MULTI_V7
 805         select ARM_AMBA
 806         select ARM_GIC
 807         select ARM_GIC_V2M if PCI_MSI
 808         select ARM_GIC_V3
 809         select ARM_PSCI
 810         select HAVE_ARM_ARCH_TIMER
 811
 812 #
 813 # This is sorted alphabetically by mach-* pathname.  However, plat-*
 814 # Kconfigs may be included either alphabetically (according to the
 815 # plat- suffix) or along side the corresponding mach-* source.
 816 #
 817 source "arch/arm/mach-mvebu/Kconfig"
 818
 819 source "arch/arm/mach-alpine/Kconfig"
 820
 821 source "arch/arm/mach-asm9260/Kconfig"
 822
 823 source "arch/arm/mach-at91/Kconfig"
 824
 825 source "arch/arm/mach-axxia/Kconfig"
 826
 827 source "arch/arm/mach-bcm/Kconfig"
 828
 829 source "arch/arm/mach-berlin/Kconfig"
 830
 831 source "arch/arm/mach-clps711x/Kconfig"
 832
 833 source "arch/arm/mach-cns3xxx/Kconfig"
 834
 835 source "arch/arm/mach-davinci/Kconfig"
 836
 837 source "arch/arm/mach-digicolor/Kconfig"
 838
 839 source "arch/arm/mach-dove/Kconfig"
 840
 841 source "arch/arm/mach-ep93xx/Kconfig"
 842
 843 source "arch/arm/mach-footbridge/Kconfig"
 844
 845 source "arch/arm/mach-gemini/Kconfig"
 846
 847 source "arch/arm/mach-highbank/Kconfig"
 848
 849 source "arch/arm/mach-hisi/Kconfig"
 850
 851 source "arch/arm/mach-integrator/Kconfig"
 852
 853 source "arch/arm/mach-iop32x/Kconfig"
 854
 855 source "arch/arm/mach-iop33x/Kconfig"
 856
 857 source "arch/arm/mach-iop13xx/Kconfig"
 858
 859 source "arch/arm/mach-ixp4xx/Kconfig"
 860
 861 source "arch/arm/mach-keystone/Kconfig"
 862
 863 source "arch/arm/mach-ks8695/Kconfig"
 864
 865 source "arch/arm/mach-meson/Kconfig"
 866
 867 source "arch/arm/mach-moxart/Kconfig"
 868
 869 source "arch/arm/mach-mv78xx0/Kconfig"
 870
 871 source "arch/arm/mach-imx/Kconfig"
 872
 873 source "arch/arm/mach-mediatek/Kconfig"
 874
 875 source "arch/arm/mach-mxs/Kconfig"
 876
 877 source "arch/arm/mach-netx/Kconfig"
 878
 879 source "arch/arm/mach-nomadik/Kconfig"
 880
 881 source "arch/arm/mach-nspire/Kconfig"
 882
 883 source "arch/arm/plat-omap/Kconfig"
 884
 885 source "arch/arm/mach-omap1/Kconfig"
 886
 887 source "arch/arm/mach-omap2/Kconfig"
 888
 889 source "arch/arm/mach-orion5x/Kconfig"
 890
 891 source "arch/arm/mach-picoxcell/Kconfig"
 892
 893 source "arch/arm/mach-pxa/Kconfig"
 894 source "arch/arm/plat-pxa/Kconfig"
 895
 896 source "arch/arm/mach-mmp/Kconfig"
 897
 898 source "arch/arm/mach-qcom/Kconfig"
 899
 900 source "arch/arm/mach-realview/Kconfig"
 901
 902 source "arch/arm/mach-rockchip/Kconfig"
 903
 904 source "arch/arm/mach-sa1100/Kconfig"
 905
 906 source "arch/arm/mach-socfpga/Kconfig"
 907
 908 source "arch/arm/mach-spear/Kconfig"
 909
 910 source "arch/arm/mach-sti/Kconfig"
 911
 912 source "arch/arm/mach-s3c24xx/Kconfig"
 913
 914 source "arch/arm/mach-s3c64xx/Kconfig"
 915
 916 source "arch/arm/mach-s5pv210/Kconfig"
 917
 918 source "arch/arm/mach-exynos/Kconfig"
 919 source "arch/arm/plat-samsung/Kconfig"
 920
 921 source "arch/arm/mach-shmobile/Kconfig"
 922
 923 source "arch/arm/mach-sunxi/Kconfig"
 924
 925 source "arch/arm/mach-prima2/Kconfig"
 926
 927 source "arch/arm/mach-tegra/Kconfig"
 928
 929 source "arch/arm/mach-u300/Kconfig"
 930
 931 source "arch/arm/mach-uniphier/Kconfig"
 932
 933 source "arch/arm/mach-ux500/Kconfig"
 934
 935 source "arch/arm/mach-versatile/Kconfig"
 936
 937 source "arch/arm/mach-vexpress/Kconfig"
 938 source "arch/arm/plat-versatile/Kconfig"
 939
 940 source "arch/arm/mach-vt8500/Kconfig"
 941
 942 source "arch/arm/mach-w90x900/Kconfig"
 943
 944 source "arch/arm/mach-zx/Kconfig"
 945
 946 source "arch/arm/mach-zynq/Kconfig"
 947
 948 # ARMv7-M architecture
 949 config ARCH_EFM32
 950         bool "Energy Micro efm32"
 951         depends on ARM_SINGLE_ARMV7M
 952         select ARCH_REQUIRE_GPIOLIB
 953         help
 954           Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
 955           processors.
 956
 957 config ARCH_LPC18XX
 958         bool "NXP LPC18xx/LPC43xx"
 959         depends on ARM_SINGLE_ARMV7M
 960         select ARCH_HAS_RESET_CONTROLLER
 961         select ARM_AMBA
 962         select CLKSRC_LPC32XX
 963         select PINCTRL
 964         help
 965           Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
 966           high performance microcontrollers.
 967
 968 config ARCH_STM32
 969         bool "STMicrolectronics STM32"
 970         depends on ARM_SINGLE_ARMV7M
 971         select ARCH_HAS_RESET_CONTROLLER
 972         select ARMV7M_SYSTICK
 973         select CLKSRC_STM32
 974         select RESET_CONTROLLER
 975         help
 976           Support for STMicroelectronics STM32 processors.
 977
 978 # Definitions to make life easier
 979 config ARCH_ACORN
 980         bool
 981
 982 config PLAT_IOP
 983         bool
 984         select GENERIC_CLOCKEVENTS
 985
 986 config PLAT_ORION
 987         bool
 988         select CLKSRC_MMIO
 989         select COMMON_CLK
 990         select GENERIC_IRQ_CHIP
 991         select IRQ_DOMAIN
 992
 993 config PLAT_ORION_LEGACY
 994         bool
 995         select PLAT_ORION
 996
 997 config PLAT_PXA
 998         bool
 999
1000 config PLAT_VERSATILE
1001         bool
1002
1003 source "arch/arm/firmware/Kconfig"
1004
1005 source arch/arm/mm/Kconfig
1006
1007 config IWMMXT
1008         bool "Enable iWMMXt support"
1009         depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
1010         default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
1011         help
1012           Enable support for iWMMXt context switching at run time if
1013           running on a CPU that supports it.
1014
1015 config MULTI_IRQ_HANDLER
1016         bool
1017         help
1018           Allow each machine to specify it's own IRQ handler at run time.
1019
1020 if !MMU
1021 source "arch/arm/Kconfig-nommu"
1022 endif
1023
1024 config PJ4B_ERRATA_4742
1025         bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1026         depends on CPU_PJ4B && MACH_ARMADA_370
1027         default y
1028         help
1029           When coming out of either a Wait for Interrupt (WFI) or a Wait for
1030           Event (WFE) IDLE states, a specific timing sensitivity exists between
1031           the retiring WFI/WFE instructions and the newly issued subsequent
1032           instructions.  This sensitivity can result in a CPU hang scenario.
1033           Workaround:
1034           The software must insert either a Data Synchronization Barrier (DSB)
1035           or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1036           instruction
1037
1038 config ARM_ERRATA_326103
1039         bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1040         depends on CPU_V6
1041         help
1042           Executing a SWP instruction to read-only memory does not set bit 11
1043           of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1044           treat the access as a read, preventing a COW from occurring and
1045           causing the faulting task to livelock.
1046
1047 config ARM_ERRATA_411920
1048         bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1049         depends on CPU_V6 || CPU_V6K
1050         help
1051           Invalidation of the Instruction Cache operation can
1052           fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1053           It does not affect the MPCore. This option enables the ARM Ltd.
1054           recommended workaround.
1055
1056 config ARM_ERRATA_430973
1057         bool "ARM errata: Stale prediction on replaced interworking branch"
1058         depends on CPU_V7
1059         help
1060           This option enables the workaround for the 430973 Cortex-A8
1061           r1p* erratum. If a code sequence containing an ARM/Thumb
1062           interworking branch is replaced with another code sequence at the
1063           same virtual address, whether due to self-modifying code or virtual
1064           to physical address re-mapping, Cortex-A8 does not recover from the
1065           stale interworking branch prediction. This results in Cortex-A8
1066           executing the new code sequence in the incorrect ARM or Thumb state.
1067           The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1068           and also flushes the branch target cache at every context switch.
1069           Note that setting specific bits in the ACTLR register may not be
1070           available in non-secure mode.
1071
1072 config ARM_ERRATA_458693
1073         bool "ARM errata: Processor deadlock when a false hazard is created"
1074         depends on CPU_V7
1075         depends on !ARCH_MULTIPLATFORM
1076         help
1077           This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1078           erratum. For very specific sequences of memory operations, it is
1079           possible for a hazard condition intended for a cache line to instead
1080           be incorrectly associated with a different cache line. This false
1081           hazard might then cause a processor deadlock. The workaround enables
1082           the L1 caching of the NEON accesses and disables the PLD instruction
1083           in the ACTLR register. Note that setting specific bits in the ACTLR
1084           register may not be available in non-secure mode.
1085
1086 config ARM_ERRATA_460075
1087         bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1088         depends on CPU_V7
1089         depends on !ARCH_MULTIPLATFORM
1090         help
1091           This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1092           erratum. Any asynchronous access to the L2 cache may encounter a
1093           situation in which recent store transactions to the L2 cache are lost
1094           and overwritten with stale memory contents from external memory. The
1095           workaround disables the write-allocate mode for the L2 cache via the
1096           ACTLR register. Note that setting specific bits in the ACTLR register
1097           may not be available in non-secure mode.
1098
1099 config ARM_ERRATA_742230
1100         bool "ARM errata: DMB operation may be faulty"
1101         depends on CPU_V7 && SMP
1102         depends on !ARCH_MULTIPLATFORM
1103         help
1104           This option enables the workaround for the 742230 Cortex-A9
1105           (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1106           between two write operations may not ensure the correct visibility
1107           ordering of the two writes. This workaround sets a specific bit in
1108           the diagnostic register of the Cortex-A9 which causes the DMB
1109           instruction to behave as a DSB, ensuring the correct behaviour of
1110           the two writes.
1111
1112 config ARM_ERRATA_742231
1113         bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1114         depends on CPU_V7 && SMP
1115         depends on !ARCH_MULTIPLATFORM
1116         help
1117           This option enables the workaround for the 742231 Cortex-A9
1118           (r2p0..r2p2) erratum. Under certain conditions, specific to the
1119           Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1120           accessing some data located in the same cache line, may get corrupted
1121           data due to bad handling of the address hazard when the line gets
1122           replaced from one of the CPUs at the same time as another CPU is
1123           accessing it. This workaround sets specific bits in the diagnostic
1124           register of the Cortex-A9 which reduces the linefill issuing
1125           capabilities of the processor.
1126
1127 config ARM_ERRATA_643719
1128         bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1129         depends on CPU_V7 && SMP
1130         default y
1131         help
1132           This option enables the workaround for the 643719 Cortex-A9 (prior to
1133           r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1134           register returns zero when it should return one. The workaround
1135           corrects this value, ensuring cache maintenance operations which use
1136           it behave as intended and avoiding data corruption.
1137
1138 config ARM_ERRATA_720789
1139         bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1140         depends on CPU_V7
1141         help
1142           This option enables the workaround for the 720789 Cortex-A9 (prior to
1143           r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1144           broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1145           As a consequence of this erratum, some TLB entries which should be
1146           invalidated are not, resulting in an incoherency in the system page
1147           tables. The workaround changes the TLB flushing routines to invalidate
1148           entries regardless of the ASID.
1149
1150 config ARM_ERRATA_743622
1151         bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1152         depends on CPU_V7
1153         depends on !ARCH_MULTIPLATFORM
1154         help
1155           This option enables the workaround for the 743622 Cortex-A9
1156           (r2p*) erratum. Under very rare conditions, a faulty
1157           optimisation in the Cortex-A9 Store Buffer may lead to data
1158           corruption. This workaround sets a specific bit in the diagnostic
1159           register of the Cortex-A9 which disables the Store Buffer
1160           optimisation, preventing the defect from occurring. This has no
1161           visible impact on the overall performance or power consumption of the
1162           processor.
1163
1164 config ARM_ERRATA_751472
1165         bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1166         depends on CPU_V7
1167         depends on !ARCH_MULTIPLATFORM
1168         help
1169           This option enables the workaround for the 751472 Cortex-A9 (prior
1170           to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1171           completion of a following broadcasted operation if the second
1172           operation is received by a CPU before the ICIALLUIS has completed,
1173           potentially leading to corrupted entries in the cache or TLB.
1174
1175 config ARM_ERRATA_754322
1176         bool "ARM errata: possible faulty MMU translations following an ASID switch"
1177         depends on CPU_V7
1178         help
1179           This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1180           r3p*) erratum. A speculative memory access may cause a page table walk
1181           which starts prior to an ASID switch but completes afterwards. This
1182           can populate the micro-TLB with a stale entry which may be hit with
1183           the new ASID. This workaround places two dsb instructions in the mm
1184           switching code so that no page table walks can cross the ASID switch.
1185
1186 config ARM_ERRATA_754327
1187         bool "ARM errata: no automatic Store Buffer drain"
1188         depends on CPU_V7 && SMP
1189         help
1190           This option enables the workaround for the 754327 Cortex-A9 (prior to
1191           r2p0) erratum. The Store Buffer does not have any automatic draining
1192           mechanism and therefore a livelock may occur if an external agent
1193           continuously polls a memory location waiting to observe an update.
1194           This workaround defines cpu_relax() as smp_mb(), preventing correctly
1195           written polling loops from denying visibility of updates to memory.
1196
1197 config ARM_ERRATA_364296
1198         bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1199         depends on CPU_V6
1200         help
1201           This options enables the workaround for the 364296 ARM1136
1202           r0p2 erratum (possible cache data corruption with
1203           hit-under-miss enabled). It sets the undocumented bit 31 in
1204           the auxiliary control register and the FI bit in the control
1205           register, thus disabling hit-under-miss without putting the
1206           processor into full low interrupt latency mode. ARM11MPCore
1207           is not affected.
1208
1209 config ARM_ERRATA_764369
1210         bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1211         depends on CPU_V7 && SMP
1212         help
1213           This option enables the workaround for erratum 764369
1214           affecting Cortex-A9 MPCore with two or more processors (all
1215           current revisions). Under certain timing circumstances, a data
1216           cache line maintenance operation by MVA targeting an Inner
1217           Shareable memory region may fail to proceed up to either the
1218           Point of Coherency or to the Point of Unification of the
1219           system. This workaround adds a DSB instruction before the
1220           relevant cache maintenance functions and sets a specific bit
1221           in the diagnostic control register of the SCU.
1222
1223 config ARM_ERRATA_775420
1224        bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1225        depends on CPU_V7
1226        help
1227          This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1228          r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1229          operation aborts with MMU exception, it might cause the processor
1230          to deadlock. This workaround puts DSB before executing ISB if
1231          an abort may occur on cache maintenance.
1232
1233 config ARM_ERRATA_798181
1234         bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1235         depends on CPU_V7 && SMP
1236         help
1237           On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1238           adequately shooting down all use of the old entries. This
1239           option enables the Linux kernel workaround for this erratum
1240           which sends an IPI to the CPUs that are running the same ASID
1241           as the one being invalidated.
1242
1243 config ARM_ERRATA_773022
1244         bool "ARM errata: incorrect instructions may be executed from loop buffer"
1245         depends on CPU_V7
1246         help
1247           This option enables the workaround for the 773022 Cortex-A15
1248           (up to r0p4) erratum. In certain rare sequences of code, the
1249           loop buffer may deliver incorrect instructions. This
1250           workaround disables the loop buffer to avoid the erratum.
1251
1252 endmenu
1253
1254 source "arch/arm/common/Kconfig"
1255
1256 menu "Bus support"
1257
1258 config ISA
1259         bool
1260         help
1261           Find out whether you have ISA slots on your motherboard.  ISA is the
1262           name of a bus system, i.e. the way the CPU talks to the other stuff
1263           inside your box.  Other bus systems are PCI, EISA, MicroChannel
1264           (MCA) or VESA.  ISA is an older system, now being displaced by PCI;
1265           newer boards don't support it.  If you have ISA, say Y, otherwise N.
1266
1267 # Select ISA DMA controller support
1268 config ISA_DMA
1269         bool
1270         select ISA_DMA_API
1271
1272 # Select ISA DMA interface
1273 config ISA_DMA_API
1274         bool
1275
1276 config PCI
1277         bool "PCI support" if MIGHT_HAVE_PCI
1278         help
1279           Find out whether you have a PCI motherboard. PCI is the name of a
1280           bus system, i.e. the way the CPU talks to the other stuff inside
1281           your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1282           VESA. If you have PCI, say Y, otherwise N.
1283
1284 config PCI_DOMAINS
1285         bool
1286         depends on PCI
1287
1288 config PCI_DOMAINS_GENERIC
1289         def_bool PCI_DOMAINS
1290
1291 config PCI_NANOENGINE
1292         bool "BSE nanoEngine PCI support"
1293         depends on SA1100_NANOENGINE
1294         help
1295           Enable PCI on the BSE nanoEngine board.
1296
1297 config PCI_SYSCALL
1298         def_bool PCI
1299
1300 config PCI_HOST_ITE8152
1301         bool
1302         depends on PCI && MACH_ARMCORE
1303         default y
1304         select DMABOUNCE
1305
1306 source "drivers/pci/Kconfig"
1307 source "drivers/pci/pcie/Kconfig"
1308
1309 source "drivers/pcmcia/Kconfig"
1310
1311 endmenu
1312
1313 menu "Kernel Features"
1314
1315 config HAVE_SMP
1316         bool
1317         help
1318           This option should be selected by machines which have an SMP-
1319           capable CPU.
1320
1321           The only effect of this option is to make the SMP-related
1322           options available to the user for configuration.
1323
1324 config SMP
1325         bool "Symmetric Multi-Processing"
1326         depends on CPU_V6K || CPU_V7
1327         depends on GENERIC_CLOCKEVENTS
1328         depends on HAVE_SMP
1329         depends on MMU || ARM_MPU
1330         select IRQ_WORK
1331         help
1332           This enables support for systems with more than one CPU. If you have
1333           a system with only one CPU, say N. If you have a system with more
1334           than one CPU, say Y.
1335
1336           If you say N here, the kernel will run on uni- and multiprocessor
1337           machines, but will use only one CPU of a multiprocessor machine. If
1338           you say Y here, the kernel will run on many, but not all,
1339           uniprocessor machines. On a uniprocessor machine, the kernel
1340           will run faster if you say N here.
1341
1342           See also <file:Documentation/x86/i386/IO-APIC.txt>,
1343           <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1344           <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1345
1346           If you don't know what to do here, say N.
1347
1348 config SMP_ON_UP
1349         bool "Allow booting SMP kernel on uniprocessor systems"
1350         depends on SMP && !XIP_KERNEL && MMU
1351         default y
1352         help
1353           SMP kernels contain instructions which fail on non-SMP processors.
1354           Enabling this option allows the kernel to modify itself to make
1355           these instructions safe.  Disabling it allows about 1K of space
1356           savings.
1357
1358           If you don't know what to do here, say Y.
1359
1360 config ARM_CPU_TOPOLOGY
1361         bool "Support cpu topology definition"
1362         depends on SMP && CPU_V7
1363         default y
1364         help
1365           Support ARM cpu topology definition. The MPIDR register defines
1366           affinity between processors which is then used to describe the cpu
1367           topology of an ARM System.
1368
1369 config SCHED_MC
1370         bool "Multi-core scheduler support"
1371         depends on ARM_CPU_TOPOLOGY
1372         help
1373           Multi-core scheduler support improves the CPU scheduler's decision
1374           making when dealing with multi-core CPU chips at a cost of slightly
1375           increased overhead in some places. If unsure say N here.
1376
1377 config SCHED_SMT
1378         bool "SMT scheduler support"
1379         depends on ARM_CPU_TOPOLOGY
1380         help
1381           Improves the CPU scheduler's decision making when dealing with
1382           MultiThreading at a cost of slightly increased overhead in some
1383           places. If unsure say N here.
1384
1385 config HAVE_ARM_SCU
1386         bool
1387         help
1388           This option enables support for the ARM system coherency unit
1389
1390 config HAVE_ARM_ARCH_TIMER
1391         bool "Architected timer support"
1392         depends on CPU_V7
1393         select ARM_ARCH_TIMER
1394         select GENERIC_CLOCKEVENTS
1395         help
1396           This option enables support for the ARM architected timer
1397
1398 config HAVE_ARM_TWD
1399         bool
1400         select CLKSRC_OF if OF
1401         help
1402           This options enables support for the ARM timer and watchdog unit
1403
1404 config MCPM
1405         bool "Multi-Cluster Power Management"
1406         depends on CPU_V7 && SMP
1407         help
1408           This option provides the common power management infrastructure
1409           for (multi-)cluster based systems, such as big.LITTLE based
1410           systems.
1411
1412 config MCPM_QUAD_CLUSTER
1413         bool
1414         depends on MCPM
1415         help
1416           To avoid wasting resources unnecessarily, MCPM only supports up
1417           to 2 clusters by default.
1418           Platforms with 3 or 4 clusters that use MCPM must select this
1419           option to allow the additional clusters to be managed.
1420
1421 config BIG_LITTLE
1422         bool "big.LITTLE support (Experimental)"
1423         depends on CPU_V7 && SMP
1424         select MCPM
1425         help
1426           This option enables support selections for the big.LITTLE
1427           system architecture.
1428
1429 config BL_SWITCHER
1430         bool "big.LITTLE switcher support"
1431         depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1432         select ARM_CPU_SUSPEND
1433         select CPU_PM
1434         help
1435           The big.LITTLE "switcher" provides the core functionality to
1436           transparently handle transition between a cluster of A15's
1437           and a cluster of A7's in a big.LITTLE system.
1438
1439 config BL_SWITCHER_DUMMY_IF
1440         tristate "Simple big.LITTLE switcher user interface"
1441         depends on BL_SWITCHER && DEBUG_KERNEL
1442         help
1443           This is a simple and dummy char dev interface to control
1444           the big.LITTLE switcher core code.  It is meant for
1445           debugging purposes only.
1446
1447 choice
1448         prompt "Memory split"
1449         depends on MMU
1450         default VMSPLIT_3G
1451         help
1452           Select the desired split between kernel and user memory.
1453
1454           If you are not absolutely sure what you are doing, leave this
1455           option alone!
1456
1457         config VMSPLIT_3G
1458                 bool "3G/1G user/kernel split"
1459         config VMSPLIT_3G_OPT
1460                 bool "3G/1G user/kernel split (for full 1G low memory)"
1461         config VMSPLIT_2G
1462                 bool "2G/2G user/kernel split"
1463         config VMSPLIT_1G
1464                 bool "1G/3G user/kernel split"
1465 endchoice
1466
1467 config PAGE_OFFSET
1468         hex
1469         default PHYS_OFFSET if !MMU
1470         default 0x40000000 if VMSPLIT_1G
1471         default 0x80000000 if VMSPLIT_2G
1472         default 0xB0000000 if VMSPLIT_3G_OPT
1473         default 0xC0000000
1474
1475 config NR_CPUS
1476         int "Maximum number of CPUs (2-32)"
1477         range 2 32
1478         depends on SMP
1479         default "4"
1480
1481 config HOTPLUG_CPU
1482         bool "Support for hot-pluggable CPUs"
1483         depends on SMP
1484         help
1485           Say Y here to experiment with turning CPUs off and on.  CPUs
1486           can be controlled through /sys/devices/system/cpu.
1487
1488 config ARM_PSCI
1489         bool "Support for the ARM Power State Coordination Interface (PSCI)"
1490         depends on HAVE_ARM_SMCCC
1491         select ARM_PSCI_FW
1492         help
1493           Say Y here if you want Linux to communicate with system firmware
1494           implementing the PSCI specification for CPU-centric power
1495           management operations described in ARM document number ARM DEN
1496           0022A ("Power State Coordination Interface System Software on
1497           ARM processors").
1498
1499 # The GPIO number here must be sorted by descending number. In case of
1500 # a multiplatform kernel, we just want the highest value required by the
1501 # selected platforms.
1502 config ARCH_NR_GPIO
1503         int
1504         default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \
1505                 ARCH_ZYNQ
1506         default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1507                 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1508         default 416 if ARCH_SUNXI
1509         default 392 if ARCH_U8500
1510         default 352 if ARCH_VT8500
1511         default 288 if ARCH_ROCKCHIP
1512         default 264 if MACH_H4700
1513         default 0
1514         help
1515           Maximum number of GPIOs in the system.
1516
1517           If unsure, leave the default value.
1518
1519 source kernel/Kconfig.preempt
1520
1521 config HZ_FIXED
1522         int
1523         default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1524                 ARCH_S5PV210 || ARCH_EXYNOS4
1525         default 128 if SOC_AT91RM9200
1526         default 0
1527
1528 choice
1529         depends on HZ_FIXED = 0
1530         prompt "Timer frequency"
1531
1532 config HZ_100
1533         bool "100 Hz"
1534
1535 config HZ_200
1536         bool "200 Hz"
1537
1538 config HZ_250
1539         bool "250 Hz"
1540
1541 config HZ_300
1542         bool "300 Hz"
1543
1544 config HZ_500
1545         bool "500 Hz"
1546
1547 config HZ_1000
1548         bool "1000 Hz"
1549
1550 endchoice
1551
1552 config HZ
1553         int
1554         default HZ_FIXED if HZ_FIXED != 0
1555         default 100 if HZ_100
1556         default 200 if HZ_200
1557         default 250 if HZ_250
1558         default 300 if HZ_300
1559         default 500 if HZ_500
1560         default 1000
1561
1562 config SCHED_HRTICK
1563         def_bool HIGH_RES_TIMERS
1564
1565 config THUMB2_KERNEL
1566         bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1567         depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1568         default y if CPU_THUMBONLY
1569         select AEABI
1570         select ARM_ASM_UNIFIED
1571         select ARM_UNWIND
1572         help
1573           By enabling this option, the kernel will be compiled in
1574           Thumb-2 mode. A compiler/assembler that understand the unified
1575           ARM-Thumb syntax is needed.
1576
1577           If unsure, say N.
1578
1579 config THUMB2_AVOID_R_ARM_THM_JUMP11
1580         bool "Work around buggy Thumb-2 short branch relocations in gas"
1581         depends on THUMB2_KERNEL && MODULES
1582         default y
1583         help
1584           Various binutils versions can resolve Thumb-2 branches to
1585           locally-defined, preemptible global symbols as short-range "b.n"
1586           branch instructions.
1587
1588           This is a problem, because there's no guarantee the final
1589           destination of the symbol, or any candidate locations for a
1590           trampoline, are within range of the branch.  For this reason, the
1591           kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1592           relocation in modules at all, and it makes little sense to add
1593           support.
1594
1595           The symptom is that the kernel fails with an "unsupported
1596           relocation" error when loading some modules.
1597
1598           Until fixed tools are available, passing
1599           -fno-optimize-sibling-calls to gcc should prevent gcc generating
1600           code which hits this problem, at the cost of a bit of extra runtime
1601           stack usage in some cases.
1602
1603           The problem is described in more detail at:
1604               https://bugs.launchpad.net/binutils-linaro/+bug/725126
1605
1606           Only Thumb-2 kernels are affected.
1607
1608           Unless you are sure your tools don't have this problem, say Y.
1609
1610 config ARM_ASM_UNIFIED
1611         bool
1612
1613 config ARM_PATCH_IDIV
1614         bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1615         depends on CPU_32v7 && !XIP_KERNEL
1616         default y
1617         help
1618           The ARM compiler inserts calls to __aeabi_idiv() and
1619           __aeabi_uidiv() when it needs to perform division on signed
1620           and unsigned integers. Some v7 CPUs have support for the sdiv
1621           and udiv instructions that can be used to implement those
1622           functions.
1623
1624           Enabling this option allows the kernel to modify itself to
1625           replace the first two instructions of these library functions
1626           with the sdiv or udiv plus "bx lr" instructions when the CPU
1627           it is running on supports them. Typically this will be faster
1628           and less power intensive than running the original library
1629           code to do integer division.
1630
1631 config AEABI
1632         bool "Use the ARM EABI to compile the kernel"
1633         help
1634           This option allows for the kernel to be compiled using the latest
1635           ARM ABI (aka EABI).  This is only useful if you are using a user
1636           space environment that is also compiled with EABI.
1637
1638           Since there are major incompatibilities between the legacy ABI and
1639           EABI, especially with regard to structure member alignment, this
1640           option also changes the kernel syscall calling convention to
1641           disambiguate both ABIs and allow for backward compatibility support
1642           (selected with CONFIG_OABI_COMPAT).
1643
1644           To use this you need GCC version 4.0.0 or later.
1645
1646 config OABI_COMPAT
1647         bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1648         depends on AEABI && !THUMB2_KERNEL
1649         help
1650           This option preserves the old syscall interface along with the
1651           new (ARM EABI) one. It also provides a compatibility layer to
1652           intercept syscalls that have structure arguments which layout
1653           in memory differs between the legacy ABI and the new ARM EABI
1654           (only for non "thumb" binaries). This option adds a tiny
1655           overhead to all syscalls and produces a slightly larger kernel.
1656
1657           The seccomp filter system will not be available when this is
1658           selected, since there is no way yet to sensibly distinguish
1659           between calling conventions during filtering.
1660
1661           If you know you'll be using only pure EABI user space then you
1662           can say N here. If this option is not selected and you attempt
1663           to execute a legacy ABI binary then the result will be
1664           UNPREDICTABLE (in fact it can be predicted that it won't work
1665           at all). If in doubt say N.
1666
1667 config ARCH_HAS_HOLES_MEMORYMODEL
1668         bool
1669
1670 config ARCH_SPARSEMEM_ENABLE
1671         bool
1672
1673 config ARCH_SPARSEMEM_DEFAULT
1674         def_bool ARCH_SPARSEMEM_ENABLE
1675
1676 config ARCH_SELECT_MEMORY_MODEL
1677         def_bool ARCH_SPARSEMEM_ENABLE
1678
1679 config HAVE_ARCH_PFN_VALID
1680         def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1681
1682 config HAVE_GENERIC_RCU_GUP
1683         def_bool y
1684         depends on ARM_LPAE
1685
1686 config HIGHMEM
1687         bool "High Memory Support"
1688         depends on MMU
1689         help
1690           The address space of ARM processors is only 4 Gigabytes large
1691           and it has to accommodate user address space, kernel address
1692           space as well as some memory mapped IO. That means that, if you
1693           have a large amount of physical memory and/or IO, not all of the
1694           memory can be "permanently mapped" by the kernel. The physical
1695           memory that is not permanently mapped is called "high memory".
1696
1697           Depending on the selected kernel/user memory split, minimum
1698           vmalloc space and actual amount of RAM, you may not need this
1699           option which should result in a slightly faster kernel.
1700
1701           If unsure, say n.
1702
1703 config HIGHPTE
1704         bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1705         depends on HIGHMEM
1706         default y
1707         help
1708           The VM uses one page of physical memory for each page table.
1709           For systems with a lot of processes, this can use a lot of
1710           precious low memory, eventually leading to low memory being
1711           consumed by page tables.  Setting this option will allow
1712           user-space 2nd level page tables to reside in high memory.
1713
1714 config CPU_SW_DOMAIN_PAN
1715         bool "Enable use of CPU domains to implement privileged no-access"
1716         depends on MMU && !ARM_LPAE
1717         default y
1718         help
1719           Increase kernel security by ensuring that normal kernel accesses
1720           are unable to access userspace addresses.  This can help prevent
1721           use-after-free bugs becoming an exploitable privilege escalation
1722           by ensuring that magic values (such as LIST_POISON) will always
1723           fault when dereferenced.
1724
1725           CPUs with low-vector mappings use a best-efforts implementation.
1726           Their lower 1MB needs to remain accessible for the vectors, but
1727           the remainder of userspace will become appropriately inaccessible.
1728
1729 config HW_PERF_EVENTS
1730         def_bool y
1731         depends on ARM_PMU
1732
1733 config SYS_SUPPORTS_HUGETLBFS
1734        def_bool y
1735        depends on ARM_LPAE
1736
1737 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1738        def_bool y
1739        depends on ARM_LPAE
1740
1741 config ARCH_WANT_GENERAL_HUGETLB
1742         def_bool y
1743
1744 config ARM_MODULE_PLTS
1745         bool "Use PLTs to allow module memory to spill over into vmalloc area"
1746         depends on MODULES
1747         help
1748           Allocate PLTs when loading modules so that jumps and calls whose
1749           targets are too far away for their relative offsets to be encoded
1750           in the instructions themselves can be bounced via veneers in the
1751           module's PLT. This allows modules to be allocated in the generic
1752           vmalloc area after the dedicated module memory area has been
1753           exhausted. The modules will use slightly more memory, but after
1754           rounding up to page size, the actual memory footprint is usually
1755           the same.
1756
1757           Say y if you are getting out of memory errors while loading modules
1758
1759 source "mm/Kconfig"
1760
1761 config FORCE_MAX_ZONEORDER
1762         int "Maximum zone order"
1763         default "12" if SOC_AM33XX
1764         default "9" if SA1111 || ARCH_EFM32
1765         default "11"
1766         help
1767           The kernel memory allocator divides physically contiguous memory
1768           blocks into "zones", where each zone is a power of two number of
1769           pages.  This option selects the largest power of two that the kernel
1770           keeps in the memory allocator.  If you need to allocate very large
1771           blocks of physically contiguous memory, then you may need to
1772           increase this value.
1773
1774           This config option is actually maximum order plus one. For example,
1775           a value of 11 means that the largest free memory block is 2^10 pages.
1776
1777 config ALIGNMENT_TRAP
1778         bool
1779         depends on CPU_CP15_MMU
1780         default y if !ARCH_EBSA110
1781         select HAVE_PROC_CPU if PROC_FS
1782         help
1783           ARM processors cannot fetch/store information which is not
1784           naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1785           address divisible by 4. On 32-bit ARM processors, these non-aligned
1786           fetch/store instructions will be emulated in software if you say
1787           here, which has a severe performance impact. This is necessary for
1788           correct operation of some network protocols. With an IP-only
1789           configuration it is safe to say N, otherwise say Y.
1790
1791 config UACCESS_WITH_MEMCPY
1792         bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1793         depends on MMU
1794         default y if CPU_FEROCEON
1795         help
1796           Implement faster copy_to_user and clear_user methods for CPU
1797           cores where a 8-word STM instruction give significantly higher
1798           memory write throughput than a sequence of individual 32bit stores.
1799
1800           A possible side effect is a slight increase in scheduling latency
1801           between threads sharing the same address space if they invoke
1802           such copy operations with large buffers.
1803
1804           However, if the CPU data cache is using a write-allocate mode,
1805           this option is unlikely to provide any performance gain.
1806
1807 config SECCOMP
1808         bool
1809         prompt "Enable seccomp to safely compute untrusted bytecode"
1810         ---help---
1811           This kernel feature is useful for number crunching applications
1812           that may need to compute untrusted bytecode during their
1813           execution. By using pipes or other transports made available to
1814           the process as file descriptors supporting the read/write
1815           syscalls, it's possible to isolate those applications in
1816           their own address space using seccomp. Once seccomp is
1817           enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1818           and the task is only allowed to execute a few safe syscalls
1819           defined by each seccomp mode.
1820
1821 config SWIOTLB
1822         def_bool y
1823
1824 config IOMMU_HELPER
1825         def_bool SWIOTLB
1826
1827 config PARAVIRT
1828         bool "Enable paravirtualization code"
1829         help
1830           This changes the kernel so it can modify itself when it is run
1831           under a hypervisor, potentially improving performance significantly
1832           over full virtualization.
1833
1834 config PARAVIRT_TIME_ACCOUNTING
1835         bool "Paravirtual steal time accounting"
1836         select PARAVIRT
1837         default n
1838         help
1839           Select this option to enable fine granularity task steal time
1840           accounting. Time spent executing other tasks in parallel with
1841           the current vCPU is discounted from the vCPU power. To account for
1842           that, there can be a small performance impact.
1843
1844           If in doubt, say N here.
1845
1846 config XEN_DOM0
1847         def_bool y
1848         depends on XEN
1849
1850 config XEN
1851         bool "Xen guest support on ARM"
1852         depends on ARM && AEABI && OF
1853         depends on CPU_V7 && !CPU_V6
1854         depends on !GENERIC_ATOMIC64
1855         depends on MMU
1856         select ARCH_DMA_ADDR_T_64BIT
1857         select ARM_PSCI
1858         select SWIOTLB_XEN
1859         select PARAVIRT
1860         help
1861           Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1862
1863 endmenu
1864
1865 menu "Boot options"
1866
1867 config USE_OF
1868         bool "Flattened Device Tree support"
1869         select IRQ_DOMAIN
1870         select OF
1871         help
1872           Include support for flattened device tree machine descriptions.
1873
1874 config ATAGS
1875         bool "Support for the traditional ATAGS boot data passing" if USE_OF
1876         default y
1877         help
1878           This is the traditional way of passing data to the kernel at boot
1879           time. If you are solely relying on the flattened device tree (or
1880           the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1881           to remove ATAGS support from your kernel binary.  If unsure,
1882           leave this to y.
1883
1884 config DEPRECATED_PARAM_STRUCT
1885         bool "Provide old way to pass kernel parameters"
1886         depends on ATAGS
1887         help
1888           This was deprecated in 2001 and announced to live on for 5 years.
1889           Some old boot loaders still use this way.
1890
1891 # Compressed boot loader in ROM.  Yes, we really want to ask about
1892 # TEXT and BSS so we preserve their values in the config files.
1893 config ZBOOT_ROM_TEXT
1894         hex "Compressed ROM boot loader base address"
1895         default "0"
1896         help
1897           The physical address at which the ROM-able zImage is to be
1898           placed in the target.  Platforms which normally make use of
1899           ROM-able zImage formats normally set this to a suitable
1900           value in their defconfig file.
1901
1902           If ZBOOT_ROM is not enabled, this has no effect.
1903
1904 config ZBOOT_ROM_BSS
1905         hex "Compressed ROM boot loader BSS address"
1906         default "0"
1907         help
1908           The base address of an area of read/write memory in the target
1909           for the ROM-able zImage which must be available while the
1910           decompressor is running. It must be large enough to hold the
1911           entire decompressed kernel plus an additional 128 KiB.
1912           Platforms which normally make use of ROM-able zImage formats
1913           normally set this to a suitable value in their defconfig file.
1914
1915           If ZBOOT_ROM is not enabled, this has no effect.
1916
1917 config ZBOOT_ROM
1918         bool "Compressed boot loader in ROM/flash"
1919         depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1920         depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1921         help
1922           Say Y here if you intend to execute your compressed kernel image
1923           (zImage) directly from ROM or flash.  If unsure, say N.
1924
1925 config ARM_APPENDED_DTB
1926         bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1927         depends on OF
1928         help
1929           With this option, the boot code will look for a device tree binary
1930           (DTB) appended to zImage
1931           (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1932
1933           This is meant as a backward compatibility convenience for those
1934           systems with a bootloader that can't be upgraded to accommodate
1935           the documented boot protocol using a device tree.
1936
1937           Beware that there is very little in terms of protection against
1938           this option being confused by leftover garbage in memory that might
1939           look like a DTB header after a reboot if no actual DTB is appended
1940           to zImage.  Do not leave this option active in a production kernel
1941           if you don't intend to always append a DTB.  Proper passing of the
1942           location into r2 of a bootloader provided DTB is always preferable
1943           to this option.
1944
1945 config ARM_ATAG_DTB_COMPAT
1946         bool "Supplement the appended DTB with traditional ATAG information"
1947         depends on ARM_APPENDED_DTB
1948         help
1949           Some old bootloaders can't be updated to a DTB capable one, yet
1950           they provide ATAGs with memory configuration, the ramdisk address,
1951           the kernel cmdline string, etc.  Such information is dynamically
1952           provided by the bootloader and can't always be stored in a static
1953           DTB.  To allow a device tree enabled kernel to be used with such
1954           bootloaders, this option allows zImage to extract the information
1955           from the ATAG list and store it at run time into the appended DTB.
1956
1957 choice
1958         prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1959         default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1960
1961 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1962         bool "Use bootloader kernel arguments if available"
1963         help
1964           Uses the command-line options passed by the boot loader instead of
1965           the device tree bootargs property. If the boot loader doesn't provide
1966           any, the device tree bootargs property will be used.
1967
1968 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1969         bool "Extend with bootloader kernel arguments"
1970         help
1971           The command-line arguments provided by the boot loader will be
1972           appended to the the device tree bootargs property.
1973
1974 endchoice
1975
1976 config CMDLINE
1977         string "Default kernel command string"
1978         default ""
1979         help
1980           On some architectures (EBSA110 and CATS), there is currently no way
1981           for the boot loader to pass arguments to the kernel. For these
1982           architectures, you should supply some command-line options at build
1983           time by entering them here. As a minimum, you should specify the
1984           memory size and the root device (e.g., mem=64M root=/dev/nfs).
1985
1986 choice
1987         prompt "Kernel command line type" if CMDLINE != ""
1988         default CMDLINE_FROM_BOOTLOADER
1989         depends on ATAGS
1990
1991 config CMDLINE_FROM_BOOTLOADER
1992         bool "Use bootloader kernel arguments if available"
1993         help
1994           Uses the command-line options passed by the boot loader. If
1995           the boot loader doesn't provide any, the default kernel command
1996           string provided in CMDLINE will be used.
1997
1998 config CMDLINE_EXTEND
1999         bool "Extend bootloader kernel arguments"
2000         help
2001           The command-line arguments provided by the boot loader will be
2002           appended to the default kernel command string.
2003
2004 config CMDLINE_FORCE
2005         bool "Always use the default kernel command string"
2006         help
2007           Always use the default kernel command string, even if the boot
2008           loader passes other arguments to the kernel.
2009           This is useful if you cannot or don't want to change the
2010           command-line options your boot loader passes to the kernel.
2011 endchoice
2012
2013 config XIP_KERNEL
2014         bool "Kernel Execute-In-Place from ROM"
2015         depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
2016         help
2017           Execute-In-Place allows the kernel to run from non-volatile storage
2018           directly addressable by the CPU, such as NOR flash. This saves RAM
2019           space since the text section of the kernel is not loaded from flash
2020           to RAM.  Read-write sections, such as the data section and stack,
2021           are still copied to RAM.  The XIP kernel is not compressed since
2022           it has to run directly from flash, so it will take more space to
2023           store it.  The flash address used to link the kernel object files,
2024           and for storing it, is configuration dependent. Therefore, if you
2025           say Y here, you must know the proper physical address where to
2026           store the kernel image depending on your own flash memory usage.
2027
2028           Also note that the make target becomes "make xipImage" rather than
2029           "make zImage" or "make Image".  The final kernel binary to put in
2030           ROM memory will be arch/arm/boot/xipImage.
2031
2032           If unsure, say N.
2033
2034 config XIP_PHYS_ADDR
2035         hex "XIP Kernel Physical Location"
2036         depends on XIP_KERNEL
2037         default "0x00080000"
2038         help
2039           This is the physical address in your flash memory the kernel will
2040           be linked for and stored to.  This address is dependent on your
2041           own flash usage.
2042
2043 config KEXEC
2044         bool "Kexec system call (EXPERIMENTAL)"
2045         depends on (!SMP || PM_SLEEP_SMP)
2046         depends on !CPU_V7M
2047         select KEXEC_CORE
2048         help
2049           kexec is a system call that implements the ability to shutdown your
2050           current kernel, and to start another kernel.  It is like a reboot
2051           but it is independent of the system firmware.   And like a reboot
2052           you can start any kernel with it, not just Linux.
2053
2054           It is an ongoing process to be certain the hardware in a machine
2055           is properly shutdown, so do not be surprised if this code does not
2056           initially work for you.
2057
2058 config ATAGS_PROC
2059         bool "Export atags in procfs"
2060         depends on ATAGS && KEXEC
2061         default y
2062         help
2063           Should the atags used to boot the kernel be exported in an "atags"
2064           file in procfs. Useful with kexec.
2065
2066 config CRASH_DUMP
2067         bool "Build kdump crash kernel (EXPERIMENTAL)"
2068         help
2069           Generate crash dump after being started by kexec. This should
2070           be normally only set in special crash dump kernels which are
2071           loaded in the main kernel with kexec-tools into a specially
2072           reserved region and then later executed after a crash by
2073           kdump/kexec. The crash dump kernel must be compiled to a
2074           memory address not used by the main kernel
2075
2076           For more details see Documentation/kdump/kdump.txt
2077
2078 config AUTO_ZRELADDR
2079         bool "Auto calculation of the decompressed kernel image address"
2080         help
2081           ZRELADDR is the physical address where the decompressed kernel
2082           image will be placed. If AUTO_ZRELADDR is selected, the address
2083           will be determined at run-time by masking the current IP with
2084           0xf8000000. This assumes the zImage being placed in the first 128MB
2085           from start of memory.
2086
2087 config EFI_STUB
2088         bool
2089
2090 config EFI
2091         bool "UEFI runtime support"
2092         depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
2093         select UCS2_STRING
2094         select EFI_PARAMS_FROM_FDT
2095         select EFI_STUB
2096         select EFI_ARMSTUB
2097         select EFI_RUNTIME_WRAPPERS
2098         ---help---
2099           This option provides support for runtime services provided
2100           by UEFI firmware (such as non-volatile variables, realtime
2101           clock, and platform reset). A UEFI stub is also provided to
2102           allow the kernel to be booted as an EFI application. This
2103           is only useful for kernels that may run on systems that have
2104           UEFI firmware.
2105
2106 endmenu
2107
2108 menu "CPU Power Management"
2109
2110 source "drivers/cpufreq/Kconfig"
2111
2112 source "drivers/cpuidle/Kconfig"
2113
2114 endmenu
2115
2116 menu "Floating point emulation"
2117
2118 comment "At least one emulation must be selected"
2119
2120 config FPE_NWFPE
2121         bool "NWFPE math emulation"
2122         depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2123         ---help---
2124           Say Y to include the NWFPE floating point emulator in the kernel.
2125           This is necessary to run most binaries. Linux does not currently
2126           support floating point hardware so you need to say Y here even if
2127           your machine has an FPA or floating point co-processor podule.
2128
2129           You may say N here if you are going to load the Acorn FPEmulator
2130           early in the bootup.
2131
2132 config FPE_NWFPE_XP
2133         bool "Support extended precision"
2134         depends on FPE_NWFPE
2135         help
2136           Say Y to include 80-bit support in the kernel floating-point
2137           emulator.  Otherwise, only 32 and 64-bit support is compiled in.
2138           Note that gcc does not generate 80-bit operations by default,
2139           so in most cases this option only enlarges the size of the
2140           floating point emulator without any good reason.
2141
2142           You almost surely want to say N here.
2143
2144 config FPE_FASTFPE
2145         bool "FastFPE math emulation (EXPERIMENTAL)"
2146         depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2147         ---help---
2148           Say Y here to include the FAST floating point emulator in the kernel.
2149           This is an experimental much faster emulator which now also has full
2150           precision for the mantissa.  It does not support any exceptions.
2151           It is very simple, and approximately 3-6 times faster than NWFPE.
2152
2153           It should be sufficient for most programs.  It may be not suitable
2154           for scientific calculations, but you have to check this for yourself.
2155           If you do not feel you need a faster FP emulation you should better
2156           choose NWFPE.
2157
2158 config VFP
2159         bool "VFP-format floating point maths"
2160         depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2161         help
2162           Say Y to include VFP support code in the kernel. This is needed
2163           if your hardware includes a VFP unit.
2164
2165           Please see <file:Documentation/arm/VFP/release-notes.txt> for
2166           release notes and additional status information.
2167
2168           Say N if your target does not have VFP hardware.
2169
2170 config VFPv3
2171         bool
2172         depends on VFP
2173         default y if CPU_V7
2174
2175 config NEON
2176         bool "Advanced SIMD (NEON) Extension support"
2177         depends on VFPv3 && CPU_V7
2178         help
2179           Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2180           Extension.
2181
2182 config KERNEL_MODE_NEON
2183         bool "Support for NEON in kernel mode"
2184         depends on NEON && AEABI
2185         help
2186           Say Y to include support for NEON in kernel mode.
2187
2188 endmenu
2189
2190 menu "Userspace binary formats"
2191
2192 source "fs/Kconfig.binfmt"
2193
2194 endmenu
2195
2196 menu "Power management options"
2197
2198 source "kernel/power/Kconfig"
2199
2200 config ARCH_SUSPEND_POSSIBLE
2201         depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2202                 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2203         def_bool y
2204
2205 config ARM_CPU_SUSPEND
2206         def_bool PM_SLEEP
2207
2208 config ARCH_HIBERNATION_POSSIBLE
2209         bool
2210         depends on MMU
2211         default y if ARCH_SUSPEND_POSSIBLE
2212
2213 endmenu
2214
2215 source "net/Kconfig"
2216
2217 source "drivers/Kconfig"
2218
2219 source "drivers/firmware/Kconfig"
2220
2221 source "fs/Kconfig"
2222
2223 source "arch/arm/Kconfig.debug"
2224
2225 source "security/Kconfig"
2226
2227 source "crypto/Kconfig"
2228 if CRYPTO
2229 source "arch/arm/crypto/Kconfig"
2230 endif
2231
2232 source "lib/Kconfig"
2233
2234 source "arch/arm/kvm/Kconfig"