4 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
5 select ARCH_HAS_DEVMEM_IS_ALLOWED
6 select ARCH_HAS_ELF_RANDOMIZE
7 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
8 select ARCH_HAVE_CUSTOM_GPIO_H
9 select ARCH_HAS_GCOV_PROFILE_ALL
10 select ARCH_MIGHT_HAVE_PC_PARPORT
11 select ARCH_SUPPORTS_ATOMIC_RMW
12 select ARCH_USE_BUILTIN_BSWAP
13 select ARCH_USE_CMPXCHG_LOCKREF
14 select ARCH_WANT_IPC_PARSE_VERSION
15 select BUILDTIME_EXTABLE_SORT if MMU
16 select CLONE_BACKWARDS
17 select CPU_PM if (SUSPEND || CPU_IDLE)
18 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
20 select EDAC_ATOMIC_SCRUB
21 select GENERIC_ALLOCATOR
22 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
23 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
24 select GENERIC_EARLY_IOREMAP
25 select GENERIC_IDLE_POLL_SETUP
26 select GENERIC_IRQ_PROBE
27 select GENERIC_IRQ_SHOW
28 select GENERIC_IRQ_SHOW_LEVEL
29 select GENERIC_PCI_IOMAP
30 select GENERIC_SCHED_CLOCK
31 select GENERIC_SMP_IDLE_THREAD
32 select GENERIC_STRNCPY_FROM_USER
33 select GENERIC_STRNLEN_USER
34 select HANDLE_DOMAIN_IRQ
35 select HARDIRQS_SW_RESEND
36 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
37 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
38 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
39 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
40 select HAVE_ARCH_MMAP_RND_BITS if MMU
41 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
42 select HAVE_ARCH_TRACEHOOK
43 select HAVE_ARM_SMCCC if CPU_V7
45 select HAVE_CC_STACKPROTECTOR
46 select HAVE_CONTEXT_TRACKING
47 select HAVE_C_RECORDMCOUNT
48 select HAVE_DEBUG_KMEMLEAK
49 select HAVE_DMA_API_DEBUG
50 select HAVE_DMA_CONTIGUOUS if MMU
51 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32 && MMU
52 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
53 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
54 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
55 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
56 select HAVE_GENERIC_DMA_COHERENT
57 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
58 select HAVE_IDE if PCI || ISA || PCMCIA
59 select HAVE_IRQ_TIME_ACCOUNTING
60 select HAVE_KERNEL_GZIP
61 select HAVE_KERNEL_LZ4
62 select HAVE_KERNEL_LZMA
63 select HAVE_KERNEL_LZO
65 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
66 select HAVE_KRETPROBES if (HAVE_KPROBES)
68 select HAVE_MOD_ARCH_SPECIFIC
69 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
70 select HAVE_OPTPROBES if !THUMB2_KERNEL
71 select HAVE_PERF_EVENTS
73 select HAVE_PERF_USER_STACK_DUMP
74 select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
75 select HAVE_REGS_AND_STACK_ACCESS_API
76 select HAVE_SYSCALL_TRACEPOINTS
78 select HAVE_VIRT_CPU_ACCOUNTING_GEN
79 select IRQ_FORCED_THREADING
80 select MODULES_USE_ELF_REL
82 select OF_EARLY_FLATTREE if OF
83 select OF_RESERVED_MEM if OF
85 select OLD_SIGSUSPEND3
86 select PERF_USE_VMALLOC
88 select SYS_SUPPORTS_APM_EMULATION
89 # Above selects are sorted alphabetically; please add new ones
90 # according to that. Thanks.
92 The ARM series is a line of low-power-consumption RISC chip designs
93 licensed by ARM Ltd and targeted at embedded applications and
94 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
95 manufactured, but legacy ARM-based PC hardware remains popular in
96 Europe. There is an ARM Linux project with a web page at
97 <http://www.arm.linux.org.uk/>.
99 config ARM_HAS_SG_CHAIN
100 select ARCH_HAS_SG_CHAIN
103 config NEED_SG_DMA_LENGTH
106 config ARM_DMA_USE_IOMMU
108 select ARM_HAS_SG_CHAIN
109 select NEED_SG_DMA_LENGTH
113 config ARM_DMA_IOMMU_ALIGNMENT
114 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
118 DMA mapping framework by default aligns all buffers to the smallest
119 PAGE_SIZE order which is greater than or equal to the requested buffer
120 size. This works well for buffers up to a few hundreds kilobytes, but
121 for larger buffers it just a waste of address space. Drivers which has
122 relatively small addressing window (like 64Mib) might run out of
123 virtual space with just a few allocations.
125 With this parameter you can specify the maximum PAGE_SIZE order for
126 DMA IOMMU buffers. Larger buffers will be aligned only to this
127 specified order. The order is expressed as a power of two multiplied
132 config MIGHT_HAVE_PCI
135 config SYS_SUPPORTS_APM_EMULATION
140 select GENERIC_ALLOCATOR
151 The Extended Industry Standard Architecture (EISA) bus was
152 developed as an open alternative to the IBM MicroChannel bus.
154 The EISA bus provided some of the features of the IBM MicroChannel
155 bus while maintaining backward compatibility with cards made for
156 the older ISA bus. The EISA bus saw limited use between 1988 and
157 1995 when it was made obsolete by the PCI bus.
159 Say Y here if you are building a kernel for an EISA-based machine.
166 config STACKTRACE_SUPPORT
170 config LOCKDEP_SUPPORT
174 config TRACE_IRQFLAGS_SUPPORT
178 config RWSEM_XCHGADD_ALGORITHM
182 config ARCH_HAS_ILOG2_U32
185 config ARCH_HAS_ILOG2_U64
188 config ARCH_HAS_BANDGAP
191 config FIX_EARLYCON_MEM
194 config GENERIC_HWEIGHT
198 config GENERIC_CALIBRATE_DELAY
202 config ARCH_MAY_HAVE_PC_FDC
208 config NEED_DMA_MAP_STATE
211 config ARCH_SUPPORTS_UPROBES
214 config ARCH_HAS_DMA_SET_COHERENT_MASK
217 config GENERIC_ISA_DMA
223 config NEED_RET_TO_USER
231 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
232 default DRAM_BASE if REMAP_VECTORS_TO_RAM
235 The base address of exception vectors. This must be two pages
238 config ARM_PATCH_PHYS_VIRT
239 bool "Patch physical to virtual translations at runtime" if EMBEDDED
241 depends on !XIP_KERNEL && MMU
243 Patch phys-to-virt and virt-to-phys translation functions at
244 boot and module load time according to the position of the
245 kernel in system memory.
247 This can only be used with non-XIP MMU kernels where the base
248 of physical memory is at a 16MB boundary.
250 Only disable this option if you know that you do not require
251 this feature (eg, building a kernel for a single machine) and
252 you need to shrink the kernel to the minimal size.
254 config NEED_MACH_IO_H
257 Select this when mach/io.h is required to provide special
258 definitions for this platform. The need for mach/io.h should
259 be avoided when possible.
261 config NEED_MACH_MEMORY_H
264 Select this when mach/memory.h is required to provide special
265 definitions for this platform. The need for mach/memory.h should
266 be avoided when possible.
269 hex "Physical address of main memory" if MMU
270 depends on !ARM_PATCH_PHYS_VIRT
271 default DRAM_BASE if !MMU
272 default 0x00000000 if ARCH_EBSA110 || \
277 (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET)
278 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
279 default 0x20000000 if ARCH_S5PV210
280 default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET
281 default 0xc0000000 if ARCH_SA1100
283 Please provide the physical address corresponding to the
284 location of main memory in your system.
290 config PGTABLE_LEVELS
292 default 3 if ARM_LPAE
295 source "init/Kconfig"
297 source "kernel/Kconfig.freezer"
302 bool "MMU-based Paged Memory Management Support"
305 Select if you want MMU-based virtualised addressing space
306 support by paged memory management. If unsure, say 'Y'.
308 config ARCH_MMAP_RND_BITS_MIN
311 config ARCH_MMAP_RND_BITS_MAX
312 default 14 if PAGE_OFFSET=0x40000000
313 default 15 if PAGE_OFFSET=0x80000000
317 # The "ARM system type" choice list is ordered alphabetically by option
318 # text. Please add new entries in the option alphabetic order.
321 prompt "ARM system type"
322 default ARM_SINGLE_ARMV7M if !MMU
323 default ARCH_MULTIPLATFORM if MMU
325 config ARCH_MULTIPLATFORM
326 bool "Allow multiple platforms to be selected"
328 select ARCH_WANT_OPTIONAL_GPIOLIB
329 select ARM_HAS_SG_CHAIN
330 select ARM_PATCH_PHYS_VIRT
334 select GENERIC_CLOCKEVENTS
335 select MIGHT_HAVE_PCI
336 select MULTI_IRQ_HANDLER
340 config ARM_SINGLE_ARMV7M
341 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
343 select ARCH_WANT_OPTIONAL_GPIOLIB
349 select GENERIC_CLOCKEVENTS
356 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
357 select ARCH_REQUIRE_GPIOLIB
362 select GENERIC_CLOCKEVENTS
366 Support for Cirrus Logic 711x/721x/731x based boards.
369 bool "Cortina Systems Gemini"
370 select ARCH_REQUIRE_GPIOLIB
373 select GENERIC_CLOCKEVENTS
375 Support for the Cortina Systems Gemini family SoCs
379 select ARCH_USES_GETTIMEOFFSET
382 select NEED_MACH_IO_H
383 select NEED_MACH_MEMORY_H
386 This is an evaluation board for the StrongARM processor available
387 from Digital. It has limited hardware on-board, including an
388 Ethernet interface, two PCMCIA sockets, two serial ports and a
393 select ARCH_HAS_HOLES_MEMORYMODEL
394 select ARCH_REQUIRE_GPIOLIB
396 select ARM_PATCH_PHYS_VIRT
402 select GENERIC_CLOCKEVENTS
404 This enables support for the Cirrus EP93xx series of CPUs.
406 config ARCH_FOOTBRIDGE
410 select GENERIC_CLOCKEVENTS
412 select NEED_MACH_IO_H if !MMU
413 select NEED_MACH_MEMORY_H
415 Support for systems based on the DC21285 companion chip
416 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
419 bool "Hilscher NetX based"
423 select GENERIC_CLOCKEVENTS
425 This enables support for systems based on the Hilscher NetX Soc
431 select NEED_MACH_MEMORY_H
432 select NEED_RET_TO_USER
438 Support for Intel's IOP13XX (XScale) family of processors.
443 select ARCH_REQUIRE_GPIOLIB
446 select NEED_RET_TO_USER
450 Support for Intel's 80219 and IOP32X (XScale) family of
456 select ARCH_REQUIRE_GPIOLIB
459 select NEED_RET_TO_USER
463 Support for Intel's IOP33X (XScale) family of processors.
468 select ARCH_HAS_DMA_SET_COHERENT_MASK
469 select ARCH_REQUIRE_GPIOLIB
470 select ARCH_SUPPORTS_BIG_ENDIAN
473 select DMABOUNCE if PCI
474 select GENERIC_CLOCKEVENTS
475 select MIGHT_HAVE_PCI
476 select NEED_MACH_IO_H
477 select USB_EHCI_BIG_ENDIAN_DESC
478 select USB_EHCI_BIG_ENDIAN_MMIO
480 Support for Intel's IXP4XX (XScale) family of processors.
484 select ARCH_REQUIRE_GPIOLIB
486 select GENERIC_CLOCKEVENTS
487 select MIGHT_HAVE_PCI
488 select MULTI_IRQ_HANDLER
492 select PLAT_ORION_LEGACY
494 select PM_GENERIC_DOMAINS if PM
496 Support for the Marvell Dove SoC 88AP510
499 bool "Micrel/Kendin KS8695"
500 select ARCH_REQUIRE_GPIOLIB
503 select GENERIC_CLOCKEVENTS
504 select NEED_MACH_MEMORY_H
506 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
507 System-on-Chip devices.
510 bool "Nuvoton W90X900 CPU"
511 select ARCH_REQUIRE_GPIOLIB
515 select GENERIC_CLOCKEVENTS
517 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
518 At present, the w90x900 has been renamed nuc900, regarding
519 the ARM series product line, you can login the following
520 link address to know more.
522 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
523 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
527 select ARCH_REQUIRE_GPIOLIB
530 select CLKSRC_LPC32XX
533 select GENERIC_CLOCKEVENTS
534 select MULTI_IRQ_HANDLER
538 Support for the NXP LPC32XX family of processors
541 bool "PXA2xx/PXA3xx-based"
544 select ARCH_REQUIRE_GPIOLIB
545 select ARM_CPU_SUSPEND if PM
552 select CPU_XSCALE if !CPU_XSC3
553 select GENERIC_CLOCKEVENTS
557 select MULTI_IRQ_HANDLER
561 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
567 select ARCH_MAY_HAVE_PC_FDC
568 select ARCH_SPARSEMEM_ENABLE
569 select ARCH_USES_GETTIMEOFFSET
573 select HAVE_PATA_PLATFORM
575 select NEED_MACH_IO_H
576 select NEED_MACH_MEMORY_H
579 On the Acorn Risc-PC, Linux can support the internal IDE disk and
580 CD-ROM interface, serial and parallel port, and the floppy drive.
585 select ARCH_REQUIRE_GPIOLIB
586 select ARCH_SPARSEMEM_ENABLE
590 select CLKSRC_OF if OF
593 select GENERIC_CLOCKEVENTS
597 select MULTI_IRQ_HANDLER
598 select NEED_MACH_MEMORY_H
601 Support for StrongARM 11x0 based boards.
604 bool "Samsung S3C24XX SoCs"
605 select ARCH_REQUIRE_GPIOLIB
608 select CLKSRC_SAMSUNG_PWM
609 select GENERIC_CLOCKEVENTS
611 select HAVE_S3C2410_I2C if I2C
612 select HAVE_S3C2410_WATCHDOG if WATCHDOG
613 select HAVE_S3C_RTC if RTC_CLASS
614 select MULTI_IRQ_HANDLER
615 select NEED_MACH_IO_H
618 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
619 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
620 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
621 Samsung SMDK2410 development board (and derivatives).
625 select ARCH_HAS_HOLES_MEMORYMODEL
626 select ARCH_REQUIRE_GPIOLIB
629 select GENERIC_ALLOCATOR
630 select GENERIC_CLOCKEVENTS
631 select GENERIC_IRQ_CHIP
636 Support for TI's DaVinci platform.
641 select ARCH_HAS_HOLES_MEMORYMODEL
643 select ARCH_REQUIRE_GPIOLIB
646 select GENERIC_CLOCKEVENTS
647 select GENERIC_IRQ_CHIP
650 select MULTI_IRQ_HANDLER
651 select NEED_MACH_IO_H if PCCARD
652 select NEED_MACH_MEMORY_H
655 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
659 menu "Multiple platform selection"
660 depends on ARCH_MULTIPLATFORM
662 comment "CPU Core family selection"
665 bool "ARMv4 based platforms (FA526)"
666 depends on !ARCH_MULTI_V6_V7
667 select ARCH_MULTI_V4_V5
670 config ARCH_MULTI_V4T
671 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
672 depends on !ARCH_MULTI_V6_V7
673 select ARCH_MULTI_V4_V5
674 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
675 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
676 CPU_ARM925T || CPU_ARM940T)
679 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
680 depends on !ARCH_MULTI_V6_V7
681 select ARCH_MULTI_V4_V5
682 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
683 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
684 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
686 config ARCH_MULTI_V4_V5
690 bool "ARMv6 based platforms (ARM11)"
691 select ARCH_MULTI_V6_V7
695 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
697 select ARCH_MULTI_V6_V7
701 config ARCH_MULTI_V6_V7
703 select MIGHT_HAVE_CACHE_L2X0
705 config ARCH_MULTI_CPU_AUTO
706 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
712 bool "Dummy Virtual Machine"
713 depends on ARCH_MULTI_V7
716 select ARM_GIC_V2M if PCI_MSI
719 select HAVE_ARM_ARCH_TIMER
722 # This is sorted alphabetically by mach-* pathname. However, plat-*
723 # Kconfigs may be included either alphabetically (according to the
724 # plat- suffix) or along side the corresponding mach-* source.
726 source "arch/arm/mach-mvebu/Kconfig"
728 source "arch/arm/mach-alpine/Kconfig"
730 source "arch/arm/mach-artpec/Kconfig"
732 source "arch/arm/mach-asm9260/Kconfig"
734 source "arch/arm/mach-at91/Kconfig"
736 source "arch/arm/mach-axxia/Kconfig"
738 source "arch/arm/mach-bcm/Kconfig"
740 source "arch/arm/mach-berlin/Kconfig"
742 source "arch/arm/mach-clps711x/Kconfig"
744 source "arch/arm/mach-cns3xxx/Kconfig"
746 source "arch/arm/mach-davinci/Kconfig"
748 source "arch/arm/mach-digicolor/Kconfig"
750 source "arch/arm/mach-dove/Kconfig"
752 source "arch/arm/mach-ep93xx/Kconfig"
754 source "arch/arm/mach-footbridge/Kconfig"
756 source "arch/arm/mach-gemini/Kconfig"
758 source "arch/arm/mach-highbank/Kconfig"
760 source "arch/arm/mach-hisi/Kconfig"
762 source "arch/arm/mach-integrator/Kconfig"
764 source "arch/arm/mach-iop32x/Kconfig"
766 source "arch/arm/mach-iop33x/Kconfig"
768 source "arch/arm/mach-iop13xx/Kconfig"
770 source "arch/arm/mach-ixp4xx/Kconfig"
772 source "arch/arm/mach-keystone/Kconfig"
774 source "arch/arm/mach-ks8695/Kconfig"
776 source "arch/arm/mach-meson/Kconfig"
778 source "arch/arm/mach-moxart/Kconfig"
780 source "arch/arm/mach-mv78xx0/Kconfig"
782 source "arch/arm/mach-imx/Kconfig"
784 source "arch/arm/mach-mediatek/Kconfig"
786 source "arch/arm/mach-mxs/Kconfig"
788 source "arch/arm/mach-netx/Kconfig"
790 source "arch/arm/mach-nomadik/Kconfig"
792 source "arch/arm/mach-nspire/Kconfig"
794 source "arch/arm/plat-omap/Kconfig"
796 source "arch/arm/mach-omap1/Kconfig"
798 source "arch/arm/mach-omap2/Kconfig"
800 source "arch/arm/mach-orion5x/Kconfig"
802 source "arch/arm/mach-picoxcell/Kconfig"
804 source "arch/arm/mach-pxa/Kconfig"
805 source "arch/arm/plat-pxa/Kconfig"
807 source "arch/arm/mach-mmp/Kconfig"
809 source "arch/arm/mach-qcom/Kconfig"
811 source "arch/arm/mach-realview/Kconfig"
813 source "arch/arm/mach-rockchip/Kconfig"
815 source "arch/arm/mach-sa1100/Kconfig"
817 source "arch/arm/mach-socfpga/Kconfig"
819 source "arch/arm/mach-spear/Kconfig"
821 source "arch/arm/mach-sti/Kconfig"
823 source "arch/arm/mach-s3c24xx/Kconfig"
825 source "arch/arm/mach-s3c64xx/Kconfig"
827 source "arch/arm/mach-s5pv210/Kconfig"
829 source "arch/arm/mach-exynos/Kconfig"
830 source "arch/arm/plat-samsung/Kconfig"
832 source "arch/arm/mach-shmobile/Kconfig"
834 source "arch/arm/mach-sunxi/Kconfig"
836 source "arch/arm/mach-prima2/Kconfig"
838 source "arch/arm/mach-tango/Kconfig"
840 source "arch/arm/mach-tegra/Kconfig"
842 source "arch/arm/mach-u300/Kconfig"
844 source "arch/arm/mach-uniphier/Kconfig"
846 source "arch/arm/mach-ux500/Kconfig"
848 source "arch/arm/mach-versatile/Kconfig"
850 source "arch/arm/mach-vexpress/Kconfig"
851 source "arch/arm/plat-versatile/Kconfig"
853 source "arch/arm/mach-vt8500/Kconfig"
855 source "arch/arm/mach-w90x900/Kconfig"
857 source "arch/arm/mach-zx/Kconfig"
859 source "arch/arm/mach-zynq/Kconfig"
861 # ARMv7-M architecture
863 bool "Energy Micro efm32"
864 depends on ARM_SINGLE_ARMV7M
865 select ARCH_REQUIRE_GPIOLIB
867 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
871 bool "NXP LPC18xx/LPC43xx"
872 depends on ARM_SINGLE_ARMV7M
873 select ARCH_HAS_RESET_CONTROLLER
875 select CLKSRC_LPC32XX
878 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
879 high performance microcontrollers.
882 bool "STMicrolectronics STM32"
883 depends on ARM_SINGLE_ARMV7M
884 select ARCH_HAS_RESET_CONTROLLER
885 select ARMV7M_SYSTICK
888 select RESET_CONTROLLER
890 Support for STMicroelectronics STM32 processors.
892 config MACH_STM32F429
893 bool "STMicrolectronics STM32F429"
894 depends on ARCH_STM32
897 # Definitions to make life easier
903 select GENERIC_CLOCKEVENTS
909 select GENERIC_IRQ_CHIP
912 config PLAT_ORION_LEGACY
919 config PLAT_VERSATILE
922 source "arch/arm/firmware/Kconfig"
924 source arch/arm/mm/Kconfig
927 bool "Enable iWMMXt support"
928 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
929 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
931 Enable support for iWMMXt context switching at run time if
932 running on a CPU that supports it.
934 config MULTI_IRQ_HANDLER
937 Allow each machine to specify it's own IRQ handler at run time.
940 source "arch/arm/Kconfig-nommu"
943 config PJ4B_ERRATA_4742
944 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
945 depends on CPU_PJ4B && MACH_ARMADA_370
948 When coming out of either a Wait for Interrupt (WFI) or a Wait for
949 Event (WFE) IDLE states, a specific timing sensitivity exists between
950 the retiring WFI/WFE instructions and the newly issued subsequent
951 instructions. This sensitivity can result in a CPU hang scenario.
953 The software must insert either a Data Synchronization Barrier (DSB)
954 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
957 config ARM_ERRATA_326103
958 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
961 Executing a SWP instruction to read-only memory does not set bit 11
962 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
963 treat the access as a read, preventing a COW from occurring and
964 causing the faulting task to livelock.
966 config ARM_ERRATA_411920
967 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
968 depends on CPU_V6 || CPU_V6K
970 Invalidation of the Instruction Cache operation can
971 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
972 It does not affect the MPCore. This option enables the ARM Ltd.
973 recommended workaround.
975 config ARM_ERRATA_430973
976 bool "ARM errata: Stale prediction on replaced interworking branch"
979 This option enables the workaround for the 430973 Cortex-A8
980 r1p* erratum. If a code sequence containing an ARM/Thumb
981 interworking branch is replaced with another code sequence at the
982 same virtual address, whether due to self-modifying code or virtual
983 to physical address re-mapping, Cortex-A8 does not recover from the
984 stale interworking branch prediction. This results in Cortex-A8
985 executing the new code sequence in the incorrect ARM or Thumb state.
986 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
987 and also flushes the branch target cache at every context switch.
988 Note that setting specific bits in the ACTLR register may not be
989 available in non-secure mode.
991 config ARM_ERRATA_458693
992 bool "ARM errata: Processor deadlock when a false hazard is created"
994 depends on !ARCH_MULTIPLATFORM
996 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
997 erratum. For very specific sequences of memory operations, it is
998 possible for a hazard condition intended for a cache line to instead
999 be incorrectly associated with a different cache line. This false
1000 hazard might then cause a processor deadlock. The workaround enables
1001 the L1 caching of the NEON accesses and disables the PLD instruction
1002 in the ACTLR register. Note that setting specific bits in the ACTLR
1003 register may not be available in non-secure mode.
1005 config ARM_ERRATA_460075
1006 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1008 depends on !ARCH_MULTIPLATFORM
1010 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1011 erratum. Any asynchronous access to the L2 cache may encounter a
1012 situation in which recent store transactions to the L2 cache are lost
1013 and overwritten with stale memory contents from external memory. The
1014 workaround disables the write-allocate mode for the L2 cache via the
1015 ACTLR register. Note that setting specific bits in the ACTLR register
1016 may not be available in non-secure mode.
1018 config ARM_ERRATA_742230
1019 bool "ARM errata: DMB operation may be faulty"
1020 depends on CPU_V7 && SMP
1021 depends on !ARCH_MULTIPLATFORM
1023 This option enables the workaround for the 742230 Cortex-A9
1024 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1025 between two write operations may not ensure the correct visibility
1026 ordering of the two writes. This workaround sets a specific bit in
1027 the diagnostic register of the Cortex-A9 which causes the DMB
1028 instruction to behave as a DSB, ensuring the correct behaviour of
1031 config ARM_ERRATA_742231
1032 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1033 depends on CPU_V7 && SMP
1034 depends on !ARCH_MULTIPLATFORM
1036 This option enables the workaround for the 742231 Cortex-A9
1037 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1038 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1039 accessing some data located in the same cache line, may get corrupted
1040 data due to bad handling of the address hazard when the line gets
1041 replaced from one of the CPUs at the same time as another CPU is
1042 accessing it. This workaround sets specific bits in the diagnostic
1043 register of the Cortex-A9 which reduces the linefill issuing
1044 capabilities of the processor.
1046 config ARM_ERRATA_643719
1047 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1048 depends on CPU_V7 && SMP
1051 This option enables the workaround for the 643719 Cortex-A9 (prior to
1052 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1053 register returns zero when it should return one. The workaround
1054 corrects this value, ensuring cache maintenance operations which use
1055 it behave as intended and avoiding data corruption.
1057 config ARM_ERRATA_720789
1058 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1061 This option enables the workaround for the 720789 Cortex-A9 (prior to
1062 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1063 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1064 As a consequence of this erratum, some TLB entries which should be
1065 invalidated are not, resulting in an incoherency in the system page
1066 tables. The workaround changes the TLB flushing routines to invalidate
1067 entries regardless of the ASID.
1069 config ARM_ERRATA_743622
1070 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1072 depends on !ARCH_MULTIPLATFORM
1074 This option enables the workaround for the 743622 Cortex-A9
1075 (r2p*) erratum. Under very rare conditions, a faulty
1076 optimisation in the Cortex-A9 Store Buffer may lead to data
1077 corruption. This workaround sets a specific bit in the diagnostic
1078 register of the Cortex-A9 which disables the Store Buffer
1079 optimisation, preventing the defect from occurring. This has no
1080 visible impact on the overall performance or power consumption of the
1083 config ARM_ERRATA_751472
1084 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1086 depends on !ARCH_MULTIPLATFORM
1088 This option enables the workaround for the 751472 Cortex-A9 (prior
1089 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1090 completion of a following broadcasted operation if the second
1091 operation is received by a CPU before the ICIALLUIS has completed,
1092 potentially leading to corrupted entries in the cache or TLB.
1094 config ARM_ERRATA_754322
1095 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1098 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1099 r3p*) erratum. A speculative memory access may cause a page table walk
1100 which starts prior to an ASID switch but completes afterwards. This
1101 can populate the micro-TLB with a stale entry which may be hit with
1102 the new ASID. This workaround places two dsb instructions in the mm
1103 switching code so that no page table walks can cross the ASID switch.
1105 config ARM_ERRATA_754327
1106 bool "ARM errata: no automatic Store Buffer drain"
1107 depends on CPU_V7 && SMP
1109 This option enables the workaround for the 754327 Cortex-A9 (prior to
1110 r2p0) erratum. The Store Buffer does not have any automatic draining
1111 mechanism and therefore a livelock may occur if an external agent
1112 continuously polls a memory location waiting to observe an update.
1113 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1114 written polling loops from denying visibility of updates to memory.
1116 config ARM_ERRATA_364296
1117 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1120 This options enables the workaround for the 364296 ARM1136
1121 r0p2 erratum (possible cache data corruption with
1122 hit-under-miss enabled). It sets the undocumented bit 31 in
1123 the auxiliary control register and the FI bit in the control
1124 register, thus disabling hit-under-miss without putting the
1125 processor into full low interrupt latency mode. ARM11MPCore
1128 config ARM_ERRATA_764369
1129 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1130 depends on CPU_V7 && SMP
1132 This option enables the workaround for erratum 764369
1133 affecting Cortex-A9 MPCore with two or more processors (all
1134 current revisions). Under certain timing circumstances, a data
1135 cache line maintenance operation by MVA targeting an Inner
1136 Shareable memory region may fail to proceed up to either the
1137 Point of Coherency or to the Point of Unification of the
1138 system. This workaround adds a DSB instruction before the
1139 relevant cache maintenance functions and sets a specific bit
1140 in the diagnostic control register of the SCU.
1142 config ARM_ERRATA_775420
1143 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1146 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1147 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1148 operation aborts with MMU exception, it might cause the processor
1149 to deadlock. This workaround puts DSB before executing ISB if
1150 an abort may occur on cache maintenance.
1152 config ARM_ERRATA_798181
1153 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1154 depends on CPU_V7 && SMP
1156 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1157 adequately shooting down all use of the old entries. This
1158 option enables the Linux kernel workaround for this erratum
1159 which sends an IPI to the CPUs that are running the same ASID
1160 as the one being invalidated.
1162 config ARM_ERRATA_773022
1163 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1166 This option enables the workaround for the 773022 Cortex-A15
1167 (up to r0p4) erratum. In certain rare sequences of code, the
1168 loop buffer may deliver incorrect instructions. This
1169 workaround disables the loop buffer to avoid the erratum.
1173 source "arch/arm/common/Kconfig"
1180 Find out whether you have ISA slots on your motherboard. ISA is the
1181 name of a bus system, i.e. the way the CPU talks to the other stuff
1182 inside your box. Other bus systems are PCI, EISA, MicroChannel
1183 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1184 newer boards don't support it. If you have ISA, say Y, otherwise N.
1186 # Select ISA DMA controller support
1191 # Select ISA DMA interface
1196 bool "PCI support" if MIGHT_HAVE_PCI
1198 Find out whether you have a PCI motherboard. PCI is the name of a
1199 bus system, i.e. the way the CPU talks to the other stuff inside
1200 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1201 VESA. If you have PCI, say Y, otherwise N.
1207 config PCI_DOMAINS_GENERIC
1208 def_bool PCI_DOMAINS
1210 config PCI_NANOENGINE
1211 bool "BSE nanoEngine PCI support"
1212 depends on SA1100_NANOENGINE
1214 Enable PCI on the BSE nanoEngine board.
1219 config PCI_HOST_ITE8152
1221 depends on PCI && MACH_ARMCORE
1225 source "drivers/pci/Kconfig"
1227 source "drivers/pcmcia/Kconfig"
1231 menu "Kernel Features"
1236 This option should be selected by machines which have an SMP-
1239 The only effect of this option is to make the SMP-related
1240 options available to the user for configuration.
1243 bool "Symmetric Multi-Processing"
1244 depends on CPU_V6K || CPU_V7
1245 depends on GENERIC_CLOCKEVENTS
1247 depends on MMU || ARM_MPU
1250 This enables support for systems with more than one CPU. If you have
1251 a system with only one CPU, say N. If you have a system with more
1252 than one CPU, say Y.
1254 If you say N here, the kernel will run on uni- and multiprocessor
1255 machines, but will use only one CPU of a multiprocessor machine. If
1256 you say Y here, the kernel will run on many, but not all,
1257 uniprocessor machines. On a uniprocessor machine, the kernel
1258 will run faster if you say N here.
1260 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1261 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1262 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1264 If you don't know what to do here, say N.
1267 bool "Allow booting SMP kernel on uniprocessor systems"
1268 depends on SMP && !XIP_KERNEL && MMU
1271 SMP kernels contain instructions which fail on non-SMP processors.
1272 Enabling this option allows the kernel to modify itself to make
1273 these instructions safe. Disabling it allows about 1K of space
1276 If you don't know what to do here, say Y.
1278 config ARM_CPU_TOPOLOGY
1279 bool "Support cpu topology definition"
1280 depends on SMP && CPU_V7
1283 Support ARM cpu topology definition. The MPIDR register defines
1284 affinity between processors which is then used to describe the cpu
1285 topology of an ARM System.
1288 bool "Multi-core scheduler support"
1289 depends on ARM_CPU_TOPOLOGY
1291 Multi-core scheduler support improves the CPU scheduler's decision
1292 making when dealing with multi-core CPU chips at a cost of slightly
1293 increased overhead in some places. If unsure say N here.
1296 bool "SMT scheduler support"
1297 depends on ARM_CPU_TOPOLOGY
1299 Improves the CPU scheduler's decision making when dealing with
1300 MultiThreading at a cost of slightly increased overhead in some
1301 places. If unsure say N here.
1306 This option enables support for the ARM system coherency unit
1308 config HAVE_ARM_ARCH_TIMER
1309 bool "Architected timer support"
1311 select ARM_ARCH_TIMER
1312 select GENERIC_CLOCKEVENTS
1314 This option enables support for the ARM architected timer
1318 select CLKSRC_OF if OF
1320 This options enables support for the ARM timer and watchdog unit
1323 bool "Multi-Cluster Power Management"
1324 depends on CPU_V7 && SMP
1326 This option provides the common power management infrastructure
1327 for (multi-)cluster based systems, such as big.LITTLE based
1330 config MCPM_QUAD_CLUSTER
1334 To avoid wasting resources unnecessarily, MCPM only supports up
1335 to 2 clusters by default.
1336 Platforms with 3 or 4 clusters that use MCPM must select this
1337 option to allow the additional clusters to be managed.
1340 bool "big.LITTLE support (Experimental)"
1341 depends on CPU_V7 && SMP
1344 This option enables support selections for the big.LITTLE
1345 system architecture.
1348 bool "big.LITTLE switcher support"
1349 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1352 The big.LITTLE "switcher" provides the core functionality to
1353 transparently handle transition between a cluster of A15's
1354 and a cluster of A7's in a big.LITTLE system.
1356 config BL_SWITCHER_DUMMY_IF
1357 tristate "Simple big.LITTLE switcher user interface"
1358 depends on BL_SWITCHER && DEBUG_KERNEL
1360 This is a simple and dummy char dev interface to control
1361 the big.LITTLE switcher core code. It is meant for
1362 debugging purposes only.
1365 prompt "Memory split"
1369 Select the desired split between kernel and user memory.
1371 If you are not absolutely sure what you are doing, leave this
1375 bool "3G/1G user/kernel split"
1376 config VMSPLIT_3G_OPT
1377 bool "3G/1G user/kernel split (for full 1G low memory)"
1379 bool "2G/2G user/kernel split"
1381 bool "1G/3G user/kernel split"
1386 default PHYS_OFFSET if !MMU
1387 default 0x40000000 if VMSPLIT_1G
1388 default 0x80000000 if VMSPLIT_2G
1389 default 0xB0000000 if VMSPLIT_3G_OPT
1393 int "Maximum number of CPUs (2-32)"
1399 bool "Support for hot-pluggable CPUs"
1402 Say Y here to experiment with turning CPUs off and on. CPUs
1403 can be controlled through /sys/devices/system/cpu.
1406 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1407 depends on HAVE_ARM_SMCCC
1410 Say Y here if you want Linux to communicate with system firmware
1411 implementing the PSCI specification for CPU-centric power
1412 management operations described in ARM document number ARM DEN
1413 0022A ("Power State Coordination Interface System Software on
1416 # The GPIO number here must be sorted by descending number. In case of
1417 # a multiplatform kernel, we just want the highest value required by the
1418 # selected platforms.
1421 default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \
1423 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1424 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1425 default 416 if ARCH_SUNXI
1426 default 392 if ARCH_U8500
1427 default 352 if ARCH_VT8500
1428 default 288 if ARCH_ROCKCHIP
1429 default 264 if MACH_H4700
1432 Maximum number of GPIOs in the system.
1434 If unsure, leave the default value.
1436 source kernel/Kconfig.preempt
1440 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1441 ARCH_S5PV210 || ARCH_EXYNOS4
1442 default 128 if SOC_AT91RM9200
1446 depends on HZ_FIXED = 0
1447 prompt "Timer frequency"
1471 default HZ_FIXED if HZ_FIXED != 0
1472 default 100 if HZ_100
1473 default 200 if HZ_200
1474 default 250 if HZ_250
1475 default 300 if HZ_300
1476 default 500 if HZ_500
1480 def_bool HIGH_RES_TIMERS
1482 config THUMB2_KERNEL
1483 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1484 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1485 default y if CPU_THUMBONLY
1487 select ARM_ASM_UNIFIED
1490 By enabling this option, the kernel will be compiled in
1491 Thumb-2 mode. A compiler/assembler that understand the unified
1492 ARM-Thumb syntax is needed.
1496 config THUMB2_AVOID_R_ARM_THM_JUMP11
1497 bool "Work around buggy Thumb-2 short branch relocations in gas"
1498 depends on THUMB2_KERNEL && MODULES
1501 Various binutils versions can resolve Thumb-2 branches to
1502 locally-defined, preemptible global symbols as short-range "b.n"
1503 branch instructions.
1505 This is a problem, because there's no guarantee the final
1506 destination of the symbol, or any candidate locations for a
1507 trampoline, are within range of the branch. For this reason, the
1508 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1509 relocation in modules at all, and it makes little sense to add
1512 The symptom is that the kernel fails with an "unsupported
1513 relocation" error when loading some modules.
1515 Until fixed tools are available, passing
1516 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1517 code which hits this problem, at the cost of a bit of extra runtime
1518 stack usage in some cases.
1520 The problem is described in more detail at:
1521 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1523 Only Thumb-2 kernels are affected.
1525 Unless you are sure your tools don't have this problem, say Y.
1527 config ARM_ASM_UNIFIED
1530 config ARM_PATCH_IDIV
1531 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1532 depends on CPU_32v7 && !XIP_KERNEL
1535 The ARM compiler inserts calls to __aeabi_idiv() and
1536 __aeabi_uidiv() when it needs to perform division on signed
1537 and unsigned integers. Some v7 CPUs have support for the sdiv
1538 and udiv instructions that can be used to implement those
1541 Enabling this option allows the kernel to modify itself to
1542 replace the first two instructions of these library functions
1543 with the sdiv or udiv plus "bx lr" instructions when the CPU
1544 it is running on supports them. Typically this will be faster
1545 and less power intensive than running the original library
1546 code to do integer division.
1549 bool "Use the ARM EABI to compile the kernel"
1551 This option allows for the kernel to be compiled using the latest
1552 ARM ABI (aka EABI). This is only useful if you are using a user
1553 space environment that is also compiled with EABI.
1555 Since there are major incompatibilities between the legacy ABI and
1556 EABI, especially with regard to structure member alignment, this
1557 option also changes the kernel syscall calling convention to
1558 disambiguate both ABIs and allow for backward compatibility support
1559 (selected with CONFIG_OABI_COMPAT).
1561 To use this you need GCC version 4.0.0 or later.
1564 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1565 depends on AEABI && !THUMB2_KERNEL
1567 This option preserves the old syscall interface along with the
1568 new (ARM EABI) one. It also provides a compatibility layer to
1569 intercept syscalls that have structure arguments which layout
1570 in memory differs between the legacy ABI and the new ARM EABI
1571 (only for non "thumb" binaries). This option adds a tiny
1572 overhead to all syscalls and produces a slightly larger kernel.
1574 The seccomp filter system will not be available when this is
1575 selected, since there is no way yet to sensibly distinguish
1576 between calling conventions during filtering.
1578 If you know you'll be using only pure EABI user space then you
1579 can say N here. If this option is not selected and you attempt
1580 to execute a legacy ABI binary then the result will be
1581 UNPREDICTABLE (in fact it can be predicted that it won't work
1582 at all). If in doubt say N.
1584 config ARCH_HAS_HOLES_MEMORYMODEL
1587 config ARCH_SPARSEMEM_ENABLE
1590 config ARCH_SPARSEMEM_DEFAULT
1591 def_bool ARCH_SPARSEMEM_ENABLE
1593 config ARCH_SELECT_MEMORY_MODEL
1594 def_bool ARCH_SPARSEMEM_ENABLE
1596 config HAVE_ARCH_PFN_VALID
1597 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1599 config HAVE_GENERIC_RCU_GUP
1604 bool "High Memory Support"
1607 The address space of ARM processors is only 4 Gigabytes large
1608 and it has to accommodate user address space, kernel address
1609 space as well as some memory mapped IO. That means that, if you
1610 have a large amount of physical memory and/or IO, not all of the
1611 memory can be "permanently mapped" by the kernel. The physical
1612 memory that is not permanently mapped is called "high memory".
1614 Depending on the selected kernel/user memory split, minimum
1615 vmalloc space and actual amount of RAM, you may not need this
1616 option which should result in a slightly faster kernel.
1621 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1625 The VM uses one page of physical memory for each page table.
1626 For systems with a lot of processes, this can use a lot of
1627 precious low memory, eventually leading to low memory being
1628 consumed by page tables. Setting this option will allow
1629 user-space 2nd level page tables to reside in high memory.
1631 config CPU_SW_DOMAIN_PAN
1632 bool "Enable use of CPU domains to implement privileged no-access"
1633 depends on MMU && !ARM_LPAE
1636 Increase kernel security by ensuring that normal kernel accesses
1637 are unable to access userspace addresses. This can help prevent
1638 use-after-free bugs becoming an exploitable privilege escalation
1639 by ensuring that magic values (such as LIST_POISON) will always
1640 fault when dereferenced.
1642 CPUs with low-vector mappings use a best-efforts implementation.
1643 Their lower 1MB needs to remain accessible for the vectors, but
1644 the remainder of userspace will become appropriately inaccessible.
1646 config HW_PERF_EVENTS
1650 config SYS_SUPPORTS_HUGETLBFS
1654 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1658 config ARCH_WANT_GENERAL_HUGETLB
1661 config ARM_MODULE_PLTS
1662 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1665 Allocate PLTs when loading modules so that jumps and calls whose
1666 targets are too far away for their relative offsets to be encoded
1667 in the instructions themselves can be bounced via veneers in the
1668 module's PLT. This allows modules to be allocated in the generic
1669 vmalloc area after the dedicated module memory area has been
1670 exhausted. The modules will use slightly more memory, but after
1671 rounding up to page size, the actual memory footprint is usually
1674 Say y if you are getting out of memory errors while loading modules
1678 config FORCE_MAX_ZONEORDER
1679 int "Maximum zone order"
1680 default "12" if SOC_AM33XX
1681 default "9" if SA1111 || ARCH_EFM32
1684 The kernel memory allocator divides physically contiguous memory
1685 blocks into "zones", where each zone is a power of two number of
1686 pages. This option selects the largest power of two that the kernel
1687 keeps in the memory allocator. If you need to allocate very large
1688 blocks of physically contiguous memory, then you may need to
1689 increase this value.
1691 This config option is actually maximum order plus one. For example,
1692 a value of 11 means that the largest free memory block is 2^10 pages.
1694 config ALIGNMENT_TRAP
1696 depends on CPU_CP15_MMU
1697 default y if !ARCH_EBSA110
1698 select HAVE_PROC_CPU if PROC_FS
1700 ARM processors cannot fetch/store information which is not
1701 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1702 address divisible by 4. On 32-bit ARM processors, these non-aligned
1703 fetch/store instructions will be emulated in software if you say
1704 here, which has a severe performance impact. This is necessary for
1705 correct operation of some network protocols. With an IP-only
1706 configuration it is safe to say N, otherwise say Y.
1708 config UACCESS_WITH_MEMCPY
1709 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1711 default y if CPU_FEROCEON
1713 Implement faster copy_to_user and clear_user methods for CPU
1714 cores where a 8-word STM instruction give significantly higher
1715 memory write throughput than a sequence of individual 32bit stores.
1717 A possible side effect is a slight increase in scheduling latency
1718 between threads sharing the same address space if they invoke
1719 such copy operations with large buffers.
1721 However, if the CPU data cache is using a write-allocate mode,
1722 this option is unlikely to provide any performance gain.
1726 prompt "Enable seccomp to safely compute untrusted bytecode"
1728 This kernel feature is useful for number crunching applications
1729 that may need to compute untrusted bytecode during their
1730 execution. By using pipes or other transports made available to
1731 the process as file descriptors supporting the read/write
1732 syscalls, it's possible to isolate those applications in
1733 their own address space using seccomp. Once seccomp is
1734 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1735 and the task is only allowed to execute a few safe syscalls
1736 defined by each seccomp mode.
1745 bool "Enable paravirtualization code"
1747 This changes the kernel so it can modify itself when it is run
1748 under a hypervisor, potentially improving performance significantly
1749 over full virtualization.
1751 config PARAVIRT_TIME_ACCOUNTING
1752 bool "Paravirtual steal time accounting"
1756 Select this option to enable fine granularity task steal time
1757 accounting. Time spent executing other tasks in parallel with
1758 the current vCPU is discounted from the vCPU power. To account for
1759 that, there can be a small performance impact.
1761 If in doubt, say N here.
1768 bool "Xen guest support on ARM"
1769 depends on ARM && AEABI && OF
1770 depends on CPU_V7 && !CPU_V6
1771 depends on !GENERIC_ATOMIC64
1773 select ARCH_DMA_ADDR_T_64BIT
1778 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1785 bool "Flattened Device Tree support"
1789 Include support for flattened device tree machine descriptions.
1792 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1795 This is the traditional way of passing data to the kernel at boot
1796 time. If you are solely relying on the flattened device tree (or
1797 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1798 to remove ATAGS support from your kernel binary. If unsure,
1801 config DEPRECATED_PARAM_STRUCT
1802 bool "Provide old way to pass kernel parameters"
1805 This was deprecated in 2001 and announced to live on for 5 years.
1806 Some old boot loaders still use this way.
1808 # Compressed boot loader in ROM. Yes, we really want to ask about
1809 # TEXT and BSS so we preserve their values in the config files.
1810 config ZBOOT_ROM_TEXT
1811 hex "Compressed ROM boot loader base address"
1814 The physical address at which the ROM-able zImage is to be
1815 placed in the target. Platforms which normally make use of
1816 ROM-able zImage formats normally set this to a suitable
1817 value in their defconfig file.
1819 If ZBOOT_ROM is not enabled, this has no effect.
1821 config ZBOOT_ROM_BSS
1822 hex "Compressed ROM boot loader BSS address"
1825 The base address of an area of read/write memory in the target
1826 for the ROM-able zImage which must be available while the
1827 decompressor is running. It must be large enough to hold the
1828 entire decompressed kernel plus an additional 128 KiB.
1829 Platforms which normally make use of ROM-able zImage formats
1830 normally set this to a suitable value in their defconfig file.
1832 If ZBOOT_ROM is not enabled, this has no effect.
1835 bool "Compressed boot loader in ROM/flash"
1836 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1837 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1839 Say Y here if you intend to execute your compressed kernel image
1840 (zImage) directly from ROM or flash. If unsure, say N.
1842 config ARM_APPENDED_DTB
1843 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1846 With this option, the boot code will look for a device tree binary
1847 (DTB) appended to zImage
1848 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1850 This is meant as a backward compatibility convenience for those
1851 systems with a bootloader that can't be upgraded to accommodate
1852 the documented boot protocol using a device tree.
1854 Beware that there is very little in terms of protection against
1855 this option being confused by leftover garbage in memory that might
1856 look like a DTB header after a reboot if no actual DTB is appended
1857 to zImage. Do not leave this option active in a production kernel
1858 if you don't intend to always append a DTB. Proper passing of the
1859 location into r2 of a bootloader provided DTB is always preferable
1862 config ARM_ATAG_DTB_COMPAT
1863 bool "Supplement the appended DTB with traditional ATAG information"
1864 depends on ARM_APPENDED_DTB
1866 Some old bootloaders can't be updated to a DTB capable one, yet
1867 they provide ATAGs with memory configuration, the ramdisk address,
1868 the kernel cmdline string, etc. Such information is dynamically
1869 provided by the bootloader and can't always be stored in a static
1870 DTB. To allow a device tree enabled kernel to be used with such
1871 bootloaders, this option allows zImage to extract the information
1872 from the ATAG list and store it at run time into the appended DTB.
1875 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1876 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1878 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1879 bool "Use bootloader kernel arguments if available"
1881 Uses the command-line options passed by the boot loader instead of
1882 the device tree bootargs property. If the boot loader doesn't provide
1883 any, the device tree bootargs property will be used.
1885 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1886 bool "Extend with bootloader kernel arguments"
1888 The command-line arguments provided by the boot loader will be
1889 appended to the the device tree bootargs property.
1894 string "Default kernel command string"
1897 On some architectures (EBSA110 and CATS), there is currently no way
1898 for the boot loader to pass arguments to the kernel. For these
1899 architectures, you should supply some command-line options at build
1900 time by entering them here. As a minimum, you should specify the
1901 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1904 prompt "Kernel command line type" if CMDLINE != ""
1905 default CMDLINE_FROM_BOOTLOADER
1908 config CMDLINE_FROM_BOOTLOADER
1909 bool "Use bootloader kernel arguments if available"
1911 Uses the command-line options passed by the boot loader. If
1912 the boot loader doesn't provide any, the default kernel command
1913 string provided in CMDLINE will be used.
1915 config CMDLINE_EXTEND
1916 bool "Extend bootloader kernel arguments"
1918 The command-line arguments provided by the boot loader will be
1919 appended to the default kernel command string.
1921 config CMDLINE_FORCE
1922 bool "Always use the default kernel command string"
1924 Always use the default kernel command string, even if the boot
1925 loader passes other arguments to the kernel.
1926 This is useful if you cannot or don't want to change the
1927 command-line options your boot loader passes to the kernel.
1931 bool "Kernel Execute-In-Place from ROM"
1932 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1934 Execute-In-Place allows the kernel to run from non-volatile storage
1935 directly addressable by the CPU, such as NOR flash. This saves RAM
1936 space since the text section of the kernel is not loaded from flash
1937 to RAM. Read-write sections, such as the data section and stack,
1938 are still copied to RAM. The XIP kernel is not compressed since
1939 it has to run directly from flash, so it will take more space to
1940 store it. The flash address used to link the kernel object files,
1941 and for storing it, is configuration dependent. Therefore, if you
1942 say Y here, you must know the proper physical address where to
1943 store the kernel image depending on your own flash memory usage.
1945 Also note that the make target becomes "make xipImage" rather than
1946 "make zImage" or "make Image". The final kernel binary to put in
1947 ROM memory will be arch/arm/boot/xipImage.
1951 config XIP_PHYS_ADDR
1952 hex "XIP Kernel Physical Location"
1953 depends on XIP_KERNEL
1954 default "0x00080000"
1956 This is the physical address in your flash memory the kernel will
1957 be linked for and stored to. This address is dependent on your
1961 bool "Kexec system call (EXPERIMENTAL)"
1962 depends on (!SMP || PM_SLEEP_SMP)
1966 kexec is a system call that implements the ability to shutdown your
1967 current kernel, and to start another kernel. It is like a reboot
1968 but it is independent of the system firmware. And like a reboot
1969 you can start any kernel with it, not just Linux.
1971 It is an ongoing process to be certain the hardware in a machine
1972 is properly shutdown, so do not be surprised if this code does not
1973 initially work for you.
1976 bool "Export atags in procfs"
1977 depends on ATAGS && KEXEC
1980 Should the atags used to boot the kernel be exported in an "atags"
1981 file in procfs. Useful with kexec.
1984 bool "Build kdump crash kernel (EXPERIMENTAL)"
1986 Generate crash dump after being started by kexec. This should
1987 be normally only set in special crash dump kernels which are
1988 loaded in the main kernel with kexec-tools into a specially
1989 reserved region and then later executed after a crash by
1990 kdump/kexec. The crash dump kernel must be compiled to a
1991 memory address not used by the main kernel
1993 For more details see Documentation/kdump/kdump.txt
1995 config AUTO_ZRELADDR
1996 bool "Auto calculation of the decompressed kernel image address"
1998 ZRELADDR is the physical address where the decompressed kernel
1999 image will be placed. If AUTO_ZRELADDR is selected, the address
2000 will be determined at run-time by masking the current IP with
2001 0xf8000000. This assumes the zImage being placed in the first 128MB
2002 from start of memory.
2008 bool "UEFI runtime support"
2009 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
2011 select EFI_PARAMS_FROM_FDT
2014 select EFI_RUNTIME_WRAPPERS
2016 This option provides support for runtime services provided
2017 by UEFI firmware (such as non-volatile variables, realtime
2018 clock, and platform reset). A UEFI stub is also provided to
2019 allow the kernel to be booted as an EFI application. This
2020 is only useful for kernels that may run on systems that have
2025 menu "CPU Power Management"
2027 source "drivers/cpufreq/Kconfig"
2029 source "drivers/cpuidle/Kconfig"
2033 menu "Floating point emulation"
2035 comment "At least one emulation must be selected"
2038 bool "NWFPE math emulation"
2039 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2041 Say Y to include the NWFPE floating point emulator in the kernel.
2042 This is necessary to run most binaries. Linux does not currently
2043 support floating point hardware so you need to say Y here even if
2044 your machine has an FPA or floating point co-processor podule.
2046 You may say N here if you are going to load the Acorn FPEmulator
2047 early in the bootup.
2050 bool "Support extended precision"
2051 depends on FPE_NWFPE
2053 Say Y to include 80-bit support in the kernel floating-point
2054 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2055 Note that gcc does not generate 80-bit operations by default,
2056 so in most cases this option only enlarges the size of the
2057 floating point emulator without any good reason.
2059 You almost surely want to say N here.
2062 bool "FastFPE math emulation (EXPERIMENTAL)"
2063 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2065 Say Y here to include the FAST floating point emulator in the kernel.
2066 This is an experimental much faster emulator which now also has full
2067 precision for the mantissa. It does not support any exceptions.
2068 It is very simple, and approximately 3-6 times faster than NWFPE.
2070 It should be sufficient for most programs. It may be not suitable
2071 for scientific calculations, but you have to check this for yourself.
2072 If you do not feel you need a faster FP emulation you should better
2076 bool "VFP-format floating point maths"
2077 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2079 Say Y to include VFP support code in the kernel. This is needed
2080 if your hardware includes a VFP unit.
2082 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2083 release notes and additional status information.
2085 Say N if your target does not have VFP hardware.
2093 bool "Advanced SIMD (NEON) Extension support"
2094 depends on VFPv3 && CPU_V7
2096 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2099 config KERNEL_MODE_NEON
2100 bool "Support for NEON in kernel mode"
2101 depends on NEON && AEABI
2103 Say Y to include support for NEON in kernel mode.
2107 menu "Userspace binary formats"
2109 source "fs/Kconfig.binfmt"
2113 menu "Power management options"
2115 source "kernel/power/Kconfig"
2117 config ARCH_SUSPEND_POSSIBLE
2118 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2119 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2122 config ARM_CPU_SUSPEND
2123 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
2124 depends on ARCH_SUSPEND_POSSIBLE
2126 config ARCH_HIBERNATION_POSSIBLE
2129 default y if ARCH_SUSPEND_POSSIBLE
2133 source "net/Kconfig"
2135 source "drivers/Kconfig"
2137 source "drivers/firmware/Kconfig"
2141 source "arch/arm/Kconfig.debug"
2143 source "security/Kconfig"
2145 source "crypto/Kconfig"
2147 source "arch/arm/crypto/Kconfig"
2150 source "lib/Kconfig"
2152 source "arch/arm/kvm/Kconfig"