4 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
5 select ARCH_HAS_DEVMEM_IS_ALLOWED
6 select ARCH_HAS_ELF_RANDOMIZE
7 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
8 select ARCH_HAVE_CUSTOM_GPIO_H
9 select ARCH_HAS_GCOV_PROFILE_ALL
10 select ARCH_MIGHT_HAVE_PC_PARPORT
11 select ARCH_SUPPORTS_ATOMIC_RMW
12 select ARCH_USE_BUILTIN_BSWAP
13 select ARCH_USE_CMPXCHG_LOCKREF
14 select ARCH_WANT_IPC_PARSE_VERSION
15 select BUILDTIME_EXTABLE_SORT if MMU
16 select CLONE_BACKWARDS
17 select CPU_PM if (SUSPEND || CPU_IDLE)
18 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
20 select EDAC_ATOMIC_SCRUB
21 select GENERIC_ALLOCATOR
22 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
23 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
24 select GENERIC_EARLY_IOREMAP
25 select GENERIC_IDLE_POLL_SETUP
26 select GENERIC_IRQ_PROBE
27 select GENERIC_IRQ_SHOW
28 select GENERIC_IRQ_SHOW_LEVEL
29 select GENERIC_PCI_IOMAP
30 select GENERIC_SCHED_CLOCK
31 select GENERIC_SMP_IDLE_THREAD
32 select GENERIC_STRNCPY_FROM_USER
33 select GENERIC_STRNLEN_USER
34 select HANDLE_DOMAIN_IRQ
35 select HARDIRQS_SW_RESEND
36 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
37 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
38 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
39 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
40 select HAVE_ARCH_MMAP_RND_BITS if MMU
41 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
42 select HAVE_ARCH_TRACEHOOK
43 select HAVE_ARM_SMCCC if CPU_V7
45 select HAVE_CC_STACKPROTECTOR
46 select HAVE_CONTEXT_TRACKING
47 select HAVE_C_RECORDMCOUNT
48 select HAVE_DEBUG_KMEMLEAK
49 select HAVE_DMA_API_DEBUG
51 select HAVE_DMA_CONTIGUOUS if MMU
52 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32 && MMU
53 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
54 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
55 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
56 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
57 select HAVE_GENERIC_DMA_COHERENT
58 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
59 select HAVE_IDE if PCI || ISA || PCMCIA
60 select HAVE_IRQ_TIME_ACCOUNTING
61 select HAVE_KERNEL_GZIP
62 select HAVE_KERNEL_LZ4
63 select HAVE_KERNEL_LZMA
64 select HAVE_KERNEL_LZO
66 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
67 select HAVE_KRETPROBES if (HAVE_KPROBES)
69 select HAVE_MOD_ARCH_SPECIFIC
70 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
71 select HAVE_OPTPROBES if !THUMB2_KERNEL
72 select HAVE_PERF_EVENTS
74 select HAVE_PERF_USER_STACK_DUMP
75 select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
76 select HAVE_REGS_AND_STACK_ACCESS_API
77 select HAVE_SYSCALL_TRACEPOINTS
79 select HAVE_VIRT_CPU_ACCOUNTING_GEN
80 select IRQ_FORCED_THREADING
81 select MODULES_USE_ELF_REL
83 select OF_EARLY_FLATTREE if OF
84 select OF_RESERVED_MEM if OF
86 select OLD_SIGSUSPEND3
87 select PERF_USE_VMALLOC
89 select SYS_SUPPORTS_APM_EMULATION
90 # Above selects are sorted alphabetically; please add new ones
91 # according to that. Thanks.
93 The ARM series is a line of low-power-consumption RISC chip designs
94 licensed by ARM Ltd and targeted at embedded applications and
95 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
96 manufactured, but legacy ARM-based PC hardware remains popular in
97 Europe. There is an ARM Linux project with a web page at
98 <http://www.arm.linux.org.uk/>.
100 config ARM_HAS_SG_CHAIN
101 select ARCH_HAS_SG_CHAIN
104 config NEED_SG_DMA_LENGTH
107 config ARM_DMA_USE_IOMMU
109 select ARM_HAS_SG_CHAIN
110 select NEED_SG_DMA_LENGTH
114 config ARM_DMA_IOMMU_ALIGNMENT
115 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
119 DMA mapping framework by default aligns all buffers to the smallest
120 PAGE_SIZE order which is greater than or equal to the requested buffer
121 size. This works well for buffers up to a few hundreds kilobytes, but
122 for larger buffers it just a waste of address space. Drivers which has
123 relatively small addressing window (like 64Mib) might run out of
124 virtual space with just a few allocations.
126 With this parameter you can specify the maximum PAGE_SIZE order for
127 DMA IOMMU buffers. Larger buffers will be aligned only to this
128 specified order. The order is expressed as a power of two multiplied
133 config MIGHT_HAVE_PCI
136 config SYS_SUPPORTS_APM_EMULATION
141 select GENERIC_ALLOCATOR
152 The Extended Industry Standard Architecture (EISA) bus was
153 developed as an open alternative to the IBM MicroChannel bus.
155 The EISA bus provided some of the features of the IBM MicroChannel
156 bus while maintaining backward compatibility with cards made for
157 the older ISA bus. The EISA bus saw limited use between 1988 and
158 1995 when it was made obsolete by the PCI bus.
160 Say Y here if you are building a kernel for an EISA-based machine.
167 config STACKTRACE_SUPPORT
171 config LOCKDEP_SUPPORT
175 config TRACE_IRQFLAGS_SUPPORT
179 config RWSEM_XCHGADD_ALGORITHM
183 config ARCH_HAS_ILOG2_U32
186 config ARCH_HAS_ILOG2_U64
189 config ARCH_HAS_BANDGAP
192 config FIX_EARLYCON_MEM
195 config GENERIC_HWEIGHT
199 config GENERIC_CALIBRATE_DELAY
203 config ARCH_MAY_HAVE_PC_FDC
209 config NEED_DMA_MAP_STATE
212 config ARCH_SUPPORTS_UPROBES
215 config ARCH_HAS_DMA_SET_COHERENT_MASK
218 config GENERIC_ISA_DMA
224 config NEED_RET_TO_USER
232 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
233 default DRAM_BASE if REMAP_VECTORS_TO_RAM
236 The base address of exception vectors. This must be two pages
239 config ARM_PATCH_PHYS_VIRT
240 bool "Patch physical to virtual translations at runtime" if EMBEDDED
242 depends on !XIP_KERNEL && MMU
244 Patch phys-to-virt and virt-to-phys translation functions at
245 boot and module load time according to the position of the
246 kernel in system memory.
248 This can only be used with non-XIP MMU kernels where the base
249 of physical memory is at a 16MB boundary.
251 Only disable this option if you know that you do not require
252 this feature (eg, building a kernel for a single machine) and
253 you need to shrink the kernel to the minimal size.
255 config NEED_MACH_IO_H
258 Select this when mach/io.h is required to provide special
259 definitions for this platform. The need for mach/io.h should
260 be avoided when possible.
262 config NEED_MACH_MEMORY_H
265 Select this when mach/memory.h is required to provide special
266 definitions for this platform. The need for mach/memory.h should
267 be avoided when possible.
270 hex "Physical address of main memory" if MMU
271 depends on !ARM_PATCH_PHYS_VIRT
272 default DRAM_BASE if !MMU
273 default 0x00000000 if ARCH_EBSA110 || \
278 (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET)
279 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
280 default 0x20000000 if ARCH_S5PV210
281 default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET
282 default 0xc0000000 if ARCH_SA1100
284 Please provide the physical address corresponding to the
285 location of main memory in your system.
291 config PGTABLE_LEVELS
293 default 3 if ARM_LPAE
296 source "init/Kconfig"
298 source "kernel/Kconfig.freezer"
303 bool "MMU-based Paged Memory Management Support"
306 Select if you want MMU-based virtualised addressing space
307 support by paged memory management. If unsure, say 'Y'.
309 config ARCH_MMAP_RND_BITS_MIN
312 config ARCH_MMAP_RND_BITS_MAX
313 default 14 if PAGE_OFFSET=0x40000000
314 default 15 if PAGE_OFFSET=0x80000000
318 # The "ARM system type" choice list is ordered alphabetically by option
319 # text. Please add new entries in the option alphabetic order.
322 prompt "ARM system type"
323 default ARM_SINGLE_ARMV7M if !MMU
324 default ARCH_MULTIPLATFORM if MMU
326 config ARCH_MULTIPLATFORM
327 bool "Allow multiple platforms to be selected"
329 select ARCH_WANT_OPTIONAL_GPIOLIB
330 select ARM_HAS_SG_CHAIN
331 select ARM_PATCH_PHYS_VIRT
335 select GENERIC_CLOCKEVENTS
336 select MIGHT_HAVE_PCI
337 select MULTI_IRQ_HANDLER
341 config ARM_SINGLE_ARMV7M
342 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
344 select ARCH_WANT_OPTIONAL_GPIOLIB
350 select GENERIC_CLOCKEVENTS
357 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
358 select ARCH_REQUIRE_GPIOLIB
363 select GENERIC_CLOCKEVENTS
367 Support for Cirrus Logic 711x/721x/731x based boards.
370 bool "Cortina Systems Gemini"
371 select ARCH_REQUIRE_GPIOLIB
374 select GENERIC_CLOCKEVENTS
376 Support for the Cortina Systems Gemini family SoCs
380 select ARCH_USES_GETTIMEOFFSET
383 select NEED_MACH_IO_H
384 select NEED_MACH_MEMORY_H
387 This is an evaluation board for the StrongARM processor available
388 from Digital. It has limited hardware on-board, including an
389 Ethernet interface, two PCMCIA sockets, two serial ports and a
394 select ARCH_HAS_HOLES_MEMORYMODEL
395 select ARCH_REQUIRE_GPIOLIB
397 select ARM_PATCH_PHYS_VIRT
403 select GENERIC_CLOCKEVENTS
405 This enables support for the Cirrus EP93xx series of CPUs.
407 config ARCH_FOOTBRIDGE
411 select GENERIC_CLOCKEVENTS
413 select NEED_MACH_IO_H if !MMU
414 select NEED_MACH_MEMORY_H
416 Support for systems based on the DC21285 companion chip
417 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
420 bool "Hilscher NetX based"
424 select GENERIC_CLOCKEVENTS
426 This enables support for systems based on the Hilscher NetX Soc
432 select NEED_MACH_MEMORY_H
433 select NEED_RET_TO_USER
439 Support for Intel's IOP13XX (XScale) family of processors.
444 select ARCH_REQUIRE_GPIOLIB
447 select NEED_RET_TO_USER
451 Support for Intel's 80219 and IOP32X (XScale) family of
457 select ARCH_REQUIRE_GPIOLIB
460 select NEED_RET_TO_USER
464 Support for Intel's IOP33X (XScale) family of processors.
469 select ARCH_HAS_DMA_SET_COHERENT_MASK
470 select ARCH_REQUIRE_GPIOLIB
471 select ARCH_SUPPORTS_BIG_ENDIAN
474 select DMABOUNCE if PCI
475 select GENERIC_CLOCKEVENTS
476 select MIGHT_HAVE_PCI
477 select NEED_MACH_IO_H
478 select USB_EHCI_BIG_ENDIAN_DESC
479 select USB_EHCI_BIG_ENDIAN_MMIO
481 Support for Intel's IXP4XX (XScale) family of processors.
485 select ARCH_REQUIRE_GPIOLIB
487 select GENERIC_CLOCKEVENTS
488 select MIGHT_HAVE_PCI
489 select MULTI_IRQ_HANDLER
493 select PLAT_ORION_LEGACY
495 select PM_GENERIC_DOMAINS if PM
497 Support for the Marvell Dove SoC 88AP510
500 bool "Micrel/Kendin KS8695"
501 select ARCH_REQUIRE_GPIOLIB
504 select GENERIC_CLOCKEVENTS
505 select NEED_MACH_MEMORY_H
507 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
508 System-on-Chip devices.
511 bool "Nuvoton W90X900 CPU"
512 select ARCH_REQUIRE_GPIOLIB
516 select GENERIC_CLOCKEVENTS
518 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
519 At present, the w90x900 has been renamed nuc900, regarding
520 the ARM series product line, you can login the following
521 link address to know more.
523 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
524 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
528 select ARCH_REQUIRE_GPIOLIB
533 select GENERIC_CLOCKEVENTS
537 Support for the NXP LPC32XX family of processors
540 bool "PXA2xx/PXA3xx-based"
543 select ARCH_REQUIRE_GPIOLIB
544 select ARM_CPU_SUSPEND if PM
551 select GENERIC_CLOCKEVENTS
555 select MULTI_IRQ_HANDLER
559 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
565 select ARCH_MAY_HAVE_PC_FDC
566 select ARCH_SPARSEMEM_ENABLE
567 select ARCH_USES_GETTIMEOFFSET
571 select HAVE_PATA_PLATFORM
573 select NEED_MACH_IO_H
574 select NEED_MACH_MEMORY_H
578 On the Acorn Risc-PC, Linux can support the internal IDE disk and
579 CD-ROM interface, serial and parallel port, and the floppy drive.
584 select ARCH_REQUIRE_GPIOLIB
585 select ARCH_SPARSEMEM_ENABLE
589 select CLKSRC_OF if OF
592 select GENERIC_CLOCKEVENTS
596 select MULTI_IRQ_HANDLER
597 select NEED_MACH_MEMORY_H
600 Support for StrongARM 11x0 based boards.
603 bool "Samsung S3C24XX SoCs"
604 select ARCH_REQUIRE_GPIOLIB
607 select CLKSRC_SAMSUNG_PWM
608 select GENERIC_CLOCKEVENTS
610 select HAVE_S3C2410_I2C if I2C
611 select HAVE_S3C2410_WATCHDOG if WATCHDOG
612 select HAVE_S3C_RTC if RTC_CLASS
613 select MULTI_IRQ_HANDLER
614 select NEED_MACH_IO_H
617 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
618 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
619 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
620 Samsung SMDK2410 development board (and derivatives).
624 select ARCH_HAS_HOLES_MEMORYMODEL
625 select ARCH_REQUIRE_GPIOLIB
627 select GENERIC_ALLOCATOR
628 select GENERIC_CLOCKEVENTS
629 select GENERIC_IRQ_CHIP
634 Support for TI's DaVinci platform.
639 select ARCH_HAS_HOLES_MEMORYMODEL
641 select ARCH_REQUIRE_GPIOLIB
644 select GENERIC_CLOCKEVENTS
645 select GENERIC_IRQ_CHIP
648 select MULTI_IRQ_HANDLER
649 select NEED_MACH_IO_H if PCCARD
650 select NEED_MACH_MEMORY_H
653 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
657 menu "Multiple platform selection"
658 depends on ARCH_MULTIPLATFORM
660 comment "CPU Core family selection"
663 bool "ARMv4 based platforms (FA526)"
664 depends on !ARCH_MULTI_V6_V7
665 select ARCH_MULTI_V4_V5
668 config ARCH_MULTI_V4T
669 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
670 depends on !ARCH_MULTI_V6_V7
671 select ARCH_MULTI_V4_V5
672 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
673 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
674 CPU_ARM925T || CPU_ARM940T)
677 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
678 depends on !ARCH_MULTI_V6_V7
679 select ARCH_MULTI_V4_V5
680 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
681 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
682 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
684 config ARCH_MULTI_V4_V5
688 bool "ARMv6 based platforms (ARM11)"
689 select ARCH_MULTI_V6_V7
693 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
695 select ARCH_MULTI_V6_V7
699 config ARCH_MULTI_V6_V7
701 select MIGHT_HAVE_CACHE_L2X0
703 config ARCH_MULTI_CPU_AUTO
704 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
710 bool "Dummy Virtual Machine"
711 depends on ARCH_MULTI_V7
714 select ARM_GIC_V2M if PCI_MSI
717 select HAVE_ARM_ARCH_TIMER
720 # This is sorted alphabetically by mach-* pathname. However, plat-*
721 # Kconfigs may be included either alphabetically (according to the
722 # plat- suffix) or along side the corresponding mach-* source.
724 source "arch/arm/mach-mvebu/Kconfig"
726 source "arch/arm/mach-alpine/Kconfig"
728 source "arch/arm/mach-asm9260/Kconfig"
730 source "arch/arm/mach-at91/Kconfig"
732 source "arch/arm/mach-axxia/Kconfig"
734 source "arch/arm/mach-bcm/Kconfig"
736 source "arch/arm/mach-berlin/Kconfig"
738 source "arch/arm/mach-clps711x/Kconfig"
740 source "arch/arm/mach-cns3xxx/Kconfig"
742 source "arch/arm/mach-davinci/Kconfig"
744 source "arch/arm/mach-digicolor/Kconfig"
746 source "arch/arm/mach-dove/Kconfig"
748 source "arch/arm/mach-ep93xx/Kconfig"
750 source "arch/arm/mach-footbridge/Kconfig"
752 source "arch/arm/mach-gemini/Kconfig"
754 source "arch/arm/mach-highbank/Kconfig"
756 source "arch/arm/mach-hisi/Kconfig"
758 source "arch/arm/mach-integrator/Kconfig"
760 source "arch/arm/mach-iop32x/Kconfig"
762 source "arch/arm/mach-iop33x/Kconfig"
764 source "arch/arm/mach-iop13xx/Kconfig"
766 source "arch/arm/mach-ixp4xx/Kconfig"
768 source "arch/arm/mach-keystone/Kconfig"
770 source "arch/arm/mach-ks8695/Kconfig"
772 source "arch/arm/mach-meson/Kconfig"
774 source "arch/arm/mach-moxart/Kconfig"
776 source "arch/arm/mach-mv78xx0/Kconfig"
778 source "arch/arm/mach-imx/Kconfig"
780 source "arch/arm/mach-mediatek/Kconfig"
782 source "arch/arm/mach-mxs/Kconfig"
784 source "arch/arm/mach-netx/Kconfig"
786 source "arch/arm/mach-nomadik/Kconfig"
788 source "arch/arm/mach-nspire/Kconfig"
790 source "arch/arm/plat-omap/Kconfig"
792 source "arch/arm/mach-omap1/Kconfig"
794 source "arch/arm/mach-omap2/Kconfig"
796 source "arch/arm/mach-orion5x/Kconfig"
798 source "arch/arm/mach-picoxcell/Kconfig"
800 source "arch/arm/mach-pxa/Kconfig"
801 source "arch/arm/plat-pxa/Kconfig"
803 source "arch/arm/mach-mmp/Kconfig"
805 source "arch/arm/mach-qcom/Kconfig"
807 source "arch/arm/mach-realview/Kconfig"
809 source "arch/arm/mach-rockchip/Kconfig"
811 source "arch/arm/mach-sa1100/Kconfig"
813 source "arch/arm/mach-socfpga/Kconfig"
815 source "arch/arm/mach-spear/Kconfig"
817 source "arch/arm/mach-sti/Kconfig"
819 source "arch/arm/mach-s3c24xx/Kconfig"
821 source "arch/arm/mach-s3c64xx/Kconfig"
823 source "arch/arm/mach-s5pv210/Kconfig"
825 source "arch/arm/mach-exynos/Kconfig"
826 source "arch/arm/plat-samsung/Kconfig"
828 source "arch/arm/mach-shmobile/Kconfig"
830 source "arch/arm/mach-sunxi/Kconfig"
832 source "arch/arm/mach-prima2/Kconfig"
834 source "arch/arm/mach-tango/Kconfig"
836 source "arch/arm/mach-tegra/Kconfig"
838 source "arch/arm/mach-u300/Kconfig"
840 source "arch/arm/mach-uniphier/Kconfig"
842 source "arch/arm/mach-ux500/Kconfig"
844 source "arch/arm/mach-versatile/Kconfig"
846 source "arch/arm/mach-vexpress/Kconfig"
847 source "arch/arm/plat-versatile/Kconfig"
849 source "arch/arm/mach-vt8500/Kconfig"
851 source "arch/arm/mach-w90x900/Kconfig"
853 source "arch/arm/mach-zx/Kconfig"
855 source "arch/arm/mach-zynq/Kconfig"
857 # ARMv7-M architecture
859 bool "Energy Micro efm32"
860 depends on ARM_SINGLE_ARMV7M
861 select ARCH_REQUIRE_GPIOLIB
863 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
867 bool "NXP LPC18xx/LPC43xx"
868 depends on ARM_SINGLE_ARMV7M
869 select ARCH_HAS_RESET_CONTROLLER
871 select CLKSRC_LPC32XX
874 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
875 high performance microcontrollers.
878 bool "STMicrolectronics STM32"
879 depends on ARM_SINGLE_ARMV7M
880 select ARCH_HAS_RESET_CONTROLLER
881 select ARMV7M_SYSTICK
883 select RESET_CONTROLLER
885 Support for STMicroelectronics STM32 processors.
887 # Definitions to make life easier
893 select GENERIC_CLOCKEVENTS
899 select GENERIC_IRQ_CHIP
902 config PLAT_ORION_LEGACY
909 config PLAT_VERSATILE
912 source "arch/arm/firmware/Kconfig"
914 source arch/arm/mm/Kconfig
917 bool "Enable iWMMXt support"
918 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
919 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
921 Enable support for iWMMXt context switching at run time if
922 running on a CPU that supports it.
924 config MULTI_IRQ_HANDLER
927 Allow each machine to specify it's own IRQ handler at run time.
930 source "arch/arm/Kconfig-nommu"
933 config PJ4B_ERRATA_4742
934 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
935 depends on CPU_PJ4B && MACH_ARMADA_370
938 When coming out of either a Wait for Interrupt (WFI) or a Wait for
939 Event (WFE) IDLE states, a specific timing sensitivity exists between
940 the retiring WFI/WFE instructions and the newly issued subsequent
941 instructions. This sensitivity can result in a CPU hang scenario.
943 The software must insert either a Data Synchronization Barrier (DSB)
944 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
947 config ARM_ERRATA_326103
948 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
951 Executing a SWP instruction to read-only memory does not set bit 11
952 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
953 treat the access as a read, preventing a COW from occurring and
954 causing the faulting task to livelock.
956 config ARM_ERRATA_411920
957 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
958 depends on CPU_V6 || CPU_V6K
960 Invalidation of the Instruction Cache operation can
961 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
962 It does not affect the MPCore. This option enables the ARM Ltd.
963 recommended workaround.
965 config ARM_ERRATA_430973
966 bool "ARM errata: Stale prediction on replaced interworking branch"
969 This option enables the workaround for the 430973 Cortex-A8
970 r1p* erratum. If a code sequence containing an ARM/Thumb
971 interworking branch is replaced with another code sequence at the
972 same virtual address, whether due to self-modifying code or virtual
973 to physical address re-mapping, Cortex-A8 does not recover from the
974 stale interworking branch prediction. This results in Cortex-A8
975 executing the new code sequence in the incorrect ARM or Thumb state.
976 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
977 and also flushes the branch target cache at every context switch.
978 Note that setting specific bits in the ACTLR register may not be
979 available in non-secure mode.
981 config ARM_ERRATA_458693
982 bool "ARM errata: Processor deadlock when a false hazard is created"
984 depends on !ARCH_MULTIPLATFORM
986 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
987 erratum. For very specific sequences of memory operations, it is
988 possible for a hazard condition intended for a cache line to instead
989 be incorrectly associated with a different cache line. This false
990 hazard might then cause a processor deadlock. The workaround enables
991 the L1 caching of the NEON accesses and disables the PLD instruction
992 in the ACTLR register. Note that setting specific bits in the ACTLR
993 register may not be available in non-secure mode.
995 config ARM_ERRATA_460075
996 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
998 depends on !ARCH_MULTIPLATFORM
1000 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1001 erratum. Any asynchronous access to the L2 cache may encounter a
1002 situation in which recent store transactions to the L2 cache are lost
1003 and overwritten with stale memory contents from external memory. The
1004 workaround disables the write-allocate mode for the L2 cache via the
1005 ACTLR register. Note that setting specific bits in the ACTLR register
1006 may not be available in non-secure mode.
1008 config ARM_ERRATA_742230
1009 bool "ARM errata: DMB operation may be faulty"
1010 depends on CPU_V7 && SMP
1011 depends on !ARCH_MULTIPLATFORM
1013 This option enables the workaround for the 742230 Cortex-A9
1014 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1015 between two write operations may not ensure the correct visibility
1016 ordering of the two writes. This workaround sets a specific bit in
1017 the diagnostic register of the Cortex-A9 which causes the DMB
1018 instruction to behave as a DSB, ensuring the correct behaviour of
1021 config ARM_ERRATA_742231
1022 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1023 depends on CPU_V7 && SMP
1024 depends on !ARCH_MULTIPLATFORM
1026 This option enables the workaround for the 742231 Cortex-A9
1027 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1028 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1029 accessing some data located in the same cache line, may get corrupted
1030 data due to bad handling of the address hazard when the line gets
1031 replaced from one of the CPUs at the same time as another CPU is
1032 accessing it. This workaround sets specific bits in the diagnostic
1033 register of the Cortex-A9 which reduces the linefill issuing
1034 capabilities of the processor.
1036 config ARM_ERRATA_643719
1037 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1038 depends on CPU_V7 && SMP
1041 This option enables the workaround for the 643719 Cortex-A9 (prior to
1042 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1043 register returns zero when it should return one. The workaround
1044 corrects this value, ensuring cache maintenance operations which use
1045 it behave as intended and avoiding data corruption.
1047 config ARM_ERRATA_720789
1048 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1051 This option enables the workaround for the 720789 Cortex-A9 (prior to
1052 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1053 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1054 As a consequence of this erratum, some TLB entries which should be
1055 invalidated are not, resulting in an incoherency in the system page
1056 tables. The workaround changes the TLB flushing routines to invalidate
1057 entries regardless of the ASID.
1059 config ARM_ERRATA_743622
1060 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1062 depends on !ARCH_MULTIPLATFORM
1064 This option enables the workaround for the 743622 Cortex-A9
1065 (r2p*) erratum. Under very rare conditions, a faulty
1066 optimisation in the Cortex-A9 Store Buffer may lead to data
1067 corruption. This workaround sets a specific bit in the diagnostic
1068 register of the Cortex-A9 which disables the Store Buffer
1069 optimisation, preventing the defect from occurring. This has no
1070 visible impact on the overall performance or power consumption of the
1073 config ARM_ERRATA_751472
1074 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1076 depends on !ARCH_MULTIPLATFORM
1078 This option enables the workaround for the 751472 Cortex-A9 (prior
1079 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1080 completion of a following broadcasted operation if the second
1081 operation is received by a CPU before the ICIALLUIS has completed,
1082 potentially leading to corrupted entries in the cache or TLB.
1084 config ARM_ERRATA_754322
1085 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1088 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1089 r3p*) erratum. A speculative memory access may cause a page table walk
1090 which starts prior to an ASID switch but completes afterwards. This
1091 can populate the micro-TLB with a stale entry which may be hit with
1092 the new ASID. This workaround places two dsb instructions in the mm
1093 switching code so that no page table walks can cross the ASID switch.
1095 config ARM_ERRATA_754327
1096 bool "ARM errata: no automatic Store Buffer drain"
1097 depends on CPU_V7 && SMP
1099 This option enables the workaround for the 754327 Cortex-A9 (prior to
1100 r2p0) erratum. The Store Buffer does not have any automatic draining
1101 mechanism and therefore a livelock may occur if an external agent
1102 continuously polls a memory location waiting to observe an update.
1103 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1104 written polling loops from denying visibility of updates to memory.
1106 config ARM_ERRATA_364296
1107 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1110 This options enables the workaround for the 364296 ARM1136
1111 r0p2 erratum (possible cache data corruption with
1112 hit-under-miss enabled). It sets the undocumented bit 31 in
1113 the auxiliary control register and the FI bit in the control
1114 register, thus disabling hit-under-miss without putting the
1115 processor into full low interrupt latency mode. ARM11MPCore
1118 config ARM_ERRATA_764369
1119 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1120 depends on CPU_V7 && SMP
1122 This option enables the workaround for erratum 764369
1123 affecting Cortex-A9 MPCore with two or more processors (all
1124 current revisions). Under certain timing circumstances, a data
1125 cache line maintenance operation by MVA targeting an Inner
1126 Shareable memory region may fail to proceed up to either the
1127 Point of Coherency or to the Point of Unification of the
1128 system. This workaround adds a DSB instruction before the
1129 relevant cache maintenance functions and sets a specific bit
1130 in the diagnostic control register of the SCU.
1132 config ARM_ERRATA_775420
1133 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1136 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1137 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1138 operation aborts with MMU exception, it might cause the processor
1139 to deadlock. This workaround puts DSB before executing ISB if
1140 an abort may occur on cache maintenance.
1142 config ARM_ERRATA_798181
1143 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1144 depends on CPU_V7 && SMP
1146 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1147 adequately shooting down all use of the old entries. This
1148 option enables the Linux kernel workaround for this erratum
1149 which sends an IPI to the CPUs that are running the same ASID
1150 as the one being invalidated.
1152 config ARM_ERRATA_773022
1153 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1156 This option enables the workaround for the 773022 Cortex-A15
1157 (up to r0p4) erratum. In certain rare sequences of code, the
1158 loop buffer may deliver incorrect instructions. This
1159 workaround disables the loop buffer to avoid the erratum.
1163 source "arch/arm/common/Kconfig"
1170 Find out whether you have ISA slots on your motherboard. ISA is the
1171 name of a bus system, i.e. the way the CPU talks to the other stuff
1172 inside your box. Other bus systems are PCI, EISA, MicroChannel
1173 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1174 newer boards don't support it. If you have ISA, say Y, otherwise N.
1176 # Select ISA DMA controller support
1181 # Select ISA DMA interface
1186 bool "PCI support" if MIGHT_HAVE_PCI
1188 Find out whether you have a PCI motherboard. PCI is the name of a
1189 bus system, i.e. the way the CPU talks to the other stuff inside
1190 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1191 VESA. If you have PCI, say Y, otherwise N.
1197 config PCI_DOMAINS_GENERIC
1198 def_bool PCI_DOMAINS
1200 config PCI_NANOENGINE
1201 bool "BSE nanoEngine PCI support"
1202 depends on SA1100_NANOENGINE
1204 Enable PCI on the BSE nanoEngine board.
1209 config PCI_HOST_ITE8152
1211 depends on PCI && MACH_ARMCORE
1215 source "drivers/pci/Kconfig"
1216 source "drivers/pci/pcie/Kconfig"
1218 source "drivers/pcmcia/Kconfig"
1222 menu "Kernel Features"
1227 This option should be selected by machines which have an SMP-
1230 The only effect of this option is to make the SMP-related
1231 options available to the user for configuration.
1234 bool "Symmetric Multi-Processing"
1235 depends on CPU_V6K || CPU_V7
1236 depends on GENERIC_CLOCKEVENTS
1238 depends on MMU || ARM_MPU
1241 This enables support for systems with more than one CPU. If you have
1242 a system with only one CPU, say N. If you have a system with more
1243 than one CPU, say Y.
1245 If you say N here, the kernel will run on uni- and multiprocessor
1246 machines, but will use only one CPU of a multiprocessor machine. If
1247 you say Y here, the kernel will run on many, but not all,
1248 uniprocessor machines. On a uniprocessor machine, the kernel
1249 will run faster if you say N here.
1251 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1252 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1253 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1255 If you don't know what to do here, say N.
1258 bool "Allow booting SMP kernel on uniprocessor systems"
1259 depends on SMP && !XIP_KERNEL && MMU
1262 SMP kernels contain instructions which fail on non-SMP processors.
1263 Enabling this option allows the kernel to modify itself to make
1264 these instructions safe. Disabling it allows about 1K of space
1267 If you don't know what to do here, say Y.
1269 config ARM_CPU_TOPOLOGY
1270 bool "Support cpu topology definition"
1271 depends on SMP && CPU_V7
1274 Support ARM cpu topology definition. The MPIDR register defines
1275 affinity between processors which is then used to describe the cpu
1276 topology of an ARM System.
1279 bool "Multi-core scheduler support"
1280 depends on ARM_CPU_TOPOLOGY
1282 Multi-core scheduler support improves the CPU scheduler's decision
1283 making when dealing with multi-core CPU chips at a cost of slightly
1284 increased overhead in some places. If unsure say N here.
1287 bool "SMT scheduler support"
1288 depends on ARM_CPU_TOPOLOGY
1290 Improves the CPU scheduler's decision making when dealing with
1291 MultiThreading at a cost of slightly increased overhead in some
1292 places. If unsure say N here.
1297 This option enables support for the ARM system coherency unit
1299 config HAVE_ARM_ARCH_TIMER
1300 bool "Architected timer support"
1302 select ARM_ARCH_TIMER
1303 select GENERIC_CLOCKEVENTS
1305 This option enables support for the ARM architected timer
1309 select CLKSRC_OF if OF
1311 This options enables support for the ARM timer and watchdog unit
1314 bool "Multi-Cluster Power Management"
1315 depends on CPU_V7 && SMP
1317 This option provides the common power management infrastructure
1318 for (multi-)cluster based systems, such as big.LITTLE based
1321 config MCPM_QUAD_CLUSTER
1325 To avoid wasting resources unnecessarily, MCPM only supports up
1326 to 2 clusters by default.
1327 Platforms with 3 or 4 clusters that use MCPM must select this
1328 option to allow the additional clusters to be managed.
1331 bool "big.LITTLE support (Experimental)"
1332 depends on CPU_V7 && SMP
1335 This option enables support selections for the big.LITTLE
1336 system architecture.
1339 bool "big.LITTLE switcher support"
1340 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1341 select ARM_CPU_SUSPEND
1344 The big.LITTLE "switcher" provides the core functionality to
1345 transparently handle transition between a cluster of A15's
1346 and a cluster of A7's in a big.LITTLE system.
1348 config BL_SWITCHER_DUMMY_IF
1349 tristate "Simple big.LITTLE switcher user interface"
1350 depends on BL_SWITCHER && DEBUG_KERNEL
1352 This is a simple and dummy char dev interface to control
1353 the big.LITTLE switcher core code. It is meant for
1354 debugging purposes only.
1357 prompt "Memory split"
1361 Select the desired split between kernel and user memory.
1363 If you are not absolutely sure what you are doing, leave this
1367 bool "3G/1G user/kernel split"
1368 config VMSPLIT_3G_OPT
1369 bool "3G/1G user/kernel split (for full 1G low memory)"
1371 bool "2G/2G user/kernel split"
1373 bool "1G/3G user/kernel split"
1378 default PHYS_OFFSET if !MMU
1379 default 0x40000000 if VMSPLIT_1G
1380 default 0x80000000 if VMSPLIT_2G
1381 default 0xB0000000 if VMSPLIT_3G_OPT
1385 int "Maximum number of CPUs (2-32)"
1391 bool "Support for hot-pluggable CPUs"
1394 Say Y here to experiment with turning CPUs off and on. CPUs
1395 can be controlled through /sys/devices/system/cpu.
1398 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1399 depends on HAVE_ARM_SMCCC
1402 Say Y here if you want Linux to communicate with system firmware
1403 implementing the PSCI specification for CPU-centric power
1404 management operations described in ARM document number ARM DEN
1405 0022A ("Power State Coordination Interface System Software on
1408 # The GPIO number here must be sorted by descending number. In case of
1409 # a multiplatform kernel, we just want the highest value required by the
1410 # selected platforms.
1413 default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \
1415 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1416 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1417 default 416 if ARCH_SUNXI
1418 default 392 if ARCH_U8500
1419 default 352 if ARCH_VT8500
1420 default 288 if ARCH_ROCKCHIP
1421 default 264 if MACH_H4700
1424 Maximum number of GPIOs in the system.
1426 If unsure, leave the default value.
1428 source kernel/Kconfig.preempt
1432 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1433 ARCH_S5PV210 || ARCH_EXYNOS4
1434 default 128 if SOC_AT91RM9200
1438 depends on HZ_FIXED = 0
1439 prompt "Timer frequency"
1463 default HZ_FIXED if HZ_FIXED != 0
1464 default 100 if HZ_100
1465 default 200 if HZ_200
1466 default 250 if HZ_250
1467 default 300 if HZ_300
1468 default 500 if HZ_500
1472 def_bool HIGH_RES_TIMERS
1474 config THUMB2_KERNEL
1475 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1476 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1477 default y if CPU_THUMBONLY
1479 select ARM_ASM_UNIFIED
1482 By enabling this option, the kernel will be compiled in
1483 Thumb-2 mode. A compiler/assembler that understand the unified
1484 ARM-Thumb syntax is needed.
1488 config THUMB2_AVOID_R_ARM_THM_JUMP11
1489 bool "Work around buggy Thumb-2 short branch relocations in gas"
1490 depends on THUMB2_KERNEL && MODULES
1493 Various binutils versions can resolve Thumb-2 branches to
1494 locally-defined, preemptible global symbols as short-range "b.n"
1495 branch instructions.
1497 This is a problem, because there's no guarantee the final
1498 destination of the symbol, or any candidate locations for a
1499 trampoline, are within range of the branch. For this reason, the
1500 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1501 relocation in modules at all, and it makes little sense to add
1504 The symptom is that the kernel fails with an "unsupported
1505 relocation" error when loading some modules.
1507 Until fixed tools are available, passing
1508 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1509 code which hits this problem, at the cost of a bit of extra runtime
1510 stack usage in some cases.
1512 The problem is described in more detail at:
1513 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1515 Only Thumb-2 kernels are affected.
1517 Unless you are sure your tools don't have this problem, say Y.
1519 config ARM_ASM_UNIFIED
1522 config ARM_PATCH_IDIV
1523 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1524 depends on CPU_32v7 && !XIP_KERNEL
1527 The ARM compiler inserts calls to __aeabi_idiv() and
1528 __aeabi_uidiv() when it needs to perform division on signed
1529 and unsigned integers. Some v7 CPUs have support for the sdiv
1530 and udiv instructions that can be used to implement those
1533 Enabling this option allows the kernel to modify itself to
1534 replace the first two instructions of these library functions
1535 with the sdiv or udiv plus "bx lr" instructions when the CPU
1536 it is running on supports them. Typically this will be faster
1537 and less power intensive than running the original library
1538 code to do integer division.
1541 bool "Use the ARM EABI to compile the kernel"
1543 This option allows for the kernel to be compiled using the latest
1544 ARM ABI (aka EABI). This is only useful if you are using a user
1545 space environment that is also compiled with EABI.
1547 Since there are major incompatibilities between the legacy ABI and
1548 EABI, especially with regard to structure member alignment, this
1549 option also changes the kernel syscall calling convention to
1550 disambiguate both ABIs and allow for backward compatibility support
1551 (selected with CONFIG_OABI_COMPAT).
1553 To use this you need GCC version 4.0.0 or later.
1556 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1557 depends on AEABI && !THUMB2_KERNEL
1559 This option preserves the old syscall interface along with the
1560 new (ARM EABI) one. It also provides a compatibility layer to
1561 intercept syscalls that have structure arguments which layout
1562 in memory differs between the legacy ABI and the new ARM EABI
1563 (only for non "thumb" binaries). This option adds a tiny
1564 overhead to all syscalls and produces a slightly larger kernel.
1566 The seccomp filter system will not be available when this is
1567 selected, since there is no way yet to sensibly distinguish
1568 between calling conventions during filtering.
1570 If you know you'll be using only pure EABI user space then you
1571 can say N here. If this option is not selected and you attempt
1572 to execute a legacy ABI binary then the result will be
1573 UNPREDICTABLE (in fact it can be predicted that it won't work
1574 at all). If in doubt say N.
1576 config ARCH_HAS_HOLES_MEMORYMODEL
1579 config ARCH_SPARSEMEM_ENABLE
1582 config ARCH_SPARSEMEM_DEFAULT
1583 def_bool ARCH_SPARSEMEM_ENABLE
1585 config ARCH_SELECT_MEMORY_MODEL
1586 def_bool ARCH_SPARSEMEM_ENABLE
1588 config HAVE_ARCH_PFN_VALID
1589 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1591 config HAVE_GENERIC_RCU_GUP
1596 bool "High Memory Support"
1599 The address space of ARM processors is only 4 Gigabytes large
1600 and it has to accommodate user address space, kernel address
1601 space as well as some memory mapped IO. That means that, if you
1602 have a large amount of physical memory and/or IO, not all of the
1603 memory can be "permanently mapped" by the kernel. The physical
1604 memory that is not permanently mapped is called "high memory".
1606 Depending on the selected kernel/user memory split, minimum
1607 vmalloc space and actual amount of RAM, you may not need this
1608 option which should result in a slightly faster kernel.
1613 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1617 The VM uses one page of physical memory for each page table.
1618 For systems with a lot of processes, this can use a lot of
1619 precious low memory, eventually leading to low memory being
1620 consumed by page tables. Setting this option will allow
1621 user-space 2nd level page tables to reside in high memory.
1623 config CPU_SW_DOMAIN_PAN
1624 bool "Enable use of CPU domains to implement privileged no-access"
1625 depends on MMU && !ARM_LPAE
1628 Increase kernel security by ensuring that normal kernel accesses
1629 are unable to access userspace addresses. This can help prevent
1630 use-after-free bugs becoming an exploitable privilege escalation
1631 by ensuring that magic values (such as LIST_POISON) will always
1632 fault when dereferenced.
1634 CPUs with low-vector mappings use a best-efforts implementation.
1635 Their lower 1MB needs to remain accessible for the vectors, but
1636 the remainder of userspace will become appropriately inaccessible.
1638 config HW_PERF_EVENTS
1642 config SYS_SUPPORTS_HUGETLBFS
1646 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1650 config ARCH_WANT_GENERAL_HUGETLB
1653 config ARM_MODULE_PLTS
1654 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1657 Allocate PLTs when loading modules so that jumps and calls whose
1658 targets are too far away for their relative offsets to be encoded
1659 in the instructions themselves can be bounced via veneers in the
1660 module's PLT. This allows modules to be allocated in the generic
1661 vmalloc area after the dedicated module memory area has been
1662 exhausted. The modules will use slightly more memory, but after
1663 rounding up to page size, the actual memory footprint is usually
1666 Say y if you are getting out of memory errors while loading modules
1670 config FORCE_MAX_ZONEORDER
1671 int "Maximum zone order"
1672 default "12" if SOC_AM33XX
1673 default "9" if SA1111 || ARCH_EFM32
1676 The kernel memory allocator divides physically contiguous memory
1677 blocks into "zones", where each zone is a power of two number of
1678 pages. This option selects the largest power of two that the kernel
1679 keeps in the memory allocator. If you need to allocate very large
1680 blocks of physically contiguous memory, then you may need to
1681 increase this value.
1683 This config option is actually maximum order plus one. For example,
1684 a value of 11 means that the largest free memory block is 2^10 pages.
1686 config ALIGNMENT_TRAP
1688 depends on CPU_CP15_MMU
1689 default y if !ARCH_EBSA110
1690 select HAVE_PROC_CPU if PROC_FS
1692 ARM processors cannot fetch/store information which is not
1693 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1694 address divisible by 4. On 32-bit ARM processors, these non-aligned
1695 fetch/store instructions will be emulated in software if you say
1696 here, which has a severe performance impact. This is necessary for
1697 correct operation of some network protocols. With an IP-only
1698 configuration it is safe to say N, otherwise say Y.
1700 config UACCESS_WITH_MEMCPY
1701 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1703 default y if CPU_FEROCEON
1705 Implement faster copy_to_user and clear_user methods for CPU
1706 cores where a 8-word STM instruction give significantly higher
1707 memory write throughput than a sequence of individual 32bit stores.
1709 A possible side effect is a slight increase in scheduling latency
1710 between threads sharing the same address space if they invoke
1711 such copy operations with large buffers.
1713 However, if the CPU data cache is using a write-allocate mode,
1714 this option is unlikely to provide any performance gain.
1718 prompt "Enable seccomp to safely compute untrusted bytecode"
1720 This kernel feature is useful for number crunching applications
1721 that may need to compute untrusted bytecode during their
1722 execution. By using pipes or other transports made available to
1723 the process as file descriptors supporting the read/write
1724 syscalls, it's possible to isolate those applications in
1725 their own address space using seccomp. Once seccomp is
1726 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1727 and the task is only allowed to execute a few safe syscalls
1728 defined by each seccomp mode.
1737 bool "Enable paravirtualization code"
1739 This changes the kernel so it can modify itself when it is run
1740 under a hypervisor, potentially improving performance significantly
1741 over full virtualization.
1743 config PARAVIRT_TIME_ACCOUNTING
1744 bool "Paravirtual steal time accounting"
1748 Select this option to enable fine granularity task steal time
1749 accounting. Time spent executing other tasks in parallel with
1750 the current vCPU is discounted from the vCPU power. To account for
1751 that, there can be a small performance impact.
1753 If in doubt, say N here.
1760 bool "Xen guest support on ARM"
1761 depends on ARM && AEABI && OF
1762 depends on CPU_V7 && !CPU_V6
1763 depends on !GENERIC_ATOMIC64
1765 select ARCH_DMA_ADDR_T_64BIT
1770 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1777 bool "Flattened Device Tree support"
1781 Include support for flattened device tree machine descriptions.
1784 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1787 This is the traditional way of passing data to the kernel at boot
1788 time. If you are solely relying on the flattened device tree (or
1789 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1790 to remove ATAGS support from your kernel binary. If unsure,
1793 config DEPRECATED_PARAM_STRUCT
1794 bool "Provide old way to pass kernel parameters"
1797 This was deprecated in 2001 and announced to live on for 5 years.
1798 Some old boot loaders still use this way.
1800 # Compressed boot loader in ROM. Yes, we really want to ask about
1801 # TEXT and BSS so we preserve their values in the config files.
1802 config ZBOOT_ROM_TEXT
1803 hex "Compressed ROM boot loader base address"
1806 The physical address at which the ROM-able zImage is to be
1807 placed in the target. Platforms which normally make use of
1808 ROM-able zImage formats normally set this to a suitable
1809 value in their defconfig file.
1811 If ZBOOT_ROM is not enabled, this has no effect.
1813 config ZBOOT_ROM_BSS
1814 hex "Compressed ROM boot loader BSS address"
1817 The base address of an area of read/write memory in the target
1818 for the ROM-able zImage which must be available while the
1819 decompressor is running. It must be large enough to hold the
1820 entire decompressed kernel plus an additional 128 KiB.
1821 Platforms which normally make use of ROM-able zImage formats
1822 normally set this to a suitable value in their defconfig file.
1824 If ZBOOT_ROM is not enabled, this has no effect.
1827 bool "Compressed boot loader in ROM/flash"
1828 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1829 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1831 Say Y here if you intend to execute your compressed kernel image
1832 (zImage) directly from ROM or flash. If unsure, say N.
1834 config ARM_APPENDED_DTB
1835 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1838 With this option, the boot code will look for a device tree binary
1839 (DTB) appended to zImage
1840 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1842 This is meant as a backward compatibility convenience for those
1843 systems with a bootloader that can't be upgraded to accommodate
1844 the documented boot protocol using a device tree.
1846 Beware that there is very little in terms of protection against
1847 this option being confused by leftover garbage in memory that might
1848 look like a DTB header after a reboot if no actual DTB is appended
1849 to zImage. Do not leave this option active in a production kernel
1850 if you don't intend to always append a DTB. Proper passing of the
1851 location into r2 of a bootloader provided DTB is always preferable
1854 config ARM_ATAG_DTB_COMPAT
1855 bool "Supplement the appended DTB with traditional ATAG information"
1856 depends on ARM_APPENDED_DTB
1858 Some old bootloaders can't be updated to a DTB capable one, yet
1859 they provide ATAGs with memory configuration, the ramdisk address,
1860 the kernel cmdline string, etc. Such information is dynamically
1861 provided by the bootloader and can't always be stored in a static
1862 DTB. To allow a device tree enabled kernel to be used with such
1863 bootloaders, this option allows zImage to extract the information
1864 from the ATAG list and store it at run time into the appended DTB.
1867 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1868 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1870 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1871 bool "Use bootloader kernel arguments if available"
1873 Uses the command-line options passed by the boot loader instead of
1874 the device tree bootargs property. If the boot loader doesn't provide
1875 any, the device tree bootargs property will be used.
1877 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1878 bool "Extend with bootloader kernel arguments"
1880 The command-line arguments provided by the boot loader will be
1881 appended to the the device tree bootargs property.
1886 string "Default kernel command string"
1889 On some architectures (EBSA110 and CATS), there is currently no way
1890 for the boot loader to pass arguments to the kernel. For these
1891 architectures, you should supply some command-line options at build
1892 time by entering them here. As a minimum, you should specify the
1893 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1896 prompt "Kernel command line type" if CMDLINE != ""
1897 default CMDLINE_FROM_BOOTLOADER
1900 config CMDLINE_FROM_BOOTLOADER
1901 bool "Use bootloader kernel arguments if available"
1903 Uses the command-line options passed by the boot loader. If
1904 the boot loader doesn't provide any, the default kernel command
1905 string provided in CMDLINE will be used.
1907 config CMDLINE_EXTEND
1908 bool "Extend bootloader kernel arguments"
1910 The command-line arguments provided by the boot loader will be
1911 appended to the default kernel command string.
1913 config CMDLINE_FORCE
1914 bool "Always use the default kernel command string"
1916 Always use the default kernel command string, even if the boot
1917 loader passes other arguments to the kernel.
1918 This is useful if you cannot or don't want to change the
1919 command-line options your boot loader passes to the kernel.
1923 bool "Kernel Execute-In-Place from ROM"
1924 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1926 Execute-In-Place allows the kernel to run from non-volatile storage
1927 directly addressable by the CPU, such as NOR flash. This saves RAM
1928 space since the text section of the kernel is not loaded from flash
1929 to RAM. Read-write sections, such as the data section and stack,
1930 are still copied to RAM. The XIP kernel is not compressed since
1931 it has to run directly from flash, so it will take more space to
1932 store it. The flash address used to link the kernel object files,
1933 and for storing it, is configuration dependent. Therefore, if you
1934 say Y here, you must know the proper physical address where to
1935 store the kernel image depending on your own flash memory usage.
1937 Also note that the make target becomes "make xipImage" rather than
1938 "make zImage" or "make Image". The final kernel binary to put in
1939 ROM memory will be arch/arm/boot/xipImage.
1943 config XIP_PHYS_ADDR
1944 hex "XIP Kernel Physical Location"
1945 depends on XIP_KERNEL
1946 default "0x00080000"
1948 This is the physical address in your flash memory the kernel will
1949 be linked for and stored to. This address is dependent on your
1953 bool "Kexec system call (EXPERIMENTAL)"
1954 depends on (!SMP || PM_SLEEP_SMP)
1958 kexec is a system call that implements the ability to shutdown your
1959 current kernel, and to start another kernel. It is like a reboot
1960 but it is independent of the system firmware. And like a reboot
1961 you can start any kernel with it, not just Linux.
1963 It is an ongoing process to be certain the hardware in a machine
1964 is properly shutdown, so do not be surprised if this code does not
1965 initially work for you.
1968 bool "Export atags in procfs"
1969 depends on ATAGS && KEXEC
1972 Should the atags used to boot the kernel be exported in an "atags"
1973 file in procfs. Useful with kexec.
1976 bool "Build kdump crash kernel (EXPERIMENTAL)"
1978 Generate crash dump after being started by kexec. This should
1979 be normally only set in special crash dump kernels which are
1980 loaded in the main kernel with kexec-tools into a specially
1981 reserved region and then later executed after a crash by
1982 kdump/kexec. The crash dump kernel must be compiled to a
1983 memory address not used by the main kernel
1985 For more details see Documentation/kdump/kdump.txt
1987 config AUTO_ZRELADDR
1988 bool "Auto calculation of the decompressed kernel image address"
1990 ZRELADDR is the physical address where the decompressed kernel
1991 image will be placed. If AUTO_ZRELADDR is selected, the address
1992 will be determined at run-time by masking the current IP with
1993 0xf8000000. This assumes the zImage being placed in the first 128MB
1994 from start of memory.
2000 bool "UEFI runtime support"
2001 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
2003 select EFI_PARAMS_FROM_FDT
2006 select EFI_RUNTIME_WRAPPERS
2008 This option provides support for runtime services provided
2009 by UEFI firmware (such as non-volatile variables, realtime
2010 clock, and platform reset). A UEFI stub is also provided to
2011 allow the kernel to be booted as an EFI application. This
2012 is only useful for kernels that may run on systems that have
2017 menu "CPU Power Management"
2019 source "drivers/cpufreq/Kconfig"
2021 source "drivers/cpuidle/Kconfig"
2025 menu "Floating point emulation"
2027 comment "At least one emulation must be selected"
2030 bool "NWFPE math emulation"
2031 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2033 Say Y to include the NWFPE floating point emulator in the kernel.
2034 This is necessary to run most binaries. Linux does not currently
2035 support floating point hardware so you need to say Y here even if
2036 your machine has an FPA or floating point co-processor podule.
2038 You may say N here if you are going to load the Acorn FPEmulator
2039 early in the bootup.
2042 bool "Support extended precision"
2043 depends on FPE_NWFPE
2045 Say Y to include 80-bit support in the kernel floating-point
2046 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2047 Note that gcc does not generate 80-bit operations by default,
2048 so in most cases this option only enlarges the size of the
2049 floating point emulator without any good reason.
2051 You almost surely want to say N here.
2054 bool "FastFPE math emulation (EXPERIMENTAL)"
2055 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2057 Say Y here to include the FAST floating point emulator in the kernel.
2058 This is an experimental much faster emulator which now also has full
2059 precision for the mantissa. It does not support any exceptions.
2060 It is very simple, and approximately 3-6 times faster than NWFPE.
2062 It should be sufficient for most programs. It may be not suitable
2063 for scientific calculations, but you have to check this for yourself.
2064 If you do not feel you need a faster FP emulation you should better
2068 bool "VFP-format floating point maths"
2069 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2071 Say Y to include VFP support code in the kernel. This is needed
2072 if your hardware includes a VFP unit.
2074 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2075 release notes and additional status information.
2077 Say N if your target does not have VFP hardware.
2085 bool "Advanced SIMD (NEON) Extension support"
2086 depends on VFPv3 && CPU_V7
2088 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2091 config KERNEL_MODE_NEON
2092 bool "Support for NEON in kernel mode"
2093 depends on NEON && AEABI
2095 Say Y to include support for NEON in kernel mode.
2099 menu "Userspace binary formats"
2101 source "fs/Kconfig.binfmt"
2105 menu "Power management options"
2107 source "kernel/power/Kconfig"
2109 config ARCH_SUSPEND_POSSIBLE
2110 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2111 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2114 config ARM_CPU_SUSPEND
2117 config ARCH_HIBERNATION_POSSIBLE
2120 default y if ARCH_SUSPEND_POSSIBLE
2124 source "net/Kconfig"
2126 source "drivers/Kconfig"
2128 source "drivers/firmware/Kconfig"
2132 source "arch/arm/Kconfig.debug"
2134 source "security/Kconfig"
2136 source "crypto/Kconfig"
2138 source "arch/arm/crypto/Kconfig"
2141 source "lib/Kconfig"
2143 source "arch/arm/kvm/Kconfig"