4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAVE_CUSTOM_GPIO_H
7 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
8 select ARCH_WANT_IPC_PARSE_VERSION
9 select BUILDTIME_EXTABLE_SORT if MMU
10 select CPU_PM if (SUSPEND || CPU_IDLE)
11 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
12 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
13 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
14 select GENERIC_IRQ_PROBE
15 select GENERIC_IRQ_SHOW
16 select GENERIC_PCI_IOMAP
17 select GENERIC_SCHED_CLOCK
18 select GENERIC_SMP_IDLE_THREAD
19 select GENERIC_IDLE_POLL_SETUP
20 select GENERIC_STRNCPY_FROM_USER
21 select GENERIC_STRNLEN_USER
22 select HARDIRQS_SW_RESEND
23 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
25 select HAVE_ARCH_SECCOMP_FILTER
26 select HAVE_ARCH_TRACEHOOK
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_DEBUG_KMEMLEAK
30 select HAVE_DMA_API_DEBUG
32 select HAVE_DMA_CONTIGUOUS if MMU
33 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
34 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
35 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
36 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
37 select HAVE_GENERIC_DMA_COHERENT
38 select HAVE_GENERIC_HARDIRQS
39 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
40 select HAVE_IDE if PCI || ISA || PCMCIA
41 select HAVE_IRQ_TIME_ACCOUNTING
42 select HAVE_KERNEL_GZIP
43 select HAVE_KERNEL_LZ4
44 select HAVE_KERNEL_LZMA
45 select HAVE_KERNEL_LZO
47 select HAVE_KPROBES if !XIP_KERNEL
48 select HAVE_KRETPROBES if (HAVE_KPROBES)
50 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
51 select HAVE_PERF_EVENTS
52 select HAVE_REGS_AND_STACK_ACCESS_API
53 select HAVE_SYSCALL_TRACEPOINTS
55 select IRQ_FORCED_THREADING
57 select PERF_USE_VMALLOC
59 select SYS_SUPPORTS_APM_EMULATION
60 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
61 select MODULES_USE_ELF_REL
62 select CLONE_BACKWARDS
63 select OLD_SIGSUSPEND3
65 select HAVE_CONTEXT_TRACKING
67 The ARM series is a line of low-power-consumption RISC chip designs
68 licensed by ARM Ltd and targeted at embedded applications and
69 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
70 manufactured, but legacy ARM-based PC hardware remains popular in
71 Europe. There is an ARM Linux project with a web page at
72 <http://www.arm.linux.org.uk/>.
74 config ARM_HAS_SG_CHAIN
77 config NEED_SG_DMA_LENGTH
80 config ARM_DMA_USE_IOMMU
82 select ARM_HAS_SG_CHAIN
83 select NEED_SG_DMA_LENGTH
87 config ARM_DMA_IOMMU_ALIGNMENT
88 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
92 DMA mapping framework by default aligns all buffers to the smallest
93 PAGE_SIZE order which is greater than or equal to the requested buffer
94 size. This works well for buffers up to a few hundreds kilobytes, but
95 for larger buffers it just a waste of address space. Drivers which has
96 relatively small addressing window (like 64Mib) might run out of
97 virtual space with just a few allocations.
99 With this parameter you can specify the maximum PAGE_SIZE order for
100 DMA IOMMU buffers. Larger buffers will be aligned only to this
101 specified order. The order is expressed as a power of two multiplied
109 config MIGHT_HAVE_PCI
112 config SYS_SUPPORTS_APM_EMULATION
117 select GENERIC_ALLOCATOR
128 The Extended Industry Standard Architecture (EISA) bus was
129 developed as an open alternative to the IBM MicroChannel bus.
131 The EISA bus provided some of the features of the IBM MicroChannel
132 bus while maintaining backward compatibility with cards made for
133 the older ISA bus. The EISA bus saw limited use between 1988 and
134 1995 when it was made obsolete by the PCI bus.
136 Say Y here if you are building a kernel for an EISA-based machine.
143 config STACKTRACE_SUPPORT
147 config HAVE_LATENCYTOP_SUPPORT
152 config LOCKDEP_SUPPORT
156 config TRACE_IRQFLAGS_SUPPORT
160 config RWSEM_GENERIC_SPINLOCK
164 config RWSEM_XCHGADD_ALGORITHM
167 config ARCH_HAS_ILOG2_U32
170 config ARCH_HAS_ILOG2_U64
173 config ARCH_HAS_CPUFREQ
176 Internal node to signify that the ARCH has CPUFREQ support
177 and that the relevant menu configurations are displayed for
180 config ARCH_HAS_BANDGAP
183 config GENERIC_HWEIGHT
187 config GENERIC_CALIBRATE_DELAY
191 config ARCH_MAY_HAVE_PC_FDC
197 config NEED_DMA_MAP_STATE
200 config ARCH_HAS_DMA_SET_COHERENT_MASK
203 config GENERIC_ISA_DMA
209 config NEED_RET_TO_USER
217 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
218 default DRAM_BASE if REMAP_VECTORS_TO_RAM
221 The base address of exception vectors. This must be two pages
224 config ARM_PATCH_PHYS_VIRT
225 bool "Patch physical to virtual translations at runtime" if EMBEDDED
227 depends on !XIP_KERNEL && MMU
228 depends on !ARCH_REALVIEW || !SPARSEMEM
230 Patch phys-to-virt and virt-to-phys translation functions at
231 boot and module load time according to the position of the
232 kernel in system memory.
234 This can only be used with non-XIP MMU kernels where the base
235 of physical memory is at a 16MB boundary.
237 Only disable this option if you know that you do not require
238 this feature (eg, building a kernel for a single machine) and
239 you need to shrink the kernel to the minimal size.
241 config NEED_MACH_GPIO_H
244 Select this when mach/gpio.h is required to provide special
245 definitions for this platform. The need for mach/gpio.h should
246 be avoided when possible.
248 config NEED_MACH_IO_H
251 Select this when mach/io.h is required to provide special
252 definitions for this platform. The need for mach/io.h should
253 be avoided when possible.
255 config NEED_MACH_MEMORY_H
258 Select this when mach/memory.h is required to provide special
259 definitions for this platform. The need for mach/memory.h should
260 be avoided when possible.
263 hex "Physical address of main memory" if MMU
264 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
265 default DRAM_BASE if !MMU
267 Please provide the physical address corresponding to the
268 location of main memory in your system.
274 source "init/Kconfig"
276 source "kernel/Kconfig.freezer"
281 bool "MMU-based Paged Memory Management Support"
284 Select if you want MMU-based virtualised addressing space
285 support by paged memory management. If unsure, say 'Y'.
288 # The "ARM system type" choice list is ordered alphabetically by option
289 # text. Please add new entries in the option alphabetic order.
292 prompt "ARM system type"
293 default ARCH_VERSATILE if !MMU
294 default ARCH_MULTIPLATFORM if MMU
296 config ARCH_MULTIPLATFORM
297 bool "Allow multiple platforms to be selected"
299 select ARM_PATCH_PHYS_VIRT
302 select MULTI_IRQ_HANDLER
306 config ARCH_INTEGRATOR
307 bool "ARM Ltd. Integrator family"
308 select ARCH_HAS_CPUFREQ
311 select COMMON_CLK_VERSATILE
312 select GENERIC_CLOCKEVENTS
315 select MULTI_IRQ_HANDLER
316 select NEED_MACH_MEMORY_H
317 select PLAT_VERSATILE
319 select VERSATILE_FPGA_IRQ
321 Support for ARM's Integrator platform.
324 bool "ARM Ltd. RealView family"
325 select ARCH_WANT_OPTIONAL_GPIOLIB
327 select ARM_TIMER_SP804
329 select COMMON_CLK_VERSATILE
330 select GENERIC_CLOCKEVENTS
331 select GPIO_PL061 if GPIOLIB
333 select NEED_MACH_MEMORY_H
334 select PLAT_VERSATILE
335 select PLAT_VERSATILE_CLCD
337 This enables support for ARM Ltd RealView boards.
339 config ARCH_VERSATILE
340 bool "ARM Ltd. Versatile family"
341 select ARCH_WANT_OPTIONAL_GPIOLIB
343 select ARM_TIMER_SP804
346 select GENERIC_CLOCKEVENTS
347 select HAVE_MACH_CLKDEV
349 select PLAT_VERSATILE
350 select PLAT_VERSATILE_CLCD
351 select PLAT_VERSATILE_CLOCK
352 select VERSATILE_FPGA_IRQ
354 This enables support for ARM Ltd Versatile board.
358 select ARCH_REQUIRE_GPIOLIB
362 select NEED_MACH_GPIO_H
363 select NEED_MACH_IO_H if PCCARD
365 select PINCTRL_AT91 if USE_OF
367 This enables support for systems based on Atmel
368 AT91RM9200 and AT91SAM9* processors.
371 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
372 select ARCH_REQUIRE_GPIOLIB
378 select GENERIC_CLOCKEVENTS
380 select MULTI_IRQ_HANDLER
383 Support for Cirrus Logic 711x/721x/731x based boards.
386 bool "Cortina Systems Gemini"
387 select ARCH_REQUIRE_GPIOLIB
388 select ARCH_USES_GETTIMEOFFSET
389 select NEED_MACH_GPIO_H
392 Support for the Cortina Systems Gemini family SoCs
396 select ARCH_USES_GETTIMEOFFSET
399 select NEED_MACH_IO_H
400 select NEED_MACH_MEMORY_H
403 This is an evaluation board for the StrongARM processor available
404 from Digital. It has limited hardware on-board, including an
405 Ethernet interface, two PCMCIA sockets, two serial ports and a
410 select ARCH_HAS_HOLES_MEMORYMODEL
411 select ARCH_REQUIRE_GPIOLIB
412 select ARCH_USES_GETTIMEOFFSET
417 select NEED_MACH_MEMORY_H
419 This enables support for the Cirrus EP93xx series of CPUs.
421 config ARCH_FOOTBRIDGE
425 select GENERIC_CLOCKEVENTS
427 select NEED_MACH_IO_H if !MMU
428 select NEED_MACH_MEMORY_H
430 Support for systems based on the DC21285 companion chip
431 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
434 bool "Hilscher NetX based"
438 select GENERIC_CLOCKEVENTS
440 This enables support for systems based on the Hilscher NetX Soc
446 select NEED_MACH_MEMORY_H
447 select NEED_RET_TO_USER
452 Support for Intel's IOP13XX (XScale) family of processors.
457 select ARCH_REQUIRE_GPIOLIB
459 select NEED_MACH_GPIO_H
460 select NEED_RET_TO_USER
464 Support for Intel's 80219 and IOP32X (XScale) family of
470 select ARCH_REQUIRE_GPIOLIB
472 select NEED_MACH_GPIO_H
473 select NEED_RET_TO_USER
477 Support for Intel's IOP33X (XScale) family of processors.
482 select ARCH_HAS_DMA_SET_COHERENT_MASK
483 select ARCH_REQUIRE_GPIOLIB
486 select DMABOUNCE if PCI
487 select GENERIC_CLOCKEVENTS
488 select MIGHT_HAVE_PCI
489 select NEED_MACH_IO_H
490 select USB_EHCI_BIG_ENDIAN_MMIO
491 select USB_EHCI_BIG_ENDIAN_DESC
493 Support for Intel's IXP4XX (XScale) family of processors.
497 select ARCH_REQUIRE_GPIOLIB
499 select GENERIC_CLOCKEVENTS
500 select MIGHT_HAVE_PCI
503 select PLAT_ORION_LEGACY
504 select USB_ARCH_HAS_EHCI
507 Support for the Marvell Dove SoC 88AP510
510 bool "Marvell Kirkwood"
511 select ARCH_HAS_CPUFREQ
512 select ARCH_REQUIRE_GPIOLIB
514 select GENERIC_CLOCKEVENTS
518 select PINCTRL_KIRKWOOD
519 select PLAT_ORION_LEGACY
522 Support for the following Marvell Kirkwood series SoCs:
523 88F6180, 88F6192 and 88F6281.
526 bool "Marvell MV78xx0"
527 select ARCH_REQUIRE_GPIOLIB
529 select GENERIC_CLOCKEVENTS
531 select PLAT_ORION_LEGACY
534 Support for the following Marvell MV78xx0 series SoCs:
540 select ARCH_REQUIRE_GPIOLIB
542 select GENERIC_CLOCKEVENTS
544 select PLAT_ORION_LEGACY
547 Support for the following Marvell Orion 5x series SoCs:
548 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
549 Orion-2 (5281), Orion-1-90 (6183).
552 bool "Marvell PXA168/910/MMP2"
554 select ARCH_REQUIRE_GPIOLIB
556 select GENERIC_ALLOCATOR
557 select GENERIC_CLOCKEVENTS
560 select NEED_MACH_GPIO_H
565 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
568 bool "Micrel/Kendin KS8695"
569 select ARCH_REQUIRE_GPIOLIB
572 select GENERIC_CLOCKEVENTS
573 select NEED_MACH_MEMORY_H
575 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
576 System-on-Chip devices.
579 bool "Nuvoton W90X900 CPU"
580 select ARCH_REQUIRE_GPIOLIB
584 select GENERIC_CLOCKEVENTS
586 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
587 At present, the w90x900 has been renamed nuc900, regarding
588 the ARM series product line, you can login the following
589 link address to know more.
591 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
592 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
596 select ARCH_REQUIRE_GPIOLIB
601 select GENERIC_CLOCKEVENTS
604 select USB_ARCH_HAS_OHCI
607 Support for the NXP LPC32XX family of processors
610 bool "PXA2xx/PXA3xx-based"
612 select ARCH_HAS_CPUFREQ
614 select ARCH_REQUIRE_GPIOLIB
615 select ARM_CPU_SUSPEND if PM
619 select GENERIC_CLOCKEVENTS
622 select MULTI_IRQ_HANDLER
623 select NEED_MACH_GPIO_H
627 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
631 select ARCH_REQUIRE_GPIOLIB
633 select CLKSRC_OF if OF
635 select GENERIC_CLOCKEVENTS
637 Support for Qualcomm MSM/QSD based systems. This runs on the
638 apps processor of the MSM/QSD and depends on a shared memory
639 interface to the modem processor which runs the baseband
640 stack and controls some vital subsystems
641 (clock and power control, etc).
644 bool "Renesas SH-Mobile / R-Mobile"
645 select ARM_PATCH_PHYS_VIRT
647 select GENERIC_CLOCKEVENTS
648 select HAVE_ARM_SCU if SMP
649 select HAVE_ARM_TWD if SMP
651 select HAVE_MACH_CLKDEV
653 select MIGHT_HAVE_CACHE_L2X0
654 select MULTI_IRQ_HANDLER
657 select PM_GENERIC_DOMAINS if PM
660 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
665 select ARCH_MAY_HAVE_PC_FDC
666 select ARCH_SPARSEMEM_ENABLE
667 select ARCH_USES_GETTIMEOFFSET
670 select HAVE_PATA_PLATFORM
672 select NEED_MACH_IO_H
673 select NEED_MACH_MEMORY_H
677 On the Acorn Risc-PC, Linux can support the internal IDE disk and
678 CD-ROM interface, serial and parallel port, and the floppy drive.
682 select ARCH_HAS_CPUFREQ
684 select ARCH_REQUIRE_GPIOLIB
685 select ARCH_SPARSEMEM_ENABLE
690 select GENERIC_CLOCKEVENTS
693 select NEED_MACH_GPIO_H
694 select NEED_MACH_MEMORY_H
697 Support for StrongARM 11x0 based boards.
700 bool "Samsung S3C24XX SoCs"
701 select ARCH_HAS_CPUFREQ
702 select ARCH_REQUIRE_GPIOLIB
704 select CLKSRC_SAMSUNG_PWM
705 select GENERIC_CLOCKEVENTS
708 select HAVE_S3C2410_I2C if I2C
709 select HAVE_S3C2410_WATCHDOG if WATCHDOG
710 select HAVE_S3C_RTC if RTC_CLASS
711 select MULTI_IRQ_HANDLER
712 select NEED_MACH_GPIO_H
713 select NEED_MACH_IO_H
716 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
717 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
718 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
719 Samsung SMDK2410 development board (and derivatives).
722 bool "Samsung S3C64XX"
723 select ARCH_HAS_CPUFREQ
724 select ARCH_REQUIRE_GPIOLIB
727 select CLKSRC_SAMSUNG_PWM
729 select GENERIC_CLOCKEVENTS
732 select HAVE_S3C2410_I2C if I2C
733 select HAVE_S3C2410_WATCHDOG if WATCHDOG
735 select NEED_MACH_GPIO_H
739 select S3C_GPIO_TRACK
741 select SAMSUNG_CLKSRC
742 select SAMSUNG_GPIOLIB_4BIT
743 select SAMSUNG_WDT_RESET
744 select USB_ARCH_HAS_OHCI
746 Samsung S3C64XX series based systems
749 bool "Samsung S5P6440 S5P6450"
751 select CLKSRC_SAMSUNG_PWM
753 select GENERIC_CLOCKEVENTS
756 select HAVE_S3C2410_I2C if I2C
757 select HAVE_S3C2410_WATCHDOG if WATCHDOG
758 select HAVE_S3C_RTC if RTC_CLASS
759 select NEED_MACH_GPIO_H
760 select SAMSUNG_WDT_RESET
763 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
767 bool "Samsung S5PC100"
768 select ARCH_REQUIRE_GPIOLIB
770 select CLKSRC_SAMSUNG_PWM
772 select GENERIC_CLOCKEVENTS
775 select HAVE_S3C2410_I2C if I2C
776 select HAVE_S3C2410_WATCHDOG if WATCHDOG
777 select HAVE_S3C_RTC if RTC_CLASS
778 select NEED_MACH_GPIO_H
779 select SAMSUNG_WDT_RESET
782 Samsung S5PC100 series based systems
785 bool "Samsung S5PV210/S5PC110"
786 select ARCH_HAS_CPUFREQ
787 select ARCH_HAS_HOLES_MEMORYMODEL
788 select ARCH_SPARSEMEM_ENABLE
790 select CLKSRC_SAMSUNG_PWM
792 select GENERIC_CLOCKEVENTS
795 select HAVE_S3C2410_I2C if I2C
796 select HAVE_S3C2410_WATCHDOG if WATCHDOG
797 select HAVE_S3C_RTC if RTC_CLASS
798 select NEED_MACH_GPIO_H
799 select NEED_MACH_MEMORY_H
802 Samsung S5PV210/S5PC110 series based systems
805 bool "Samsung EXYNOS"
806 select ARCH_HAS_CPUFREQ
807 select ARCH_HAS_HOLES_MEMORYMODEL
808 select ARCH_REQUIRE_GPIOLIB
809 select ARCH_SPARSEMEM_ENABLE
814 select GENERIC_CLOCKEVENTS
816 select HAVE_S3C2410_I2C if I2C
817 select HAVE_S3C2410_WATCHDOG if WATCHDOG
818 select HAVE_S3C_RTC if RTC_CLASS
819 select NEED_MACH_MEMORY_H
823 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
827 select ARCH_USES_GETTIMEOFFSET
831 select NEED_MACH_MEMORY_H
836 Support for the StrongARM based Digital DNARD machine, also known
837 as "Shark" (<http://www.shark-linux.de/shark.html>).
841 select ARCH_HAS_HOLES_MEMORYMODEL
842 select ARCH_REQUIRE_GPIOLIB
844 select GENERIC_ALLOCATOR
845 select GENERIC_CLOCKEVENTS
846 select GENERIC_IRQ_CHIP
848 select NEED_MACH_GPIO_H
853 Support for TI's DaVinci platform.
858 select ARCH_HAS_CPUFREQ
859 select ARCH_HAS_HOLES_MEMORYMODEL
861 select ARCH_REQUIRE_GPIOLIB
864 select GENERIC_CLOCKEVENTS
865 select GENERIC_IRQ_CHIP
869 select NEED_MACH_IO_H if PCCARD
870 select NEED_MACH_MEMORY_H
872 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
876 menu "Multiple platform selection"
877 depends on ARCH_MULTIPLATFORM
879 comment "CPU Core family selection"
881 config ARCH_MULTI_V4T
882 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
883 depends on !ARCH_MULTI_V6_V7
884 select ARCH_MULTI_V4_V5
885 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
886 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
887 CPU_ARM925T || CPU_ARM940T)
890 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
891 depends on !ARCH_MULTI_V6_V7
892 select ARCH_MULTI_V4_V5
893 select CPU_ARM926T if (!CPU_ARM946E || CPU_ARM1020 || \
894 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
895 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
897 config ARCH_MULTI_V4_V5
901 bool "ARMv6 based platforms (ARM11)"
902 select ARCH_MULTI_V6_V7
906 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
908 select ARCH_MULTI_V6_V7
911 config ARCH_MULTI_V6_V7
914 config ARCH_MULTI_CPU_AUTO
915 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
921 # This is sorted alphabetically by mach-* pathname. However, plat-*
922 # Kconfigs may be included either alphabetically (according to the
923 # plat- suffix) or along side the corresponding mach-* source.
925 source "arch/arm/mach-mvebu/Kconfig"
927 source "arch/arm/mach-at91/Kconfig"
929 source "arch/arm/mach-bcm/Kconfig"
931 source "arch/arm/mach-bcm2835/Kconfig"
933 source "arch/arm/mach-clps711x/Kconfig"
935 source "arch/arm/mach-cns3xxx/Kconfig"
937 source "arch/arm/mach-davinci/Kconfig"
939 source "arch/arm/mach-dove/Kconfig"
941 source "arch/arm/mach-ep93xx/Kconfig"
943 source "arch/arm/mach-footbridge/Kconfig"
945 source "arch/arm/mach-gemini/Kconfig"
947 source "arch/arm/mach-highbank/Kconfig"
949 source "arch/arm/mach-integrator/Kconfig"
951 source "arch/arm/mach-iop32x/Kconfig"
953 source "arch/arm/mach-iop33x/Kconfig"
955 source "arch/arm/mach-iop13xx/Kconfig"
957 source "arch/arm/mach-ixp4xx/Kconfig"
959 source "arch/arm/mach-keystone/Kconfig"
961 source "arch/arm/mach-kirkwood/Kconfig"
963 source "arch/arm/mach-ks8695/Kconfig"
965 source "arch/arm/mach-msm/Kconfig"
967 source "arch/arm/mach-mv78xx0/Kconfig"
969 source "arch/arm/mach-imx/Kconfig"
971 source "arch/arm/mach-mxs/Kconfig"
973 source "arch/arm/mach-netx/Kconfig"
975 source "arch/arm/mach-nomadik/Kconfig"
977 source "arch/arm/mach-nspire/Kconfig"
979 source "arch/arm/plat-omap/Kconfig"
981 source "arch/arm/mach-omap1/Kconfig"
983 source "arch/arm/mach-omap2/Kconfig"
985 source "arch/arm/mach-orion5x/Kconfig"
987 source "arch/arm/mach-picoxcell/Kconfig"
989 source "arch/arm/mach-pxa/Kconfig"
990 source "arch/arm/plat-pxa/Kconfig"
992 source "arch/arm/mach-mmp/Kconfig"
994 source "arch/arm/mach-realview/Kconfig"
996 source "arch/arm/mach-rockchip/Kconfig"
998 source "arch/arm/mach-sa1100/Kconfig"
1000 source "arch/arm/plat-samsung/Kconfig"
1002 source "arch/arm/mach-socfpga/Kconfig"
1004 source "arch/arm/mach-spear/Kconfig"
1006 source "arch/arm/mach-sti/Kconfig"
1008 source "arch/arm/mach-s3c24xx/Kconfig"
1011 source "arch/arm/mach-s3c64xx/Kconfig"
1014 source "arch/arm/mach-s5p64x0/Kconfig"
1016 source "arch/arm/mach-s5pc100/Kconfig"
1018 source "arch/arm/mach-s5pv210/Kconfig"
1020 source "arch/arm/mach-exynos/Kconfig"
1022 source "arch/arm/mach-shmobile/Kconfig"
1024 source "arch/arm/mach-sunxi/Kconfig"
1026 source "arch/arm/mach-prima2/Kconfig"
1028 source "arch/arm/mach-tegra/Kconfig"
1030 source "arch/arm/mach-u300/Kconfig"
1032 source "arch/arm/mach-ux500/Kconfig"
1034 source "arch/arm/mach-versatile/Kconfig"
1036 source "arch/arm/mach-vexpress/Kconfig"
1037 source "arch/arm/plat-versatile/Kconfig"
1039 source "arch/arm/mach-virt/Kconfig"
1041 source "arch/arm/mach-vt8500/Kconfig"
1043 source "arch/arm/mach-w90x900/Kconfig"
1045 source "arch/arm/mach-zynq/Kconfig"
1047 # Definitions to make life easier
1053 select GENERIC_CLOCKEVENTS
1059 select GENERIC_IRQ_CHIP
1062 config PLAT_ORION_LEGACY
1069 config PLAT_VERSATILE
1072 config ARM_TIMER_SP804
1075 select CLKSRC_OF if OF
1077 source arch/arm/mm/Kconfig
1081 default 16 if ARCH_EP93XX
1085 bool "Enable iWMMXt support" if !CPU_PJ4
1086 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1087 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4
1089 Enable support for iWMMXt context switching at run time if
1090 running on a CPU that supports it.
1094 depends on CPU_XSCALE
1097 config MULTI_IRQ_HANDLER
1100 Allow each machine to specify it's own IRQ handler at run time.
1103 source "arch/arm/Kconfig-nommu"
1106 config PJ4B_ERRATA_4742
1107 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1108 depends on CPU_PJ4B && MACH_ARMADA_370
1111 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1112 Event (WFE) IDLE states, a specific timing sensitivity exists between
1113 the retiring WFI/WFE instructions and the newly issued subsequent
1114 instructions. This sensitivity can result in a CPU hang scenario.
1116 The software must insert either a Data Synchronization Barrier (DSB)
1117 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1120 config ARM_ERRATA_326103
1121 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1124 Executing a SWP instruction to read-only memory does not set bit 11
1125 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1126 treat the access as a read, preventing a COW from occurring and
1127 causing the faulting task to livelock.
1129 config ARM_ERRATA_411920
1130 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1131 depends on CPU_V6 || CPU_V6K
1133 Invalidation of the Instruction Cache operation can
1134 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1135 It does not affect the MPCore. This option enables the ARM Ltd.
1136 recommended workaround.
1138 config ARM_ERRATA_430973
1139 bool "ARM errata: Stale prediction on replaced interworking branch"
1142 This option enables the workaround for the 430973 Cortex-A8
1143 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1144 interworking branch is replaced with another code sequence at the
1145 same virtual address, whether due to self-modifying code or virtual
1146 to physical address re-mapping, Cortex-A8 does not recover from the
1147 stale interworking branch prediction. This results in Cortex-A8
1148 executing the new code sequence in the incorrect ARM or Thumb state.
1149 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1150 and also flushes the branch target cache at every context switch.
1151 Note that setting specific bits in the ACTLR register may not be
1152 available in non-secure mode.
1154 config ARM_ERRATA_458693
1155 bool "ARM errata: Processor deadlock when a false hazard is created"
1157 depends on !ARCH_MULTIPLATFORM
1159 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1160 erratum. For very specific sequences of memory operations, it is
1161 possible for a hazard condition intended for a cache line to instead
1162 be incorrectly associated with a different cache line. This false
1163 hazard might then cause a processor deadlock. The workaround enables
1164 the L1 caching of the NEON accesses and disables the PLD instruction
1165 in the ACTLR register. Note that setting specific bits in the ACTLR
1166 register may not be available in non-secure mode.
1168 config ARM_ERRATA_460075
1169 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1171 depends on !ARCH_MULTIPLATFORM
1173 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1174 erratum. Any asynchronous access to the L2 cache may encounter a
1175 situation in which recent store transactions to the L2 cache are lost
1176 and overwritten with stale memory contents from external memory. The
1177 workaround disables the write-allocate mode for the L2 cache via the
1178 ACTLR register. Note that setting specific bits in the ACTLR register
1179 may not be available in non-secure mode.
1181 config ARM_ERRATA_742230
1182 bool "ARM errata: DMB operation may be faulty"
1183 depends on CPU_V7 && SMP
1184 depends on !ARCH_MULTIPLATFORM
1186 This option enables the workaround for the 742230 Cortex-A9
1187 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1188 between two write operations may not ensure the correct visibility
1189 ordering of the two writes. This workaround sets a specific bit in
1190 the diagnostic register of the Cortex-A9 which causes the DMB
1191 instruction to behave as a DSB, ensuring the correct behaviour of
1194 config ARM_ERRATA_742231
1195 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1196 depends on CPU_V7 && SMP
1197 depends on !ARCH_MULTIPLATFORM
1199 This option enables the workaround for the 742231 Cortex-A9
1200 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1201 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1202 accessing some data located in the same cache line, may get corrupted
1203 data due to bad handling of the address hazard when the line gets
1204 replaced from one of the CPUs at the same time as another CPU is
1205 accessing it. This workaround sets specific bits in the diagnostic
1206 register of the Cortex-A9 which reduces the linefill issuing
1207 capabilities of the processor.
1209 config PL310_ERRATA_588369
1210 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1211 depends on CACHE_L2X0
1213 The PL310 L2 cache controller implements three types of Clean &
1214 Invalidate maintenance operations: by Physical Address
1215 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1216 They are architecturally defined to behave as the execution of a
1217 clean operation followed immediately by an invalidate operation,
1218 both performing to the same memory location. This functionality
1219 is not correctly implemented in PL310 as clean lines are not
1220 invalidated as a result of these operations.
1222 config ARM_ERRATA_643719
1223 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1224 depends on CPU_V7 && SMP
1226 This option enables the workaround for the 643719 Cortex-A9 (prior to
1227 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1228 register returns zero when it should return one. The workaround
1229 corrects this value, ensuring cache maintenance operations which use
1230 it behave as intended and avoiding data corruption.
1232 config ARM_ERRATA_720789
1233 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1236 This option enables the workaround for the 720789 Cortex-A9 (prior to
1237 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1238 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1239 As a consequence of this erratum, some TLB entries which should be
1240 invalidated are not, resulting in an incoherency in the system page
1241 tables. The workaround changes the TLB flushing routines to invalidate
1242 entries regardless of the ASID.
1244 config PL310_ERRATA_727915
1245 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1246 depends on CACHE_L2X0
1248 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1249 operation (offset 0x7FC). This operation runs in background so that
1250 PL310 can handle normal accesses while it is in progress. Under very
1251 rare circumstances, due to this erratum, write data can be lost when
1252 PL310 treats a cacheable write transaction during a Clean &
1253 Invalidate by Way operation.
1255 config ARM_ERRATA_743622
1256 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1258 depends on !ARCH_MULTIPLATFORM
1260 This option enables the workaround for the 743622 Cortex-A9
1261 (r2p*) erratum. Under very rare conditions, a faulty
1262 optimisation in the Cortex-A9 Store Buffer may lead to data
1263 corruption. This workaround sets a specific bit in the diagnostic
1264 register of the Cortex-A9 which disables the Store Buffer
1265 optimisation, preventing the defect from occurring. This has no
1266 visible impact on the overall performance or power consumption of the
1269 config ARM_ERRATA_751472
1270 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1272 depends on !ARCH_MULTIPLATFORM
1274 This option enables the workaround for the 751472 Cortex-A9 (prior
1275 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1276 completion of a following broadcasted operation if the second
1277 operation is received by a CPU before the ICIALLUIS has completed,
1278 potentially leading to corrupted entries in the cache or TLB.
1280 config PL310_ERRATA_753970
1281 bool "PL310 errata: cache sync operation may be faulty"
1282 depends on CACHE_PL310
1284 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1286 Under some condition the effect of cache sync operation on
1287 the store buffer still remains when the operation completes.
1288 This means that the store buffer is always asked to drain and
1289 this prevents it from merging any further writes. The workaround
1290 is to replace the normal offset of cache sync operation (0x730)
1291 by another offset targeting an unmapped PL310 register 0x740.
1292 This has the same effect as the cache sync operation: store buffer
1293 drain and waiting for all buffers empty.
1295 config ARM_ERRATA_754322
1296 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1299 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1300 r3p*) erratum. A speculative memory access may cause a page table walk
1301 which starts prior to an ASID switch but completes afterwards. This
1302 can populate the micro-TLB with a stale entry which may be hit with
1303 the new ASID. This workaround places two dsb instructions in the mm
1304 switching code so that no page table walks can cross the ASID switch.
1306 config ARM_ERRATA_754327
1307 bool "ARM errata: no automatic Store Buffer drain"
1308 depends on CPU_V7 && SMP
1310 This option enables the workaround for the 754327 Cortex-A9 (prior to
1311 r2p0) erratum. The Store Buffer does not have any automatic draining
1312 mechanism and therefore a livelock may occur if an external agent
1313 continuously polls a memory location waiting to observe an update.
1314 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1315 written polling loops from denying visibility of updates to memory.
1317 config ARM_ERRATA_364296
1318 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1321 This options enables the workaround for the 364296 ARM1136
1322 r0p2 erratum (possible cache data corruption with
1323 hit-under-miss enabled). It sets the undocumented bit 31 in
1324 the auxiliary control register and the FI bit in the control
1325 register, thus disabling hit-under-miss without putting the
1326 processor into full low interrupt latency mode. ARM11MPCore
1329 config ARM_ERRATA_764369
1330 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1331 depends on CPU_V7 && SMP
1333 This option enables the workaround for erratum 764369
1334 affecting Cortex-A9 MPCore with two or more processors (all
1335 current revisions). Under certain timing circumstances, a data
1336 cache line maintenance operation by MVA targeting an Inner
1337 Shareable memory region may fail to proceed up to either the
1338 Point of Coherency or to the Point of Unification of the
1339 system. This workaround adds a DSB instruction before the
1340 relevant cache maintenance functions and sets a specific bit
1341 in the diagnostic control register of the SCU.
1343 config PL310_ERRATA_769419
1344 bool "PL310 errata: no automatic Store Buffer drain"
1345 depends on CACHE_L2X0
1347 On revisions of the PL310 prior to r3p2, the Store Buffer does
1348 not automatically drain. This can cause normal, non-cacheable
1349 writes to be retained when the memory system is idle, leading
1350 to suboptimal I/O performance for drivers using coherent DMA.
1351 This option adds a write barrier to the cpu_idle loop so that,
1352 on systems with an outer cache, the store buffer is drained
1355 config ARM_ERRATA_775420
1356 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1359 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1360 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1361 operation aborts with MMU exception, it might cause the processor
1362 to deadlock. This workaround puts DSB before executing ISB if
1363 an abort may occur on cache maintenance.
1365 config ARM_ERRATA_798181
1366 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1367 depends on CPU_V7 && SMP
1369 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1370 adequately shooting down all use of the old entries. This
1371 option enables the Linux kernel workaround for this erratum
1372 which sends an IPI to the CPUs that are running the same ASID
1373 as the one being invalidated.
1375 config ARM_ERRATA_773022
1376 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1379 This option enables the workaround for the 773022 Cortex-A15
1380 (up to r0p4) erratum. In certain rare sequences of code, the
1381 loop buffer may deliver incorrect instructions. This
1382 workaround disables the loop buffer to avoid the erratum.
1386 source "arch/arm/common/Kconfig"
1396 Find out whether you have ISA slots on your motherboard. ISA is the
1397 name of a bus system, i.e. the way the CPU talks to the other stuff
1398 inside your box. Other bus systems are PCI, EISA, MicroChannel
1399 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1400 newer boards don't support it. If you have ISA, say Y, otherwise N.
1402 # Select ISA DMA controller support
1407 # Select ISA DMA interface
1412 bool "PCI support" if MIGHT_HAVE_PCI
1414 Find out whether you have a PCI motherboard. PCI is the name of a
1415 bus system, i.e. the way the CPU talks to the other stuff inside
1416 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1417 VESA. If you have PCI, say Y, otherwise N.
1423 config PCI_NANOENGINE
1424 bool "BSE nanoEngine PCI support"
1425 depends on SA1100_NANOENGINE
1427 Enable PCI on the BSE nanoEngine board.
1432 # Select the host bridge type
1433 config PCI_HOST_VIA82C505
1435 depends on PCI && ARCH_SHARK
1438 config PCI_HOST_ITE8152
1440 depends on PCI && MACH_ARMCORE
1444 source "drivers/pci/Kconfig"
1445 source "drivers/pci/pcie/Kconfig"
1447 source "drivers/pcmcia/Kconfig"
1451 menu "Kernel Features"
1456 This option should be selected by machines which have an SMP-
1459 The only effect of this option is to make the SMP-related
1460 options available to the user for configuration.
1463 bool "Symmetric Multi-Processing"
1464 depends on CPU_V6K || CPU_V7
1465 depends on GENERIC_CLOCKEVENTS
1467 depends on MMU || ARM_MPU
1468 select USE_GENERIC_SMP_HELPERS
1470 This enables support for systems with more than one CPU. If you have
1471 a system with only one CPU, like most personal computers, say N. If
1472 you have a system with more than one CPU, say Y.
1474 If you say N here, the kernel will run on single and multiprocessor
1475 machines, but will use only one CPU of a multiprocessor machine. If
1476 you say Y here, the kernel will run on many, but not all, single
1477 processor machines. On a single processor machine, the kernel will
1478 run faster if you say N here.
1480 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1481 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1482 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1484 If you don't know what to do here, say N.
1487 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1488 depends on SMP && !XIP_KERNEL && MMU
1491 SMP kernels contain instructions which fail on non-SMP processors.
1492 Enabling this option allows the kernel to modify itself to make
1493 these instructions safe. Disabling it allows about 1K of space
1496 If you don't know what to do here, say Y.
1498 config ARM_CPU_TOPOLOGY
1499 bool "Support cpu topology definition"
1500 depends on SMP && CPU_V7
1503 Support ARM cpu topology definition. The MPIDR register defines
1504 affinity between processors which is then used to describe the cpu
1505 topology of an ARM System.
1508 bool "Multi-core scheduler support"
1509 depends on ARM_CPU_TOPOLOGY
1511 Multi-core scheduler support improves the CPU scheduler's decision
1512 making when dealing with multi-core CPU chips at a cost of slightly
1513 increased overhead in some places. If unsure say N here.
1516 bool "SMT scheduler support"
1517 depends on ARM_CPU_TOPOLOGY
1519 Improves the CPU scheduler's decision making when dealing with
1520 MultiThreading at a cost of slightly increased overhead in some
1521 places. If unsure say N here.
1526 This option enables support for the ARM system coherency unit
1528 config HAVE_ARM_ARCH_TIMER
1529 bool "Architected timer support"
1531 select ARM_ARCH_TIMER
1533 This option enables support for the ARM architected timer
1538 select CLKSRC_OF if OF
1540 This options enables support for the ARM timer and watchdog unit
1543 bool "Multi-Cluster Power Management"
1544 depends on CPU_V7 && SMP
1546 This option provides the common power management infrastructure
1547 for (multi-)cluster based systems, such as big.LITTLE based
1551 prompt "Memory split"
1554 Select the desired split between kernel and user memory.
1556 If you are not absolutely sure what you are doing, leave this
1560 bool "3G/1G user/kernel split"
1562 bool "2G/2G user/kernel split"
1564 bool "1G/3G user/kernel split"
1569 default 0x40000000 if VMSPLIT_1G
1570 default 0x80000000 if VMSPLIT_2G
1574 int "Maximum number of CPUs (2-32)"
1580 bool "Support for hot-pluggable CPUs"
1583 Say Y here to experiment with turning CPUs off and on. CPUs
1584 can be controlled through /sys/devices/system/cpu.
1587 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1590 Say Y here if you want Linux to communicate with system firmware
1591 implementing the PSCI specification for CPU-centric power
1592 management operations described in ARM document number ARM DEN
1593 0022A ("Power State Coordination Interface System Software on
1596 # The GPIO number here must be sorted by descending number. In case of
1597 # a multiplatform kernel, we just want the highest value required by the
1598 # selected platforms.
1601 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1602 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX
1603 default 392 if ARCH_U8500
1604 default 352 if ARCH_VT8500
1605 default 288 if ARCH_SUNXI
1606 default 264 if MACH_H4700
1609 Maximum number of GPIOs in the system.
1611 If unsure, leave the default value.
1613 source kernel/Kconfig.preempt
1617 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1618 ARCH_S5PV210 || ARCH_EXYNOS4
1619 default AT91_TIMER_HZ if ARCH_AT91
1620 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1623 depends on !HZ_FIXED
1624 prompt "Timer frequency"
1648 default HZ_FIXED if HZ_FIXED
1649 default 100 if HZ_100
1650 default 200 if HZ_200
1651 default 250 if HZ_250
1652 default 300 if HZ_300
1653 default 500 if HZ_500
1657 def_bool HIGH_RES_TIMERS
1660 def_bool HIGH_RES_TIMERS
1662 config THUMB2_KERNEL
1663 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1664 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1665 default y if CPU_THUMBONLY
1667 select ARM_ASM_UNIFIED
1670 By enabling this option, the kernel will be compiled in
1671 Thumb-2 mode. A compiler/assembler that understand the unified
1672 ARM-Thumb syntax is needed.
1676 config THUMB2_AVOID_R_ARM_THM_JUMP11
1677 bool "Work around buggy Thumb-2 short branch relocations in gas"
1678 depends on THUMB2_KERNEL && MODULES
1681 Various binutils versions can resolve Thumb-2 branches to
1682 locally-defined, preemptible global symbols as short-range "b.n"
1683 branch instructions.
1685 This is a problem, because there's no guarantee the final
1686 destination of the symbol, or any candidate locations for a
1687 trampoline, are within range of the branch. For this reason, the
1688 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1689 relocation in modules at all, and it makes little sense to add
1692 The symptom is that the kernel fails with an "unsupported
1693 relocation" error when loading some modules.
1695 Until fixed tools are available, passing
1696 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1697 code which hits this problem, at the cost of a bit of extra runtime
1698 stack usage in some cases.
1700 The problem is described in more detail at:
1701 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1703 Only Thumb-2 kernels are affected.
1705 Unless you are sure your tools don't have this problem, say Y.
1707 config ARM_ASM_UNIFIED
1711 bool "Use the ARM EABI to compile the kernel"
1713 This option allows for the kernel to be compiled using the latest
1714 ARM ABI (aka EABI). This is only useful if you are using a user
1715 space environment that is also compiled with EABI.
1717 Since there are major incompatibilities between the legacy ABI and
1718 EABI, especially with regard to structure member alignment, this
1719 option also changes the kernel syscall calling convention to
1720 disambiguate both ABIs and allow for backward compatibility support
1721 (selected with CONFIG_OABI_COMPAT).
1723 To use this you need GCC version 4.0.0 or later.
1726 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1727 depends on AEABI && !THUMB2_KERNEL
1730 This option preserves the old syscall interface along with the
1731 new (ARM EABI) one. It also provides a compatibility layer to
1732 intercept syscalls that have structure arguments which layout
1733 in memory differs between the legacy ABI and the new ARM EABI
1734 (only for non "thumb" binaries). This option adds a tiny
1735 overhead to all syscalls and produces a slightly larger kernel.
1736 If you know you'll be using only pure EABI user space then you
1737 can say N here. If this option is not selected and you attempt
1738 to execute a legacy ABI binary then the result will be
1739 UNPREDICTABLE (in fact it can be predicted that it won't work
1740 at all). If in doubt say Y.
1742 config ARCH_HAS_HOLES_MEMORYMODEL
1745 config ARCH_SPARSEMEM_ENABLE
1748 config ARCH_SPARSEMEM_DEFAULT
1749 def_bool ARCH_SPARSEMEM_ENABLE
1751 config ARCH_SELECT_MEMORY_MODEL
1752 def_bool ARCH_SPARSEMEM_ENABLE
1754 config HAVE_ARCH_PFN_VALID
1755 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1758 bool "High Memory Support"
1761 The address space of ARM processors is only 4 Gigabytes large
1762 and it has to accommodate user address space, kernel address
1763 space as well as some memory mapped IO. That means that, if you
1764 have a large amount of physical memory and/or IO, not all of the
1765 memory can be "permanently mapped" by the kernel. The physical
1766 memory that is not permanently mapped is called "high memory".
1768 Depending on the selected kernel/user memory split, minimum
1769 vmalloc space and actual amount of RAM, you may not need this
1770 option which should result in a slightly faster kernel.
1775 bool "Allocate 2nd-level pagetables from highmem"
1778 config HW_PERF_EVENTS
1779 bool "Enable hardware performance counter support for perf events"
1780 depends on PERF_EVENTS
1783 Enable hardware performance counter support for perf events. If
1784 disabled, perf events will use software events only.
1786 config SYS_SUPPORTS_HUGETLBFS
1790 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1794 config ARCH_WANT_GENERAL_HUGETLB
1799 config FORCE_MAX_ZONEORDER
1800 int "Maximum zone order" if ARCH_SHMOBILE
1801 range 11 64 if ARCH_SHMOBILE
1802 default "12" if SOC_AM33XX
1803 default "9" if SA1111
1806 The kernel memory allocator divides physically contiguous memory
1807 blocks into "zones", where each zone is a power of two number of
1808 pages. This option selects the largest power of two that the kernel
1809 keeps in the memory allocator. If you need to allocate very large
1810 blocks of physically contiguous memory, then you may need to
1811 increase this value.
1813 This config option is actually maximum order plus one. For example,
1814 a value of 11 means that the largest free memory block is 2^10 pages.
1816 config ALIGNMENT_TRAP
1818 depends on CPU_CP15_MMU
1819 default y if !ARCH_EBSA110
1820 select HAVE_PROC_CPU if PROC_FS
1822 ARM processors cannot fetch/store information which is not
1823 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1824 address divisible by 4. On 32-bit ARM processors, these non-aligned
1825 fetch/store instructions will be emulated in software if you say
1826 here, which has a severe performance impact. This is necessary for
1827 correct operation of some network protocols. With an IP-only
1828 configuration it is safe to say N, otherwise say Y.
1830 config UACCESS_WITH_MEMCPY
1831 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1833 default y if CPU_FEROCEON
1835 Implement faster copy_to_user and clear_user methods for CPU
1836 cores where a 8-word STM instruction give significantly higher
1837 memory write throughput than a sequence of individual 32bit stores.
1839 A possible side effect is a slight increase in scheduling latency
1840 between threads sharing the same address space if they invoke
1841 such copy operations with large buffers.
1843 However, if the CPU data cache is using a write-allocate mode,
1844 this option is unlikely to provide any performance gain.
1848 prompt "Enable seccomp to safely compute untrusted bytecode"
1850 This kernel feature is useful for number crunching applications
1851 that may need to compute untrusted bytecode during their
1852 execution. By using pipes or other transports made available to
1853 the process as file descriptors supporting the read/write
1854 syscalls, it's possible to isolate those applications in
1855 their own address space using seccomp. Once seccomp is
1856 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1857 and the task is only allowed to execute a few safe syscalls
1858 defined by each seccomp mode.
1860 config CC_STACKPROTECTOR
1861 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1863 This option turns on the -fstack-protector GCC feature. This
1864 feature puts, at the beginning of functions, a canary value on
1865 the stack just before the return address, and validates
1866 the value just before actually returning. Stack based buffer
1867 overflows (that need to overwrite this return address) now also
1868 overwrite the canary, which gets detected and the attack is then
1869 neutralized via a kernel panic.
1870 This feature requires gcc version 4.2 or above.
1877 bool "Xen guest support on ARM (EXPERIMENTAL)"
1878 depends on ARM && AEABI && OF
1879 depends on CPU_V7 && !CPU_V6
1880 depends on !GENERIC_ATOMIC64
1883 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1890 bool "Flattened Device Tree support"
1893 select OF_EARLY_FLATTREE
1895 Include support for flattened device tree machine descriptions.
1898 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1901 This is the traditional way of passing data to the kernel at boot
1902 time. If you are solely relying on the flattened device tree (or
1903 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1904 to remove ATAGS support from your kernel binary. If unsure,
1907 config DEPRECATED_PARAM_STRUCT
1908 bool "Provide old way to pass kernel parameters"
1911 This was deprecated in 2001 and announced to live on for 5 years.
1912 Some old boot loaders still use this way.
1914 # Compressed boot loader in ROM. Yes, we really want to ask about
1915 # TEXT and BSS so we preserve their values in the config files.
1916 config ZBOOT_ROM_TEXT
1917 hex "Compressed ROM boot loader base address"
1920 The physical address at which the ROM-able zImage is to be
1921 placed in the target. Platforms which normally make use of
1922 ROM-able zImage formats normally set this to a suitable
1923 value in their defconfig file.
1925 If ZBOOT_ROM is not enabled, this has no effect.
1927 config ZBOOT_ROM_BSS
1928 hex "Compressed ROM boot loader BSS address"
1931 The base address of an area of read/write memory in the target
1932 for the ROM-able zImage which must be available while the
1933 decompressor is running. It must be large enough to hold the
1934 entire decompressed kernel plus an additional 128 KiB.
1935 Platforms which normally make use of ROM-able zImage formats
1936 normally set this to a suitable value in their defconfig file.
1938 If ZBOOT_ROM is not enabled, this has no effect.
1941 bool "Compressed boot loader in ROM/flash"
1942 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1944 Say Y here if you intend to execute your compressed kernel image
1945 (zImage) directly from ROM or flash. If unsure, say N.
1948 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1949 depends on ZBOOT_ROM && ARCH_SH7372
1950 default ZBOOT_ROM_NONE
1952 Include experimental SD/MMC loading code in the ROM-able zImage.
1953 With this enabled it is possible to write the ROM-able zImage
1954 kernel image to an MMC or SD card and boot the kernel straight
1955 from the reset vector. At reset the processor Mask ROM will load
1956 the first part of the ROM-able zImage which in turn loads the
1957 rest the kernel image to RAM.
1959 config ZBOOT_ROM_NONE
1960 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1962 Do not load image from SD or MMC
1964 config ZBOOT_ROM_MMCIF
1965 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1967 Load image from MMCIF hardware block.
1969 config ZBOOT_ROM_SH_MOBILE_SDHI
1970 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1972 Load image from SDHI hardware block
1976 config ARM_APPENDED_DTB
1977 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1978 depends on OF && !ZBOOT_ROM
1980 With this option, the boot code will look for a device tree binary
1981 (DTB) appended to zImage
1982 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1984 This is meant as a backward compatibility convenience for those
1985 systems with a bootloader that can't be upgraded to accommodate
1986 the documented boot protocol using a device tree.
1988 Beware that there is very little in terms of protection against
1989 this option being confused by leftover garbage in memory that might
1990 look like a DTB header after a reboot if no actual DTB is appended
1991 to zImage. Do not leave this option active in a production kernel
1992 if you don't intend to always append a DTB. Proper passing of the
1993 location into r2 of a bootloader provided DTB is always preferable
1996 config ARM_ATAG_DTB_COMPAT
1997 bool "Supplement the appended DTB with traditional ATAG information"
1998 depends on ARM_APPENDED_DTB
2000 Some old bootloaders can't be updated to a DTB capable one, yet
2001 they provide ATAGs with memory configuration, the ramdisk address,
2002 the kernel cmdline string, etc. Such information is dynamically
2003 provided by the bootloader and can't always be stored in a static
2004 DTB. To allow a device tree enabled kernel to be used with such
2005 bootloaders, this option allows zImage to extract the information
2006 from the ATAG list and store it at run time into the appended DTB.
2009 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
2010 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2012 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2013 bool "Use bootloader kernel arguments if available"
2015 Uses the command-line options passed by the boot loader instead of
2016 the device tree bootargs property. If the boot loader doesn't provide
2017 any, the device tree bootargs property will be used.
2019 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2020 bool "Extend with bootloader kernel arguments"
2022 The command-line arguments provided by the boot loader will be
2023 appended to the the device tree bootargs property.
2028 string "Default kernel command string"
2031 On some architectures (EBSA110 and CATS), there is currently no way
2032 for the boot loader to pass arguments to the kernel. For these
2033 architectures, you should supply some command-line options at build
2034 time by entering them here. As a minimum, you should specify the
2035 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2038 prompt "Kernel command line type" if CMDLINE != ""
2039 default CMDLINE_FROM_BOOTLOADER
2042 config CMDLINE_FROM_BOOTLOADER
2043 bool "Use bootloader kernel arguments if available"
2045 Uses the command-line options passed by the boot loader. If
2046 the boot loader doesn't provide any, the default kernel command
2047 string provided in CMDLINE will be used.
2049 config CMDLINE_EXTEND
2050 bool "Extend bootloader kernel arguments"
2052 The command-line arguments provided by the boot loader will be
2053 appended to the default kernel command string.
2055 config CMDLINE_FORCE
2056 bool "Always use the default kernel command string"
2058 Always use the default kernel command string, even if the boot
2059 loader passes other arguments to the kernel.
2060 This is useful if you cannot or don't want to change the
2061 command-line options your boot loader passes to the kernel.
2065 bool "Kernel Execute-In-Place from ROM"
2066 depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2068 Execute-In-Place allows the kernel to run from non-volatile storage
2069 directly addressable by the CPU, such as NOR flash. This saves RAM
2070 space since the text section of the kernel is not loaded from flash
2071 to RAM. Read-write sections, such as the data section and stack,
2072 are still copied to RAM. The XIP kernel is not compressed since
2073 it has to run directly from flash, so it will take more space to
2074 store it. The flash address used to link the kernel object files,
2075 and for storing it, is configuration dependent. Therefore, if you
2076 say Y here, you must know the proper physical address where to
2077 store the kernel image depending on your own flash memory usage.
2079 Also note that the make target becomes "make xipImage" rather than
2080 "make zImage" or "make Image". The final kernel binary to put in
2081 ROM memory will be arch/arm/boot/xipImage.
2085 config XIP_PHYS_ADDR
2086 hex "XIP Kernel Physical Location"
2087 depends on XIP_KERNEL
2088 default "0x00080000"
2090 This is the physical address in your flash memory the kernel will
2091 be linked for and stored to. This address is dependent on your
2095 bool "Kexec system call (EXPERIMENTAL)"
2096 depends on (!SMP || PM_SLEEP_SMP)
2098 kexec is a system call that implements the ability to shutdown your
2099 current kernel, and to start another kernel. It is like a reboot
2100 but it is independent of the system firmware. And like a reboot
2101 you can start any kernel with it, not just Linux.
2103 It is an ongoing process to be certain the hardware in a machine
2104 is properly shutdown, so do not be surprised if this code does not
2105 initially work for you.
2108 bool "Export atags in procfs"
2109 depends on ATAGS && KEXEC
2112 Should the atags used to boot the kernel be exported in an "atags"
2113 file in procfs. Useful with kexec.
2116 bool "Build kdump crash kernel (EXPERIMENTAL)"
2118 Generate crash dump after being started by kexec. This should
2119 be normally only set in special crash dump kernels which are
2120 loaded in the main kernel with kexec-tools into a specially
2121 reserved region and then later executed after a crash by
2122 kdump/kexec. The crash dump kernel must be compiled to a
2123 memory address not used by the main kernel
2125 For more details see Documentation/kdump/kdump.txt
2127 config AUTO_ZRELADDR
2128 bool "Auto calculation of the decompressed kernel image address"
2129 depends on !ZBOOT_ROM
2131 ZRELADDR is the physical address where the decompressed kernel
2132 image will be placed. If AUTO_ZRELADDR is selected, the address
2133 will be determined at run-time by masking the current IP with
2134 0xf8000000. This assumes the zImage being placed in the first 128MB
2135 from start of memory.
2139 menu "CPU Power Management"
2142 source "drivers/cpufreq/Kconfig"
2145 source "drivers/cpuidle/Kconfig"
2149 menu "Floating point emulation"
2151 comment "At least one emulation must be selected"
2154 bool "NWFPE math emulation"
2155 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2157 Say Y to include the NWFPE floating point emulator in the kernel.
2158 This is necessary to run most binaries. Linux does not currently
2159 support floating point hardware so you need to say Y here even if
2160 your machine has an FPA or floating point co-processor podule.
2162 You may say N here if you are going to load the Acorn FPEmulator
2163 early in the bootup.
2166 bool "Support extended precision"
2167 depends on FPE_NWFPE
2169 Say Y to include 80-bit support in the kernel floating-point
2170 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2171 Note that gcc does not generate 80-bit operations by default,
2172 so in most cases this option only enlarges the size of the
2173 floating point emulator without any good reason.
2175 You almost surely want to say N here.
2178 bool "FastFPE math emulation (EXPERIMENTAL)"
2179 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2181 Say Y here to include the FAST floating point emulator in the kernel.
2182 This is an experimental much faster emulator which now also has full
2183 precision for the mantissa. It does not support any exceptions.
2184 It is very simple, and approximately 3-6 times faster than NWFPE.
2186 It should be sufficient for most programs. It may be not suitable
2187 for scientific calculations, but you have to check this for yourself.
2188 If you do not feel you need a faster FP emulation you should better
2192 bool "VFP-format floating point maths"
2193 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2195 Say Y to include VFP support code in the kernel. This is needed
2196 if your hardware includes a VFP unit.
2198 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2199 release notes and additional status information.
2201 Say N if your target does not have VFP hardware.
2209 bool "Advanced SIMD (NEON) Extension support"
2210 depends on VFPv3 && CPU_V7
2212 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2215 config KERNEL_MODE_NEON
2216 bool "Support for NEON in kernel mode"
2220 Say Y to include support for NEON in kernel mode.
2224 menu "Userspace binary formats"
2226 source "fs/Kconfig.binfmt"
2229 tristate "RISC OS personality"
2232 Say Y here to include the kernel code necessary if you want to run
2233 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2234 experimental; if this sounds frightening, say N and sleep in peace.
2235 You can also say M here to compile this support as a module (which
2236 will be called arthur).
2240 menu "Power management options"
2242 source "kernel/power/Kconfig"
2244 config ARCH_SUSPEND_POSSIBLE
2245 depends on !ARCH_S5PC100
2246 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2247 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2250 config ARM_CPU_SUSPEND
2255 source "net/Kconfig"
2257 source "drivers/Kconfig"
2261 source "arch/arm/Kconfig.debug"
2263 source "security/Kconfig"
2265 source "crypto/Kconfig"
2267 source "lib/Kconfig"
2269 source "arch/arm/kvm/Kconfig"