2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
13 #include "am4372.dtsi"
14 #include <dt-bindings/pinctrl/am43xx.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/pwm/pwm.h>
19 model = "TI AM43x EPOS EVM";
20 compatible = "ti,am43x-epos-evm","ti,am4372","ti,am43";
26 vmmcsd_fixed: fixedregulator-sd {
27 compatible = "regulator-fixed";
28 regulator-name = "vmmcsd_fixed";
29 regulator-min-microvolt = <3300000>;
30 regulator-max-microvolt = <3300000>;
35 compatible = "osddisplays,osd057T0559-34ts", "panel-dpi";
38 pinctrl-names = "default";
39 pinctrl-0 = <&lcd_pins>;
42 * SelLCDorHDMI, LOW to select HDMI. This is not really the
43 * panel's enable GPIO, but we don't have HDMI driver support nor
44 * support to switch between two displays, so using this gpio as
45 * panel's enable should be safe.
47 enable-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
50 clock-frequency = <33000000>;
62 pixelclk-active = <1>;
67 remote-endpoint = <&dpi_out>;
72 am43xx_pinmux: pinmux@44e10800 {
73 cpsw_default: cpsw_default {
74 pinctrl-single,pins = <
76 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs */
77 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */
78 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */
79 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxdv.rmii1_rxdv */
80 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */
81 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */
82 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */
83 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */
84 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_refclk.rmii1_refclk */
88 cpsw_sleep: cpsw_sleep {
89 pinctrl-single,pins = <
90 /* Slave 1 reset value */
91 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7)
92 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
93 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
94 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
95 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
96 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
97 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
98 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
99 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7)
103 davinci_mdio_default: davinci_mdio_default {
104 pinctrl-single,pins = <
106 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
107 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
111 davinci_mdio_sleep: davinci_mdio_sleep {
112 pinctrl-single,pins = <
113 /* MDIO reset value */
114 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
115 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
119 i2c0_pins: pinmux_i2c0_pins {
120 pinctrl-single,pins = <
121 0x188 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
122 0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
126 nand_flash_x8: nand_flash_x8 {
127 pinctrl-single,pins = <
128 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.SELQSPIorNAND/GPIO */
129 0x0 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
130 0x4 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
131 0x8 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
132 0xc (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
133 0x10 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
134 0x14 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
135 0x18 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
136 0x1c (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
137 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
138 0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */
139 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
140 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
141 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
142 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
143 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
147 ecap0_pins: backlight_pins {
148 pinctrl-single,pins = <
149 0x164 MUX_MODE0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
153 i2c2_pins: pinmux_i2c2_pins {
154 pinctrl-single,pins = <
155 0x1c0 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8) /* i2c2_sda.i2c2_sda */
156 0x1c4 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8) /* i2c2_scl.i2c2_scl */
160 spi0_pins: pinmux_spi0_pins {
161 pinctrl-single,pins = <
162 0x150 (PIN_INPUT | MUX_MODE0) /* spi0_clk.spi0_clk */
163 0x154 (PIN_OUTPUT | MUX_MODE0) /* spi0_d0.spi0_d0 */
164 0x158 (PIN_INPUT | MUX_MODE0) /* spi0_d1.spi0_d1 */
165 0x15c (PIN_OUTPUT | MUX_MODE0) /* spi0_cs0.spi0_cs0 */
169 spi1_pins: pinmux_spi1_pins {
170 pinctrl-single,pins = <
171 0x190 (PIN_INPUT | MUX_MODE3) /* mcasp0_aclkx.spi1_clk */
172 0x194 (PIN_OUTPUT | MUX_MODE3) /* mcasp0_fsx.spi1_d0 */
173 0x198 (PIN_INPUT | MUX_MODE3) /* mcasp0_axr0.spi1_d1 */
174 0x19c (PIN_OUTPUT | MUX_MODE3) /* mcasp0_ahclkr.spi1_cs0 */
178 mmc1_pins: pinmux_mmc1_pins {
179 pinctrl-single,pins = <
180 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
184 qspi1_default: qspi1_default {
185 pinctrl-single,pins = <
186 0x7c (PIN_INPUT_PULLUP | MUX_MODE3)
187 0x88 (PIN_INPUT_PULLUP | MUX_MODE2)
188 0x90 (PIN_INPUT_PULLUP | MUX_MODE3)
189 0x94 (PIN_INPUT_PULLUP | MUX_MODE3)
190 0x98 (PIN_INPUT_PULLUP | MUX_MODE3)
191 0x9c (PIN_INPUT_PULLUP | MUX_MODE3)
195 pixcir_ts_pins: pixcir_ts_pins {
196 pinctrl-single,pins = <
197 0x44 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a1.gpio1_17 */
201 hdq_pins: pinmux_hdq_pins {
202 pinctrl-single,pins = <
203 0x234 (PIN_INPUT_PULLUP | MUX_MODE1) /* cam1_wen.hdq_gpio */
208 pinctrl-single,pins = <
209 0x020 (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */
210 0x024 (PIN_OUTPUT_PULLUP | MUX_MODE1)
211 0x028 (PIN_OUTPUT_PULLUP | MUX_MODE1)
212 0x02C (PIN_OUTPUT_PULLUP | MUX_MODE1)
213 0x030 (PIN_OUTPUT_PULLUP | MUX_MODE1)
214 0x034 (PIN_OUTPUT_PULLUP | MUX_MODE1)
215 0x038 (PIN_OUTPUT_PULLUP | MUX_MODE1)
216 0x03C (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */
217 0x0A0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */
218 0x0A4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
219 0x0A8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
220 0x0AC (PIN_OUTPUT_PULLUP | MUX_MODE0)
221 0x0B0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
222 0x0B4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
223 0x0B8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
224 0x0BC (PIN_OUTPUT_PULLUP | MUX_MODE0)
225 0x0C0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
226 0x0C4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
227 0x0C8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
228 0x0CC (PIN_OUTPUT_PULLUP | MUX_MODE0)
229 0x0D0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
230 0x0D4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
231 0x0D8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
232 0x0DC (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */
233 0x0E0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */
234 0x0E4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
235 0x0E8 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */
236 0x0EC (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */
241 pinctrl-single,pins = <
242 /* GPMC CLK -> GPIO 2_1 to select LCD / HDMI */
243 0x08C (PIN_OUTPUT_PULLUP | MUX_MODE7)
248 matrix_keypad: matrix_keypad@0 {
249 compatible = "gpio-matrix-keypad";
250 debounce-delay-ms = <5>;
251 col-scan-delay-us = <2>;
253 row-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH /* Bank0, pin12 */
254 &gpio0 13 GPIO_ACTIVE_HIGH /* Bank0, pin13 */
255 &gpio0 14 GPIO_ACTIVE_HIGH /* Bank0, pin14 */
256 &gpio0 15 GPIO_ACTIVE_HIGH>; /* Bank0, pin15 */
258 col-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH /* Bank3, pin9 */
259 &gpio3 10 GPIO_ACTIVE_HIGH /* Bank3, pin10 */
260 &gpio2 18 GPIO_ACTIVE_HIGH /* Bank2, pin18 */
261 &gpio2 19 GPIO_ACTIVE_HIGH>; /* Bank2, pin19 */
263 linux,keymap = <0x00000201 /* P1 */
266 0x0300020a /* NUMERIC_STAR */
274 0x0302020b /* NUMERIC_POUND */
276 0x0103006a /* RIGHT */
277 0x0203006c /* DOWN */
278 0x03030069>; /* LEFT */
282 compatible = "pwm-backlight";
283 pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
284 brightness-levels = <0 51 53 56 62 75 101 152 255>;
285 default-brightness-level = <8>;
291 vmmc-supply = <&vmmcsd_fixed>;
293 pinctrl-names = "default";
294 pinctrl-0 = <&mmc1_pins>;
295 cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
299 pinctrl-names = "default", "sleep";
300 pinctrl-0 = <&cpsw_default>;
301 pinctrl-1 = <&cpsw_sleep>;
306 pinctrl-names = "default", "sleep";
307 pinctrl-0 = <&davinci_mdio_default>;
308 pinctrl-1 = <&davinci_mdio_sleep>;
313 phy_id = <&davinci_mdio>, <16>;
318 phy_id = <&davinci_mdio>, <1>;
328 pinctrl-names = "default";
329 pinctrl-0 = <&i2c0_pins>;
330 clock-frequency = <400000>;
332 tps65218: tps65218@24 {
334 compatible = "ti,tps65218";
335 interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* NMIn */
336 interrupt-parent = <&gic>;
337 interrupt-controller;
338 #interrupt-cells = <2>;
340 dcdc1: regulator-dcdc1 {
341 compatible = "ti,tps65218-dcdc1";
342 regulator-name = "vdd_core";
343 regulator-min-microvolt = <912000>;
344 regulator-max-microvolt = <1144000>;
349 dcdc2: regulator-dcdc2 {
350 compatible = "ti,tps65218-dcdc2";
351 regulator-name = "vdd_mpu";
352 regulator-min-microvolt = <912000>;
353 regulator-max-microvolt = <1378000>;
358 dcdc3: regulator-dcdc3 {
359 compatible = "ti,tps65218-dcdc3";
360 regulator-name = "vdcdc3";
361 regulator-min-microvolt = <1350000>;
362 regulator-max-microvolt = <1350000>;
367 dcdc5: regulator-dcdc5 {
368 compatible = "ti,tps65218-dcdc5";
369 regulator-name = "v1_0bat";
370 regulator-min-microvolt = <1000000>;
371 regulator-max-microvolt = <1000000>;
374 dcdc6: regulator-dcdc6 {
375 compatible = "ti,tps65218-dcdc6";
376 regulator-name = "v1_8bat";
377 regulator-min-microvolt = <1800000>;
378 regulator-max-microvolt = <1800000>;
381 ldo1: regulator-ldo1 {
382 compatible = "ti,tps65218-ldo1";
383 regulator-min-microvolt = <1800000>;
384 regulator-max-microvolt = <1800000>;
391 compatible = "at24,24c256";
397 compatible = "pixcir,pixcir_tangoc";
398 pinctrl-names = "default";
399 pinctrl-0 = <&pixcir_ts_pins>;
401 interrupt-parent = <&gpio1>;
404 attb-gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>;
406 touchscreen-size-x = <1024>;
407 touchscreen-size-y = <600>;
412 pinctrl-names = "default";
413 pinctrl-0 = <&i2c2_pins>;
438 status = "okay"; /* Disable QSPI when enabling GPMC (NAND) */
439 pinctrl-names = "default";
440 pinctrl-0 = <&nand_flash_x8>;
441 ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */
443 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
444 ti,nand-ecc-opt = "bch16";
446 nand-bus-width = <8>;
447 gpmc,device-width = <1>;
448 gpmc,sync-clk-ps = <0>;
450 gpmc,cs-rd-off-ns = <40>; /* tCEA + tCHZ + 1 */
451 gpmc,cs-wr-off-ns = <40>;
452 gpmc,adv-on-ns = <0>; /* cs-on-ns */
453 gpmc,adv-rd-off-ns = <25>; /* min( tALH + tALS + 1) */
454 gpmc,adv-wr-off-ns = <25>; /* min( tALH + tALS + 1) */
455 gpmc,we-on-ns = <0>; /* cs-on-ns */
456 gpmc,we-off-ns = <20>; /* we-on-time + tWP + 2 */
457 gpmc,oe-on-ns = <3>; /* cs-on-ns + tRR + 2 */
458 gpmc,oe-off-ns = <30>; /* oe-on-ns + tRP + 2 */
459 gpmc,access-ns = <30>; /* tCEA + 4*/
460 gpmc,rd-cycle-ns = <40>;
461 gpmc,wr-cycle-ns = <40>;
463 gpmc,bus-turnaround-ns = <0>;
464 gpmc,cycle2cycle-delay-ns = <0>;
465 gpmc,clk-activation-ns = <0>;
466 gpmc,wait-monitoring-ns = <0>;
467 gpmc,wr-access-ns = <40>;
468 gpmc,wr-data-mux-bus-ns = <0>;
469 /* MTD partition table */
470 /* All SPL-* partitions are sized to minimal length
471 * which can be independently programmable. For
472 * NAND flash this is equal to size of erase-block */
473 #address-cells = <1>;
477 reg = <0x00000000 0x00040000>;
480 label = "NAND.SPL.backup1";
481 reg = <0x00040000 0x00040000>;
484 label = "NAND.SPL.backup2";
485 reg = <0x00080000 0x00040000>;
488 label = "NAND.SPL.backup3";
489 reg = <0x000C0000 0x00040000>;
492 label = "NAND.u-boot-spl-os";
493 reg = <0x00100000 0x00080000>;
496 label = "NAND.u-boot";
497 reg = <0x00180000 0x00100000>;
500 label = "NAND.u-boot-env";
501 reg = <0x00280000 0x00040000>;
504 label = "NAND.u-boot-env.backup1";
505 reg = <0x002C0000 0x00040000>;
508 label = "NAND.kernel";
509 reg = <0x00300000 0x00700000>;
512 label = "NAND.file-system";
513 reg = <0x00a00000 0x1f600000>;
526 ti,adc-channels = <0 1 2 3 4 5 6 7>;
532 pinctrl-names = "default";
533 pinctrl-0 = <&ecap0_pins>;
537 pinctrl-names = "default";
538 pinctrl-0 = <&spi0_pins>;
543 pinctrl-names = "default";
544 pinctrl-0 = <&spi1_pins>;
553 dr_mode = "peripheral";
567 status = "disabled"; /* Disable GPMC (NAND) when enabling QSPI */
568 pinctrl-names = "default";
569 pinctrl-0 = <&qspi1_default>;
571 spi-max-frequency = <48000000>;
573 compatible = "mx66l51235l";
574 spi-max-frequency = <48000000>;
578 spi-tx-bus-width = <1>;
579 spi-rx-bus-width = <4>;
580 #address-cells = <1>;
583 /* MTD partition table.
584 * The ROM checks the first 512KiB
585 * for a valid file to boot(XIP).
588 label = "QSPI.U_BOOT";
589 reg = <0x00000000 0x000080000>;
592 label = "QSPI.U_BOOT.backup";
593 reg = <0x00080000 0x00080000>;
596 label = "QSPI.U-BOOT-SPL_OS";
597 reg = <0x00100000 0x00010000>;
600 label = "QSPI.U_BOOT_ENV";
601 reg = <0x00110000 0x00010000>;
604 label = "QSPI.U-BOOT-ENV.backup";
605 reg = <0x00120000 0x00010000>;
608 label = "QSPI.KERNEL";
609 reg = <0x00130000 0x0800000>;
612 label = "QSPI.FILESYSTEM";
613 reg = <0x00930000 0x36D0000>;
620 pinctrl-names = "default";
621 pinctrl-0 = <&hdq_pins>;
627 pinctrl-names = "default";
628 pinctrl-0 = <&dss_pins>;
631 dpi_out: endpoint@0 {
632 remote-endpoint = <&lcd_in>;